[llvm] [WIP][RISCV] tt-ascalon-d8 vector scheduling (PR #167066)

[Min-Yih Hsu via llvm-commits]

mshockwave wrote:

> Does max(ReleaseAtCycles) have to be less than Latency?

In most of the cases Latency should be no less than the largest occupancy / ReleaseAtCycles. But both MachineScheduler and MCA support cases where the occupancy is larger. Here is a more detailed explanation I made somewhere else: https://github.com/mshockwave/portfolio/discussions/13#discussioncomment-14852592

> Can AcquireAtCycles overlap for different pipelines?

I don't quite get the question, could you give an example? I just skimmed over your code and the AcquireAtCycles in it look pretty typical to me

https://github.com/llvm/llvm-project/pull/167066