[llvm] [AMDGPU] [DO NOT MERGE] Nonsuccessful Attempt At Using SelectionDAG Hooks for abs i8/i16 (PR #167064)
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Fri Nov 7 16:48:24 PST 2025
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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/AMDGPU/SIISelLowering.h --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index c56ce443f..3b2da9ae6 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -181,7 +181,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
// We don't want the default expansion of 16-bit ABS since we can
// sign-extend and use the 32-bit ABS operation for 16-bit ABS with SGPRs
- setOperationAction(ISD::ABS, {MVT::i8,MVT::i16}, Custom);
+ setOperationAction(ISD::ABS, {MVT::i8, MVT::i16}, Custom);
}
addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
@@ -7281,7 +7281,7 @@ static SDValue lowerLaneOp(const SITargetLowering &TLI, SDNode *N,
void SITargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const {
- switch (N->getOpcode()) {
+ switch (N->getOpcode()) {
case ISD::INSERT_VECTOR_ELT: {
if (SDValue Res = lowerINSERT_VECTOR_ELT(SDValue(N, 0), DAG))
Results.push_back(Res);
@@ -7462,7 +7462,7 @@ void SITargetLowering::ReplaceNodeResults(SDNode *N,
case ISD::ABS:
if (N->getValueType(0) == MVT::i16 || N->getValueType(0) == MVT::i8) {
SDValue result = lowerABSi16(SDValue(N, 0), DAG);
- if(result!=SDValue()) {
+ if (result != SDValue()) {
Results.push_back(result);
return;
}
@@ -16892,7 +16892,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
return SDValue();
switch (N->getOpcode()) {
- case ISD::ADD:
+ case ISD::ADD:
return performAddCombine(N, DCI);
case ISD::PTRADD:
return performPtrAddCombine(N, DCI);
``````````
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https://github.com/llvm/llvm-project/pull/167064
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