[llvm] 6d516c6 - [llvm][RISCV] Do not assume V extension on seeing vector type. (#166994)
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Fri Nov 7 14:41:10 PST 2025
Author: Chenguang Wang
Date: 2025-11-07T14:41:06-08:00
New Revision: 6d516c6e28a1fdac7229ab0a1ad47adc17ac0d92
URL: https://github.com/llvm/llvm-project/commit/6d516c6e28a1fdac7229ab0a1ad47adc17ac0d92
DIFF: https://github.com/llvm/llvm-project/commit/6d516c6e28a1fdac7229ab0a1ad47adc17ac0d92.diff
LOG: [llvm][RISCV] Do not assume V extension on seeing vector type. (#166994)
We have a private extension which also uses the vector type in the
frontend. Our platform does not have the V extension, so it triggered
assertion failures from within getLMULCost().
It feels reasonable to check for V extension before assuming LMUL
exists.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 7bc0b5b394828..332433b4e530b 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2140,7 +2140,8 @@ InstructionCost RISCVTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
// Assume memory ops cost scale with the number of vector registers
// possible accessed by the instruction. Note that BasicTTI already
// handles the LT.first term for us.
- if (LT.second.isVector() && CostKind != TTI::TCK_CodeSize)
+ if (ST->hasVInstructions() && LT.second.isVector() &&
+ CostKind != TTI::TCK_CodeSize)
BaseCost *= TLI->getLMULCost(LT.second);
return Cost + BaseCost;
}
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