[llvm] [AMDGPU] Add pattern to select scalar ops for fshr with uniform operands (PR #165295)
Akash Dutta via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 7 13:28:00 PST 2025
https://github.com/akadutta updated https://github.com/llvm/llvm-project/pull/165295
>From f03b6f97dc0855d4a2606a712d94ff0c6f777fbc Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Mon, 27 Oct 2025 13:49:05 -0500
Subject: [PATCH 1/8] add ISEL pattern for fshr with uniform operands
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 5 +
llvm/test/CodeGen/AMDGPU/fshr.ll | 518 +++++++++++++++++------
2 files changed, 393 insertions(+), 130 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 6f1feb1dc2996..6e64a1514d27d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2763,6 +2763,11 @@ def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
/* src2_modifiers */ 0,
$src2, /* clamp */ 0, /* op_sel */ 0)
>;
+
+def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
+ (S_OR_B32 (S_LSHR_B32 $src1, (S_AND_B32 $src2, (i32 0xffffffff))), (S_LSHL_B32 $src0, (S_SUB_I32 (i32 32), (S_AND_B32 $src2, (i32 0xffffffff)))))
+>;
+
} // end True16Predicate = UseFakeTrue16Insts
/********** ====================== **********/
diff --git a/llvm/test/CodeGen/AMDGPU/fshr.ll b/llvm/test/CodeGen/AMDGPU/fshr.ll
index ef68f44bac203..4be928f0ef6f1 100644
--- a/llvm/test/CodeGen/AMDGPU/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshr.ll
@@ -103,10 +103,15 @@ define amdgpu_kernel void @fshr_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, s1, v0
-; GFX11-FAKE16-NEXT: global_store_b32 v1, v0, s[4:5]
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, -1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_sub_i32 s3, 32, s2
+; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s1, s2
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s3
+; GFX11-FAKE16-NEXT: s_or_b32 s0, s1, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-FAKE16-NEXT: global_store_b32 v0, v1, s[4:5]
; GFX11-FAKE16-NEXT: s_endpgm
;
; GFX12-TRUE16-LABEL: fshr_i32:
@@ -128,10 +133,15 @@ define amdgpu_kernel void @fshr_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; GFX12-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c
; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_alignbit_b32 v0, s0, s1, v0
-; GFX12-FAKE16-NEXT: global_store_b32 v1, v0, s[4:5]
+; GFX12-FAKE16-NEXT: s_and_b32 s2, s2, -1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX12-FAKE16-NEXT: s_sub_co_i32 s3, 32, s2
+; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s1, s2
+; GFX12-FAKE16-NEXT: s_lshl_b32 s0, s0, s3
+; GFX12-FAKE16-NEXT: s_or_b32 s0, s1, s0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX12-FAKE16-NEXT: global_store_b32 v0, v1, s[4:5]
; GFX12-FAKE16-NEXT: s_endpgm
entry:
%0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
@@ -195,23 +205,49 @@ define amdgpu_kernel void @fshr_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_endpgm
;
-; GFX11-LABEL: fshr_i32_imm:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_alignbit_b32 v1, s2, s3, 7
-; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX12-LABEL: fshr_i32_imm:
-; GFX12: ; %bb.0: ; %entry
-; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_alignbit_b32 v1, s2, s3, 7
-; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX12-NEXT: s_endpgm
+; GFX11-TRUE16-LABEL: fshr_i32_imm:
+; GFX11-TRUE16: ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, s2, s3, 7
+; GFX11-TRUE16-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-TRUE16-NEXT: s_endpgm
+;
+; GFX11-FAKE16-LABEL: fshr_i32_imm:
+; GFX11-FAKE16: ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT: s_sub_i32 s4, 32, 7
+; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, s4
+; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s3, 7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_or_b32 s2, s3, s2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-FAKE16-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT: s_endpgm
+;
+; GFX12-TRUE16-LABEL: fshr_i32_imm:
+; GFX12-TRUE16: ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, s2, s3, 7
+; GFX12-TRUE16-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: fshr_i32_imm:
+; GFX12-FAKE16: ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT: s_sub_co_i32 s4, 32, 7
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: s_lshl_b32 s2, s2, s4
+; GFX12-FAKE16-NEXT: s_lshr_b32 s3, s3, 7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-FAKE16-NEXT: s_or_b32 s2, s3, s2
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-FAKE16-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT: s_endpgm
entry:
%0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 7)
store i32 %0, ptr addrspace(1) %in
@@ -321,12 +357,20 @@ define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s7
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, s1, s3, v0
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, s2, v2
-; GFX11-FAKE16-NEXT: global_store_b64 v3, v[0:1], s[4:5]
+; GFX11-FAKE16-NEXT: s_and_b32 s7, s7, -1
+; GFX11-FAKE16-NEXT: s_and_b32 s6, s6, -1
+; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s3, s7
+; GFX11-FAKE16-NEXT: s_sub_i32 s7, 32, s7
+; GFX11-FAKE16-NEXT: s_sub_i32 s8, 32, s6
+; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, s6
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s8
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, s7
+; GFX11-FAKE16-NEXT: s_or_b32 s0, s2, s0
+; GFX11-FAKE16-NEXT: s_or_b32 s1, s3, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
; GFX11-FAKE16-NEXT: s_endpgm
;
; GFX12-TRUE16-LABEL: fshr_v2i32:
@@ -352,12 +396,20 @@ define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s7
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s6
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_alignbit_b32 v1, s1, s3, v0
-; GFX12-FAKE16-NEXT: v_alignbit_b32 v0, s0, s2, v2
-; GFX12-FAKE16-NEXT: global_store_b64 v3, v[0:1], s[4:5]
+; GFX12-FAKE16-NEXT: s_and_b32 s7, s7, -1
+; GFX12-FAKE16-NEXT: s_and_b32 s6, s6, -1
+; GFX12-FAKE16-NEXT: s_lshr_b32 s3, s3, s7
+; GFX12-FAKE16-NEXT: s_sub_co_i32 s7, 32, s7
+; GFX12-FAKE16-NEXT: s_sub_co_i32 s8, 32, s6
+; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s2, s6
+; GFX12-FAKE16-NEXT: s_lshl_b32 s0, s0, s8
+; GFX12-FAKE16-NEXT: s_lshl_b32 s1, s1, s7
+; GFX12-FAKE16-NEXT: s_or_b32 s0, s2, s0
+; GFX12-FAKE16-NEXT: s_or_b32 s1, s3, s1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
; GFX12-FAKE16-NEXT: s_endpgm
entry:
%0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
@@ -433,29 +485,69 @@ define amdgpu_kernel void @fshr_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX10-NEXT: s_endpgm
;
-; GFX11-LABEL: fshr_v2i32_imm:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_alignbit_b32 v1, s1, s3, 9
-; GFX11-NEXT: v_alignbit_b32 v0, s0, s2, 7
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]
-; GFX11-NEXT: s_endpgm
-;
-; GFX12-LABEL: fshr_v2i32_imm:
-; GFX12: ; %bb.0: ; %entry
-; GFX12-NEXT: s_clause 0x1
-; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_alignbit_b32 v1, s1, s3, 9
-; GFX12-NEXT: v_alignbit_b32 v0, s0, s2, 7
-; GFX12-NEXT: global_store_b64 v2, v[0:1], s[4:5]
-; GFX12-NEXT: s_endpgm
+; GFX11-TRUE16-LABEL: fshr_v2i32_imm:
+; GFX11-TRUE16: ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, s1, s3, 9
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, s2, 7
+; GFX11-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
+; GFX11-TRUE16-NEXT: s_endpgm
+;
+; GFX11-FAKE16-LABEL: fshr_v2i32_imm:
+; GFX11-FAKE16: ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-FAKE16-NEXT: s_sub_i32 s6, 32, 9
+; GFX11-FAKE16-NEXT: s_sub_i32 s7, 32, 7
+; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, s6
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s7
+; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, 7
+; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s3, 9
+; GFX11-FAKE16-NEXT: s_or_b32 s0, s2, s0
+; GFX11-FAKE16-NEXT: s_or_b32 s1, s3, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
+; GFX11-FAKE16-NEXT: s_endpgm
+;
+; GFX12-TRUE16-LABEL: fshr_v2i32_imm:
+; GFX12-TRUE16: ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT: s_clause 0x1
+; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX12-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, s1, s3, 9
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, s0, s2, 7
+; GFX12-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: fshr_v2i32_imm:
+; GFX12-FAKE16: ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT: s_clause 0x1
+; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-FAKE16-NEXT: s_sub_co_i32 s6, 32, 9
+; GFX12-FAKE16-NEXT: s_sub_co_i32 s7, 32, 7
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: s_lshl_b32 s1, s1, s6
+; GFX12-FAKE16-NEXT: s_lshl_b32 s0, s0, s7
+; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s2, 7
+; GFX12-FAKE16-NEXT: s_lshr_b32 s3, s3, 9
+; GFX12-FAKE16-NEXT: s_or_b32 s0, s2, s0
+; GFX12-FAKE16-NEXT: s_or_b32 s1, s3, s1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
+; GFX12-FAKE16-NEXT: s_endpgm
entry:
%0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)
store <2 x i32> %0, ptr addrspace(1) %in
@@ -595,17 +687,32 @@ define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
; GFX11-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, 0
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v3, s11, s15, v0
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v2, s10, s14, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, s9, s13, v4
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s8, s12, v5
-; GFX11-FAKE16-NEXT: global_store_b128 v6, v[0:3], s[4:5]
+; GFX11-FAKE16-NEXT: s_and_b32 s3, s3, -1
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, -1
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, -1
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, -1
+; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s15, s3
+; GFX11-FAKE16-NEXT: s_sub_i32 s3, 32, s3
+; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s14, s2
+; GFX11-FAKE16-NEXT: s_sub_i32 s2, 32, s2
+; GFX11-FAKE16-NEXT: s_lshr_b32 s13, s13, s1
+; GFX11-FAKE16-NEXT: s_sub_i32 s1, 32, s1
+; GFX11-FAKE16-NEXT: s_lshr_b32 s12, s12, s0
+; GFX11-FAKE16-NEXT: s_sub_i32 s0, 32, s0
+; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s11, s3
+; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s10, s2
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s9, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s8, s0
+; GFX11-FAKE16-NEXT: s_or_b32 s3, s6, s3
+; GFX11-FAKE16-NEXT: s_or_b32 s2, s7, s2
+; GFX11-FAKE16-NEXT: s_or_b32 s0, s12, s0
+; GFX11-FAKE16-NEXT: s_or_b32 s1, s13, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[4:5]
; GFX11-FAKE16-NEXT: s_endpgm
;
; GFX12-TRUE16-LABEL: fshr_v4i32:
@@ -635,17 +742,32 @@ define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
; GFX12-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, 0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s2
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_alignbit_b32 v3, s11, s15, v0
-; GFX12-FAKE16-NEXT: v_alignbit_b32 v2, s10, s14, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_alignbit_b32 v1, s9, s13, v4
-; GFX12-FAKE16-NEXT: v_alignbit_b32 v0, s8, s12, v5
-; GFX12-FAKE16-NEXT: global_store_b128 v6, v[0:3], s[4:5]
+; GFX12-FAKE16-NEXT: s_and_b32 s3, s3, -1
+; GFX12-FAKE16-NEXT: s_and_b32 s2, s2, -1
+; GFX12-FAKE16-NEXT: s_and_b32 s1, s1, -1
+; GFX12-FAKE16-NEXT: s_and_b32 s0, s0, -1
+; GFX12-FAKE16-NEXT: s_lshr_b32 s6, s15, s3
+; GFX12-FAKE16-NEXT: s_sub_co_i32 s3, 32, s3
+; GFX12-FAKE16-NEXT: s_lshr_b32 s7, s14, s2
+; GFX12-FAKE16-NEXT: s_sub_co_i32 s2, 32, s2
+; GFX12-FAKE16-NEXT: s_lshr_b32 s13, s13, s1
+; GFX12-FAKE16-NEXT: s_sub_co_i32 s1, 32, s1
+; GFX12-FAKE16-NEXT: s_lshr_b32 s12, s12, s0
+; GFX12-FAKE16-NEXT: s_sub_co_i32 s0, 32, s0
+; GFX12-FAKE16-NEXT: s_lshl_b32 s3, s11, s3
+; GFX12-FAKE16-NEXT: s_lshl_b32 s2, s10, s2
+; GFX12-FAKE16-NEXT: s_lshl_b32 s1, s9, s1
+; GFX12-FAKE16-NEXT: s_lshl_b32 s0, s8, s0
+; GFX12-FAKE16-NEXT: s_or_b32 s3, s6, s3
+; GFX12-FAKE16-NEXT: s_or_b32 s2, s7, s2
+; GFX12-FAKE16-NEXT: s_or_b32 s0, s12, s0
+; GFX12-FAKE16-NEXT: s_or_b32 s1, s13, s1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX12-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[4:5]
; GFX12-FAKE16-NEXT: s_endpgm
entry:
%0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)
@@ -737,33 +859,89 @@ define amdgpu_kernel void @fshr_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm
;
-; GFX11-LABEL: fshr_v4i32_imm:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v4, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_alignbit_b32 v3, s11, s15, 1
-; GFX11-NEXT: v_alignbit_b32 v2, s10, s14, 9
-; GFX11-NEXT: v_alignbit_b32 v1, s9, s13, 7
-; GFX11-NEXT: v_alignbit_b32 v0, s8, s12, 1
-; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX12-LABEL: fshr_v4i32_imm:
-; GFX12: ; %bb.0: ; %entry
-; GFX12-NEXT: s_clause 0x1
-; GFX12-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
-; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT: v_mov_b32_e32 v4, 0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_alignbit_b32 v3, s11, s15, 1
-; GFX12-NEXT: v_alignbit_b32 v2, s10, s14, 9
-; GFX12-NEXT: v_alignbit_b32 v1, s9, s13, 7
-; GFX12-NEXT: v_alignbit_b32 v0, s8, s12, 1
-; GFX12-NEXT: global_store_b128 v4, v[0:3], s[0:1]
-; GFX12-NEXT: s_endpgm
+; GFX11-TRUE16-LABEL: fshr_v4i32_imm:
+; GFX11-TRUE16: ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v3, s11, s15, 1
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v2, s10, s14, 9
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, s9, s13, 7
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s8, s12, 1
+; GFX11-TRUE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX11-TRUE16-NEXT: s_endpgm
+;
+; GFX11-FAKE16-LABEL: fshr_v4i32_imm:
+; GFX11-FAKE16: ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-FAKE16-NEXT: s_sub_i32 s2, 32, 1
+; GFX11-FAKE16-NEXT: s_sub_i32 s3, 32, 9
+; GFX11-FAKE16-NEXT: s_sub_i32 s6, 32, 7
+; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s11, s2
+; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s15, 1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s10, s3
+; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s14, 9
+; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s9, s6
+; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s13, 7
+; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s8, s2
+; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s12, 1
+; GFX11-FAKE16-NEXT: s_or_b32 s4, s5, s4
+; GFX11-FAKE16-NEXT: s_or_b32 s3, s7, s3
+; GFX11-FAKE16-NEXT: s_or_b32 s2, s8, s2
+; GFX11-FAKE16-NEXT: s_or_b32 s5, s9, s6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s4
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s3
+; GFX11-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX11-FAKE16-NEXT: s_endpgm
+;
+; GFX12-TRUE16-LABEL: fshr_v4i32_imm:
+; GFX12-TRUE16: ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT: s_clause 0x1
+; GFX12-TRUE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, 0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v3, s11, s15, 1
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v2, s10, s14, 9
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, s9, s13, 7
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, s8, s12, 1
+; GFX12-TRUE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: fshr_v4i32_imm:
+; GFX12-FAKE16: ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT: s_clause 0x1
+; GFX12-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-FAKE16-NEXT: s_sub_co_i32 s2, 32, 1
+; GFX12-FAKE16-NEXT: s_sub_co_i32 s3, 32, 9
+; GFX12-FAKE16-NEXT: s_sub_co_i32 s6, 32, 7
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s11, s2
+; GFX12-FAKE16-NEXT: s_lshr_b32 s5, s15, 1
+; GFX12-FAKE16-NEXT: s_lshl_b32 s3, s10, s3
+; GFX12-FAKE16-NEXT: s_lshr_b32 s7, s14, 9
+; GFX12-FAKE16-NEXT: s_lshl_b32 s6, s9, s6
+; GFX12-FAKE16-NEXT: s_lshr_b32 s9, s13, 7
+; GFX12-FAKE16-NEXT: s_lshl_b32 s2, s8, s2
+; GFX12-FAKE16-NEXT: s_lshr_b32 s8, s12, 1
+; GFX12-FAKE16-NEXT: s_or_b32 s4, s5, s4
+; GFX12-FAKE16-NEXT: s_or_b32 s3, s7, s3
+; GFX12-FAKE16-NEXT: s_or_b32 s2, s8, s2
+; GFX12-FAKE16-NEXT: s_or_b32 s5, s9, s6
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s3
+; GFX12-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX12-FAKE16-NEXT: s_endpgm
entry:
%0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>)
store <4 x i32> %0, ptr addrspace(1) %in
@@ -2091,29 +2269,109 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %src0, <2 x i24> %src1, <2 x i24> %src2
; GFX10-NEXT: v_alignbit_b32 v1, v1, v3, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fshr_v2i24:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_mul_hi_u32 v6, 0xaaaaaab, v4
-; GFX11-NEXT: v_mul_hi_u32 v7, 0xaaaaaab, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mul_u32_u24_e32 v6, 24, v6
-; GFX11-NEXT: v_mul_u32_u24_e32 v7, 24, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_sub_nc_u32_e32 v4, v4, v6
-; GFX11-NEXT: v_sub_nc_u32_e32 v5, v5, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 8, v4
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 8, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_alignbit_b32 v0, v0, v2, v4
-; GFX11-NEXT: v_alignbit_b32 v1, v1, v3, v5
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fshr_v2i24:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffffff, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mul_hi_u32 v6, 0xaaaaaab, v4
+; GFX11-TRUE16-NEXT: v_mul_hi_u32 v7, 0xaaaaaab, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mul_u32_u24_e32 v6, 24, v6
+; GFX11-TRUE16-NEXT: v_mul_u32_u24_e32 v7, 24, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v4, v4, v6
+; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v5, v5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 8, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 8, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v2, v4.l
+; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, v1, v3, v5.l
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fshr_v2i24:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffffff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_mul_hi_u32 v6, 0xaaaaaab, v4
+; GFX11-FAKE16-NEXT: v_mul_hi_u32 v7, 0xaaaaaab, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_mul_u32_u24_e32 v6, 24, v6
+; GFX11-FAKE16-NEXT: v_mul_u32_u24_e32 v7, 24, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v4, v4, v6
+; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v5, v5, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 8, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 8, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, v0, v2, v4
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, v1, v3, v5
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_fshr_v2i24:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffffff, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_mul_hi_u32 v6, 0xaaaaaab, v4
+; GFX12-TRUE16-NEXT: v_mul_hi_u32 v7, 0xaaaaaab, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_mul_u32_u24_e32 v6, 24, v6
+; GFX12-TRUE16-NEXT: v_mul_u32_u24_e32 v7, 24, v7
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_sub_nc_u32_e32 v4, v4, v6
+; GFX12-TRUE16-NEXT: v_sub_nc_u32_e32 v5, v5, v7
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v4, 8, v4
+; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v5, 8, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, v0, v2, v4.l
+; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, v1, v3, v5.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fshr_v2i24:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffffff, v5
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT: v_mul_hi_u32 v6, 0xaaaaaab, v4
+; GFX12-FAKE16-NEXT: v_mul_hi_u32 v7, 0xaaaaaab, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_mul_u32_u24_e32 v6, 24, v6
+; GFX12-FAKE16-NEXT: v_mul_u32_u24_e32 v7, 24, v7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_sub_nc_u32_e32 v4, v4, v6
+; GFX12-FAKE16-NEXT: v_sub_nc_u32_e32 v5, v5, v7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_add_nc_u32_e32 v4, 8, v4
+; GFX12-FAKE16-NEXT: v_add_nc_u32_e32 v5, 8, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v0, v0, v2, v4
+; GFX12-FAKE16-NEXT: v_alignbit_b32 v1, v1, v3, v5
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%ret = call <2 x i24> @llvm.fshr.v2i24(<2 x i24> %src0, <2 x i24> %src1, <2 x i24> %src2)
ret <2 x i24> %ret
}
>From adf0f1948ef3d1c5e2f5eba46e2f0d74d8e28b23 Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Tue, 28 Oct 2025 12:06:58 -0500
Subject: [PATCH 2/8] remove redundant S_ADD nop
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 2 +-
llvm/test/CodeGen/AMDGPU/fshr.ll | 24 ++++--------------------
2 files changed, 5 insertions(+), 21 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 6e64a1514d27d..bb02a562aa0da 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2765,7 +2765,7 @@ def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
>;
def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
- (S_OR_B32 (S_LSHR_B32 $src1, (S_AND_B32 $src2, (i32 0xffffffff))), (S_LSHL_B32 $src0, (S_SUB_I32 (i32 32), (S_AND_B32 $src2, (i32 0xffffffff)))))
+ (S_OR_B32 (S_LSHR_B32 $src1, $src2), (S_LSHL_B32 $src0, (S_SUB_I32 (i32 32), $src2)))
>;
} // end True16Predicate = UseFakeTrue16Insts
diff --git a/llvm/test/CodeGen/AMDGPU/fshr.ll b/llvm/test/CodeGen/AMDGPU/fshr.ll
index 4be928f0ef6f1..59bda3df8c76e 100644
--- a/llvm/test/CodeGen/AMDGPU/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshr.ll
@@ -103,13 +103,11 @@ define amdgpu_kernel void @fshr_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, -1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_sub_i32 s3, 32, s2
; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s1, s2
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_or_b32 s0, s1, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: global_store_b32 v0, v1, s[4:5]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -133,13 +131,11 @@ define amdgpu_kernel void @fshr_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; GFX12-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c
; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_and_b32 s2, s2, -1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX12-FAKE16-NEXT: s_sub_co_i32 s3, 32, s2
; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s1, s2
; GFX12-FAKE16-NEXT: s_lshl_b32 s0, s0, s3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-FAKE16-NEXT: s_or_b32 s0, s1, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX12-FAKE16-NEXT: global_store_b32 v0, v1, s[4:5]
; GFX12-FAKE16-NEXT: s_endpgm
@@ -357,11 +353,9 @@ define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_and_b32 s7, s7, -1
-; GFX11-FAKE16-NEXT: s_and_b32 s6, s6, -1
+; GFX11-FAKE16-NEXT: s_sub_i32 s8, 32, s6
; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s3, s7
; GFX11-FAKE16-NEXT: s_sub_i32 s7, 32, s7
-; GFX11-FAKE16-NEXT: s_sub_i32 s8, 32, s6
; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, s6
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s8
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, s7
@@ -396,11 +390,9 @@ define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_and_b32 s7, s7, -1
-; GFX12-FAKE16-NEXT: s_and_b32 s6, s6, -1
+; GFX12-FAKE16-NEXT: s_sub_co_i32 s8, 32, s6
; GFX12-FAKE16-NEXT: s_lshr_b32 s3, s3, s7
; GFX12-FAKE16-NEXT: s_sub_co_i32 s7, 32, s7
-; GFX12-FAKE16-NEXT: s_sub_co_i32 s8, 32, s6
; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s2, s6
; GFX12-FAKE16-NEXT: s_lshl_b32 s0, s0, s8
; GFX12-FAKE16-NEXT: s_lshl_b32 s1, s1, s7
@@ -688,10 +680,6 @@ define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX11-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_and_b32 s3, s3, -1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, -1
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, -1
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, -1
; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s15, s3
; GFX11-FAKE16-NEXT: s_sub_i32 s3, 32, s3
; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s14, s2
@@ -743,10 +731,6 @@ define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX12-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_and_b32 s3, s3, -1
-; GFX12-FAKE16-NEXT: s_and_b32 s2, s2, -1
-; GFX12-FAKE16-NEXT: s_and_b32 s1, s1, -1
-; GFX12-FAKE16-NEXT: s_and_b32 s0, s0, -1
; GFX12-FAKE16-NEXT: s_lshr_b32 s6, s15, s3
; GFX12-FAKE16-NEXT: s_sub_co_i32 s3, 32, s3
; GFX12-FAKE16-NEXT: s_lshr_b32 s7, s14, s2
>From a46e1087e4d6e5bb61d2ce8cf19f44acce35de8e Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Wed, 29 Oct 2025 17:31:35 -0500
Subject: [PATCH 3/8] replace previous instr sequence with reg_sequence and
s_lshr_b64 based one
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 12 +-
llvm/test/CodeGen/AMDGPU/fshr.ll | 236 ++++++++++-------------
2 files changed, 117 insertions(+), 131 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index bb02a562aa0da..e7e0dd72e78dd 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2764,10 +2764,20 @@ def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
$src2, /* clamp */ 0, /* op_sel */ 0)
>;
+// The commented out code has been left intentionally to aid the review process, if needed.
+// Will delete before landing.
+//def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
+// (S_OR_B32 (S_LSHR_B32 $src1, $src2), (S_LSHL_B32 $src0, (S_SUB_I32 (i32 32), $src2)))
+//>;
+
def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
- (S_OR_B32 (S_LSHR_B32 $src1, $src2), (S_LSHL_B32 $src0, (S_SUB_I32 (i32 32), $src2)))
+ (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), (S_AND_B32 $src2, (i32 31))), sub0))
>;
+//def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, (i32 ShiftAmt32Imm:$src2)),
+// (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), $src2), sub0))
+//>;
+
} // end True16Predicate = UseFakeTrue16Insts
/********** ====================== **********/
diff --git a/llvm/test/CodeGen/AMDGPU/fshr.ll b/llvm/test/CodeGen/AMDGPU/fshr.ll
index 59bda3df8c76e..4fccebabce04f 100644
--- a/llvm/test/CodeGen/AMDGPU/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshr.ll
@@ -103,11 +103,11 @@ define amdgpu_kernel void @fshr_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_sub_i32 s3, 32, s2
-; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s1, s2
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s3
+; GFX11-FAKE16-NEXT: s_mov_b32 s6, s1
+; GFX11-FAKE16-NEXT: s_mov_b32 s7, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, 31
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_or_b32 s0, s1, s0
+; GFX11-FAKE16-NEXT: s_lshr_b64 s[0:1], s[6:7], s0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: global_store_b32 v0, v1, s[4:5]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -131,11 +131,11 @@ define amdgpu_kernel void @fshr_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; GFX12-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c
; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_sub_co_i32 s3, 32, s2
-; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s1, s2
-; GFX12-FAKE16-NEXT: s_lshl_b32 s0, s0, s3
+; GFX12-FAKE16-NEXT: s_mov_b32 s6, s1
+; GFX12-FAKE16-NEXT: s_mov_b32 s7, s0
+; GFX12-FAKE16-NEXT: s_and_b32 s0, s2, 31
; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-FAKE16-NEXT: s_or_b32 s0, s1, s0
+; GFX12-FAKE16-NEXT: s_lshr_b64 s[0:1], s[6:7], s0
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX12-FAKE16-NEXT: global_store_b32 v0, v1, s[4:5]
; GFX12-FAKE16-NEXT: s_endpgm
@@ -213,12 +213,11 @@ define amdgpu_kernel void @fshr_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
; GFX11-FAKE16-LABEL: fshr_i32_imm:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-FAKE16-NEXT: s_sub_i32 s4, 32, 7
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, s4
-; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s3, 7
+; GFX11-FAKE16-NEXT: s_mov_b32 s4, s3
+; GFX11-FAKE16-NEXT: s_mov_b32 s5, s2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_or_b32 s2, s3, s2
+; GFX11-FAKE16-NEXT: s_lshr_b64 s[2:3], s[4:5], 7
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-FAKE16-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -235,12 +234,11 @@ define amdgpu_kernel void @fshr_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
; GFX12-FAKE16-LABEL: fshr_i32_imm:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: s_sub_co_i32 s4, 32, 7
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_lshl_b32 s2, s2, s4
-; GFX12-FAKE16-NEXT: s_lshr_b32 s3, s3, 7
+; GFX12-FAKE16-NEXT: s_mov_b32 s4, s3
+; GFX12-FAKE16-NEXT: s_mov_b32 s5, s2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-FAKE16-NEXT: s_or_b32 s2, s3, s2
+; GFX12-FAKE16-NEXT: s_lshr_b64 s[2:3], s[4:5], 7
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX12-FAKE16-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
@@ -349,20 +347,19 @@ define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX11-FAKE16-LABEL: fshr_v2i32:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_clause 0x2
-; GFX11-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_sub_i32 s8, 32, s6
-; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s3, s7
-; GFX11-FAKE16-NEXT: s_sub_i32 s7, 32, s7
-; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, s6
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, s7
-; GFX11-FAKE16-NEXT: s_or_b32 s0, s2, s0
-; GFX11-FAKE16-NEXT: s_or_b32 s1, s3, s1
+; GFX11-FAKE16-NEXT: s_mov_b32 s8, s3
+; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
+; GFX11-FAKE16-NEXT: s_mov_b32 s3, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s6, 31
+; GFX11-FAKE16-NEXT: s_and_b32 s6, s7, 31
+; GFX11-FAKE16-NEXT: s_lshr_b64 s[0:1], s[2:3], s0
+; GFX11-FAKE16-NEXT: s_lshr_b64 s[2:3], s[8:9], s6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0
; GFX11-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -386,20 +383,19 @@ define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX12-FAKE16-LABEL: fshr_v2i32:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_clause 0x2
-; GFX12-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX12-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_sub_co_i32 s8, 32, s6
-; GFX12-FAKE16-NEXT: s_lshr_b32 s3, s3, s7
-; GFX12-FAKE16-NEXT: s_sub_co_i32 s7, 32, s7
-; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s2, s6
-; GFX12-FAKE16-NEXT: s_lshl_b32 s0, s0, s8
-; GFX12-FAKE16-NEXT: s_lshl_b32 s1, s1, s7
-; GFX12-FAKE16-NEXT: s_or_b32 s0, s2, s0
-; GFX12-FAKE16-NEXT: s_or_b32 s1, s3, s1
+; GFX12-FAKE16-NEXT: s_mov_b32 s8, s3
+; GFX12-FAKE16-NEXT: s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT: s_mov_b32 s3, s0
+; GFX12-FAKE16-NEXT: s_and_b32 s0, s6, 31
+; GFX12-FAKE16-NEXT: s_and_b32 s6, s7, 31
+; GFX12-FAKE16-NEXT: s_lshr_b64 s[0:1], s[2:3], s0
+; GFX12-FAKE16-NEXT: s_lshr_b64 s[2:3], s[8:9], s6
; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s0
; GFX12-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
; GFX12-FAKE16-NEXT: s_endpgm
@@ -494,17 +490,14 @@ define amdgpu_kernel void @fshr_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-FAKE16-NEXT: s_sub_i32 s6, 32, 9
-; GFX11-FAKE16-NEXT: s_sub_i32 s7, 32, 7
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, s6
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s7
-; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, 7
-; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s3, 9
-; GFX11-FAKE16-NEXT: s_or_b32 s0, s2, s0
-; GFX11-FAKE16-NEXT: s_or_b32 s1, s3, s1
+; GFX11-FAKE16-NEXT: s_mov_b32 s6, s3
+; GFX11-FAKE16-NEXT: s_mov_b32 s3, s0
+; GFX11-FAKE16-NEXT: s_mov_b32 s7, s1
+; GFX11-FAKE16-NEXT: s_lshr_b64 s[0:1], s[2:3], 7
+; GFX11-FAKE16-NEXT: s_lshr_b64 s[2:3], s[6:7], 9
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0
; GFX11-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -526,17 +519,14 @@ define amdgpu_kernel void @fshr_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; GFX12-FAKE16-NEXT: s_clause 0x1
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: s_sub_co_i32 s6, 32, 9
-; GFX12-FAKE16-NEXT: s_sub_co_i32 s7, 32, 7
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_lshl_b32 s1, s1, s6
-; GFX12-FAKE16-NEXT: s_lshl_b32 s0, s0, s7
-; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s2, 7
-; GFX12-FAKE16-NEXT: s_lshr_b32 s3, s3, 9
-; GFX12-FAKE16-NEXT: s_or_b32 s0, s2, s0
-; GFX12-FAKE16-NEXT: s_or_b32 s1, s3, s1
+; GFX12-FAKE16-NEXT: s_mov_b32 s6, s3
+; GFX12-FAKE16-NEXT: s_mov_b32 s3, s0
+; GFX12-FAKE16-NEXT: s_mov_b32 s7, s1
+; GFX12-FAKE16-NEXT: s_lshr_b64 s[0:1], s[2:3], 7
+; GFX12-FAKE16-NEXT: s_lshr_b64 s[2:3], s[6:7], 9
; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s0
; GFX12-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
; GFX12-FAKE16-NEXT: s_endpgm
@@ -676,30 +666,28 @@ define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX11-FAKE16-LABEL: fshr_v4i32:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_clause 0x2
-; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
; GFX11-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s15, s3
-; GFX11-FAKE16-NEXT: s_sub_i32 s3, 32, s3
-; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s14, s2
-; GFX11-FAKE16-NEXT: s_sub_i32 s2, 32, s2
-; GFX11-FAKE16-NEXT: s_lshr_b32 s13, s13, s1
-; GFX11-FAKE16-NEXT: s_sub_i32 s1, 32, s1
-; GFX11-FAKE16-NEXT: s_lshr_b32 s12, s12, s0
-; GFX11-FAKE16-NEXT: s_sub_i32 s0, 32, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s11, s3
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s10, s2
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s9, s1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s8, s0
-; GFX11-FAKE16-NEXT: s_or_b32 s3, s6, s3
-; GFX11-FAKE16-NEXT: s_or_b32 s2, s7, s2
-; GFX11-FAKE16-NEXT: s_or_b32 s0, s12, s0
-; GFX11-FAKE16-NEXT: s_or_b32 s1, s13, s1
+; GFX11-FAKE16-NEXT: s_mov_b32 s6, s15
+; GFX11-FAKE16-NEXT: s_mov_b32 s7, s11
+; GFX11-FAKE16-NEXT: s_and_b32 s11, s3, 31
+; GFX11-FAKE16-NEXT: s_mov_b32 s15, s10
+; GFX11-FAKE16-NEXT: s_and_b32 s10, s2, 31
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, s13
+; GFX11-FAKE16-NEXT: s_mov_b32 s3, s9
+; GFX11-FAKE16-NEXT: s_and_b32 s16, s1, 31
+; GFX11-FAKE16-NEXT: s_mov_b32 s13, s8
+; GFX11-FAKE16-NEXT: s_and_b32 s8, s0, 31
+; GFX11-FAKE16-NEXT: s_lshr_b64 s[0:1], s[6:7], s11
+; GFX11-FAKE16-NEXT: s_lshr_b64 s[6:7], s[14:15], s10
+; GFX11-FAKE16-NEXT: s_lshr_b64 s[8:9], s[12:13], s8
+; GFX11-FAKE16-NEXT: s_lshr_b64 s[2:3], s[2:3], s16
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s6
; GFX11-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[4:5]
; GFX11-FAKE16-NEXT: s_endpgm
;
@@ -727,30 +715,28 @@ define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX12-FAKE16-LABEL: fshr_v4i32:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_clause 0x2
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
; GFX12-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_lshr_b32 s6, s15, s3
-; GFX12-FAKE16-NEXT: s_sub_co_i32 s3, 32, s3
-; GFX12-FAKE16-NEXT: s_lshr_b32 s7, s14, s2
-; GFX12-FAKE16-NEXT: s_sub_co_i32 s2, 32, s2
-; GFX12-FAKE16-NEXT: s_lshr_b32 s13, s13, s1
-; GFX12-FAKE16-NEXT: s_sub_co_i32 s1, 32, s1
-; GFX12-FAKE16-NEXT: s_lshr_b32 s12, s12, s0
-; GFX12-FAKE16-NEXT: s_sub_co_i32 s0, 32, s0
-; GFX12-FAKE16-NEXT: s_lshl_b32 s3, s11, s3
-; GFX12-FAKE16-NEXT: s_lshl_b32 s2, s10, s2
-; GFX12-FAKE16-NEXT: s_lshl_b32 s1, s9, s1
-; GFX12-FAKE16-NEXT: s_lshl_b32 s0, s8, s0
-; GFX12-FAKE16-NEXT: s_or_b32 s3, s6, s3
-; GFX12-FAKE16-NEXT: s_or_b32 s2, s7, s2
-; GFX12-FAKE16-NEXT: s_or_b32 s0, s12, s0
-; GFX12-FAKE16-NEXT: s_or_b32 s1, s13, s1
+; GFX12-FAKE16-NEXT: s_mov_b32 s6, s15
+; GFX12-FAKE16-NEXT: s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT: s_and_b32 s11, s3, 31
+; GFX12-FAKE16-NEXT: s_mov_b32 s15, s10
+; GFX12-FAKE16-NEXT: s_and_b32 s10, s2, 31
+; GFX12-FAKE16-NEXT: s_mov_b32 s2, s13
+; GFX12-FAKE16-NEXT: s_mov_b32 s3, s9
+; GFX12-FAKE16-NEXT: s_and_b32 s16, s1, 31
+; GFX12-FAKE16-NEXT: s_mov_b32 s13, s8
+; GFX12-FAKE16-NEXT: s_and_b32 s8, s0, 31
+; GFX12-FAKE16-NEXT: s_lshr_b64 s[0:1], s[6:7], s11
+; GFX12-FAKE16-NEXT: s_lshr_b64 s[6:7], s[14:15], s10
+; GFX12-FAKE16-NEXT: s_lshr_b64 s[8:9], s[12:13], s8
+; GFX12-FAKE16-NEXT: s_lshr_b64 s[2:3], s[2:3], s16
; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s0
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s6
; GFX12-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[4:5]
; GFX12-FAKE16-NEXT: s_endpgm
entry:
@@ -862,26 +848,21 @@ define amdgpu_kernel void @fshr_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-FAKE16-NEXT: s_sub_i32 s2, 32, 1
-; GFX11-FAKE16-NEXT: s_sub_i32 s3, 32, 9
-; GFX11-FAKE16-NEXT: s_sub_i32 s6, 32, 7
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s11, s2
-; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s15, 1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s10, s3
-; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s14, 9
-; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s9, s6
-; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s13, 7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s8, s2
-; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s12, 1
-; GFX11-FAKE16-NEXT: s_or_b32 s4, s5, s4
-; GFX11-FAKE16-NEXT: s_or_b32 s3, s7, s3
-; GFX11-FAKE16-NEXT: s_or_b32 s2, s8, s2
-; GFX11-FAKE16-NEXT: s_or_b32 s5, s9, s6
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, s15
+; GFX11-FAKE16-NEXT: s_mov_b32 s3, s11
+; GFX11-FAKE16-NEXT: s_mov_b32 s15, s10
+; GFX11-FAKE16-NEXT: s_mov_b32 s4, s13
+; GFX11-FAKE16-NEXT: s_mov_b32 s5, s9
+; GFX11-FAKE16-NEXT: s_mov_b32 s13, s8
+; GFX11-FAKE16-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GFX11-FAKE16-NEXT: s_lshr_b64 s[6:7], s[14:15], 9
+; GFX11-FAKE16-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
+; GFX11-FAKE16-NEXT: s_lshr_b64 s[4:5], s[4:5], 7
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s4
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s2
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s6
; GFX11-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
;
@@ -904,26 +885,21 @@ define amdgpu_kernel void @fshr_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; GFX12-FAKE16-NEXT: s_clause 0x1
; GFX12-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX12-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: s_sub_co_i32 s2, 32, 1
-; GFX12-FAKE16-NEXT: s_sub_co_i32 s3, 32, 9
-; GFX12-FAKE16-NEXT: s_sub_co_i32 s6, 32, 7
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s11, s2
-; GFX12-FAKE16-NEXT: s_lshr_b32 s5, s15, 1
-; GFX12-FAKE16-NEXT: s_lshl_b32 s3, s10, s3
-; GFX12-FAKE16-NEXT: s_lshr_b32 s7, s14, 9
-; GFX12-FAKE16-NEXT: s_lshl_b32 s6, s9, s6
-; GFX12-FAKE16-NEXT: s_lshr_b32 s9, s13, 7
-; GFX12-FAKE16-NEXT: s_lshl_b32 s2, s8, s2
-; GFX12-FAKE16-NEXT: s_lshr_b32 s8, s12, 1
-; GFX12-FAKE16-NEXT: s_or_b32 s4, s5, s4
-; GFX12-FAKE16-NEXT: s_or_b32 s3, s7, s3
-; GFX12-FAKE16-NEXT: s_or_b32 s2, s8, s2
-; GFX12-FAKE16-NEXT: s_or_b32 s5, s9, s6
+; GFX12-FAKE16-NEXT: s_mov_b32 s2, s15
+; GFX12-FAKE16-NEXT: s_mov_b32 s3, s11
+; GFX12-FAKE16-NEXT: s_mov_b32 s15, s10
+; GFX12-FAKE16-NEXT: s_mov_b32 s4, s13
+; GFX12-FAKE16-NEXT: s_mov_b32 s5, s9
+; GFX12-FAKE16-NEXT: s_mov_b32 s13, s8
+; GFX12-FAKE16-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GFX12-FAKE16-NEXT: s_lshr_b64 s[6:7], s[14:15], 9
+; GFX12-FAKE16-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
+; GFX12-FAKE16-NEXT: s_lshr_b64 s[4:5], s[4:5], 7
; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s4
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s3
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s4
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s2
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s6
; GFX12-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
entry:
>From a862618f6c8dba05e5db15d438dc5bcce062df77 Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Sat, 1 Nov 2025 16:58:52 -0500
Subject: [PATCH 4/8] extending new uniform patterns to all fshr cases;tests
updated
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 36 +-
llvm/lib/Target/AMDGPU/SOPInstructions.td | 11 +
llvm/test/CodeGen/AMDGPU/fshl.ll | 380 ++++---
llvm/test/CodeGen/AMDGPU/fshr.ll | 1191 +++++++++++++--------
4 files changed, 1022 insertions(+), 596 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index e7e0dd72e78dd..f71f7ea42d48e 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2694,12 +2694,21 @@ def : GCNPat<pat,
$src1, /* clamp */ 0, /* op_sel */ 0)
>;
-def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
+def : GCNPat<(DivergentTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
(V_ALIGNBIT_B32_opsel_e64 /* src0_modifiers */ 0, $src0,
/* src1_modifiers */ 0, $src1,
/* src2_modifiers */ 0,
$src2, /* clamp */ 0, /* op_sel */ 0)
>;
+
+def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
+ (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), (S_AND_B32 $src2, (i32 31))), sub0))
+>;
+
+def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, (i32 ShiftAmt32Imm:$src2)),
+ (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), $src2), sub0))
+>;
+
} // isGFX9GFX10
} // end True16Predicate = NotHasTrue16BitInsts
@@ -2722,12 +2731,21 @@ def : GCNPat<(i32 (DivergentUnaryFrag<trunc> (srl i64:$src0, (i32 ShiftAmt32Imm:
(i16 (EXTRACT_SUBREG VGPR_32:$src1, lo16)),
/* clamp */ 0, /* op_sel */ 0)>;
-def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
+def : GCNPat<(DivergentTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
(V_ALIGNBIT_B32_t16_e64 /* src0_modifiers */ 0, $src0,
/* src1_modifiers */ 0, $src1,
/* src2_modifiers */ 0,
(EXTRACT_SUBREG VGPR_32:$src2, lo16),
/* clamp */ 0, /* op_sel */ 0)>;
+
+def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
+ (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), (S_AND_B32 $src2, (i32 31))), sub0))
+>;
+
+def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, (i32 ShiftAmt32Imm:$src2)),
+ (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), $src2), sub0))
+>;
+
} // end True16Predicate = UseRealTrue16Insts
let True16Predicate = UseFakeTrue16Insts in {
@@ -2757,26 +2775,20 @@ def : GCNPat<(i32 (DivergentUnaryFrag<trunc> (srl i64:$src0, (i32 ShiftAmt32Imm:
$src1, /* clamp */ 0, /* op_sel */ 0)
>;
-def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
+def : GCNPat<(DivergentTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
(V_ALIGNBIT_B32_fake16_e64 /* src0_modifiers */ 0, $src0,
/* src1_modifiers */ 0, $src1,
/* src2_modifiers */ 0,
$src2, /* clamp */ 0, /* op_sel */ 0)
>;
-// The commented out code has been left intentionally to aid the review process, if needed.
-// Will delete before landing.
-//def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
-// (S_OR_B32 (S_LSHR_B32 $src1, $src2), (S_LSHL_B32 $src0, (S_SUB_I32 (i32 32), $src2)))
-//>;
-
def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
(i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), (S_AND_B32 $src2, (i32 31))), sub0))
>;
-//def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, (i32 ShiftAmt32Imm:$src2)),
-// (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), $src2), sub0))
-//>;
+def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, (i32 ShiftAmt32Imm:$src2)),
+ (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), $src2), sub0))
+>;
} // end True16Predicate = UseFakeTrue16Insts
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 84287b621fe78..bc54ef847305d 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -207,6 +207,17 @@ class DivergentBinFrag<SDPatternOperator Op> : PatFrag <
let GISelPredicateCode = [{return true;}];
}
+class DivergentTernaryFrag<SDPatternOperator Op> : PatFrag <
+ (ops node:$src0, node:$src1, node:$src2),
+ (Op $src0, $src1, $src2),
+ [{ return N->isDivergent(); }]> {
+ // This check is unnecessary as it's captured by the result register
+ // bank constraint.
+ //
+ // FIXME: Should add a way for the emitter to recognize this is a
+ // trivially true predicate to eliminate the check.
+ let GISelPredicateCode = [{return true;}];
+}
let isMoveImm = 1 in {
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
diff --git a/llvm/test/CodeGen/AMDGPU/fshl.ll b/llvm/test/CodeGen/AMDGPU/fshl.ll
index ed1ee4527ed89..792f2aa711455 100644
--- a/llvm/test/CodeGen/AMDGPU/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshl.ll
@@ -49,12 +49,15 @@ define amdgpu_kernel void @fshl_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: s_mov_b32 s4, s1
+; GFX9-NEXT: s_mov_b32 s5, s0
+; GFX9-NEXT: s_lshr_b32 s3, s0, 1
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
; GFX9-NEXT: s_not_b32 s2, s2
-; GFX9-NEXT: s_lshr_b32 s1, s0, 1
-; GFX9-NEXT: v_alignbit_b32 v1, s0, v1, 1
-; GFX9-NEXT: v_mov_b32_e32 v2, s2
-; GFX9-NEXT: v_alignbit_b32 v1, s1, v1, v2
+; GFX9-NEXT: s_mov_b32 s1, s3
+; GFX9-NEXT: s_and_b32 s2, s2, 31
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: global_store_dword v0, v1, s[6:7]
; GFX9-NEXT: s_endpgm
;
@@ -77,13 +80,18 @@ define amdgpu_kernel void @fshl_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, 1
-; GFX10-NEXT: s_lshr_b32 s0, s0, 1
-; GFX10-NEXT: s_not_b32 s1, s2
-; GFX10-NEXT: v_alignbit_b32 v0, s0, v0, s1
-; GFX10-NEXT: global_store_dword v1, v0, s[6:7]
+; GFX10-NEXT: s_mov_b32 s4, s1
+; GFX10-NEXT: s_mov_b32 s5, s0
+; GFX10-NEXT: s_lshr_b32 s3, s0, 1
+; GFX10-NEXT: s_not_b32 s2, s2
+; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_and_b32 s2, s2, 31
+; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; GFX10-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-NEXT: global_store_dword v0, v1, s[6:7]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: fshl_i32:
@@ -91,14 +99,18 @@ define amdgpu_kernel void @fshl_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 1
-; GFX11-NEXT: s_lshr_b32 s0, s0, 1
-; GFX11-NEXT: s_not_b32 s1, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_alignbit_b32 v0, s0, v0, s1
-; GFX11-NEXT: global_store_b32 v1, v0, s[4:5]
+; GFX11-NEXT: s_mov_b32 s6, s1
+; GFX11-NEXT: s_mov_b32 s7, s0
+; GFX11-NEXT: s_lshr_b32 s3, s0, 1
+; GFX11-NEXT: s_not_b32 s2, s2
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_and_b32 s2, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: global_store_b32 v0, v1, s[4:5]
; GFX11-NEXT: s_endpgm
entry:
%0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
@@ -136,8 +148,10 @@ define amdgpu_kernel void @fshl_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: v_alignbit_b32 v1, s2, v1, 25
+; GFX9-NEXT: s_mov_b32 s4, s3
+; GFX9-NEXT: s_mov_b32 s5, s2
+; GFX9-NEXT: s_lshr_b64 s[2:3], s[4:5], 25
+; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
@@ -158,16 +172,22 @@ define amdgpu_kernel void @fshl_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_alignbit_b32 v1, s2, s3, 25
+; GFX10-NEXT: s_mov_b32 s4, s3
+; GFX10-NEXT: s_mov_b32 s5, s2
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[4:5], 25
+; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: fshl_i32_imm:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_alignbit_b32 v1, s2, s3, 25
+; GFX11-NEXT: s_mov_b32 s4, s3
+; GFX11-NEXT: s_mov_b32 s5, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[4:5], 25
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
entry:
@@ -230,18 +250,23 @@ define amdgpu_kernel void @fshl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x3c
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v0, s3
-; GFX9-NEXT: s_lshr_b32 s3, s1, 1
-; GFX9-NEXT: v_alignbit_b32 v0, s1, v0, 1
+; GFX9-NEXT: s_mov_b32 s4, s3
+; GFX9-NEXT: s_mov_b32 s5, s1
+; GFX9-NEXT: s_lshr_b32 s10, s1, 1
+; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
; GFX9-NEXT: s_not_b32 s1, s9
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_alignbit_b32 v1, s3, v0, v1
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: s_not_b32 s1, s8
-; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, 1
-; GFX9-NEXT: s_lshr_b32 s0, s0, 1
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
-; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, v3
+; GFX9-NEXT: s_mov_b32 s5, s10
+; GFX9-NEXT: s_and_b32 s1, s1, 31
+; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s1
+; GFX9-NEXT: s_mov_b32 s3, s0
+; GFX9-NEXT: s_lshr_b32 s5, s0, 1
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[2:3], 1
+; GFX9-NEXT: s_not_b32 s2, s8
+; GFX9-NEXT: s_mov_b32 s1, s5
+; GFX9-NEXT: s_and_b32 s2, s2, 31
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX9-NEXT: s_endpgm
;
@@ -271,14 +296,23 @@ define amdgpu_kernel void @fshl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX10-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_alignbit_b32 v0, s1, s3, 1
-; GFX10-NEXT: v_alignbit_b32 v3, s0, s2, 1
-; GFX10-NEXT: s_lshr_b32 s1, s1, 1
-; GFX10-NEXT: s_not_b32 s2, s7
-; GFX10-NEXT: s_lshr_b32 s0, s0, 1
-; GFX10-NEXT: s_not_b32 s3, s6
-; GFX10-NEXT: v_alignbit_b32 v1, s1, v0, s2
-; GFX10-NEXT: v_alignbit_b32 v0, s0, v3, s3
+; GFX10-NEXT: s_mov_b32 s4, s3
+; GFX10-NEXT: s_mov_b32 s5, s1
+; GFX10-NEXT: s_mov_b32 s3, s0
+; GFX10-NEXT: s_lshr_b32 s10, s1, 1
+; GFX10-NEXT: s_not_b32 s7, s7
+; GFX10-NEXT: s_lshr_b32 s11, s0, 1
+; GFX10-NEXT: s_not_b32 s6, s6
+; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GFX10-NEXT: s_and_b32 s4, s7, 31
+; GFX10-NEXT: s_and_b32 s5, s6, 31
+; GFX10-NEXT: s_mov_b32 s3, s11
+; GFX10-NEXT: s_mov_b32 s1, s10
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s5
+; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s4
+; GFX10-NEXT: v_mov_b32_e32 v0, s2
+; GFX10-NEXT: v_mov_b32_e32 v1, s0
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
; GFX10-NEXT: s_endpgm
;
@@ -288,16 +322,25 @@ define amdgpu_kernel void @fshl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_alignbit_b32 v0, s1, s3, 1
-; GFX11-NEXT: v_alignbit_b32 v3, s0, s2, 1
-; GFX11-NEXT: s_lshr_b32 s1, s1, 1
-; GFX11-NEXT: s_not_b32 s2, s7
-; GFX11-NEXT: s_lshr_b32 s0, s0, 1
-; GFX11-NEXT: s_not_b32 s3, s6
-; GFX11-NEXT: v_alignbit_b32 v1, s1, v0, s2
-; GFX11-NEXT: v_alignbit_b32 v0, s0, v3, s3
+; GFX11-NEXT: s_mov_b32 s8, s3
+; GFX11-NEXT: s_mov_b32 s9, s1
+; GFX11-NEXT: s_mov_b32 s3, s0
+; GFX11-NEXT: s_lshr_b32 s10, s1, 1
+; GFX11-NEXT: s_not_b32 s7, s7
+; GFX11-NEXT: s_lshr_b32 s11, s0, 1
+; GFX11-NEXT: s_not_b32 s6, s6
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[8:9], 1
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GFX11-NEXT: s_and_b32 s7, s7, 31
+; GFX11-NEXT: s_and_b32 s6, s6, 31
+; GFX11-NEXT: s_mov_b32 s3, s11
+; GFX11-NEXT: s_mov_b32 s1, s10
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s6
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]
; GFX11-NEXT: s_endpgm
entry:
@@ -341,10 +384,13 @@ define amdgpu_kernel void @fshl_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v0, s3
-; GFX9-NEXT: v_mov_b32_e32 v3, s2
-; GFX9-NEXT: v_alignbit_b32 v1, s1, v0, 23
-; GFX9-NEXT: v_alignbit_b32 v0, s0, v3, 25
+; GFX9-NEXT: s_mov_b32 s4, s3
+; GFX9-NEXT: s_mov_b32 s5, s1
+; GFX9-NEXT: s_mov_b32 s3, s0
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], 23
+; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], 25
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX9-NEXT: s_endpgm
;
@@ -369,8 +415,13 @@ define amdgpu_kernel void @fshl_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_alignbit_b32 v1, s1, s3, 23
-; GFX10-NEXT: v_alignbit_b32 v0, s0, s2, 25
+; GFX10-NEXT: s_mov_b32 s4, s3
+; GFX10-NEXT: s_mov_b32 s3, s0
+; GFX10-NEXT: s_mov_b32 s5, s1
+; GFX10-NEXT: s_lshr_b64 s[0:1], s[2:3], 25
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[4:5], 23
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX10-NEXT: s_endpgm
;
@@ -379,10 +430,15 @@ define amdgpu_kernel void @fshl_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_alignbit_b32 v1, s1, s3, 23
-; GFX11-NEXT: v_alignbit_b32 v0, s0, s2, 25
+; GFX11-NEXT: s_mov_b32 s6, s3
+; GFX11-NEXT: s_mov_b32 s3, s0
+; GFX11-NEXT: s_mov_b32 s7, s1
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[2:3], 25
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[6:7], 23
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]
; GFX11-NEXT: s_endpgm
entry:
@@ -465,34 +521,44 @@ define amdgpu_kernel void @fshl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX9-LABEL: fshl_v4i32:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x54
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x54
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_mov_b32 s4, s15
+; GFX9-NEXT: s_mov_b32 s5, s11
+; GFX9-NEXT: s_lshr_b32 s16, s11, 1
+; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
; GFX9-NEXT: s_not_b32 s3, s3
-; GFX9-NEXT: v_mov_b32_e32 v0, s15
-; GFX9-NEXT: s_lshr_b32 s4, s11, 1
-; GFX9-NEXT: v_alignbit_b32 v0, s11, v0, 1
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: v_alignbit_b32 v3, s4, v0, v1
-; GFX9-NEXT: v_mov_b32_e32 v0, s14
-; GFX9-NEXT: s_not_b32 s2, s2
-; GFX9-NEXT: v_alignbit_b32 v0, s10, v0, 1
+; GFX9-NEXT: s_mov_b32 s5, s16
+; GFX9-NEXT: s_and_b32 s3, s3, 31
+; GFX9-NEXT: s_mov_b32 s15, s10
+; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s3
; GFX9-NEXT: s_lshr_b32 s3, s10, 1
-; GFX9-NEXT: v_mov_b32_e32 v1, s2
-; GFX9-NEXT: v_alignbit_b32 v2, s3, v0, v1
-; GFX9-NEXT: v_mov_b32_e32 v0, s13
+; GFX9-NEXT: s_lshr_b64 s[10:11], s[14:15], 1
+; GFX9-NEXT: s_not_b32 s2, s2
+; GFX9-NEXT: s_mov_b32 s11, s3
+; GFX9-NEXT: s_and_b32 s2, s2, 31
+; GFX9-NEXT: s_lshr_b64 s[2:3], s[10:11], s2
+; GFX9-NEXT: s_mov_b32 s10, s13
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_lshr_b32 s3, s9, 1
+; GFX9-NEXT: s_lshr_b64 s[10:11], s[10:11], 1
; GFX9-NEXT: s_not_b32 s1, s1
-; GFX9-NEXT: v_alignbit_b32 v0, s9, v0, 1
-; GFX9-NEXT: s_lshr_b32 s2, s9, 1
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_alignbit_b32 v1, s2, v0, v1
-; GFX9-NEXT: v_mov_b32_e32 v0, s12
-; GFX9-NEXT: s_not_b32 s0, s0
-; GFX9-NEXT: v_alignbit_b32 v0, s8, v0, 1
+; GFX9-NEXT: s_mov_b32 s11, s3
+; GFX9-NEXT: s_and_b32 s1, s1, 31
+; GFX9-NEXT: s_mov_b32 s13, s8
+; GFX9-NEXT: s_lshr_b64 s[10:11], s[10:11], s1
; GFX9-NEXT: s_lshr_b32 s1, s8, 1
-; GFX9-NEXT: v_mov_b32_e32 v5, s0
-; GFX9-NEXT: v_alignbit_b32 v0, s1, v0, v5
+; GFX9-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
+; GFX9-NEXT: s_not_b32 s0, s0
+; GFX9-NEXT: s_mov_b32 s9, s1
+; GFX9-NEXT: s_and_b32 s0, s0, 31
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s10
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GFX9-NEXT: s_endpgm
;
@@ -530,22 +596,40 @@ define amdgpu_kernel void @fshl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_alignbit_b32 v0, s11, s15, 1
-; GFX10-NEXT: v_alignbit_b32 v1, s10, s14, 1
-; GFX10-NEXT: v_alignbit_b32 v5, s9, s13, 1
-; GFX10-NEXT: v_alignbit_b32 v6, s8, s12, 1
-; GFX10-NEXT: s_lshr_b32 s4, s11, 1
-; GFX10-NEXT: s_not_b32 s3, s3
-; GFX10-NEXT: s_lshr_b32 s5, s10, 1
-; GFX10-NEXT: s_not_b32 s2, s2
-; GFX10-NEXT: s_lshr_b32 s9, s9, 1
+; GFX10-NEXT: s_mov_b32 s4, s15
+; GFX10-NEXT: s_mov_b32 s5, s11
+; GFX10-NEXT: s_mov_b32 s15, s10
+; GFX10-NEXT: s_lshr_b32 s16, s11, 1
+; GFX10-NEXT: s_not_b32 s11, s3
+; GFX10-NEXT: s_lshr_b32 s17, s10, 1
+; GFX10-NEXT: s_not_b32 s10, s2
+; GFX10-NEXT: s_lshr_b32 s18, s9, 1
+; GFX10-NEXT: s_mov_b32 s2, s13
+; GFX10-NEXT: s_mov_b32 s3, s9
+; GFX10-NEXT: s_lshr_b32 s19, s8, 1
+; GFX10-NEXT: s_mov_b32 s13, s8
+; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
+; GFX10-NEXT: s_lshr_b64 s[8:9], s[14:15], 1
+; GFX10-NEXT: s_and_b32 s11, s11, 31
+; GFX10-NEXT: s_and_b32 s10, s10, 31
+; GFX10-NEXT: s_mov_b32 s5, s16
+; GFX10-NEXT: s_mov_b32 s9, s17
; GFX10-NEXT: s_not_b32 s1, s1
-; GFX10-NEXT: s_lshr_b32 s8, s8, 1
; GFX10-NEXT: s_not_b32 s0, s0
-; GFX10-NEXT: v_alignbit_b32 v3, s4, v0, s3
-; GFX10-NEXT: v_alignbit_b32 v2, s5, v1, s2
-; GFX10-NEXT: v_alignbit_b32 v1, s9, v5, s1
-; GFX10-NEXT: v_alignbit_b32 v0, s8, v6, s0
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], s11
+; GFX10-NEXT: s_lshr_b64 s[8:9], s[8:9], s10
+; GFX10-NEXT: s_lshr_b64 s[10:11], s[12:13], 1
+; GFX10-NEXT: s_mov_b32 s3, s18
+; GFX10-NEXT: s_mov_b32 s11, s19
+; GFX10-NEXT: s_and_b32 s0, s0, 31
+; GFX10-NEXT: s_and_b32 s5, s1, 31
+; GFX10-NEXT: s_lshr_b64 s[0:1], s[10:11], s0
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s5
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s2
+; GFX10-NEXT: v_mov_b32_e32 v2, s8
+; GFX10-NEXT: v_mov_b32_e32 v3, s4
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GFX10-NEXT: s_endpgm
;
@@ -555,24 +639,41 @@ define amdgpu_kernel void @fshl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v4, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_alignbit_b32 v0, s11, s15, 1
-; GFX11-NEXT: v_alignbit_b32 v1, s10, s14, 1
-; GFX11-NEXT: v_alignbit_b32 v5, s9, s13, 1
-; GFX11-NEXT: v_alignbit_b32 v6, s8, s12, 1
-; GFX11-NEXT: s_lshr_b32 s6, s11, 1
-; GFX11-NEXT: s_not_b32 s3, s3
-; GFX11-NEXT: s_lshr_b32 s7, s10, 1
-; GFX11-NEXT: s_not_b32 s2, s2
-; GFX11-NEXT: s_lshr_b32 s9, s9, 1
+; GFX11-NEXT: s_mov_b32 s6, s15
+; GFX11-NEXT: s_mov_b32 s7, s11
+; GFX11-NEXT: s_mov_b32 s15, s10
+; GFX11-NEXT: s_lshr_b32 s16, s11, 1
+; GFX11-NEXT: s_not_b32 s11, s3
+; GFX11-NEXT: s_lshr_b32 s17, s10, 1
+; GFX11-NEXT: s_not_b32 s10, s2
+; GFX11-NEXT: s_lshr_b32 s18, s9, 1
+; GFX11-NEXT: s_mov_b32 s2, s13
+; GFX11-NEXT: s_mov_b32 s3, s9
+; GFX11-NEXT: s_lshr_b32 s19, s8, 1
+; GFX11-NEXT: s_mov_b32 s13, s8
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], 1
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[14:15], 1
+; GFX11-NEXT: s_and_b32 s11, s11, 31
+; GFX11-NEXT: s_and_b32 s10, s10, 31
+; GFX11-NEXT: s_mov_b32 s7, s16
+; GFX11-NEXT: s_mov_b32 s9, s17
; GFX11-NEXT: s_not_b32 s1, s1
-; GFX11-NEXT: s_lshr_b32 s8, s8, 1
; GFX11-NEXT: s_not_b32 s0, s0
-; GFX11-NEXT: v_alignbit_b32 v3, s6, v0, s3
-; GFX11-NEXT: v_alignbit_b32 v2, s7, v1, s2
-; GFX11-NEXT: v_alignbit_b32 v1, s9, v5, s1
-; GFX11-NEXT: v_alignbit_b32 v0, s8, v6, s0
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], s11
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[8:9], s10
+; GFX11-NEXT: s_lshr_b64 s[10:11], s[12:13], 1
+; GFX11-NEXT: s_mov_b32 s3, s18
+; GFX11-NEXT: s_mov_b32 s11, s19
+; GFX11-NEXT: s_and_b32 s0, s0, 31
+; GFX11-NEXT: s_and_b32 s7, s1, 31
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[10:11], s0
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s6
+; GFX11-NEXT: v_mov_b32_e32 v2, s8
; GFX11-NEXT: global_store_b128 v4, v[0:3], s[4:5]
; GFX11-NEXT: s_endpgm
entry:
@@ -624,14 +725,20 @@ define amdgpu_kernel void @fshl_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v0, s15
-; GFX9-NEXT: v_mov_b32_e32 v1, s14
-; GFX9-NEXT: v_alignbit_b32 v3, s11, v0, 31
-; GFX9-NEXT: v_mov_b32_e32 v0, s13
-; GFX9-NEXT: v_alignbit_b32 v2, s10, v1, 23
-; GFX9-NEXT: v_alignbit_b32 v1, s9, v0, 25
-; GFX9-NEXT: v_mov_b32_e32 v0, s12
-; GFX9-NEXT: v_alignbit_b32 v0, s8, v0, 31
+; GFX9-NEXT: s_mov_b32 s2, s15
+; GFX9-NEXT: s_mov_b32 s3, s11
+; GFX9-NEXT: s_mov_b32 s15, s10
+; GFX9-NEXT: s_mov_b32 s6, s13
+; GFX9-NEXT: s_mov_b32 s7, s9
+; GFX9-NEXT: s_mov_b32 s13, s8
+; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], 31
+; GFX9-NEXT: s_lshr_b64 s[4:5], s[14:15], 23
+; GFX9-NEXT: s_lshr_b64 s[6:7], s[6:7], 25
+; GFX9-NEXT: s_lshr_b64 s[8:9], s[12:13], 31
+; GFX9-NEXT: v_mov_b32_e32 v0, s8
+; GFX9-NEXT: v_mov_b32_e32 v1, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm
;
@@ -660,10 +767,20 @@ define amdgpu_kernel void @fshl_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_alignbit_b32 v3, s11, s15, 31
-; GFX10-NEXT: v_alignbit_b32 v2, s10, s14, 23
-; GFX10-NEXT: v_alignbit_b32 v1, s9, s13, 25
-; GFX10-NEXT: v_alignbit_b32 v0, s8, s12, 31
+; GFX10-NEXT: s_mov_b32 s2, s15
+; GFX10-NEXT: s_mov_b32 s3, s11
+; GFX10-NEXT: s_mov_b32 s15, s10
+; GFX10-NEXT: s_mov_b32 s4, s13
+; GFX10-NEXT: s_mov_b32 s5, s9
+; GFX10-NEXT: s_mov_b32 s13, s8
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 31
+; GFX10-NEXT: s_lshr_b64 s[6:7], s[14:15], 23
+; GFX10-NEXT: s_lshr_b64 s[8:9], s[12:13], 31
+; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], 25
+; GFX10-NEXT: v_mov_b32_e32 v0, s8
+; GFX10-NEXT: v_mov_b32_e32 v1, s4
+; GFX10-NEXT: v_mov_b32_e32 v2, s6
+; GFX10-NEXT: v_mov_b32_e32 v3, s2
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm
;
@@ -672,12 +789,21 @@ define amdgpu_kernel void @fshl_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v4, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_alignbit_b32 v3, s11, s15, 31
-; GFX11-NEXT: v_alignbit_b32 v2, s10, s14, 23
-; GFX11-NEXT: v_alignbit_b32 v1, s9, s13, 25
-; GFX11-NEXT: v_alignbit_b32 v0, s8, s12, 31
+; GFX11-NEXT: s_mov_b32 s2, s15
+; GFX11-NEXT: s_mov_b32 s3, s11
+; GFX11-NEXT: s_mov_b32 s15, s10
+; GFX11-NEXT: s_mov_b32 s4, s13
+; GFX11-NEXT: s_mov_b32 s5, s9
+; GFX11-NEXT: s_mov_b32 s13, s8
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 31
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[14:15], 23
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[12:13], 31
+; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], 25
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s4
+; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT: v_mov_b32_e32 v2, s6
; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-NEXT: s_endpgm
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/fshr.ll b/llvm/test/CodeGen/AMDGPU/fshr.ll
index 4fccebabce04f..a32d4d8dcda88 100644
--- a/llvm/test/CodeGen/AMDGPU/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshr.ll
@@ -55,9 +55,11 @@ define amdgpu_kernel void @fshr_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_mov_b32_e32 v2, s2
-; GFX9-NEXT: v_alignbit_b32 v1, s0, v1, v2
+; GFX9-NEXT: s_mov_b32 s4, s1
+; GFX9-NEXT: s_mov_b32 s5, s0
+; GFX9-NEXT: s_and_b32 s0, s2, 31
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: global_store_dword v0, v1, s[6:7]
; GFX9-NEXT: s_endpgm
;
@@ -77,68 +79,45 @@ define amdgpu_kernel void @fshr_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, v0
-; GFX10-NEXT: global_store_dword v1, v0, s[6:7]
+; GFX10-NEXT: s_mov_b32 s4, s1
+; GFX10-NEXT: s_mov_b32 s5, s0
+; GFX10-NEXT: s_and_b32 s0, s2, 31
+; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-NEXT: global_store_dword v0, v1, s[6:7]
; GFX10-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: fshr_i32:
-; GFX11-TRUE16: ; %bb.0: ; %entry
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, s1, v0.l
-; GFX11-TRUE16-NEXT: global_store_b32 v1, v0, s[4:5]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: fshr_i32:
-; GFX11-FAKE16: ; %bb.0: ; %entry
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_mov_b32 s6, s1
-; GFX11-FAKE16-NEXT: s_mov_b32 s7, s0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, 31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_lshr_b64 s[0:1], s[6:7], s0
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX11-FAKE16-NEXT: global_store_b32 v0, v1, s[4:5]
-; GFX11-FAKE16-NEXT: s_endpgm
-;
-; GFX12-TRUE16-LABEL: fshr_i32:
-; GFX12-TRUE16: ; %bb.0: ; %entry
-; GFX12-TRUE16-NEXT: s_clause 0x1
-; GFX12-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c
-; GFX12-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, s0, s1, v0.l
-; GFX12-TRUE16-NEXT: global_store_b32 v1, v0, s[4:5]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: fshr_i32:
-; GFX12-FAKE16: ; %bb.0: ; %entry
-; GFX12-FAKE16-NEXT: s_clause 0x1
-; GFX12-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c
-; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_mov_b32 s6, s1
-; GFX12-FAKE16-NEXT: s_mov_b32 s7, s0
-; GFX12-FAKE16-NEXT: s_and_b32 s0, s2, 31
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-FAKE16-NEXT: s_lshr_b64 s[0:1], s[6:7], s0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX12-FAKE16-NEXT: global_store_b32 v0, v1, s[4:5]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: fshr_i32:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_mov_b32 s6, s1
+; GFX11-NEXT: s_mov_b32 s7, s0
+; GFX11-NEXT: s_and_b32 s0, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[6:7], s0
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: global_store_b32 v0, v1, s[4:5]
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fshr_i32:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s6, s1
+; GFX12-NEXT: s_mov_b32 s7, s0
+; GFX12-NEXT: s_and_b32 s0, s2, 31
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_lshr_b64 s[0:1], s[6:7], s0
+; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX12-NEXT: global_store_b32 v0, v1, s[4:5]
+; GFX12-NEXT: s_endpgm
entry:
%0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
store i32 %0, ptr addrspace(1) %in
@@ -175,8 +154,10 @@ define amdgpu_kernel void @fshr_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: v_alignbit_b32 v1, s2, v1, 7
+; GFX9-NEXT: s_mov_b32 s4, s3
+; GFX9-NEXT: s_mov_b32 s5, s2
+; GFX9-NEXT: s_lshr_b64 s[2:3], s[4:5], 7
+; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
@@ -197,57 +178,136 @@ define amdgpu_kernel void @fshr_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_alignbit_b32 v1, s2, s3, 7
+; GFX10-NEXT: s_mov_b32 s4, s3
+; GFX10-NEXT: s_mov_b32 s5, s2
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[4:5], 7
+; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: fshr_i32_imm:
-; GFX11-TRUE16: ; %bb.0: ; %entry
-; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, s2, s3, 7
-; GFX11-TRUE16-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: fshr_i32_imm:
-; GFX11-FAKE16: ; %bb.0: ; %entry
-; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_mov_b32 s4, s3
-; GFX11-FAKE16-NEXT: s_mov_b32 s5, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_lshr_b64 s[2:3], s[4:5], 7
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
-;
-; GFX12-TRUE16-LABEL: fshr_i32_imm:
-; GFX12-TRUE16: ; %bb.0: ; %entry
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, s2, s3, 7
-; GFX12-TRUE16-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: fshr_i32_imm:
-; GFX12-FAKE16: ; %bb.0: ; %entry
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_mov_b32 s4, s3
-; GFX12-FAKE16-NEXT: s_mov_b32 s5, s2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-FAKE16-NEXT: s_lshr_b64 s[2:3], s[4:5], 7
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX12-FAKE16-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: fshr_i32_imm:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_mov_b32 s4, s3
+; GFX11-NEXT: s_mov_b32 s5, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[4:5], 7
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fshr_i32_imm:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s4, s3
+; GFX12-NEXT: s_mov_b32 s5, s2
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_lshr_b64 s[2:3], s[4:5], 7
+; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT: s_endpgm
entry:
%0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 7)
store i32 %0, ptr addrspace(1) %in
ret void
}
+define amdgpu_kernel void @fshr_i32_imm_src0(ptr addrspace(1) %in, i32 %x, i32 %y) {
+; SI-LABEL: fshr_i32_imm_src0:
+; SI: ; %bb.0: ; %entry
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s2
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: v_alignbit_b32 v0, 7, s3, v0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: fshr_i32_imm_src0:
+; VI: ; %bb.0: ; %entry
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_alignbit_b32 v2, 7, s3, v0
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
+;
+; GFX9-LABEL: fshr_i32_imm_src0:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT: s_mov_b32 s5, 7
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_mov_b32 s4, s3
+; GFX9-NEXT: s_and_b32 s2, s2, 31
+; GFX9-NEXT: s_lshr_b64 s[2:3], s[4:5], s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s2
+; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX9-NEXT: s_endpgm
+;
+; R600-LABEL: fshr_i32_imm_src0:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+; R600-NEXT: ALU clause starting at 4:
+; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
+; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; R600-NEXT: BIT_ALIGN_INT * T1.X, literal.x, KC0[2].W, KC0[2].Z,
+; R600-NEXT: 7(9.809089e-45), 0(0.000000e+00)
+;
+; GFX10-LABEL: fshr_i32_imm_src0:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX10-NEXT: s_mov_b32 s5, 7
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: s_mov_b32 s4, s3
+; GFX10-NEXT: s_and_b32 s2, s2, 31
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[4:5], s2
+; GFX10-NEXT: v_mov_b32_e32 v1, s2
+; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: fshr_i32_imm_src0:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-NEXT: s_mov_b32 s5, 7
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_mov_b32 s4, s3
+; GFX11-NEXT: s_and_b32 s2, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[4:5], s2
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fshr_i32_imm_src0:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_mov_b32 s5, 7
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s4, s3
+; GFX12-NEXT: s_and_b32 s2, s2, 31
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_lshr_b64 s[2:3], s[4:5], s2
+; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT: s_endpgm
+entry:
+ %0 = call i32 @llvm.fshr.i32(i32 7, i32 %y, i32 %x)
+ store i32 %0, ptr addrspace(1) %in
+ ret void
+}
+
define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
; SI-LABEL: fshr_v2i32:
; SI: ; %bb.0: ; %entry
@@ -290,12 +350,15 @@ define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v0, s3
-; GFX9-NEXT: v_mov_b32_e32 v1, s7
-; GFX9-NEXT: v_alignbit_b32 v1, s1, v0, v1
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v3, s6
-; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, v3
+; GFX9-NEXT: s_mov_b32 s4, s3
+; GFX9-NEXT: s_mov_b32 s5, s1
+; GFX9-NEXT: s_and_b32 s1, s7, 31
+; GFX9-NEXT: s_mov_b32 s3, s0
+; GFX9-NEXT: s_and_b32 s0, s6, 31
+; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s1
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[2:3], s0
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
; GFX9-NEXT: s_endpgm
;
@@ -316,89 +379,62 @@ define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX10-LABEL: fshr_v2i32:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x2
-; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x3c
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x3c
; GFX10-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x24
-; GFX10-NEXT: v_mov_b32_e32 v3, 0
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v0, s7
-; GFX10-NEXT: v_mov_b32_e32 v2, s6
-; GFX10-NEXT: v_alignbit_b32 v1, s1, s3, v0
-; GFX10-NEXT: v_alignbit_b32 v0, s0, s2, v2
-; GFX10-NEXT: global_store_dwordx2 v3, v[0:1], s[8:9]
+; GFX10-NEXT: s_mov_b32 s4, s3
+; GFX10-NEXT: s_mov_b32 s5, s1
+; GFX10-NEXT: s_mov_b32 s3, s0
+; GFX10-NEXT: s_and_b32 s0, s6, 31
+; GFX10-NEXT: s_and_b32 s6, s7, 31
+; GFX10-NEXT: s_lshr_b64 s[0:1], s[2:3], s0
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[4:5], s6
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s2
+; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
; GFX10-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: fshr_v2i32:
-; GFX11-TRUE16: ; %bb.0: ; %entry
-; GFX11-TRUE16-NEXT: s_clause 0x2
-; GFX11-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
-; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, s1, s3, v0.l
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, s2, v0.h
-; GFX11-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: fshr_v2i32:
-; GFX11-FAKE16: ; %bb.0: ; %entry
-; GFX11-FAKE16-NEXT: s_clause 0x2
-; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX11-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
-; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_mov_b32 s8, s3
-; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
-; GFX11-FAKE16-NEXT: s_mov_b32 s3, s0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s6, 31
-; GFX11-FAKE16-NEXT: s_and_b32 s6, s7, 31
-; GFX11-FAKE16-NEXT: s_lshr_b64 s[0:1], s[2:3], s0
-; GFX11-FAKE16-NEXT: s_lshr_b64 s[2:3], s[8:9], s6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GFX11-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
-; GFX11-FAKE16-NEXT: s_endpgm
-;
-; GFX12-TRUE16-LABEL: fshr_v2i32:
-; GFX12-TRUE16: ; %bb.0: ; %entry
-; GFX12-TRUE16-NEXT: s_clause 0x2
-; GFX12-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX12-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, s6
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, s1, s3, v0.l
-; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, s0, s2, v0.h
-; GFX12-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: fshr_v2i32:
-; GFX12-FAKE16: ; %bb.0: ; %entry
-; GFX12-FAKE16-NEXT: s_clause 0x2
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX12-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
-; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_mov_b32 s8, s3
-; GFX12-FAKE16-NEXT: s_mov_b32 s9, s1
-; GFX12-FAKE16-NEXT: s_mov_b32 s3, s0
-; GFX12-FAKE16-NEXT: s_and_b32 s0, s6, 31
-; GFX12-FAKE16-NEXT: s_and_b32 s6, s7, 31
-; GFX12-FAKE16-NEXT: s_lshr_b64 s[0:1], s[2:3], s0
-; GFX12-FAKE16-NEXT: s_lshr_b64 s[2:3], s[8:9], s6
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: fshr_v2i32:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_clause 0x2
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
+; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_mov_b32 s8, s3
+; GFX11-NEXT: s_mov_b32 s9, s1
+; GFX11-NEXT: s_mov_b32 s3, s0
+; GFX11-NEXT: s_and_b32 s0, s6, 31
+; GFX11-NEXT: s_and_b32 s6, s7, 31
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[2:3], s0
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[8:9], s6
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fshr_v2i32:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x2
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX12-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s3
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_mov_b32 s3, s0
+; GFX12-NEXT: s_and_b32 s0, s6, 31
+; GFX12-NEXT: s_and_b32 s6, s7, 31
+; GFX12-NEXT: s_lshr_b64 s[0:1], s[2:3], s0
+; GFX12-NEXT: s_lshr_b64 s[2:3], s[8:9], s6
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: global_store_b64 v2, v[0:1], s[4:5]
+; GFX12-NEXT: s_endpgm
entry:
%0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
store <2 x i32> %0, ptr addrspace(1) %in
@@ -440,10 +476,13 @@ define amdgpu_kernel void @fshr_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v0, s3
-; GFX9-NEXT: v_mov_b32_e32 v3, s2
-; GFX9-NEXT: v_alignbit_b32 v1, s1, v0, 9
-; GFX9-NEXT: v_alignbit_b32 v0, s0, v3, 7
+; GFX9-NEXT: s_mov_b32 s4, s3
+; GFX9-NEXT: s_mov_b32 s5, s1
+; GFX9-NEXT: s_mov_b32 s3, s0
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], 9
+; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], 7
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX9-NEXT: s_endpgm
;
@@ -468,74 +507,182 @@ define amdgpu_kernel void @fshr_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_alignbit_b32 v1, s1, s3, 9
-; GFX10-NEXT: v_alignbit_b32 v0, s0, s2, 7
+; GFX10-NEXT: s_mov_b32 s4, s3
+; GFX10-NEXT: s_mov_b32 s3, s0
+; GFX10-NEXT: s_mov_b32 s5, s1
+; GFX10-NEXT: s_lshr_b64 s[0:1], s[2:3], 7
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[4:5], 9
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX10-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: fshr_v2i32_imm:
-; GFX11-TRUE16: ; %bb.0: ; %entry
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, s1, s3, 9
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, s2, 7
-; GFX11-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: fshr_v2i32_imm:
-; GFX11-FAKE16: ; %bb.0: ; %entry
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_mov_b32 s6, s3
-; GFX11-FAKE16-NEXT: s_mov_b32 s3, s0
-; GFX11-FAKE16-NEXT: s_mov_b32 s7, s1
-; GFX11-FAKE16-NEXT: s_lshr_b64 s[0:1], s[2:3], 7
-; GFX11-FAKE16-NEXT: s_lshr_b64 s[2:3], s[6:7], 9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GFX11-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
-; GFX11-FAKE16-NEXT: s_endpgm
-;
-; GFX12-TRUE16-LABEL: fshr_v2i32_imm:
-; GFX12-TRUE16: ; %bb.0: ; %entry
-; GFX12-TRUE16-NEXT: s_clause 0x1
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX12-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, s1, s3, 9
-; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, s0, s2, 7
-; GFX12-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: fshr_v2i32_imm:
-; GFX12-FAKE16: ; %bb.0: ; %entry
-; GFX12-FAKE16-NEXT: s_clause 0x1
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_mov_b32 s6, s3
-; GFX12-FAKE16-NEXT: s_mov_b32 s3, s0
-; GFX12-FAKE16-NEXT: s_mov_b32 s7, s1
-; GFX12-FAKE16-NEXT: s_lshr_b64 s[0:1], s[2:3], 7
-; GFX12-FAKE16-NEXT: s_lshr_b64 s[2:3], s[6:7], 9
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[4:5]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: fshr_v2i32_imm:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_mov_b32 s6, s3
+; GFX11-NEXT: s_mov_b32 s3, s0
+; GFX11-NEXT: s_mov_b32 s7, s1
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[2:3], 7
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[6:7], 9
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fshr_v2i32_imm:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s6, s3
+; GFX12-NEXT: s_mov_b32 s3, s0
+; GFX12-NEXT: s_mov_b32 s7, s1
+; GFX12-NEXT: s_lshr_b64 s[0:1], s[2:3], 7
+; GFX12-NEXT: s_lshr_b64 s[2:3], s[6:7], 9
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: global_store_b64 v2, v[0:1], s[4:5]
+; GFX12-NEXT: s_endpgm
entry:
%0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)
store <2 x i32> %0, ptr addrspace(1) %in
ret void
}
+define amdgpu_kernel void @fshr_v2i32_imm_src1(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y) {
+; SI-LABEL: fshr_v2i32_imm_src1:
+; SI: ; %bb.0: ; %entry
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s3
+; SI-NEXT: v_mov_b32_e32 v2, s2
+; SI-NEXT: v_alignbit_b32 v1, s1, 9, v0
+; SI-NEXT: v_alignbit_b32 v0, s0, 7, v2
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: fshr_v2i32_imm_src1:
+; VI: ; %bb.0: ; %entry
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s3
+; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: v_alignbit_b32 v1, s1, 9, v0
+; VI-NEXT: v_alignbit_b32 v0, s0, 7, v2
+; VI-NEXT: v_mov_b32_e32 v2, s4
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-NEXT: s_endpgm
+;
+; GFX9-LABEL: fshr_v2i32_imm_src1:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX9-NEXT: s_mov_b32 s4, 9
+; GFX9-NEXT: s_mov_b32 s8, 7
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_mov_b32 s5, s1
+; GFX9-NEXT: s_and_b32 s1, s3, 31
+; GFX9-NEXT: s_mov_b32 s9, s0
+; GFX9-NEXT: s_and_b32 s0, s2, 31
+; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s1
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
+; GFX9-NEXT: s_endpgm
+;
+; R600-LABEL: fshr_v2i32_imm_src1:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+; R600-NEXT: ALU clause starting at 4:
+; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].X, literal.x, KC0[3].Z,
+; R600-NEXT: 9(1.261169e-44), 0(0.000000e+00)
+; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[2].W, literal.x, KC0[3].Y,
+; R600-NEXT: 7(9.809089e-45), 0(0.000000e+00)
+; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX10-LABEL: fshr_v2i32_imm_src1:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX10-NEXT: s_mov_b32 s4, 9
+; GFX10-NEXT: s_mov_b32 s8, 7
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: s_mov_b32 s5, s1
+; GFX10-NEXT: s_mov_b32 s9, s0
+; GFX10-NEXT: s_and_b32 s0, s2, 31
+; GFX10-NEXT: s_and_b32 s2, s3, 31
+; GFX10-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[4:5], s2
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s2
+; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: fshr_v2i32_imm_src1:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-NEXT: s_mov_b32 s6, 9
+; GFX11-NEXT: s_mov_b32 s8, 7
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_mov_b32 s7, s1
+; GFX11-NEXT: s_mov_b32 s9, s0
+; GFX11-NEXT: s_and_b32 s0, s2, 31
+; GFX11-NEXT: s_and_b32 s2, s3, 31
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[6:7], s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fshr_v2i32_imm_src1:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-NEXT: s_mov_b32 s6, 9
+; GFX12-NEXT: s_mov_b32 s8, 7
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s7, s1
+; GFX12-NEXT: s_mov_b32 s9, s0
+; GFX12-NEXT: s_and_b32 s0, s2, 31
+; GFX12-NEXT: s_and_b32 s2, s3, 31
+; GFX12-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
+; GFX12-NEXT: s_lshr_b64 s[2:3], s[6:7], s2
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: global_store_b64 v2, v[0:1], s[4:5]
+; GFX12-NEXT: s_endpgm
+entry:
+ %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> <i32 7, i32 9>, <2 x i32> %y)
+ store <2 x i32> %0, ptr addrspace(1) %in
+ ret void
+}
+
define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
; SI-LABEL: fshr_v4i32:
; SI: ; %bb.0: ; %entry
@@ -590,18 +737,24 @@ define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v0, s15
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: v_alignbit_b32 v3, s11, v0, v1
-; GFX9-NEXT: v_mov_b32_e32 v0, s14
-; GFX9-NEXT: v_mov_b32_e32 v1, s2
-; GFX9-NEXT: v_alignbit_b32 v2, s10, v0, v1
-; GFX9-NEXT: v_mov_b32_e32 v0, s13
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_alignbit_b32 v1, s9, v0, v1
-; GFX9-NEXT: v_mov_b32_e32 v0, s12
-; GFX9-NEXT: v_mov_b32_e32 v5, s0
-; GFX9-NEXT: v_alignbit_b32 v0, s8, v0, v5
+; GFX9-NEXT: s_mov_b32 s4, s15
+; GFX9-NEXT: s_mov_b32 s5, s11
+; GFX9-NEXT: s_and_b32 s3, s3, 31
+; GFX9-NEXT: s_mov_b32 s15, s10
+; GFX9-NEXT: s_and_b32 s2, s2, 31
+; GFX9-NEXT: s_mov_b32 s10, s13
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: s_and_b32 s1, s1, 31
+; GFX9-NEXT: s_mov_b32 s13, s8
+; GFX9-NEXT: s_and_b32 s0, s0, 31
+; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s3
+; GFX9-NEXT: s_lshr_b64 s[2:3], s[14:15], s2
+; GFX9-NEXT: s_lshr_b64 s[10:11], s[10:11], s1
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[12:13], s0
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s10
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GFX9-NEXT: s_endpgm
;
@@ -626,119 +779,87 @@ define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX10-LABEL: fshr_v4i32:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x2
-; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x54
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x54
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX10-NEXT: v_mov_b32_e32 v6, 0
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v0, s3
+; GFX10-NEXT: s_mov_b32 s4, s15
+; GFX10-NEXT: s_mov_b32 s5, s11
+; GFX10-NEXT: s_and_b32 s11, s3, 31
+; GFX10-NEXT: s_mov_b32 s15, s10
+; GFX10-NEXT: s_and_b32 s10, s2, 31
+; GFX10-NEXT: s_mov_b32 s2, s13
+; GFX10-NEXT: s_mov_b32 s3, s9
+; GFX10-NEXT: s_and_b32 s16, s1, 31
+; GFX10-NEXT: s_mov_b32 s13, s8
+; GFX10-NEXT: s_and_b32 s8, s0, 31
+; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], s11
+; GFX10-NEXT: s_lshr_b64 s[4:5], s[14:15], s10
+; GFX10-NEXT: s_lshr_b64 s[8:9], s[12:13], s8
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s16
+; GFX10-NEXT: v_mov_b32_e32 v0, s8
; GFX10-NEXT: v_mov_b32_e32 v1, s2
-; GFX10-NEXT: v_mov_b32_e32 v4, s1
-; GFX10-NEXT: v_mov_b32_e32 v5, s0
-; GFX10-NEXT: v_alignbit_b32 v3, s11, s15, v0
-; GFX10-NEXT: v_alignbit_b32 v2, s10, s14, v1
-; GFX10-NEXT: v_alignbit_b32 v1, s9, s13, v4
-; GFX10-NEXT: v_alignbit_b32 v0, s8, s12, v5
-; GFX10-NEXT: global_store_dwordx4 v6, v[0:3], s[6:7]
+; GFX10-NEXT: v_mov_b32_e32 v2, s4
+; GFX10-NEXT: v_mov_b32_e32 v3, s0
+; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GFX10-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: fshr_v4i32:
-; GFX11-TRUE16: ; %bb.0: ; %entry
-; GFX11-TRUE16-NEXT: s_clause 0x2
-; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
-; GFX11-TRUE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
-; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v3, s11, s15, v0.l
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v2, s10, s14, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, s9, s13, v1.l
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s8, s12, v4.l
-; GFX11-TRUE16-NEXT: global_store_b128 v5, v[0:3], s[4:5]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: fshr_v4i32:
-; GFX11-FAKE16: ; %bb.0: ; %entry
-; GFX11-FAKE16-NEXT: s_clause 0x2
-; GFX11-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
-; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
-; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_mov_b32 s6, s15
-; GFX11-FAKE16-NEXT: s_mov_b32 s7, s11
-; GFX11-FAKE16-NEXT: s_and_b32 s11, s3, 31
-; GFX11-FAKE16-NEXT: s_mov_b32 s15, s10
-; GFX11-FAKE16-NEXT: s_and_b32 s10, s2, 31
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, s13
-; GFX11-FAKE16-NEXT: s_mov_b32 s3, s9
-; GFX11-FAKE16-NEXT: s_and_b32 s16, s1, 31
-; GFX11-FAKE16-NEXT: s_mov_b32 s13, s8
-; GFX11-FAKE16-NEXT: s_and_b32 s8, s0, 31
-; GFX11-FAKE16-NEXT: s_lshr_b64 s[0:1], s[6:7], s11
-; GFX11-FAKE16-NEXT: s_lshr_b64 s[6:7], s[14:15], s10
-; GFX11-FAKE16-NEXT: s_lshr_b64 s[8:9], s[12:13], s8
-; GFX11-FAKE16-NEXT: s_lshr_b64 s[2:3], s[2:3], s16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s6
-; GFX11-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[4:5]
-; GFX11-FAKE16-NEXT: s_endpgm
-;
-; GFX12-TRUE16-LABEL: fshr_v4i32:
-; GFX12-TRUE16: ; %bb.0: ; %entry
-; GFX12-TRUE16-NEXT: s_clause 0x2
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
-; GFX12-TRUE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
-; GFX12-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, s0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_alignbit_b32 v3, s11, s15, v0.l
-; GFX12-TRUE16-NEXT: v_alignbit_b32 v2, s10, s14, v0.h
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, s9, s13, v1.l
-; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, s8, s12, v4.l
-; GFX12-TRUE16-NEXT: global_store_b128 v5, v[0:3], s[4:5]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: fshr_v4i32:
-; GFX12-FAKE16: ; %bb.0: ; %entry
-; GFX12-FAKE16-NEXT: s_clause 0x2
-; GFX12-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
-; GFX12-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_mov_b32 s6, s15
-; GFX12-FAKE16-NEXT: s_mov_b32 s7, s11
-; GFX12-FAKE16-NEXT: s_and_b32 s11, s3, 31
-; GFX12-FAKE16-NEXT: s_mov_b32 s15, s10
-; GFX12-FAKE16-NEXT: s_and_b32 s10, s2, 31
-; GFX12-FAKE16-NEXT: s_mov_b32 s2, s13
-; GFX12-FAKE16-NEXT: s_mov_b32 s3, s9
-; GFX12-FAKE16-NEXT: s_and_b32 s16, s1, 31
-; GFX12-FAKE16-NEXT: s_mov_b32 s13, s8
-; GFX12-FAKE16-NEXT: s_and_b32 s8, s0, 31
-; GFX12-FAKE16-NEXT: s_lshr_b64 s[0:1], s[6:7], s11
-; GFX12-FAKE16-NEXT: s_lshr_b64 s[6:7], s[14:15], s10
-; GFX12-FAKE16-NEXT: s_lshr_b64 s[8:9], s[12:13], s8
-; GFX12-FAKE16-NEXT: s_lshr_b64 s[2:3], s[2:3], s16
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s2
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s0
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s6
-; GFX12-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[4:5]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: fshr_v4i32:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_clause 0x2
+; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
+; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_mov_b32 s6, s15
+; GFX11-NEXT: s_mov_b32 s7, s11
+; GFX11-NEXT: s_and_b32 s11, s3, 31
+; GFX11-NEXT: s_mov_b32 s15, s10
+; GFX11-NEXT: s_and_b32 s10, s2, 31
+; GFX11-NEXT: s_mov_b32 s2, s13
+; GFX11-NEXT: s_mov_b32 s3, s9
+; GFX11-NEXT: s_and_b32 s16, s1, 31
+; GFX11-NEXT: s_mov_b32 s13, s8
+; GFX11-NEXT: s_and_b32 s8, s0, 31
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[6:7], s11
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[14:15], s10
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[12:13], s8
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s6
+; GFX11-NEXT: global_store_b128 v4, v[0:3], s[4:5]
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fshr_v4i32:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x2
+; GFX12-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s6, s15
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_and_b32 s11, s3, 31
+; GFX12-NEXT: s_mov_b32 s15, s10
+; GFX12-NEXT: s_and_b32 s10, s2, 31
+; GFX12-NEXT: s_mov_b32 s2, s13
+; GFX12-NEXT: s_mov_b32 s3, s9
+; GFX12-NEXT: s_and_b32 s16, s1, 31
+; GFX12-NEXT: s_mov_b32 s13, s8
+; GFX12-NEXT: s_and_b32 s8, s0, 31
+; GFX12-NEXT: s_lshr_b64 s[0:1], s[6:7], s11
+; GFX12-NEXT: s_lshr_b64 s[6:7], s[14:15], s10
+; GFX12-NEXT: s_lshr_b64 s[8:9], s[12:13], s8
+; GFX12-NEXT: s_lshr_b64 s[2:3], s[2:3], s16
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s0
+; GFX12-NEXT: v_mov_b32_e32 v2, s6
+; GFX12-NEXT: global_store_b128 v4, v[0:3], s[4:5]
+; GFX12-NEXT: s_endpgm
entry:
%0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)
store <4 x i32> %0, ptr addrspace(1) %in
@@ -788,14 +909,20 @@ define amdgpu_kernel void @fshr_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v0, s15
-; GFX9-NEXT: v_mov_b32_e32 v1, s14
-; GFX9-NEXT: v_alignbit_b32 v3, s11, v0, 1
-; GFX9-NEXT: v_mov_b32_e32 v0, s13
-; GFX9-NEXT: v_alignbit_b32 v2, s10, v1, 9
-; GFX9-NEXT: v_alignbit_b32 v1, s9, v0, 7
-; GFX9-NEXT: v_mov_b32_e32 v0, s12
-; GFX9-NEXT: v_alignbit_b32 v0, s8, v0, 1
+; GFX9-NEXT: s_mov_b32 s2, s15
+; GFX9-NEXT: s_mov_b32 s3, s11
+; GFX9-NEXT: s_mov_b32 s15, s10
+; GFX9-NEXT: s_mov_b32 s6, s13
+; GFX9-NEXT: s_mov_b32 s7, s9
+; GFX9-NEXT: s_mov_b32 s13, s8
+; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GFX9-NEXT: s_lshr_b64 s[4:5], s[14:15], 9
+; GFX9-NEXT: s_lshr_b64 s[6:7], s[6:7], 7
+; GFX9-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
+; GFX9-NEXT: v_mov_b32_e32 v0, s8
+; GFX9-NEXT: v_mov_b32_e32 v1, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm
;
@@ -822,92 +949,242 @@ define amdgpu_kernel void @fshr_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_alignbit_b32 v3, s11, s15, 1
-; GFX10-NEXT: v_alignbit_b32 v2, s10, s14, 9
-; GFX10-NEXT: v_alignbit_b32 v1, s9, s13, 7
-; GFX10-NEXT: v_alignbit_b32 v0, s8, s12, 1
+; GFX10-NEXT: s_mov_b32 s2, s15
+; GFX10-NEXT: s_mov_b32 s3, s11
+; GFX10-NEXT: s_mov_b32 s15, s10
+; GFX10-NEXT: s_mov_b32 s4, s13
+; GFX10-NEXT: s_mov_b32 s5, s9
+; GFX10-NEXT: s_mov_b32 s13, s8
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GFX10-NEXT: s_lshr_b64 s[6:7], s[14:15], 9
+; GFX10-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
+; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], 7
+; GFX10-NEXT: v_mov_b32_e32 v0, s8
+; GFX10-NEXT: v_mov_b32_e32 v1, s4
+; GFX10-NEXT: v_mov_b32_e32 v2, s6
+; GFX10-NEXT: v_mov_b32_e32 v3, s2
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: fshr_v4i32_imm:
-; GFX11-TRUE16: ; %bb.0: ; %entry
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v3, s11, s15, 1
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v2, s10, s14, 9
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, s9, s13, 7
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s8, s12, 1
-; GFX11-TRUE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: fshr_v4i32_imm:
-; GFX11-FAKE16: ; %bb.0: ; %entry
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, s15
-; GFX11-FAKE16-NEXT: s_mov_b32 s3, s11
-; GFX11-FAKE16-NEXT: s_mov_b32 s15, s10
-; GFX11-FAKE16-NEXT: s_mov_b32 s4, s13
-; GFX11-FAKE16-NEXT: s_mov_b32 s5, s9
-; GFX11-FAKE16-NEXT: s_mov_b32 s13, s8
-; GFX11-FAKE16-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
-; GFX11-FAKE16-NEXT: s_lshr_b64 s[6:7], s[14:15], 9
-; GFX11-FAKE16-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
-; GFX11-FAKE16-NEXT: s_lshr_b64 s[4:5], s[4:5], 7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s2
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s6
-; GFX11-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
-;
-; GFX12-TRUE16-LABEL: fshr_v4i32_imm:
-; GFX12-TRUE16: ; %bb.0: ; %entry
-; GFX12-TRUE16-NEXT: s_clause 0x1
-; GFX12-TRUE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
-; GFX12-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_alignbit_b32 v3, s11, s15, 1
-; GFX12-TRUE16-NEXT: v_alignbit_b32 v2, s10, s14, 9
-; GFX12-TRUE16-NEXT: v_alignbit_b32 v1, s9, s13, 7
-; GFX12-TRUE16-NEXT: v_alignbit_b32 v0, s8, s12, 1
-; GFX12-TRUE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: fshr_v4i32_imm:
-; GFX12-FAKE16: ; %bb.0: ; %entry
-; GFX12-FAKE16-NEXT: s_clause 0x1
-; GFX12-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
-; GFX12-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_mov_b32 s2, s15
-; GFX12-FAKE16-NEXT: s_mov_b32 s3, s11
-; GFX12-FAKE16-NEXT: s_mov_b32 s15, s10
-; GFX12-FAKE16-NEXT: s_mov_b32 s4, s13
-; GFX12-FAKE16-NEXT: s_mov_b32 s5, s9
-; GFX12-FAKE16-NEXT: s_mov_b32 s13, s8
-; GFX12-FAKE16-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
-; GFX12-FAKE16-NEXT: s_lshr_b64 s[6:7], s[14:15], 9
-; GFX12-FAKE16-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
-; GFX12-FAKE16-NEXT: s_lshr_b64 s[4:5], s[4:5], 7
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s4
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s2
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s6
-; GFX12-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: fshr_v4i32_imm:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_mov_b32 s2, s15
+; GFX11-NEXT: s_mov_b32 s3, s11
+; GFX11-NEXT: s_mov_b32 s15, s10
+; GFX11-NEXT: s_mov_b32 s4, s13
+; GFX11-NEXT: s_mov_b32 s5, s9
+; GFX11-NEXT: s_mov_b32 s13, s8
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[14:15], 9
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
+; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], 7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s4
+; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT: v_mov_b32_e32 v2, s6
+; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fshr_v4i32_imm:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s2, s15
+; GFX12-NEXT: s_mov_b32 s3, s11
+; GFX12-NEXT: s_mov_b32 s15, s10
+; GFX12-NEXT: s_mov_b32 s4, s13
+; GFX12-NEXT: s_mov_b32 s5, s9
+; GFX12-NEXT: s_mov_b32 s13, s8
+; GFX12-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GFX12-NEXT: s_lshr_b64 s[6:7], s[14:15], 9
+; GFX12-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
+; GFX12-NEXT: s_lshr_b64 s[4:5], s[4:5], 7
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s4
+; GFX12-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s2
+; GFX12-NEXT: v_mov_b32_e32 v2, s6
+; GFX12-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX12-NEXT: s_endpgm
entry:
%0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>)
store <4 x i32> %0, ptr addrspace(1) %in
ret void
}
+define amdgpu_kernel void @fshr_v4i32_imm_src0(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y) {
+; SI-LABEL: fshr_v4i32_imm_src0:
+; SI: ; %bb.0: ; %entry
+; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s15
+; SI-NEXT: v_mov_b32_e32 v1, s14
+; SI-NEXT: v_alignbit_b32 v3, 33, s11, v0
+; SI-NEXT: v_mov_b32_e32 v0, s13
+; SI-NEXT: v_alignbit_b32 v2, 9, s10, v1
+; SI-NEXT: v_alignbit_b32 v1, 7, s9, v0
+; SI-NEXT: v_mov_b32_e32 v0, s12
+; SI-NEXT: v_alignbit_b32 v0, 1, s8, v0
+; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: fshr_v4i32_imm_src0:
+; VI: ; %bb.0: ; %entry
+; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s15
+; VI-NEXT: v_mov_b32_e32 v1, s14
+; VI-NEXT: v_mov_b32_e32 v4, s13
+; VI-NEXT: v_alignbit_b32 v3, 33, s11, v0
+; VI-NEXT: v_alignbit_b32 v2, 9, s10, v1
+; VI-NEXT: v_alignbit_b32 v1, 7, s9, v4
+; VI-NEXT: v_mov_b32_e32 v0, s12
+; VI-NEXT: v_mov_b32_e32 v5, s1
+; VI-NEXT: v_alignbit_b32 v0, 1, s8, v0
+; VI-NEXT: v_mov_b32_e32 v4, s0
+; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; VI-NEXT: s_endpgm
+;
+; GFX9-LABEL: fshr_v4i32_imm_src0:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX9-NEXT: s_mov_b32 s1, 33
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX9-NEXT: s_mov_b32 s7, 7
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_mov_b32 s0, s11
+; GFX9-NEXT: s_and_b32 s4, s15, 31
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s4
+; GFX9-NEXT: s_mov_b32 s11, 9
+; GFX9-NEXT: s_and_b32 s1, s14, 31
+; GFX9-NEXT: s_lshr_b64 s[4:5], s[10:11], s1
+; GFX9-NEXT: s_mov_b32 s6, s9
+; GFX9-NEXT: s_and_b32 s1, s13, 31
+; GFX9-NEXT: s_lshr_b64 s[6:7], s[6:7], s1
+; GFX9-NEXT: s_mov_b32 s9, 1
+; GFX9-NEXT: s_and_b32 s1, s12, 31
+; GFX9-NEXT: s_lshr_b64 s[8:9], s[8:9], s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s8
+; GFX9-NEXT: v_mov_b32_e32 v1, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_mov_b32_e32 v3, s0
+; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX9-NEXT: s_endpgm
+;
+; R600-LABEL: fshr_v4i32_imm_src0:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+; R600-NEXT: ALU clause starting at 4:
+; R600-NEXT: BIT_ALIGN_INT * T0.W, literal.x, KC0[4].X, KC0[5].X,
+; R600-NEXT: 33(4.624285e-44), 0(0.000000e+00)
+; R600-NEXT: BIT_ALIGN_INT * T0.Z, literal.x, KC0[3].W, KC0[4].W,
+; R600-NEXT: 9(1.261169e-44), 0(0.000000e+00)
+; R600-NEXT: BIT_ALIGN_INT * T0.Y, literal.x, KC0[3].Z, KC0[4].Z,
+; R600-NEXT: 7(9.809089e-45), 0(0.000000e+00)
+; R600-NEXT: BIT_ALIGN_INT * T0.X, 1, KC0[3].Y, KC0[4].Y,
+; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX10-LABEL: fshr_v4i32_imm_src0:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX10-NEXT: s_mov_b32 s1, 33
+; GFX10-NEXT: s_mov_b32 s3, 7
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: s_mov_b32 s0, s11
+; GFX10-NEXT: s_and_b32 s4, s15, 31
+; GFX10-NEXT: s_mov_b32 s11, 9
+; GFX10-NEXT: s_and_b32 s5, s14, 31
+; GFX10-NEXT: s_mov_b32 s2, s9
+; GFX10-NEXT: s_and_b32 s13, s13, 31
+; GFX10-NEXT: s_mov_b32 s9, 1
+; GFX10-NEXT: s_and_b32 s12, s12, 31
+; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s4
+; GFX10-NEXT: s_lshr_b64 s[4:5], s[10:11], s5
+; GFX10-NEXT: s_lshr_b64 s[8:9], s[8:9], s12
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s13
+; GFX10-NEXT: v_mov_b32_e32 v0, s8
+; GFX10-NEXT: v_mov_b32_e32 v1, s2
+; GFX10-NEXT: v_mov_b32_e32 v2, s4
+; GFX10-NEXT: v_mov_b32_e32 v3, s0
+; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: fshr_v4i32_imm_src0:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-NEXT: s_mov_b32 s1, 33
+; GFX11-NEXT: s_mov_b32 s3, 7
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_mov_b32 s0, s11
+; GFX11-NEXT: s_and_b32 s6, s15, 31
+; GFX11-NEXT: s_mov_b32 s11, 9
+; GFX11-NEXT: s_and_b32 s7, s14, 31
+; GFX11-NEXT: s_mov_b32 s2, s9
+; GFX11-NEXT: s_and_b32 s13, s13, 31
+; GFX11-NEXT: s_mov_b32 s9, 1
+; GFX11-NEXT: s_and_b32 s12, s12, 31
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s6
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[10:11], s7
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[8:9], s12
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s13
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s6
+; GFX11-NEXT: global_store_b128 v4, v[0:3], s[4:5]
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fshr_v4i32_imm_src0:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-NEXT: s_mov_b32 s1, 33
+; GFX12-NEXT: s_mov_b32 s3, 7
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s0, s11
+; GFX12-NEXT: s_and_b32 s6, s15, 31
+; GFX12-NEXT: s_mov_b32 s11, 9
+; GFX12-NEXT: s_and_b32 s7, s14, 31
+; GFX12-NEXT: s_mov_b32 s2, s9
+; GFX12-NEXT: s_and_b32 s13, s13, 31
+; GFX12-NEXT: s_mov_b32 s9, 1
+; GFX12-NEXT: s_and_b32 s12, s12, 31
+; GFX12-NEXT: s_lshr_b64 s[0:1], s[0:1], s6
+; GFX12-NEXT: s_lshr_b64 s[6:7], s[10:11], s7
+; GFX12-NEXT: s_lshr_b64 s[8:9], s[8:9], s12
+; GFX12-NEXT: s_lshr_b64 s[2:3], s[2:3], s13
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s0
+; GFX12-NEXT: v_mov_b32_e32 v2, s6
+; GFX12-NEXT: global_store_b128 v4, v[0:3], s[4:5]
+; GFX12-NEXT: s_endpgm
+entry:
+ %0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> <i32 1, i32 7, i32 9, i32 33>, <4 x i32> %x, <4 x i32> %y)
+ store <4 x i32> %0, ptr addrspace(1) %in
+ ret void
+}
+
define i32 @v_fshr_i32(i32 %src0, i32 %src1, i32 %src2) {
; GFX89-LABEL: v_fshr_i32:
; GFX89: ; %bb.0:
>From 418c8fbcb62c8dd9b4fa629f1c7fb78fbc0bde95 Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Tue, 4 Nov 2025 13:03:05 -0600
Subject: [PATCH 5/8] limit pattern to gfx9+; reduce multiple occurences of
same pattern
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 32 ++++++------------------
1 file changed, 8 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index f71f7ea42d48e..ad3f9d7c90b70 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2701,14 +2701,6 @@ def : GCNPat<(DivergentTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
$src2, /* clamp */ 0, /* op_sel */ 0)
>;
-def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
- (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), (S_AND_B32 $src2, (i32 31))), sub0))
->;
-
-def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, (i32 ShiftAmt32Imm:$src2)),
- (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), $src2), sub0))
->;
-
} // isGFX9GFX10
} // end True16Predicate = NotHasTrue16BitInsts
@@ -2738,14 +2730,6 @@ def : GCNPat<(DivergentTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
(EXTRACT_SUBREG VGPR_32:$src2, lo16),
/* clamp */ 0, /* op_sel */ 0)>;
-def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
- (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), (S_AND_B32 $src2, (i32 31))), sub0))
->;
-
-def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, (i32 ShiftAmt32Imm:$src2)),
- (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), $src2), sub0))
->;
-
} // end True16Predicate = UseRealTrue16Insts
let True16Predicate = UseFakeTrue16Insts in {
@@ -2782,14 +2766,6 @@ def : GCNPat<(DivergentTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
$src2, /* clamp */ 0, /* op_sel */ 0)
>;
-def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
- (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), (S_AND_B32 $src2, (i32 31))), sub0))
->;
-
-def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, (i32 ShiftAmt32Imm:$src2)),
- (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), $src2), sub0))
->;
-
} // end True16Predicate = UseFakeTrue16Insts
/********** ====================== **********/
@@ -3879,6 +3855,14 @@ class PackB32Pat<Instruction inst> : GCNPat <
>;
}
let SubtargetPredicate = isGFX9Plus in {
+ def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
+ (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), (S_AND_B32 $src2, (i32 31))), sub0))
+ >;
+
+ def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, (i32 ShiftAmt32Imm:$src2)),
+ (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), $src2), sub0))
+ >;
+
let True16Predicate = NotHasTrue16BitInsts in
def : PackB32Pat<V_PACK_B32_F16_e64>;
>From 439859611e20f780ab7633a619ecd28bf7dd07e9 Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Fri, 7 Nov 2025 15:19:31 -0600
Subject: [PATCH 6/8] enabling pattern for all archs
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 24 +-
llvm/lib/Target/AMDGPU/SOPInstructions.td | 12 -
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 24756 ++++++++--------
.../CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll | 1336 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll | 2627 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll | 216 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll | 92 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 7210 ++---
.../CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll | 662 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll | 675 +-
.../CodeGen/AMDGPU/any_extend_vector_inreg.ll | 30 +-
llvm/test/CodeGen/AMDGPU/bf16.ll | 84 +-
llvm/test/CodeGen/AMDGPU/build_vector.ll | 4 +-
.../AMDGPU/divergence-driven-buildvector.ll | 6 +-
llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll | 82 +-
llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll | 46 +-
llvm/test/CodeGen/AMDGPU/fneg.bf16.ll | 62 +-
llvm/test/CodeGen/AMDGPU/fshl.ll | 288 +-
llvm/test/CodeGen/AMDGPU/fshr.ll | 306 +-
.../CodeGen/AMDGPU/insert_vector_elt.v2i16.ll | 64 +-
llvm/test/CodeGen/AMDGPU/load-constant-i8.ll | 804 +-
llvm/test/CodeGen/AMDGPU/load-global-i8.ll | 863 +-
llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll | 8 +-
23 files changed, 21204 insertions(+), 19053 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index ad3f9d7c90b70..01c479fa1ce25 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -791,6 +791,15 @@ def : GCNPat<
(SI_CALL_ISEL $src0, (i64 0))
>;
+// Handle fshr with uniform inputs to map to scalar instructions
+def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
+ (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), (S_AND_B32 $src2, (i32 31))), sub0))
+>;
+
+def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, (i32 ShiftAmt32Imm:$src2)),
+ (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), $src2), sub0))
+>;
+
// Wrapper around s_swappc_b64 with extra $callee parameter to track
// the called function after regalloc.
def SI_CALL : SPseudoInstSI <
@@ -2694,7 +2703,7 @@ def : GCNPat<pat,
$src1, /* clamp */ 0, /* op_sel */ 0)
>;
-def : GCNPat<(DivergentTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
+def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
(V_ALIGNBIT_B32_opsel_e64 /* src0_modifiers */ 0, $src0,
/* src1_modifiers */ 0, $src1,
/* src2_modifiers */ 0,
@@ -2723,7 +2732,7 @@ def : GCNPat<(i32 (DivergentUnaryFrag<trunc> (srl i64:$src0, (i32 ShiftAmt32Imm:
(i16 (EXTRACT_SUBREG VGPR_32:$src1, lo16)),
/* clamp */ 0, /* op_sel */ 0)>;
-def : GCNPat<(DivergentTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
+def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
(V_ALIGNBIT_B32_t16_e64 /* src0_modifiers */ 0, $src0,
/* src1_modifiers */ 0, $src1,
/* src2_modifiers */ 0,
@@ -2759,7 +2768,7 @@ def : GCNPat<(i32 (DivergentUnaryFrag<trunc> (srl i64:$src0, (i32 ShiftAmt32Imm:
$src1, /* clamp */ 0, /* op_sel */ 0)
>;
-def : GCNPat<(DivergentTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
+def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
(V_ALIGNBIT_B32_fake16_e64 /* src0_modifiers */ 0, $src0,
/* src1_modifiers */ 0, $src1,
/* src2_modifiers */ 0,
@@ -3854,15 +3863,8 @@ class PackB32Pat<Instruction inst> : GCNPat <
(inst $src0_mods, VGPR_32:$src0, $src1_mods, VGPR_32:$src1)
>;
}
-let SubtargetPredicate = isGFX9Plus in {
- def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
- (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), (S_AND_B32 $src2, (i32 31))), sub0))
- >;
- def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, (i32 ShiftAmt32Imm:$src2)),
- (i32 (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), $src2), sub0))
- >;
-
+let SubtargetPredicate = isGFX9Plus in {
let True16Predicate = NotHasTrue16BitInsts in
def : PackB32Pat<V_PACK_B32_F16_e64>;
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index bc54ef847305d..337722d44f80d 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -207,18 +207,6 @@ class DivergentBinFrag<SDPatternOperator Op> : PatFrag <
let GISelPredicateCode = [{return true;}];
}
-class DivergentTernaryFrag<SDPatternOperator Op> : PatFrag <
- (ops node:$src0, node:$src1, node:$src2),
- (Op $src0, $src1, $src2),
- [{ return N->isDivergent(); }]> {
- // This check is unnecessary as it's captured by the result register
- // bank constraint.
- //
- // FIXME: Should add a way for the emitter to recognize this is a
- // trivially true predicate to eliminate the check.
- let GISelPredicateCode = [{return true;}];
-}
-
let isMoveImm = 1 in {
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
def S_MOV_B32 : SOP1_32 <"s_mov_b32">;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 74552a500ac51..3228323192059 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -23717,8 +23717,17 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a
; SI-NEXT: s_mov_b32 s72, s74
; SI-NEXT: s_mov_b32 s73, s75
; SI-NEXT: s_mov_b32 s74, s76
-; SI-NEXT: v_readlane_b32 s75, v21, 0
-; SI-NEXT: v_readlane_b32 s76, v21, 1
+; SI-NEXT: s_mov_b32 s75, s77
+; SI-NEXT: s_mov_b32 s76, s78
+; SI-NEXT: s_mov_b32 s77, s79
+; SI-NEXT: s_mov_b32 s78, s88
+; SI-NEXT: s_mov_b32 s79, s89
+; SI-NEXT: s_mov_b32 s88, s90
+; SI-NEXT: s_mov_b32 s89, s91
+; SI-NEXT: s_mov_b32 s90, s92
+; SI-NEXT: s_mov_b32 s91, s93
+; SI-NEXT: v_readlane_b32 s92, v21, 0
+; SI-NEXT: v_readlane_b32 s93, v21, 1
; SI-NEXT: s_cbranch_vccnz .LBB17_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -23780,16 +23789,16 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a
; SI-NEXT: s_lshl_b32 s62, s84, 16
; SI-NEXT: s_and_b32 s73, s83, 0xffff0000
; SI-NEXT: s_lshl_b32 s72, s83, 16
-; SI-NEXT: s_and_b32 s77, s82, 0xffff0000
+; SI-NEXT: s_and_b32 s75, s82, 0xffff0000
; SI-NEXT: s_lshl_b32 s74, s82, 16
-; SI-NEXT: s_and_b32 s79, s81, 0xffff0000
-; SI-NEXT: s_lshl_b32 s78, s81, 16
-; SI-NEXT: s_and_b32 s89, s80, 0xffff0000
-; SI-NEXT: s_lshl_b32 s88, s80, 16
-; SI-NEXT: s_and_b32 s91, s71, 0xffff0000
-; SI-NEXT: s_lshl_b32 s90, s71, 16
-; SI-NEXT: s_and_b32 s93, s70, 0xffff0000
-; SI-NEXT: s_lshl_b32 s92, s70, 16
+; SI-NEXT: s_and_b32 s77, s81, 0xffff0000
+; SI-NEXT: s_lshl_b32 s76, s81, 16
+; SI-NEXT: s_and_b32 s79, s80, 0xffff0000
+; SI-NEXT: s_lshl_b32 s78, s80, 16
+; SI-NEXT: s_and_b32 s89, s71, 0xffff0000
+; SI-NEXT: s_lshl_b32 s88, s71, 16
+; SI-NEXT: s_and_b32 s91, s70, 0xffff0000
+; SI-NEXT: s_lshl_b32 s90, s70, 16
; SI-NEXT: s_and_b32 s95, s29, 0xffff0000
; SI-NEXT: s_lshl_b32 s94, s29, 16
; SI-NEXT: s_and_b32 s31, s28, 0xffff0000
@@ -23814,8 +23823,8 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a
; SI-NEXT: s_lshl_b32 s66, s19, 16
; SI-NEXT: s_and_b32 s69, s18, 0xffff0000
; SI-NEXT: s_lshl_b32 s68, s18, 16
-; SI-NEXT: s_and_b32 s76, s17, 0xffff0000
-; SI-NEXT: s_lshl_b32 s75, s17, 16
+; SI-NEXT: s_and_b32 s93, s17, 0xffff0000
+; SI-NEXT: s_lshl_b32 s92, s17, 16
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v21, s6, 2
; SI-NEXT: s_lshl_b32 s6, s16, 16
@@ -23824,228 +23833,228 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a
; SI-NEXT: v_readlane_b32 s6, v21, 2
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6
; SI-NEXT: v_readlane_b32 s6, v21, 3
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s6
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_readlane_b32 s99, v20, 35
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s76
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s75
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s93
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s92
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s69
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s68
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s68
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s67
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s66
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s66
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s65
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s64
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s64
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s55
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s54
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s54
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s53
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s52
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s52
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s51
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s50
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s50
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s49
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s48
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s48
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s39
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s38
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s38
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s37
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s36
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s36
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s35
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s34
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s34
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s31
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s30
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s30
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s95
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s94
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s94
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s93
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s92
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s91
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s90
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s91
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s90
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s89
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s88
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s89
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s88
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s79
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s78
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s79
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s78
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s77
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s76
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s77
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s74
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s75
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s74
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s73
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s72
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s72
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s63
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s62
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s62
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s61
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s60
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s60
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s59
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s58
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s58
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s57
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s56
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s56
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s47
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s46
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s46
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s45
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s44
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s44
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s43
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s42
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s42
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s41
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s40
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s40
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s15
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s14
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s14
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s13
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s12
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s12
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s11
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s10
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s10
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s5
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s99, v20, 35
; SI-NEXT: v_readlane_b32 s98, v20, 34
; SI-NEXT: v_readlane_b32 s97, v20, 33
; SI-NEXT: v_readlane_b32 s96, v20, 32
@@ -27322,562 +27331,744 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v52, v30
-; SI-NEXT: v_mov_b32_e32 v53, v28
-; SI-NEXT: v_mov_b32_e32 v40, v12
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:40
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:68
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:68
-; SI-NEXT: v_mov_b32_e32 v55, v14
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v63, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7
+; SI-NEXT: v_mov_b32_e32 v43, v21
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_mov_b32_e32 v54, v29
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16
-; SI-NEXT: v_mul_f32_e32 v58, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v56, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v44, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v41, v23
+; SI-NEXT: v_mov_b32_e32 v29, v20
+; SI-NEXT: v_mul_f32_e32 v57, 1.0, v3
; SI-NEXT: v_mul_f32_e32 v59, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v40
-; SI-NEXT: v_mul_f32_e32 v45, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v40, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v53
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v52
+; SI-NEXT: v_mul_f32_e32 v61, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v44, 1.0, v17
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v41
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v25
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v27
+; SI-NEXT: v_mul_f32_e64 v25, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v3, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v5, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v7, 1.0, s29
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v54, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v56, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v58, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v60, 1.0, v14
+; SI-NEXT: v_mul_f32_e32 v62, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v47, 1.0, v22
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v28
+; SI-NEXT: v_mul_f32_e64 v19, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v0, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s16
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s28
+; SI-NEXT: v_mul_f32_e32 v39, 1.0, v0
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v48
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v45
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v37
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v38
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v49
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v39
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v31
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v60
-; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_mul_f32_e64 v35, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v33, 1.0, s27
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v18
+; SI-NEXT: v_mul_f32_e32 v34, 1.0, v29
+; SI-NEXT: v_mul_f32_e32 v36, 1.0, v24
+; SI-NEXT: v_mul_f32_e32 v38, 1.0, v26
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v30
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v41, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v43, 1.0, v40
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v42
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v62
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v63
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v33
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v34
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v35
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_mul_f32_e32 v42, 1.0, v36
-; SI-NEXT: v_mul_f32_e64 v12, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v34, 1.0, s24
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50
+; SI-NEXT: v_mul_f32_e32 v53, 1.0, v52
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v46
+; SI-NEXT: v_mul_f32_e64 v48, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v18, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v29, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v45, 1.0, s28
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB19_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_waitcnt expcnt(6)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v0, v3, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_alignbit_b32 v2, v2, v8, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v9, 16
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v58
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v56
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_alignbit_b32 v5, v5, v11, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v14, 16
-; SI-NEXT: v_alignbit_b32 v8, v8, v54, 16
-; SI-NEXT: v_alignbit_b32 v9, v9, v46, 16
-; SI-NEXT: v_mov_b32_e32 v62, v61
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v61
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v60, v59
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v59
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v56, v47
-; SI-NEXT: v_alignbit_b32 v13, v13, v47, 16
-; SI-NEXT: v_mov_b32_e32 v46, v45
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v45
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_alignbit_b32 v30, v30, v31, 16
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v33
-; SI-NEXT: v_alignbit_b32 v4, v4, v34, 16
-; SI-NEXT: v_mov_b32_e32 v63, v44
-; SI-NEXT: v_mov_b32_e32 v58, v57
-; SI-NEXT: v_mov_b32_e32 v44, v43
-; SI-NEXT: v_alignbit_b32 v16, v16, v43, 16
-; SI-NEXT: v_mov_b32_e32 v43, v41
-; SI-NEXT: v_alignbit_b32 v17, v17, v41, 16
-; SI-NEXT: v_alignbit_b32 v18, v18, v40, 16
-; SI-NEXT: v_mov_b32_e32 v40, v55
-; SI-NEXT: v_alignbit_b32 v19, v19, v55, 16
-; SI-NEXT: v_alignbit_b32 v20, v20, v48, 16
-; SI-NEXT: v_mov_b32_e32 v48, v53
-; SI-NEXT: v_alignbit_b32 v21, v21, v53, 16
-; SI-NEXT: v_alignbit_b32 v22, v22, v52, 16
-; SI-NEXT: v_mov_b32_e32 v52, v51
-; SI-NEXT: v_alignbit_b32 v23, v23, v51, 16
-; SI-NEXT: v_alignbit_b32 v24, v24, v50, 16
-; SI-NEXT: v_mov_b32_e32 v50, v49
-; SI-NEXT: v_alignbit_b32 v25, v25, v49, 16
-; SI-NEXT: v_mov_b32_e32 v36, v39
-; SI-NEXT: v_alignbit_b32 v26, v26, v39, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v34, v38
-; SI-NEXT: v_alignbit_b32 v27, v27, v38, 16
-; SI-NEXT: v_mov_b32_e32 v35, v37
-; SI-NEXT: v_alignbit_b32 v28, v28, v37, 16
-; SI-NEXT: v_mov_b32_e32 v37, v32
-; SI-NEXT: v_alignbit_b32 v29, v29, v32, 16
-; SI-NEXT: v_alignbit_b32 v31, v31, v42, 16
+; SI-NEXT: v_mov_b32_e32 v0, v19
+; SI-NEXT: v_mov_b32_e32 v37, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v33
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v63
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v21
; SI-NEXT: s_mov_b64 s[4:5], 0
-; SI-NEXT: v_mov_b32_e32 v32, v33
-; SI-NEXT: v_mov_b32_e32 v33, v42
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_alignbit_b32 v10, v10, v61, 16
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_alignbit_b32 v12, v12, v54, 16
-; SI-NEXT: v_mov_b32_e32 v41, v61
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_alignbit_b32 v11, v11, v59, 16
-; SI-NEXT: v_mov_b32_e32 v55, v59
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_alignbit_b32 v14, v14, v45, 16
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[0:1], v[19:20], 16
+; SI-NEXT: v_mov_b32_e32 v1, v48
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 16
+; SI-NEXT: v_mov_b32_e32 v2, v14
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v49, v15
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v3
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[2:3], v[14:15], 16
+; SI-NEXT: v_mov_b32_e32 v3, v16
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v20, v17
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v35
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[3:4], v[16:17], 16
+; SI-NEXT: v_mov_b32_e32 v4, v18
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v5
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[4:5], v[18:19], 16
+; SI-NEXT: v_mov_b32_e32 v5, v29
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[5:6], v[29:30], 16
+; SI-NEXT: v_mov_b32_e32 v6, v45
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[6:7], v[45:46], 16
+; SI-NEXT: v_mov_b32_e32 v7, v39
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[7:8], v[39:40], 16
+; SI-NEXT: v_mov_b32_e32 v8, v9
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v61
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v49
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v52
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[8:9], v[9:10], 16
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v9
+; SI-NEXT: v_mov_b32_e32 v9, v54
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[9:10], v[54:55], 16
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v55, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v10
+; SI-NEXT: v_mov_b32_e32 v10, v11
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[10:11], v[11:12], 16
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v15, v15, v47, 16
-; SI-NEXT: v_mov_b32_e32 v51, v47
-; SI-NEXT: v_mov_b32_e32 v53, v45
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v11
+; SI-NEXT: v_mov_b32_e32 v11, v56
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[11:12], v[56:57], 16
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v56, v44
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v50
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v12
+; SI-NEXT: v_lshr_b64 v[12:13], v[13:14], 16
+; SI-NEXT: v_mov_b32_e32 v13, v58
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[13:14], v[58:59], 16
+; SI-NEXT: v_mov_b32_e32 v14, v60
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[14:15], v[60:61], 16
+; SI-NEXT: v_mov_b32_e32 v15, v62
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[62:63], 16
+; SI-NEXT: v_mov_b32_e32 v16, v32
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[16:17], v[32:33], 16
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v27
+; SI-NEXT: v_mov_b32_e32 v33, v34
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v17
+; SI-NEXT: v_mov_b32_e32 v40, v17
+; SI-NEXT: v_lshr_b64 v[17:18], v[34:35], 16
+; SI-NEXT: v_lshr_b64 v[18:19], v[47:48], 16
+; SI-NEXT: v_lshr_b64 v[19:20], v[36:37], 16
+; SI-NEXT: v_mov_b32_e32 v20, v38
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[20:21], v[38:39], 16
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v34, v47
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v21
+; SI-NEXT: v_mov_b32_e32 v21, v22
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[21:22], v[22:23], 16
+; SI-NEXT: v_mov_b32_e32 v22, v31
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[22:23], v[31:32], 16
+; SI-NEXT: v_mov_b32_e32 v23, v24
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[23:24], v[24:25], 16
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v24
+; SI-NEXT: v_mov_b32_e32 v24, v41
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[24:25], v[41:42], 16
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v41, v26
+; SI-NEXT: v_mov_b32_e32 v42, v51
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v25
+; SI-NEXT: v_lshr_b64 v[25:26], v[26:27], 16
+; SI-NEXT: v_mov_b32_e32 v26, v43
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[26:27], v[43:44], 16
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v43, v28
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v27
+; SI-NEXT: v_lshr_b64 v[27:28], v[28:29], 16
+; SI-NEXT: v_lshr_b64 v[28:29], v[51:52], 16
+; SI-NEXT: v_lshr_b64 v[29:30], v[53:54], 16
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v52, v53
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v30
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshr_b64 v[30:31], v[31:32], 16
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v57
+; SI-NEXT: v_mov_b32_e32 v53, v31
+; SI-NEXT: v_lshr_b64 v[31:32], v[31:32], 16
; SI-NEXT: s_branch .LBB19_3
; SI-NEXT: .LBB19_2:
-; SI-NEXT: v_mov_b32_e32 v63, v44
-; SI-NEXT: v_mov_b32_e32 v44, v43
-; SI-NEXT: v_mov_b32_e32 v43, v41
-; SI-NEXT: v_mov_b32_e32 v40, v55
-; SI-NEXT: v_mov_b32_e32 v48, v53
-; SI-NEXT: v_mov_b32_e32 v52, v51
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v62, v61
-; SI-NEXT: v_mov_b32_e32 v60, v59
-; SI-NEXT: v_mov_b32_e32 v58, v57
-; SI-NEXT: v_mov_b32_e32 v56, v47
-; SI-NEXT: v_mov_b32_e32 v46, v45
-; SI-NEXT: v_mov_b32_e32 v50, v49
-; SI-NEXT: v_mov_b32_e32 v36, v39
+; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v56, v44
+; SI-NEXT: v_mov_b32_e32 v55, v13
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v34, v38
-; SI-NEXT: v_mov_b32_e32 v35, v37
-; SI-NEXT: v_mov_b32_e32 v37, v32
+; SI-NEXT: v_mov_b32_e32 v33, v34
+; SI-NEXT: v_mov_b32_e32 v34, v47
+; SI-NEXT: v_mov_b32_e32 v52, v53
+; SI-NEXT: v_mov_b32_e32 v53, v0
; SI-NEXT: s_mov_b64 s[4:5], -1
-; SI-NEXT: v_mov_b32_e32 v32, v33
-; SI-NEXT: v_mov_b32_e32 v33, v42
+; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_mov_b32_e32 v41, v26
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v43, v28
+; SI-NEXT: v_mov_b32_e32 v42, v51
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: .LBB19_3: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v38, v50
-; SI-NEXT: v_mov_b32_e32 v39, v52
-; SI-NEXT: v_mov_b32_e32 v49, v40
-; SI-NEXT: v_mov_b32_e32 v50, v43
-; SI-NEXT: v_mov_b32_e32 v43, v44
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mov_b32_e32 v32, v40
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v37, v34
+; SI-NEXT: v_mov_b32_e32 v34, v33
+; SI-NEXT: v_mov_b32_e32 v35, v56
; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5]
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v33, v38
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v51, v46
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v54, v46
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v44, v46
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v45, v56
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v47, v56
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v58, v60
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; SI-NEXT: s_cbranch_vccnz .LBB19_5
; SI-NEXT: ; %bb.4: ; %cmp.true
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v57
+; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v61
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v49
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v40
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v39
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v63
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v62
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v60
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v59
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v58
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v46
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v40
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v35
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v32
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v53
; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v60
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v58
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v56
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v47
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v45
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v46
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v54
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v51
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v50
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v55
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v48
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v38
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v33
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_lshr_b64 v[16:17], v[16:17], 16
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v34
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_lshr_b64 v[17:18], v[17:18], 16
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v37
; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshr_b64 v[18:19], v[18:19], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v36
; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshr_b64 v[19:20], v[19:20], 16
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshr_b64 v[20:21], v[20:21], 16
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshr_b64 v[21:22], v[21:22], 16
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshr_b64 v[22:23], v[22:23], 16
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshr_b64 v[23:24], v[23:24], 16
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshr_b64 v[24:25], v[24:25], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v41
; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshr_b64 v[25:26], v[25:26], 16
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshr_b64 v[26:27], v[26:27], 16
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v43
; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshr_b64 v[27:28], v[27:28], 16
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v42
; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshr_b64 v[28:29], v[28:29], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v52
; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v45
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v42
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v52
-; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v41
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v55
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v54
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v56
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v53
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v51
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v43
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v16, v17, v16, 16
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v50
-; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_alignbit_b32 v17, v18, v17, 16
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_alignbit_b32 v18, v19, v18, 16
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; SI-NEXT: v_alignbit_b32 v19, v20, v19, 16
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_alignbit_b32 v20, v21, v20, 16
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v48
-; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; SI-NEXT: v_alignbit_b32 v21, v22, v21, 16
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; SI-NEXT: v_alignbit_b32 v22, v23, v22, 16
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v39
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; SI-NEXT: v_alignbit_b32 v23, v24, v23, 16
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; SI-NEXT: v_alignbit_b32 v24, v25, v24, 16
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v38
-; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; SI-NEXT: v_alignbit_b32 v25, v26, v25, 16
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v36
-; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; SI-NEXT: v_alignbit_b32 v26, v27, v26, 16
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v34
-; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; SI-NEXT: v_alignbit_b32 v27, v28, v27, 16
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v35
-; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; SI-NEXT: v_alignbit_b32 v28, v29, v28, 16
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v37
; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; SI-NEXT: v_alignbit_b32 v29, v30, v29, 16
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_lshr_b64 v[29:30], v[29:30], 16
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_alignbit_b32 v30, v31, v30, 16
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v33
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; SI-NEXT: v_alignbit_b32 v31, v32, v31, 16
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v33
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_lshr_b64 v[32:33], v[32:33], 16
+; SI-NEXT: v_lshr_b64 v[30:31], v[30:31], 16
+; SI-NEXT: v_mov_b32_e32 v31, v32
; SI-NEXT: .LBB19_5: ; %end
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
@@ -27905,36 +28096,39 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_mov_b32_e32 v31, v17
; VI-NEXT: v_mov_b32_e32 v30, v16
; VI-NEXT: v_mov_b32_e32 v29, v15
-; VI-NEXT: v_mov_b32_e32 v28, v14
; VI-NEXT: v_mov_b32_e32 v27, v13
-; VI-NEXT: v_mov_b32_e32 v26, v12
; VI-NEXT: v_mov_b32_e32 v25, v11
-; VI-NEXT: v_mov_b32_e32 v24, v10
; VI-NEXT: v_mov_b32_e32 v23, v9
-; VI-NEXT: v_mov_b32_e32 v22, v8
; VI-NEXT: v_mov_b32_e32 v21, v7
-; VI-NEXT: v_mov_b32_e32 v20, v6
; VI-NEXT: v_mov_b32_e32 v19, v5
-; VI-NEXT: v_mov_b32_e32 v32, v4
; VI-NEXT: v_mov_b32_e32 v17, v3
-; VI-NEXT: v_mov_b32_e32 v16, v2
; VI-NEXT: v_mov_b32_e32 v15, v1
+; VI-NEXT: v_mov_b32_e32 v28, v14
+; VI-NEXT: v_mov_b32_e32 v26, v12
+; VI-NEXT: v_mov_b32_e32 v24, v10
+; VI-NEXT: v_mov_b32_e32 v22, v8
+; VI-NEXT: v_mov_b32_e32 v20, v6
+; VI-NEXT: v_mov_b32_e32 v32, v4
+; VI-NEXT: v_mov_b32_e32 v16, v2
; VI-NEXT: v_mov_b32_e32 v14, v0
-; VI-NEXT: v_mov_b32_e32 v0, s16
-; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-NEXT: v_mov_b32_e32 v2, s18
+; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v3, s19
-; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v5, s21
-; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v7, s23
-; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v9, s25
-; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v11, s27
-; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v13, s29
+; VI-NEXT: v_mov_b32_e32 v0, s16
+; VI-NEXT: v_mov_b32_e32 v2, s18
+; VI-NEXT: v_mov_b32_e32 v4, s20
+; VI-NEXT: v_mov_b32_e32 v6, s22
+; VI-NEXT: v_mov_b32_e32 v8, s24
+; VI-NEXT: v_mov_b32_e32 v10, s26
+; VI-NEXT: v_mov_b32_e32 v12, s28
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB19_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB19_3
@@ -27943,580 +28137,600 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v15, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v15
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
-; VI-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_alignbit_b32 v15, v15, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v15, v18, v34, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v15
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v14, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v14
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v14
+; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[33:34]
+; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_bfe_u32 v15, v14, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
-; VI-NEXT: v_cndmask_b32_e32 v14, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; VI-NEXT: v_alignbit_b32 v14, v14, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v13
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v14, v15, v18, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v14
+; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[35:36]
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v13
+; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v13, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v13
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v13
+; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
-; VI-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; VI-NEXT: v_alignbit_b32 v13, v13, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v13, v15, v18, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v12
+; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v12, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v12
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v12
+; VI-NEXT: v_lshrrev_b64 v[35:36], 16, v[35:36]
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_bfe_u32 v13, v12, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
-; VI-NEXT: v_cndmask_b32_e32 v12, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_alignbit_b32 v12, v12, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v11
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v12, v13, v15, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v12
+; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[36:37]
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v11, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v11
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v11
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
-; VI-NEXT: v_cndmask_b32_e32 v11, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; VI-NEXT: v_alignbit_b32 v11, v11, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v11, v13, v15, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v11
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v10
+; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v10, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v10
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v10
+; VI-NEXT: v_lshrrev_b64 v[36:37], 16, v[36:37]
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: v_bfe_u32 v11, v10, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
-; VI-NEXT: v_cndmask_b32_e32 v10, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_alignbit_b32 v10, v10, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v9
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v10, v11, v13, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v10
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[37:38]
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v9
+; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v9, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v9
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v9
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
-; VI-NEXT: v_cndmask_b32_e32 v9, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_alignbit_b32 v9, v9, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v8
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v8
+; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v8, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v8
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v8
+; VI-NEXT: v_lshrrev_b64 v[37:38], 16, v[37:38]
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
-; VI-NEXT: v_cndmask_b32_e32 v8, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_alignbit_b32 v8, v8, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v7
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[38:39]
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v7
+; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v7, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v7
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v7
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; VI-NEXT: v_cndmask_b32_e32 v7, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_alignbit_b32 v7, v7, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v6, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v6
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v6
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_bfe_u32 v7, v6, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
-; VI-NEXT: v_cndmask_b32_e32 v6, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_alignbit_b32 v6, v6, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v6, v7, v9, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[48:49]
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v5, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v5
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v5
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: v_cndmask_b32_e32 v5, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_alignbit_b32 v5, v5, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v4
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v4
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v4
+; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[48:49]
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_alignbit_b32 v4, v4, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v3
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v4
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[49:50]
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v3
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v3
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v3, v3, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v2
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v2
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v2
+; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50]
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_alignbit_b32 v2, v2, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v1
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v2
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[50:51]
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v1
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_alignbit_b32 v1, v1, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v0
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0
+; VI-NEXT: v_lshrrev_b64 v[50:51], 16, v[50:51]
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v31
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v31, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v31
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v31
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
-; VI-NEXT: v_cndmask_b32_e32 v31, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_alignbit_b32 v31, v31, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v30
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v30, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v30
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v30
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
-; VI-NEXT: v_cndmask_b32_e32 v30, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_alignbit_b32 v30, v30, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v29
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v29, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v29
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v29
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
-; VI-NEXT: v_cndmask_b32_e32 v29, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_alignbit_b32 v29, v29, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v28
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v28, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v28
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v28
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
-; VI-NEXT: v_cndmask_b32_e32 v28, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_alignbit_b32 v28, v28, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v27
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v27, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v27
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v27
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
-; VI-NEXT: v_cndmask_b32_e32 v27, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; VI-NEXT: v_alignbit_b32 v27, v27, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v26
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v26, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v26
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v26
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
-; VI-NEXT: v_cndmask_b32_e32 v26, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_alignbit_b32 v26, v26, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v25, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v25
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v25
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
-; VI-NEXT: v_cndmask_b32_e32 v25, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; VI-NEXT: v_alignbit_b32 v25, v25, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v24
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v24, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v24
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v24
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
-; VI-NEXT: v_cndmask_b32_e32 v24, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_alignbit_b32 v24, v24, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v23
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v23, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v23
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v23
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
-; VI-NEXT: v_cndmask_b32_e32 v23, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_alignbit_b32 v23, v23, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v22
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v22, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v22
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v22
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
-; VI-NEXT: v_cndmask_b32_e32 v22, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_alignbit_b32 v22, v22, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v21
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v21, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v21
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v21
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
-; VI-NEXT: v_cndmask_b32_e32 v21, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_alignbit_b32 v21, v21, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v20
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v20, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v20
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v20
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
-; VI-NEXT: v_cndmask_b32_e32 v20, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_alignbit_b32 v20, v20, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v19, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v19
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v19
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
-; VI-NEXT: v_cndmask_b32_e32 v19, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_alignbit_b32 v19, v19, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v32
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
-; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; VI-NEXT: v_alignbit_b32 v32, v32, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v17
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v17, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v17
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v17
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
-; VI-NEXT: v_cndmask_b32_e32 v17, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_alignbit_b32 v17, v17, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v16
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v16
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_cndmask_b32_e32 v16, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_alignbit_b32 v16, v16, v18, 16
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v0
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[51:52]
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v31
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v30
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v30
+; VI-NEXT: v_lshrrev_b64 v[51:52], 16, v[51:52]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v29
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v29
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[30:31], 16, v[52:53]
+; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v28
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
+; VI-NEXT: v_lshrrev_b64 v[52:53], 16, v[52:53]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v27
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v27
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[28:29], 16, v[53:54]
+; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v26
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v26
+; VI-NEXT: v_lshrrev_b64 v[53:54], 16, v[53:54]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v25
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[26:27], 16, v[54:55]
+; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v24
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v24
+; VI-NEXT: v_lshrrev_b64 v[38:39], 16, v[38:39]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v23
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v23
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[24:25], 16, v[39:40]
+; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v22
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
+; VI-NEXT: v_lshrrev_b64 v[39:40], 16, v[39:40]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v21
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[22:23], 16, v[40:41]
+; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v20
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v20
+; VI-NEXT: v_lshrrev_b64 v[40:41], 16, v[40:41]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v19
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v18, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v32
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v31, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v17
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v17
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[41:42]
+; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v16
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v15, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b64 v[54:55], 16, v[54:55]
+; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19]
+; VI-NEXT: v_lshrrev_b64 v[41:42], 16, v[41:42]
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[31:32]
+; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[15:16]
+; VI-NEXT: v_mov_b32_e32 v1, v50
+; VI-NEXT: v_mov_b32_e32 v3, v49
+; VI-NEXT: v_mov_b32_e32 v5, v48
+; VI-NEXT: v_mov_b32_e32 v7, v38
+; VI-NEXT: v_mov_b32_e32 v9, v37
+; VI-NEXT: v_mov_b32_e32 v11, v36
+; VI-NEXT: v_mov_b32_e32 v13, v35
+; VI-NEXT: v_mov_b32_e32 v15, v34
+; VI-NEXT: v_mov_b32_e32 v17, v41
+; VI-NEXT: v_mov_b32_e32 v19, v18
+; VI-NEXT: v_mov_b32_e32 v21, v40
+; VI-NEXT: v_mov_b32_e32 v23, v39
+; VI-NEXT: v_mov_b32_e32 v25, v54
+; VI-NEXT: v_mov_b32_e32 v27, v53
+; VI-NEXT: v_mov_b32_e32 v29, v52
+; VI-NEXT: v_mov_b32_e32 v31, v51
; VI-NEXT: .LBB19_3: ; %end
+; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v18, v32
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB19_4:
; VI-NEXT: s_branch .LBB19_2
@@ -61932,214 +62146,213 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
; SI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v61
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v61
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v60
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v59
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v59
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v58
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v57
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v57
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v56
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v47
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v47
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v46
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v45
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v45
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v44
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v43
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v42
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v41
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v41
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v40
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v55
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v55
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v53
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v53
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v52
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v51
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v51
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v50
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v49
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v39
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v37
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v35
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v33
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v31
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v31
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v30
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v29
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v29
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v28
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v27
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v27
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v26
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v25
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v25
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v24
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v23
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v23
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v22
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v21
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v20
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v19
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v19
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v18
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v17
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v17
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v15
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v14
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v13
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v13
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v11
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v5
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: v_readlane_b32 s99, v63, 35
; SI-NEXT: v_readlane_b32 s98, v63, 34
; SI-NEXT: v_readlane_b32 s97, v63, 33
@@ -62176,22 +62389,23 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg
; SI-NEXT: v_readlane_b32 s34, v63, 2
; SI-NEXT: v_readlane_b32 s31, v63, 1
; SI-NEXT: v_readlane_b32 s30, v63, 0
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -65432,562 +65646,744 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v52, v30
-; SI-NEXT: v_mov_b32_e32 v53, v28
-; SI-NEXT: v_mov_b32_e32 v40, v12
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:40
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:68
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:68
-; SI-NEXT: v_mov_b32_e32 v55, v14
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v63, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7
+; SI-NEXT: v_mov_b32_e32 v43, v21
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_mov_b32_e32 v54, v29
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16
-; SI-NEXT: v_mul_f32_e32 v58, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v56, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v44, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v41, v23
+; SI-NEXT: v_mov_b32_e32 v29, v20
+; SI-NEXT: v_mul_f32_e32 v57, 1.0, v3
; SI-NEXT: v_mul_f32_e32 v59, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v40
-; SI-NEXT: v_mul_f32_e32 v45, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v40, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v53
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v52
+; SI-NEXT: v_mul_f32_e32 v61, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v44, 1.0, v17
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v41
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v25
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v27
+; SI-NEXT: v_mul_f32_e64 v25, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v3, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v5, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v7, 1.0, s29
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v54, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v56, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v58, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v60, 1.0, v14
+; SI-NEXT: v_mul_f32_e32 v62, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v47, 1.0, v22
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v28
+; SI-NEXT: v_mul_f32_e64 v19, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v0, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s16
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s28
+; SI-NEXT: v_mul_f32_e32 v39, 1.0, v0
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v48
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v45
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v37
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v38
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v49
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v39
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v31
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v60
-; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_mul_f32_e64 v35, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v33, 1.0, s27
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v18
+; SI-NEXT: v_mul_f32_e32 v34, 1.0, v29
+; SI-NEXT: v_mul_f32_e32 v36, 1.0, v24
+; SI-NEXT: v_mul_f32_e32 v38, 1.0, v26
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v30
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v41, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v43, 1.0, v40
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v42
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v62
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v63
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v33
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v34
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v35
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_mul_f32_e32 v42, 1.0, v36
-; SI-NEXT: v_mul_f32_e64 v12, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v34, 1.0, s24
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50
+; SI-NEXT: v_mul_f32_e32 v53, 1.0, v52
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v46
+; SI-NEXT: v_mul_f32_e64 v48, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v18, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v29, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v45, 1.0, s28
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB43_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_waitcnt expcnt(6)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v0, v3, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_alignbit_b32 v2, v2, v8, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v9, 16
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v58
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v56
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_alignbit_b32 v5, v5, v11, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v14, 16
-; SI-NEXT: v_alignbit_b32 v8, v8, v54, 16
-; SI-NEXT: v_alignbit_b32 v9, v9, v46, 16
-; SI-NEXT: v_mov_b32_e32 v62, v61
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v61
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v60, v59
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v59
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v56, v47
-; SI-NEXT: v_alignbit_b32 v13, v13, v47, 16
-; SI-NEXT: v_mov_b32_e32 v46, v45
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v45
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_alignbit_b32 v30, v30, v31, 16
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v33
-; SI-NEXT: v_alignbit_b32 v4, v4, v34, 16
-; SI-NEXT: v_mov_b32_e32 v63, v44
-; SI-NEXT: v_mov_b32_e32 v58, v57
-; SI-NEXT: v_mov_b32_e32 v44, v43
-; SI-NEXT: v_alignbit_b32 v16, v16, v43, 16
-; SI-NEXT: v_mov_b32_e32 v43, v41
-; SI-NEXT: v_alignbit_b32 v17, v17, v41, 16
-; SI-NEXT: v_alignbit_b32 v18, v18, v40, 16
-; SI-NEXT: v_mov_b32_e32 v40, v55
-; SI-NEXT: v_alignbit_b32 v19, v19, v55, 16
-; SI-NEXT: v_alignbit_b32 v20, v20, v48, 16
-; SI-NEXT: v_mov_b32_e32 v48, v53
-; SI-NEXT: v_alignbit_b32 v21, v21, v53, 16
-; SI-NEXT: v_alignbit_b32 v22, v22, v52, 16
-; SI-NEXT: v_mov_b32_e32 v52, v51
-; SI-NEXT: v_alignbit_b32 v23, v23, v51, 16
-; SI-NEXT: v_alignbit_b32 v24, v24, v50, 16
-; SI-NEXT: v_mov_b32_e32 v50, v49
-; SI-NEXT: v_alignbit_b32 v25, v25, v49, 16
-; SI-NEXT: v_mov_b32_e32 v36, v39
-; SI-NEXT: v_alignbit_b32 v26, v26, v39, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v34, v38
-; SI-NEXT: v_alignbit_b32 v27, v27, v38, 16
-; SI-NEXT: v_mov_b32_e32 v35, v37
-; SI-NEXT: v_alignbit_b32 v28, v28, v37, 16
-; SI-NEXT: v_mov_b32_e32 v37, v32
-; SI-NEXT: v_alignbit_b32 v29, v29, v32, 16
-; SI-NEXT: v_alignbit_b32 v31, v31, v42, 16
+; SI-NEXT: v_mov_b32_e32 v0, v19
+; SI-NEXT: v_mov_b32_e32 v37, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v33
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v63
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v21
; SI-NEXT: s_mov_b64 s[4:5], 0
-; SI-NEXT: v_mov_b32_e32 v32, v33
-; SI-NEXT: v_mov_b32_e32 v33, v42
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_alignbit_b32 v10, v10, v61, 16
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_alignbit_b32 v12, v12, v54, 16
-; SI-NEXT: v_mov_b32_e32 v41, v61
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_alignbit_b32 v11, v11, v59, 16
-; SI-NEXT: v_mov_b32_e32 v55, v59
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_alignbit_b32 v14, v14, v45, 16
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[0:1], v[19:20], 16
+; SI-NEXT: v_mov_b32_e32 v1, v48
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 16
+; SI-NEXT: v_mov_b32_e32 v2, v14
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v49, v15
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v3
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[2:3], v[14:15], 16
+; SI-NEXT: v_mov_b32_e32 v3, v16
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v20, v17
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v35
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[3:4], v[16:17], 16
+; SI-NEXT: v_mov_b32_e32 v4, v18
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v5
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[4:5], v[18:19], 16
+; SI-NEXT: v_mov_b32_e32 v5, v29
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[5:6], v[29:30], 16
+; SI-NEXT: v_mov_b32_e32 v6, v45
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[6:7], v[45:46], 16
+; SI-NEXT: v_mov_b32_e32 v7, v39
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[7:8], v[39:40], 16
+; SI-NEXT: v_mov_b32_e32 v8, v9
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v61
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v49
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v52
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[8:9], v[9:10], 16
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v9
+; SI-NEXT: v_mov_b32_e32 v9, v54
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[9:10], v[54:55], 16
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v55, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v15, v15, v47, 16
-; SI-NEXT: v_mov_b32_e32 v51, v47
-; SI-NEXT: v_mov_b32_e32 v53, v45
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v10
+; SI-NEXT: v_mov_b32_e32 v10, v11
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[10:11], v[11:12], 16
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v11
+; SI-NEXT: v_mov_b32_e32 v11, v56
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[11:12], v[56:57], 16
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v56, v44
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v50
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v12
+; SI-NEXT: v_lshr_b64 v[12:13], v[13:14], 16
+; SI-NEXT: v_mov_b32_e32 v13, v58
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[13:14], v[58:59], 16
+; SI-NEXT: v_mov_b32_e32 v14, v60
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[14:15], v[60:61], 16
+; SI-NEXT: v_mov_b32_e32 v15, v62
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[62:63], 16
+; SI-NEXT: v_mov_b32_e32 v16, v32
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[16:17], v[32:33], 16
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v27
+; SI-NEXT: v_mov_b32_e32 v33, v34
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v17
+; SI-NEXT: v_mov_b32_e32 v40, v17
+; SI-NEXT: v_lshr_b64 v[17:18], v[34:35], 16
+; SI-NEXT: v_lshr_b64 v[18:19], v[47:48], 16
+; SI-NEXT: v_lshr_b64 v[19:20], v[36:37], 16
+; SI-NEXT: v_mov_b32_e32 v20, v38
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[20:21], v[38:39], 16
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v34, v47
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v21
+; SI-NEXT: v_mov_b32_e32 v21, v22
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[21:22], v[22:23], 16
+; SI-NEXT: v_mov_b32_e32 v22, v31
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[22:23], v[31:32], 16
+; SI-NEXT: v_mov_b32_e32 v23, v24
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[23:24], v[24:25], 16
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v24
+; SI-NEXT: v_mov_b32_e32 v24, v41
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[24:25], v[41:42], 16
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v41, v26
+; SI-NEXT: v_mov_b32_e32 v42, v51
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v25
+; SI-NEXT: v_lshr_b64 v[25:26], v[26:27], 16
+; SI-NEXT: v_mov_b32_e32 v26, v43
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[26:27], v[43:44], 16
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v43, v28
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v27
+; SI-NEXT: v_lshr_b64 v[27:28], v[28:29], 16
+; SI-NEXT: v_lshr_b64 v[28:29], v[51:52], 16
+; SI-NEXT: v_lshr_b64 v[29:30], v[53:54], 16
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v52, v53
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v30
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshr_b64 v[30:31], v[31:32], 16
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v57
+; SI-NEXT: v_mov_b32_e32 v53, v31
+; SI-NEXT: v_lshr_b64 v[31:32], v[31:32], 16
; SI-NEXT: s_branch .LBB43_3
; SI-NEXT: .LBB43_2:
-; SI-NEXT: v_mov_b32_e32 v63, v44
-; SI-NEXT: v_mov_b32_e32 v44, v43
-; SI-NEXT: v_mov_b32_e32 v43, v41
-; SI-NEXT: v_mov_b32_e32 v40, v55
-; SI-NEXT: v_mov_b32_e32 v48, v53
-; SI-NEXT: v_mov_b32_e32 v52, v51
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v62, v61
-; SI-NEXT: v_mov_b32_e32 v60, v59
-; SI-NEXT: v_mov_b32_e32 v58, v57
-; SI-NEXT: v_mov_b32_e32 v56, v47
-; SI-NEXT: v_mov_b32_e32 v46, v45
-; SI-NEXT: v_mov_b32_e32 v50, v49
-; SI-NEXT: v_mov_b32_e32 v36, v39
+; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v56, v44
+; SI-NEXT: v_mov_b32_e32 v55, v13
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v34, v38
-; SI-NEXT: v_mov_b32_e32 v35, v37
-; SI-NEXT: v_mov_b32_e32 v37, v32
+; SI-NEXT: v_mov_b32_e32 v33, v34
+; SI-NEXT: v_mov_b32_e32 v34, v47
+; SI-NEXT: v_mov_b32_e32 v52, v53
+; SI-NEXT: v_mov_b32_e32 v53, v0
; SI-NEXT: s_mov_b64 s[4:5], -1
-; SI-NEXT: v_mov_b32_e32 v32, v33
-; SI-NEXT: v_mov_b32_e32 v33, v42
+; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_mov_b32_e32 v41, v26
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v43, v28
+; SI-NEXT: v_mov_b32_e32 v42, v51
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: .LBB43_3: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v38, v50
-; SI-NEXT: v_mov_b32_e32 v39, v52
-; SI-NEXT: v_mov_b32_e32 v49, v40
-; SI-NEXT: v_mov_b32_e32 v50, v43
-; SI-NEXT: v_mov_b32_e32 v43, v44
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mov_b32_e32 v32, v40
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v37, v34
+; SI-NEXT: v_mov_b32_e32 v34, v33
+; SI-NEXT: v_mov_b32_e32 v35, v56
; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5]
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v33, v38
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v51, v46
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v54, v46
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v44, v46
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v45, v56
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v47, v56
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v58, v60
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; SI-NEXT: s_cbranch_vccnz .LBB43_5
; SI-NEXT: ; %bb.4: ; %cmp.true
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v57
+; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v61
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v49
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v40
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v39
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v63
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v62
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v60
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v59
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v58
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v46
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v40
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v35
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v32
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v53
; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v60
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v58
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v56
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v47
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v45
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v46
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v54
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v51
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v50
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v55
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v48
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v38
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v33
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_lshr_b64 v[16:17], v[16:17], 16
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v34
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_lshr_b64 v[17:18], v[17:18], 16
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v37
; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshr_b64 v[18:19], v[18:19], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v36
; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshr_b64 v[19:20], v[19:20], 16
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshr_b64 v[20:21], v[20:21], 16
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshr_b64 v[21:22], v[21:22], 16
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshr_b64 v[22:23], v[22:23], 16
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshr_b64 v[23:24], v[23:24], 16
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshr_b64 v[24:25], v[24:25], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v41
; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshr_b64 v[25:26], v[25:26], 16
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshr_b64 v[26:27], v[26:27], 16
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v43
; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshr_b64 v[27:28], v[27:28], 16
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v42
; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshr_b64 v[28:29], v[28:29], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v52
; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v45
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v42
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v52
-; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v41
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v55
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v54
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v56
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v53
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v51
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v43
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v16, v17, v16, 16
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v50
-; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_alignbit_b32 v17, v18, v17, 16
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_alignbit_b32 v18, v19, v18, 16
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; SI-NEXT: v_alignbit_b32 v19, v20, v19, 16
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_alignbit_b32 v20, v21, v20, 16
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v48
-; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; SI-NEXT: v_alignbit_b32 v21, v22, v21, 16
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; SI-NEXT: v_alignbit_b32 v22, v23, v22, 16
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v39
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; SI-NEXT: v_alignbit_b32 v23, v24, v23, 16
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; SI-NEXT: v_alignbit_b32 v24, v25, v24, 16
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v38
-; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; SI-NEXT: v_alignbit_b32 v25, v26, v25, 16
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v36
-; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; SI-NEXT: v_alignbit_b32 v26, v27, v26, 16
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v34
-; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; SI-NEXT: v_alignbit_b32 v27, v28, v27, 16
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v35
-; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; SI-NEXT: v_alignbit_b32 v28, v29, v28, 16
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v37
; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; SI-NEXT: v_alignbit_b32 v29, v30, v29, 16
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_lshr_b64 v[29:30], v[29:30], 16
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_alignbit_b32 v30, v31, v30, 16
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v33
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; SI-NEXT: v_alignbit_b32 v31, v32, v31, 16
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v33
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_lshr_b64 v[32:33], v[32:33], 16
+; SI-NEXT: v_lshr_b64 v[30:31], v[30:31], 16
+; SI-NEXT: v_mov_b32_e32 v31, v32
; SI-NEXT: .LBB43_5: ; %end
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
@@ -66015,36 +66411,39 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; VI-NEXT: v_mov_b32_e32 v31, v17
; VI-NEXT: v_mov_b32_e32 v30, v16
; VI-NEXT: v_mov_b32_e32 v29, v15
-; VI-NEXT: v_mov_b32_e32 v28, v14
; VI-NEXT: v_mov_b32_e32 v27, v13
-; VI-NEXT: v_mov_b32_e32 v26, v12
; VI-NEXT: v_mov_b32_e32 v25, v11
-; VI-NEXT: v_mov_b32_e32 v24, v10
; VI-NEXT: v_mov_b32_e32 v23, v9
-; VI-NEXT: v_mov_b32_e32 v22, v8
; VI-NEXT: v_mov_b32_e32 v21, v7
-; VI-NEXT: v_mov_b32_e32 v20, v6
; VI-NEXT: v_mov_b32_e32 v19, v5
-; VI-NEXT: v_mov_b32_e32 v32, v4
; VI-NEXT: v_mov_b32_e32 v17, v3
-; VI-NEXT: v_mov_b32_e32 v16, v2
; VI-NEXT: v_mov_b32_e32 v15, v1
+; VI-NEXT: v_mov_b32_e32 v28, v14
+; VI-NEXT: v_mov_b32_e32 v26, v12
+; VI-NEXT: v_mov_b32_e32 v24, v10
+; VI-NEXT: v_mov_b32_e32 v22, v8
+; VI-NEXT: v_mov_b32_e32 v20, v6
+; VI-NEXT: v_mov_b32_e32 v32, v4
+; VI-NEXT: v_mov_b32_e32 v16, v2
; VI-NEXT: v_mov_b32_e32 v14, v0
-; VI-NEXT: v_mov_b32_e32 v0, s16
-; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-NEXT: v_mov_b32_e32 v2, s18
+; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v3, s19
-; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v5, s21
-; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v7, s23
-; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v9, s25
-; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v11, s27
-; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v13, s29
+; VI-NEXT: v_mov_b32_e32 v0, s16
+; VI-NEXT: v_mov_b32_e32 v2, s18
+; VI-NEXT: v_mov_b32_e32 v4, s20
+; VI-NEXT: v_mov_b32_e32 v6, s22
+; VI-NEXT: v_mov_b32_e32 v8, s24
+; VI-NEXT: v_mov_b32_e32 v10, s26
+; VI-NEXT: v_mov_b32_e32 v12, s28
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB43_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB43_3
@@ -66053,580 +66452,600 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v15, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v15
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
-; VI-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_alignbit_b32 v15, v15, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v15, v18, v34, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v15
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v14, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v14
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v14
+; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[33:34]
+; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_bfe_u32 v15, v14, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
-; VI-NEXT: v_cndmask_b32_e32 v14, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; VI-NEXT: v_alignbit_b32 v14, v14, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v13
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v14, v15, v18, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v14
+; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[35:36]
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v13
+; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v13, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v13
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v13
+; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
-; VI-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; VI-NEXT: v_alignbit_b32 v13, v13, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v13, v15, v18, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v12
+; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v12, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v12
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v12
+; VI-NEXT: v_lshrrev_b64 v[35:36], 16, v[35:36]
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_bfe_u32 v13, v12, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
-; VI-NEXT: v_cndmask_b32_e32 v12, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_alignbit_b32 v12, v12, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v11
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v12, v13, v15, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v12
+; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[36:37]
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v11, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v11
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v11
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
-; VI-NEXT: v_cndmask_b32_e32 v11, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; VI-NEXT: v_alignbit_b32 v11, v11, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v11, v13, v15, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v11
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v10
+; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v10, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v10
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v10
+; VI-NEXT: v_lshrrev_b64 v[36:37], 16, v[36:37]
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: v_bfe_u32 v11, v10, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
-; VI-NEXT: v_cndmask_b32_e32 v10, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_alignbit_b32 v10, v10, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v9
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v10, v11, v13, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v10
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[37:38]
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v9
+; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v9, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v9
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v9
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
-; VI-NEXT: v_cndmask_b32_e32 v9, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_alignbit_b32 v9, v9, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v8
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v8
+; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v8, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v8
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v8
+; VI-NEXT: v_lshrrev_b64 v[37:38], 16, v[37:38]
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
-; VI-NEXT: v_cndmask_b32_e32 v8, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_alignbit_b32 v8, v8, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v7
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[38:39]
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v7
+; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v7, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v7
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v7
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; VI-NEXT: v_cndmask_b32_e32 v7, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_alignbit_b32 v7, v7, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v6, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v6
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v6
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_bfe_u32 v7, v6, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
-; VI-NEXT: v_cndmask_b32_e32 v6, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_alignbit_b32 v6, v6, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v6, v7, v9, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[48:49]
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v5, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v5
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v5
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: v_cndmask_b32_e32 v5, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_alignbit_b32 v5, v5, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v4
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v4
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v4
+; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[48:49]
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_alignbit_b32 v4, v4, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v3
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v4
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[49:50]
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v3
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v3
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v3, v3, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v2
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v2
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v2
+; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50]
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_alignbit_b32 v2, v2, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v1
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v2
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[50:51]
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v1
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_alignbit_b32 v1, v1, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v0
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0
+; VI-NEXT: v_lshrrev_b64 v[50:51], 16, v[50:51]
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v31
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v31, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v31
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v31
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
-; VI-NEXT: v_cndmask_b32_e32 v31, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_alignbit_b32 v31, v31, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v30
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v30, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v30
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v30
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
-; VI-NEXT: v_cndmask_b32_e32 v30, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_alignbit_b32 v30, v30, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v29
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v29, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v29
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v29
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
-; VI-NEXT: v_cndmask_b32_e32 v29, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_alignbit_b32 v29, v29, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v28
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v28, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v28
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v28
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
-; VI-NEXT: v_cndmask_b32_e32 v28, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_alignbit_b32 v28, v28, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v27
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v27, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v27
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v27
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
-; VI-NEXT: v_cndmask_b32_e32 v27, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; VI-NEXT: v_alignbit_b32 v27, v27, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v26
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v26, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v26
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v26
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
-; VI-NEXT: v_cndmask_b32_e32 v26, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_alignbit_b32 v26, v26, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v25, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v25
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v25
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
-; VI-NEXT: v_cndmask_b32_e32 v25, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; VI-NEXT: v_alignbit_b32 v25, v25, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v24
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v24, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v24
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v24
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
-; VI-NEXT: v_cndmask_b32_e32 v24, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_alignbit_b32 v24, v24, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v23
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v23, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v23
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v23
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
-; VI-NEXT: v_cndmask_b32_e32 v23, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_alignbit_b32 v23, v23, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v22
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v22, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v22
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v22
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
-; VI-NEXT: v_cndmask_b32_e32 v22, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_alignbit_b32 v22, v22, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v21
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v21, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v21
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v21
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
-; VI-NEXT: v_cndmask_b32_e32 v21, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_alignbit_b32 v21, v21, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v20
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v20, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v20
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v20
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
-; VI-NEXT: v_cndmask_b32_e32 v20, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_alignbit_b32 v20, v20, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v19, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v19
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v19
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
-; VI-NEXT: v_cndmask_b32_e32 v19, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_alignbit_b32 v19, v19, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v32
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
-; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; VI-NEXT: v_alignbit_b32 v32, v32, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v17
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v17, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v17
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v17
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
-; VI-NEXT: v_cndmask_b32_e32 v17, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_alignbit_b32 v17, v17, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v16
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v16
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_cndmask_b32_e32 v16, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_alignbit_b32 v16, v16, v18, 16
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v0
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[51:52]
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v31
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v30
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v30
+; VI-NEXT: v_lshrrev_b64 v[51:52], 16, v[51:52]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v29
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v29
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[30:31], 16, v[52:53]
+; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v28
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
+; VI-NEXT: v_lshrrev_b64 v[52:53], 16, v[52:53]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v27
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v27
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[28:29], 16, v[53:54]
+; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v26
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v26
+; VI-NEXT: v_lshrrev_b64 v[53:54], 16, v[53:54]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v25
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[26:27], 16, v[54:55]
+; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v24
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v24
+; VI-NEXT: v_lshrrev_b64 v[38:39], 16, v[38:39]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v23
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v23
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[24:25], 16, v[39:40]
+; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v22
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
+; VI-NEXT: v_lshrrev_b64 v[39:40], 16, v[39:40]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v21
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[22:23], 16, v[40:41]
+; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v20
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v20
+; VI-NEXT: v_lshrrev_b64 v[40:41], 16, v[40:41]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v19
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v18, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v32
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v31, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v17
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v17
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[41:42]
+; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v16
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v15, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b64 v[54:55], 16, v[54:55]
+; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19]
+; VI-NEXT: v_lshrrev_b64 v[41:42], 16, v[41:42]
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[31:32]
+; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[15:16]
+; VI-NEXT: v_mov_b32_e32 v1, v50
+; VI-NEXT: v_mov_b32_e32 v3, v49
+; VI-NEXT: v_mov_b32_e32 v5, v48
+; VI-NEXT: v_mov_b32_e32 v7, v38
+; VI-NEXT: v_mov_b32_e32 v9, v37
+; VI-NEXT: v_mov_b32_e32 v11, v36
+; VI-NEXT: v_mov_b32_e32 v13, v35
+; VI-NEXT: v_mov_b32_e32 v15, v34
+; VI-NEXT: v_mov_b32_e32 v17, v41
+; VI-NEXT: v_mov_b32_e32 v19, v18
+; VI-NEXT: v_mov_b32_e32 v21, v40
+; VI-NEXT: v_mov_b32_e32 v23, v39
+; VI-NEXT: v_mov_b32_e32 v25, v54
+; VI-NEXT: v_mov_b32_e32 v27, v53
+; VI-NEXT: v_mov_b32_e32 v29, v52
+; VI-NEXT: v_mov_b32_e32 v31, v51
; VI-NEXT: .LBB43_3: ; %end
+; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v18, v32
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB43_4:
; VI-NEXT: s_branch .LBB43_2
@@ -97697,229 +98116,229 @@ define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a
; SI-NEXT: v_writelane_b32 v21, s8, 3
; SI-NEXT: .LBB61_3: ; %end
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s69
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s68
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s68
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_readlane_b32 s4, v21, 2
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s67
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s66
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s66
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s65
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s64
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s64
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s55
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s54
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s54
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s53
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s52
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s52
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s51
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s50
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s50
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s49
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s48
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s48
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s39
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s38
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s38
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s37
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s36
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s36
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s35
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s34
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s34
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s31
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s30
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s30
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s95
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s94
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s94
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s93
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s92
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s92
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s91
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s90
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s90
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s89
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s88
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s88
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s79
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s78
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s78
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s77
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s76
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s76
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s75
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s74
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s74
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s73
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s72
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s72
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s63
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s62
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s62
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s61
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s60
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s60
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s59
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s58
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s58
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s57
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s56
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s56
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s47
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s46
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s46
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s45
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s44
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s44
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s43
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s42
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s42
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s41
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s40
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s40
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s15
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s14
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s14
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s13
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s12
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s12
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s11
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s10
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s10
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0
-; SI-NEXT: v_readlane_b32 s4, v21, 2
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
; SI-NEXT: v_readlane_b32 s4, v21, 3
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0
; SI-NEXT: v_readlane_b32 s4, v21, 0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
; SI-NEXT: v_readlane_b32 s4, v21, 1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: v_readlane_b32 s99, v20, 35
@@ -101277,562 +101696,744 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v52, v30
-; SI-NEXT: v_mov_b32_e32 v53, v28
-; SI-NEXT: v_mov_b32_e32 v40, v12
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:40
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:68
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:68
-; SI-NEXT: v_mov_b32_e32 v55, v14
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v63, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7
+; SI-NEXT: v_mov_b32_e32 v43, v21
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_mov_b32_e32 v54, v29
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16
-; SI-NEXT: v_mul_f32_e32 v58, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v56, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v44, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v41, v23
+; SI-NEXT: v_mov_b32_e32 v29, v20
+; SI-NEXT: v_mul_f32_e32 v57, 1.0, v3
; SI-NEXT: v_mul_f32_e32 v59, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v40
-; SI-NEXT: v_mul_f32_e32 v45, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v40, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v53
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v52
+; SI-NEXT: v_mul_f32_e32 v61, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v44, 1.0, v17
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v41
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v25
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v27
+; SI-NEXT: v_mul_f32_e64 v25, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v3, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v5, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v7, 1.0, s29
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v54, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v56, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v58, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v60, 1.0, v14
+; SI-NEXT: v_mul_f32_e32 v62, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v47, 1.0, v22
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v28
+; SI-NEXT: v_mul_f32_e64 v19, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v0, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s16
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s28
+; SI-NEXT: v_mul_f32_e32 v39, 1.0, v0
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v48
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v45
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v37
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v38
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v49
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v39
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v31
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v60
-; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_mul_f32_e64 v35, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v33, 1.0, s27
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v18
+; SI-NEXT: v_mul_f32_e32 v34, 1.0, v29
+; SI-NEXT: v_mul_f32_e32 v36, 1.0, v24
+; SI-NEXT: v_mul_f32_e32 v38, 1.0, v26
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v30
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v41, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v43, 1.0, v40
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v42
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v62
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v63
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v33
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v34
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v35
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_mul_f32_e32 v42, 1.0, v36
-; SI-NEXT: v_mul_f32_e64 v12, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v34, 1.0, s24
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50
+; SI-NEXT: v_mul_f32_e32 v53, 1.0, v52
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v46
+; SI-NEXT: v_mul_f32_e64 v48, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v18, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v29, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v45, 1.0, s28
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB63_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_waitcnt expcnt(6)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v0, v3, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_alignbit_b32 v2, v2, v8, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v9, 16
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v58
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v56
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_alignbit_b32 v5, v5, v11, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v14, 16
-; SI-NEXT: v_alignbit_b32 v8, v8, v54, 16
-; SI-NEXT: v_alignbit_b32 v9, v9, v46, 16
-; SI-NEXT: v_mov_b32_e32 v62, v61
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v61
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v60, v59
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v59
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v56, v47
-; SI-NEXT: v_alignbit_b32 v13, v13, v47, 16
-; SI-NEXT: v_mov_b32_e32 v46, v45
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v45
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_alignbit_b32 v30, v30, v31, 16
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v33
-; SI-NEXT: v_alignbit_b32 v4, v4, v34, 16
-; SI-NEXT: v_mov_b32_e32 v63, v44
-; SI-NEXT: v_mov_b32_e32 v58, v57
-; SI-NEXT: v_mov_b32_e32 v44, v43
-; SI-NEXT: v_alignbit_b32 v16, v16, v43, 16
-; SI-NEXT: v_mov_b32_e32 v43, v41
-; SI-NEXT: v_alignbit_b32 v17, v17, v41, 16
-; SI-NEXT: v_alignbit_b32 v18, v18, v40, 16
-; SI-NEXT: v_mov_b32_e32 v40, v55
-; SI-NEXT: v_alignbit_b32 v19, v19, v55, 16
-; SI-NEXT: v_alignbit_b32 v20, v20, v48, 16
-; SI-NEXT: v_mov_b32_e32 v48, v53
-; SI-NEXT: v_alignbit_b32 v21, v21, v53, 16
-; SI-NEXT: v_alignbit_b32 v22, v22, v52, 16
-; SI-NEXT: v_mov_b32_e32 v52, v51
-; SI-NEXT: v_alignbit_b32 v23, v23, v51, 16
-; SI-NEXT: v_alignbit_b32 v24, v24, v50, 16
-; SI-NEXT: v_mov_b32_e32 v50, v49
-; SI-NEXT: v_alignbit_b32 v25, v25, v49, 16
-; SI-NEXT: v_mov_b32_e32 v36, v39
-; SI-NEXT: v_alignbit_b32 v26, v26, v39, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v34, v38
-; SI-NEXT: v_alignbit_b32 v27, v27, v38, 16
-; SI-NEXT: v_mov_b32_e32 v35, v37
-; SI-NEXT: v_alignbit_b32 v28, v28, v37, 16
-; SI-NEXT: v_mov_b32_e32 v37, v32
-; SI-NEXT: v_alignbit_b32 v29, v29, v32, 16
-; SI-NEXT: v_alignbit_b32 v31, v31, v42, 16
+; SI-NEXT: v_mov_b32_e32 v0, v19
+; SI-NEXT: v_mov_b32_e32 v37, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v33
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v63
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v21
; SI-NEXT: s_mov_b64 s[4:5], 0
-; SI-NEXT: v_mov_b32_e32 v32, v33
-; SI-NEXT: v_mov_b32_e32 v33, v42
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_alignbit_b32 v10, v10, v61, 16
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_alignbit_b32 v12, v12, v54, 16
-; SI-NEXT: v_mov_b32_e32 v41, v61
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_alignbit_b32 v11, v11, v59, 16
-; SI-NEXT: v_mov_b32_e32 v55, v59
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_alignbit_b32 v14, v14, v45, 16
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[0:1], v[19:20], 16
+; SI-NEXT: v_mov_b32_e32 v1, v48
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 16
+; SI-NEXT: v_mov_b32_e32 v2, v14
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v49, v15
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v3
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[2:3], v[14:15], 16
+; SI-NEXT: v_mov_b32_e32 v3, v16
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v20, v17
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v35
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[3:4], v[16:17], 16
+; SI-NEXT: v_mov_b32_e32 v4, v18
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v5
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[4:5], v[18:19], 16
+; SI-NEXT: v_mov_b32_e32 v5, v29
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[5:6], v[29:30], 16
+; SI-NEXT: v_mov_b32_e32 v6, v45
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[6:7], v[45:46], 16
+; SI-NEXT: v_mov_b32_e32 v7, v39
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[7:8], v[39:40], 16
+; SI-NEXT: v_mov_b32_e32 v8, v9
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v61
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v49
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v52
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[8:9], v[9:10], 16
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v9
+; SI-NEXT: v_mov_b32_e32 v9, v54
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[9:10], v[54:55], 16
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v55, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v10
+; SI-NEXT: v_mov_b32_e32 v10, v11
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[10:11], v[11:12], 16
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v11
+; SI-NEXT: v_mov_b32_e32 v11, v56
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[11:12], v[56:57], 16
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v56, v44
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v50
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v12
+; SI-NEXT: v_lshr_b64 v[12:13], v[13:14], 16
+; SI-NEXT: v_mov_b32_e32 v13, v58
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[13:14], v[58:59], 16
+; SI-NEXT: v_mov_b32_e32 v14, v60
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[14:15], v[60:61], 16
+; SI-NEXT: v_mov_b32_e32 v15, v62
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[62:63], 16
+; SI-NEXT: v_mov_b32_e32 v16, v32
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[16:17], v[32:33], 16
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v27
+; SI-NEXT: v_mov_b32_e32 v33, v34
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v17
+; SI-NEXT: v_mov_b32_e32 v40, v17
+; SI-NEXT: v_lshr_b64 v[17:18], v[34:35], 16
+; SI-NEXT: v_lshr_b64 v[18:19], v[47:48], 16
+; SI-NEXT: v_lshr_b64 v[19:20], v[36:37], 16
+; SI-NEXT: v_mov_b32_e32 v20, v38
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[20:21], v[38:39], 16
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v34, v47
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v21
+; SI-NEXT: v_mov_b32_e32 v21, v22
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[21:22], v[22:23], 16
+; SI-NEXT: v_mov_b32_e32 v22, v31
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[22:23], v[31:32], 16
+; SI-NEXT: v_mov_b32_e32 v23, v24
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[23:24], v[24:25], 16
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v24
+; SI-NEXT: v_mov_b32_e32 v24, v41
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[24:25], v[41:42], 16
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v41, v26
+; SI-NEXT: v_mov_b32_e32 v42, v51
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v25
+; SI-NEXT: v_lshr_b64 v[25:26], v[26:27], 16
+; SI-NEXT: v_mov_b32_e32 v26, v43
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[26:27], v[43:44], 16
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v43, v28
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v27
+; SI-NEXT: v_lshr_b64 v[27:28], v[28:29], 16
+; SI-NEXT: v_lshr_b64 v[28:29], v[51:52], 16
+; SI-NEXT: v_lshr_b64 v[29:30], v[53:54], 16
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v52, v53
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v15, v15, v47, 16
-; SI-NEXT: v_mov_b32_e32 v51, v47
-; SI-NEXT: v_mov_b32_e32 v53, v45
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v30
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshr_b64 v[30:31], v[31:32], 16
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v57
+; SI-NEXT: v_mov_b32_e32 v53, v31
+; SI-NEXT: v_lshr_b64 v[31:32], v[31:32], 16
; SI-NEXT: s_branch .LBB63_3
; SI-NEXT: .LBB63_2:
-; SI-NEXT: v_mov_b32_e32 v63, v44
-; SI-NEXT: v_mov_b32_e32 v44, v43
-; SI-NEXT: v_mov_b32_e32 v43, v41
-; SI-NEXT: v_mov_b32_e32 v40, v55
-; SI-NEXT: v_mov_b32_e32 v48, v53
-; SI-NEXT: v_mov_b32_e32 v52, v51
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v62, v61
-; SI-NEXT: v_mov_b32_e32 v60, v59
-; SI-NEXT: v_mov_b32_e32 v58, v57
-; SI-NEXT: v_mov_b32_e32 v56, v47
-; SI-NEXT: v_mov_b32_e32 v46, v45
-; SI-NEXT: v_mov_b32_e32 v50, v49
-; SI-NEXT: v_mov_b32_e32 v36, v39
+; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v56, v44
+; SI-NEXT: v_mov_b32_e32 v55, v13
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v34, v38
-; SI-NEXT: v_mov_b32_e32 v35, v37
-; SI-NEXT: v_mov_b32_e32 v37, v32
+; SI-NEXT: v_mov_b32_e32 v33, v34
+; SI-NEXT: v_mov_b32_e32 v34, v47
+; SI-NEXT: v_mov_b32_e32 v52, v53
+; SI-NEXT: v_mov_b32_e32 v53, v0
; SI-NEXT: s_mov_b64 s[4:5], -1
-; SI-NEXT: v_mov_b32_e32 v32, v33
-; SI-NEXT: v_mov_b32_e32 v33, v42
+; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_mov_b32_e32 v41, v26
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v43, v28
+; SI-NEXT: v_mov_b32_e32 v42, v51
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: .LBB63_3: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v38, v50
-; SI-NEXT: v_mov_b32_e32 v39, v52
-; SI-NEXT: v_mov_b32_e32 v49, v40
-; SI-NEXT: v_mov_b32_e32 v50, v43
-; SI-NEXT: v_mov_b32_e32 v43, v44
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mov_b32_e32 v32, v40
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v37, v34
+; SI-NEXT: v_mov_b32_e32 v34, v33
+; SI-NEXT: v_mov_b32_e32 v35, v56
; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5]
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v33, v38
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v51, v46
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v54, v46
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v44, v46
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v45, v56
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v47, v56
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v58, v60
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; SI-NEXT: s_cbranch_vccnz .LBB63_5
; SI-NEXT: ; %bb.4: ; %cmp.true
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v57
+; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v61
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v49
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v40
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v39
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v63
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v62
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v60
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v59
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v58
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v46
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v40
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v35
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v32
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v53
; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v60
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v58
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v56
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v47
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v45
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v46
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v54
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v51
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v50
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v55
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v48
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v38
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v33
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_lshr_b64 v[16:17], v[16:17], 16
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v34
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_lshr_b64 v[17:18], v[17:18], 16
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v37
; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshr_b64 v[18:19], v[18:19], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v36
; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshr_b64 v[19:20], v[19:20], 16
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshr_b64 v[20:21], v[20:21], 16
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshr_b64 v[21:22], v[21:22], 16
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshr_b64 v[22:23], v[22:23], 16
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshr_b64 v[23:24], v[23:24], 16
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshr_b64 v[24:25], v[24:25], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v41
; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshr_b64 v[25:26], v[25:26], 16
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshr_b64 v[26:27], v[26:27], 16
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v43
; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshr_b64 v[27:28], v[27:28], 16
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v42
; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshr_b64 v[28:29], v[28:29], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v52
; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v45
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v42
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v52
-; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v41
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v55
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v54
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v56
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v53
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v51
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v43
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v16, v17, v16, 16
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v50
-; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_alignbit_b32 v17, v18, v17, 16
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_alignbit_b32 v18, v19, v18, 16
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; SI-NEXT: v_alignbit_b32 v19, v20, v19, 16
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_alignbit_b32 v20, v21, v20, 16
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v48
-; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; SI-NEXT: v_alignbit_b32 v21, v22, v21, 16
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; SI-NEXT: v_alignbit_b32 v22, v23, v22, 16
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v39
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; SI-NEXT: v_alignbit_b32 v23, v24, v23, 16
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; SI-NEXT: v_alignbit_b32 v24, v25, v24, 16
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v38
-; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; SI-NEXT: v_alignbit_b32 v25, v26, v25, 16
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v36
-; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; SI-NEXT: v_alignbit_b32 v26, v27, v26, 16
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v34
-; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; SI-NEXT: v_alignbit_b32 v27, v28, v27, 16
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v35
-; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; SI-NEXT: v_alignbit_b32 v28, v29, v28, 16
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v37
; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; SI-NEXT: v_alignbit_b32 v29, v30, v29, 16
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_lshr_b64 v[29:30], v[29:30], 16
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_alignbit_b32 v30, v31, v30, 16
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v33
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; SI-NEXT: v_alignbit_b32 v31, v32, v31, 16
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v33
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_lshr_b64 v[32:33], v[32:33], 16
+; SI-NEXT: v_lshr_b64 v[30:31], v[30:31], 16
+; SI-NEXT: v_mov_b32_e32 v31, v32
; SI-NEXT: .LBB63_5: ; %end
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
@@ -101860,36 +102461,39 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_mov_b32_e32 v31, v17
; VI-NEXT: v_mov_b32_e32 v30, v16
; VI-NEXT: v_mov_b32_e32 v29, v15
-; VI-NEXT: v_mov_b32_e32 v28, v14
; VI-NEXT: v_mov_b32_e32 v27, v13
-; VI-NEXT: v_mov_b32_e32 v26, v12
; VI-NEXT: v_mov_b32_e32 v25, v11
-; VI-NEXT: v_mov_b32_e32 v24, v10
; VI-NEXT: v_mov_b32_e32 v23, v9
-; VI-NEXT: v_mov_b32_e32 v22, v8
; VI-NEXT: v_mov_b32_e32 v21, v7
-; VI-NEXT: v_mov_b32_e32 v20, v6
; VI-NEXT: v_mov_b32_e32 v19, v5
-; VI-NEXT: v_mov_b32_e32 v32, v4
; VI-NEXT: v_mov_b32_e32 v17, v3
-; VI-NEXT: v_mov_b32_e32 v16, v2
; VI-NEXT: v_mov_b32_e32 v15, v1
+; VI-NEXT: v_mov_b32_e32 v28, v14
+; VI-NEXT: v_mov_b32_e32 v26, v12
+; VI-NEXT: v_mov_b32_e32 v24, v10
+; VI-NEXT: v_mov_b32_e32 v22, v8
+; VI-NEXT: v_mov_b32_e32 v20, v6
+; VI-NEXT: v_mov_b32_e32 v32, v4
+; VI-NEXT: v_mov_b32_e32 v16, v2
; VI-NEXT: v_mov_b32_e32 v14, v0
-; VI-NEXT: v_mov_b32_e32 v0, s16
-; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-NEXT: v_mov_b32_e32 v2, s18
+; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v3, s19
-; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v5, s21
-; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v7, s23
-; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v9, s25
-; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v11, s27
-; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v13, s29
+; VI-NEXT: v_mov_b32_e32 v0, s16
+; VI-NEXT: v_mov_b32_e32 v2, s18
+; VI-NEXT: v_mov_b32_e32 v4, s20
+; VI-NEXT: v_mov_b32_e32 v6, s22
+; VI-NEXT: v_mov_b32_e32 v8, s24
+; VI-NEXT: v_mov_b32_e32 v10, s26
+; VI-NEXT: v_mov_b32_e32 v12, s28
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB63_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB63_3
@@ -101898,580 +102502,600 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v15, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v15
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
-; VI-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_alignbit_b32 v15, v15, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v15, v18, v34, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v15
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v14, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v14
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v14
+; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[33:34]
+; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_bfe_u32 v15, v14, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
-; VI-NEXT: v_cndmask_b32_e32 v14, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; VI-NEXT: v_alignbit_b32 v14, v14, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v13
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v14, v15, v18, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v14
+; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[35:36]
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v13
+; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v13, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v13
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v13
+; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
-; VI-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; VI-NEXT: v_alignbit_b32 v13, v13, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v13, v15, v18, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v12
+; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v12, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v12
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v12
+; VI-NEXT: v_lshrrev_b64 v[35:36], 16, v[35:36]
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_bfe_u32 v13, v12, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
-; VI-NEXT: v_cndmask_b32_e32 v12, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_alignbit_b32 v12, v12, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v11
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v12, v13, v15, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v12
+; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[36:37]
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v11, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v11
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v11
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
-; VI-NEXT: v_cndmask_b32_e32 v11, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; VI-NEXT: v_alignbit_b32 v11, v11, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v11, v13, v15, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v11
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v10
+; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v10, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v10
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v10
+; VI-NEXT: v_lshrrev_b64 v[36:37], 16, v[36:37]
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: v_bfe_u32 v11, v10, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
-; VI-NEXT: v_cndmask_b32_e32 v10, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_alignbit_b32 v10, v10, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v9
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v10, v11, v13, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v10
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[37:38]
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v9
+; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v9, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v9
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v9
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
-; VI-NEXT: v_cndmask_b32_e32 v9, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_alignbit_b32 v9, v9, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v8
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v8
+; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v8, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v8
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v8
+; VI-NEXT: v_lshrrev_b64 v[37:38], 16, v[37:38]
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
-; VI-NEXT: v_cndmask_b32_e32 v8, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_alignbit_b32 v8, v8, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v7
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[38:39]
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v7
+; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v7, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v7
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v7
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; VI-NEXT: v_cndmask_b32_e32 v7, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_alignbit_b32 v7, v7, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v6, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v6
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v6
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_bfe_u32 v7, v6, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
-; VI-NEXT: v_cndmask_b32_e32 v6, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_alignbit_b32 v6, v6, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v6, v7, v9, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[48:49]
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v5, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v5
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v5
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: v_cndmask_b32_e32 v5, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_alignbit_b32 v5, v5, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v4
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v4
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v4
+; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[48:49]
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_alignbit_b32 v4, v4, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v3
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v4
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[49:50]
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v3
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v3
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v3, v3, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v2
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v2
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v2
+; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50]
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_alignbit_b32 v2, v2, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v1
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v2
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[50:51]
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v1
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_alignbit_b32 v1, v1, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v0
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0
+; VI-NEXT: v_lshrrev_b64 v[50:51], 16, v[50:51]
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v31
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v31, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v31
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v31
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
-; VI-NEXT: v_cndmask_b32_e32 v31, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_alignbit_b32 v31, v31, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v30
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v30, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v30
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v30
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
-; VI-NEXT: v_cndmask_b32_e32 v30, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_alignbit_b32 v30, v30, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v29
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v29, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v29
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v29
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
-; VI-NEXT: v_cndmask_b32_e32 v29, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_alignbit_b32 v29, v29, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v28
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v28, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v28
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v28
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
-; VI-NEXT: v_cndmask_b32_e32 v28, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_alignbit_b32 v28, v28, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v27
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v27, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v27
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v27
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
-; VI-NEXT: v_cndmask_b32_e32 v27, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; VI-NEXT: v_alignbit_b32 v27, v27, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v26
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v26, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v26
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v26
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
-; VI-NEXT: v_cndmask_b32_e32 v26, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_alignbit_b32 v26, v26, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v25, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v25
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v25
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
-; VI-NEXT: v_cndmask_b32_e32 v25, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; VI-NEXT: v_alignbit_b32 v25, v25, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v24
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v24, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v24
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v24
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
-; VI-NEXT: v_cndmask_b32_e32 v24, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_alignbit_b32 v24, v24, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v23
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v23, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v23
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v23
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
-; VI-NEXT: v_cndmask_b32_e32 v23, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_alignbit_b32 v23, v23, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v22
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v22, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v22
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v22
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
-; VI-NEXT: v_cndmask_b32_e32 v22, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_alignbit_b32 v22, v22, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v21
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v21, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v21
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v21
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
-; VI-NEXT: v_cndmask_b32_e32 v21, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_alignbit_b32 v21, v21, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v20
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v20, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v20
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v20
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
-; VI-NEXT: v_cndmask_b32_e32 v20, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_alignbit_b32 v20, v20, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v19, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v19
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v19
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
-; VI-NEXT: v_cndmask_b32_e32 v19, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_alignbit_b32 v19, v19, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v32
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
-; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; VI-NEXT: v_alignbit_b32 v32, v32, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v17
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v17, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v17
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v17
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
-; VI-NEXT: v_cndmask_b32_e32 v17, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_alignbit_b32 v17, v17, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v16
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v16
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_cndmask_b32_e32 v16, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_alignbit_b32 v16, v16, v18, 16
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v0
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[51:52]
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v31
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v30
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v30
+; VI-NEXT: v_lshrrev_b64 v[51:52], 16, v[51:52]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v29
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v29
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[30:31], 16, v[52:53]
+; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v28
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
+; VI-NEXT: v_lshrrev_b64 v[52:53], 16, v[52:53]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v27
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v27
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[28:29], 16, v[53:54]
+; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v26
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v26
+; VI-NEXT: v_lshrrev_b64 v[53:54], 16, v[53:54]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v25
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[26:27], 16, v[54:55]
+; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v24
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v24
+; VI-NEXT: v_lshrrev_b64 v[38:39], 16, v[38:39]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v23
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v23
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[24:25], 16, v[39:40]
+; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v22
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
+; VI-NEXT: v_lshrrev_b64 v[39:40], 16, v[39:40]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v21
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[22:23], 16, v[40:41]
+; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v20
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v20
+; VI-NEXT: v_lshrrev_b64 v[40:41], 16, v[40:41]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v19
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v18, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v32
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v31, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v17
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v17
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[41:42]
+; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v16
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v15, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b64 v[54:55], 16, v[54:55]
+; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19]
+; VI-NEXT: v_lshrrev_b64 v[41:42], 16, v[41:42]
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[31:32]
+; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[15:16]
+; VI-NEXT: v_mov_b32_e32 v1, v50
+; VI-NEXT: v_mov_b32_e32 v3, v49
+; VI-NEXT: v_mov_b32_e32 v5, v48
+; VI-NEXT: v_mov_b32_e32 v7, v38
+; VI-NEXT: v_mov_b32_e32 v9, v37
+; VI-NEXT: v_mov_b32_e32 v11, v36
+; VI-NEXT: v_mov_b32_e32 v13, v35
+; VI-NEXT: v_mov_b32_e32 v15, v34
+; VI-NEXT: v_mov_b32_e32 v17, v41
+; VI-NEXT: v_mov_b32_e32 v19, v18
+; VI-NEXT: v_mov_b32_e32 v21, v40
+; VI-NEXT: v_mov_b32_e32 v23, v39
+; VI-NEXT: v_mov_b32_e32 v25, v54
+; VI-NEXT: v_mov_b32_e32 v27, v53
+; VI-NEXT: v_mov_b32_e32 v29, v52
+; VI-NEXT: v_mov_b32_e32 v31, v51
; VI-NEXT: .LBB63_3: ; %end
+; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v18, v32
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB63_4:
; VI-NEXT: s_branch .LBB63_2
@@ -133554,94 +134178,92 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg
; SI-NEXT: v_writelane_b32 v62, s46, 3
; SI-NEXT: s_cbranch_execnz .LBB77_4
; SI-NEXT: .LBB77_2: ; %cmp.true
-; SI-NEXT: v_add_f64 v[35:36], s[44:45], 1.0
; SI-NEXT: v_add_f64 v[3:4], s[6:7], 1.0
-; SI-NEXT: v_add_f64 v[49:50], s[28:29], 1.0
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v35
; SI-NEXT: v_add_f64 v[1:2], s[22:23], 1.0
; SI-NEXT: v_add_f64 v[41:42], s[24:25], 1.0
-; SI-NEXT: v_add_f64 v[27:28], s[40:41], 1.0
-; SI-NEXT: v_add_f64 v[15:16], s[10:11], 1.0
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50
-; SI-NEXT: v_add_f64 v[31:32], s[42:43], 1.0
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v16
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v16
-; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v15
-; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v28
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v28
-; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v27
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v27
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v42
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v42
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v41
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v41
+; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v42
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v42
+; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v41
+; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v41
; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v2
; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v2
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_f64 v[2:3], s[20:21], 1.0
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
-; SI-NEXT: v_add_f64 v[11:12], s[8:9], 1.0
-; SI-NEXT: v_add_f64 v[7:8], s[4:5], 1.0
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v32
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v32
-; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v31
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v31
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v3
-; SI-NEXT: v_add_f64 v[3:4], s[16:17], 1.0
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v7
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v4
-; SI-NEXT: v_mov_b32_e32 v4, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: v_add_f64 v[51:52], s[26:27], 1.0
+; SI-NEXT: v_add_f64 v[49:50], s[28:29], 1.0
+; SI-NEXT: v_add_f64 v[35:36], s[44:45], 1.0
+; SI-NEXT: v_add_f64 v[31:32], s[42:43], 1.0
+; SI-NEXT: v_add_f64 v[27:28], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[23:24], s[14:15], 1.0
; SI-NEXT: v_add_f64 v[19:20], s[12:13], 1.0
+; SI-NEXT: v_add_f64 v[15:16], s[10:11], 1.0
+; SI-NEXT: v_add_f64 v[11:12], s[8:9], 1.0
+; SI-NEXT: v_add_f64 v[7:8], s[4:5], 1.0
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v3
; SI-NEXT: v_add_f64 v[59:60], s[18:19], 1.0
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v8
-; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v20
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v20
-; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v19
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v19
-; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v24
-; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v23
-; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v36
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v36
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v50
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v49
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v49
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_f64 v[3:4], s[16:17], 1.0
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v8
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v16
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v20
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v24
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v28
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v27
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v32
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v32
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v31
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v36
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v36
+; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v35
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
+; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v50
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v50
+; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v49
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v49
; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v52
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v52
; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v51
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v2
-; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v60
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v60
+; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v1
+; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v2
+; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v60
+; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v60
; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v59
; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v59
+; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: s_branch .LBB77_5
@@ -133716,15 +134338,18 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: s_branch .LBB77_2
; SI-NEXT: .LBB77_4:
-; SI-NEXT: v_mov_b32_e32 v1, s37
+; SI-NEXT: v_mov_b32_e32 v1, s59
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v1, s36
-; SI-NEXT: v_readlane_b32 s4, v62, 0
+; SI-NEXT: v_mov_b32_e32 v1, s58
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v1, s34
-; SI-NEXT: v_mov_b32_e32 v7, s4
+; SI-NEXT: v_mov_b32_e32 v1, s57
+; SI-NEXT: v_readlane_b32 s4, v62, 0
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s56
+; SI-NEXT: v_mov_b32_e32 v61, s4
; SI-NEXT: v_readlane_b32 s4, v62, 1
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -133732,328 +134357,329 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg
; SI-NEXT: v_readlane_b32 s4, v62, 2
; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: v_readlane_b32 s4, v62, 3
-; SI-NEXT: v_mov_b32_e32 v5, s59
-; SI-NEXT: v_mov_b32_e32 v4, s58
-; SI-NEXT: v_mov_b32_e32 v9, s57
-; SI-NEXT: v_mov_b32_e32 v6, s56
-; SI-NEXT: v_mov_b32_e32 v13, s99
-; SI-NEXT: v_mov_b32_e32 v10, s98
-; SI-NEXT: v_mov_b32_e32 v17, s97
-; SI-NEXT: v_mov_b32_e32 v14, s96
-; SI-NEXT: v_mov_b32_e32 v21, s87
-; SI-NEXT: v_mov_b32_e32 v18, s86
-; SI-NEXT: v_mov_b32_e32 v25, s85
-; SI-NEXT: v_mov_b32_e32 v22, s84
-; SI-NEXT: v_mov_b32_e32 v29, s83
-; SI-NEXT: v_mov_b32_e32 v26, s82
-; SI-NEXT: v_mov_b32_e32 v33, s81
-; SI-NEXT: v_mov_b32_e32 v30, s80
-; SI-NEXT: v_mov_b32_e32 v37, s71
-; SI-NEXT: v_mov_b32_e32 v34, s70
-; SI-NEXT: v_mov_b32_e32 v39, s69
-; SI-NEXT: v_mov_b32_e32 v38, s68
-; SI-NEXT: v_mov_b32_e32 v53, s67
-; SI-NEXT: v_mov_b32_e32 v48, s66
-; SI-NEXT: v_mov_b32_e32 v55, s65
-; SI-NEXT: v_mov_b32_e32 v54, s64
-; SI-NEXT: v_mov_b32_e32 v43, s55
-; SI-NEXT: v_mov_b32_e32 v40, s54
-; SI-NEXT: v_mov_b32_e32 v45, s53
-; SI-NEXT: v_mov_b32_e32 v44, s52
-; SI-NEXT: v_mov_b32_e32 v47, s51
-; SI-NEXT: v_mov_b32_e32 v46, s50
-; SI-NEXT: v_mov_b32_e32 v57, s49
-; SI-NEXT: v_mov_b32_e32 v56, s48
-; SI-NEXT: v_mov_b32_e32 v61, s39
-; SI-NEXT: v_mov_b32_e32 v58, s38
-; SI-NEXT: v_mov_b32_e32 v8, s35
-; SI-NEXT: v_mov_b32_e32 v24, s31
-; SI-NEXT: v_mov_b32_e32 v23, s30
+; SI-NEXT: v_mov_b32_e32 v6, s99
+; SI-NEXT: v_mov_b32_e32 v5, s98
+; SI-NEXT: v_mov_b32_e32 v8, s97
+; SI-NEXT: v_mov_b32_e32 v7, s96
+; SI-NEXT: v_mov_b32_e32 v10, s87
+; SI-NEXT: v_mov_b32_e32 v9, s86
+; SI-NEXT: v_mov_b32_e32 v12, s85
+; SI-NEXT: v_mov_b32_e32 v11, s84
+; SI-NEXT: v_mov_b32_e32 v14, s83
+; SI-NEXT: v_mov_b32_e32 v13, s82
+; SI-NEXT: v_mov_b32_e32 v16, s81
+; SI-NEXT: v_mov_b32_e32 v15, s80
+; SI-NEXT: v_mov_b32_e32 v18, s71
+; SI-NEXT: v_mov_b32_e32 v17, s70
+; SI-NEXT: v_mov_b32_e32 v20, s69
+; SI-NEXT: v_mov_b32_e32 v19, s68
+; SI-NEXT: v_mov_b32_e32 v22, s67
+; SI-NEXT: v_mov_b32_e32 v21, s66
+; SI-NEXT: v_mov_b32_e32 v24, s65
+; SI-NEXT: v_mov_b32_e32 v23, s64
+; SI-NEXT: v_mov_b32_e32 v26, s55
+; SI-NEXT: v_mov_b32_e32 v25, s54
+; SI-NEXT: v_mov_b32_e32 v28, s53
+; SI-NEXT: v_mov_b32_e32 v27, s52
+; SI-NEXT: v_mov_b32_e32 v30, s51
+; SI-NEXT: v_mov_b32_e32 v29, s50
+; SI-NEXT: v_mov_b32_e32 v32, s49
+; SI-NEXT: v_mov_b32_e32 v31, s48
+; SI-NEXT: v_mov_b32_e32 v34, s39
+; SI-NEXT: v_mov_b32_e32 v33, s38
+; SI-NEXT: v_mov_b32_e32 v36, s37
+; SI-NEXT: v_mov_b32_e32 v35, s36
+; SI-NEXT: v_mov_b32_e32 v38, s35
+; SI-NEXT: v_mov_b32_e32 v37, s34
+; SI-NEXT: v_mov_b32_e32 v48, s31
+; SI-NEXT: v_mov_b32_e32 v39, s30
; SI-NEXT: v_mov_b32_e32 v50, s95
; SI-NEXT: v_mov_b32_e32 v49, s94
; SI-NEXT: v_mov_b32_e32 v52, s93
; SI-NEXT: v_mov_b32_e32 v51, s92
-; SI-NEXT: v_mov_b32_e32 v16, s91
-; SI-NEXT: v_mov_b32_e32 v15, s90
-; SI-NEXT: v_mov_b32_e32 v28, s89
-; SI-NEXT: v_mov_b32_e32 v27, s88
+; SI-NEXT: v_mov_b32_e32 v54, s91
+; SI-NEXT: v_mov_b32_e32 v53, s90
+; SI-NEXT: v_mov_b32_e32 v40, s89
+; SI-NEXT: v_mov_b32_e32 v55, s88
; SI-NEXT: v_mov_b32_e32 v42, s79
; SI-NEXT: v_mov_b32_e32 v41, s78
-; SI-NEXT: v_mov_b32_e32 v11, s77
-; SI-NEXT: v_mov_b32_e32 v12, s76
-; SI-NEXT: v_mov_b32_e32 v32, s75
-; SI-NEXT: v_mov_b32_e32 v31, s74
-; SI-NEXT: v_mov_b32_e32 v19, s73
-; SI-NEXT: v_mov_b32_e32 v20, s72
-; SI-NEXT: v_mov_b32_e32 v36, s63
-; SI-NEXT: v_mov_b32_e32 v35, s62
+; SI-NEXT: v_mov_b32_e32 v43, s77
+; SI-NEXT: v_mov_b32_e32 v44, s76
+; SI-NEXT: v_mov_b32_e32 v46, s75
+; SI-NEXT: v_mov_b32_e32 v45, s74
+; SI-NEXT: v_mov_b32_e32 v47, s73
+; SI-NEXT: v_mov_b32_e32 v56, s72
+; SI-NEXT: v_mov_b32_e32 v58, s63
+; SI-NEXT: v_mov_b32_e32 v57, s62
; SI-NEXT: v_mov_b32_e32 v60, s61
; SI-NEXT: v_mov_b32_e32 v59, s60
; SI-NEXT: v_mov_b32_e32 v3, s4
; SI-NEXT: .LBB77_5: ; %end
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
-; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[3:4], 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
; SI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v61
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v60
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v59
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v59
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v35
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v58
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v57
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v19
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v20
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v47
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v56
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v31
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v46
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v45
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v12
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v44
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v42
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v41
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v41
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v28
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v27
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v40
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v55
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v53
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v52
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v51
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v51
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v50
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v49
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v24
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v23
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_readlane_b32 s99, v63, 35
-; SI-NEXT: v_readlane_b32 s98, v63, 34
-; SI-NEXT: v_readlane_b32 s97, v63, 33
-; SI-NEXT: v_readlane_b32 s96, v63, 32
-; SI-NEXT: v_readlane_b32 s87, v63, 31
-; SI-NEXT: v_readlane_b32 s86, v63, 30
-; SI-NEXT: v_readlane_b32 s85, v63, 29
-; SI-NEXT: v_readlane_b32 s84, v63, 28
-; SI-NEXT: v_readlane_b32 s83, v63, 27
-; SI-NEXT: v_readlane_b32 s82, v63, 26
-; SI-NEXT: v_readlane_b32 s81, v63, 25
-; SI-NEXT: v_readlane_b32 s80, v63, 24
-; SI-NEXT: v_readlane_b32 s71, v63, 23
-; SI-NEXT: v_readlane_b32 s70, v63, 22
-; SI-NEXT: v_readlane_b32 s69, v63, 21
-; SI-NEXT: v_readlane_b32 s68, v63, 20
-; SI-NEXT: v_readlane_b32 s67, v63, 19
-; SI-NEXT: v_readlane_b32 s66, v63, 18
-; SI-NEXT: v_readlane_b32 s65, v63, 17
-; SI-NEXT: v_readlane_b32 s64, v63, 16
-; SI-NEXT: v_readlane_b32 s55, v63, 15
-; SI-NEXT: v_readlane_b32 s54, v63, 14
-; SI-NEXT: v_readlane_b32 s53, v63, 13
-; SI-NEXT: v_readlane_b32 s52, v63, 12
-; SI-NEXT: v_readlane_b32 s51, v63, 11
-; SI-NEXT: v_readlane_b32 s50, v63, 10
-; SI-NEXT: v_readlane_b32 s49, v63, 9
-; SI-NEXT: v_readlane_b32 s48, v63, 8
-; SI-NEXT: v_readlane_b32 s39, v63, 7
-; SI-NEXT: v_readlane_b32 s38, v63, 6
-; SI-NEXT: v_readlane_b32 s37, v63, 5
-; SI-NEXT: v_readlane_b32 s36, v63, 4
-; SI-NEXT: v_readlane_b32 s35, v63, 3
-; SI-NEXT: v_readlane_b32 s34, v63, 2
-; SI-NEXT: v_readlane_b32 s31, v63, 1
-; SI-NEXT: v_readlane_b32 s30, v63, 0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v61
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v58
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v57
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v56
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v31
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v47
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v46
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v30
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v29
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v45
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v44
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v28
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v27
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v40
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v26
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v25
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v55
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v54
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v24
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v23
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v53
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v48
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v22
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v38
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v20
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v19
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v34
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v18
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v17
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v30
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v15
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v29
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v26
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v14
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v13
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v25
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v22
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v18
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v17
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v14
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v13
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v6
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: v_readlane_b32 s99, v63, 35
+; SI-NEXT: v_readlane_b32 s98, v63, 34
+; SI-NEXT: v_readlane_b32 s97, v63, 33
+; SI-NEXT: v_readlane_b32 s96, v63, 32
+; SI-NEXT: v_readlane_b32 s87, v63, 31
+; SI-NEXT: v_readlane_b32 s86, v63, 30
+; SI-NEXT: v_readlane_b32 s85, v63, 29
+; SI-NEXT: v_readlane_b32 s84, v63, 28
+; SI-NEXT: v_readlane_b32 s83, v63, 27
+; SI-NEXT: v_readlane_b32 s82, v63, 26
+; SI-NEXT: v_readlane_b32 s81, v63, 25
+; SI-NEXT: v_readlane_b32 s80, v63, 24
+; SI-NEXT: v_readlane_b32 s71, v63, 23
+; SI-NEXT: v_readlane_b32 s70, v63, 22
+; SI-NEXT: v_readlane_b32 s69, v63, 21
+; SI-NEXT: v_readlane_b32 s68, v63, 20
+; SI-NEXT: v_readlane_b32 s67, v63, 19
+; SI-NEXT: v_readlane_b32 s66, v63, 18
+; SI-NEXT: v_readlane_b32 s65, v63, 17
+; SI-NEXT: v_readlane_b32 s64, v63, 16
+; SI-NEXT: v_readlane_b32 s55, v63, 15
+; SI-NEXT: v_readlane_b32 s54, v63, 14
+; SI-NEXT: v_readlane_b32 s53, v63, 13
+; SI-NEXT: v_readlane_b32 s52, v63, 12
+; SI-NEXT: v_readlane_b32 s51, v63, 11
+; SI-NEXT: v_readlane_b32 s50, v63, 10
+; SI-NEXT: v_readlane_b32 s49, v63, 9
+; SI-NEXT: v_readlane_b32 s48, v63, 8
+; SI-NEXT: v_readlane_b32 s39, v63, 7
+; SI-NEXT: v_readlane_b32 s38, v63, 6
+; SI-NEXT: v_readlane_b32 s37, v63, 5
+; SI-NEXT: v_readlane_b32 s36, v63, 4
+; SI-NEXT: v_readlane_b32 s35, v63, 3
+; SI-NEXT: v_readlane_b32 s34, v63, 2
+; SI-NEXT: v_readlane_b32 s31, v63, 1
+; SI-NEXT: v_readlane_b32 s30, v63, 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -137264,562 +137890,744 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v52, v30
-; SI-NEXT: v_mov_b32_e32 v53, v28
-; SI-NEXT: v_mov_b32_e32 v40, v12
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:40
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:68
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:68
-; SI-NEXT: v_mov_b32_e32 v55, v14
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v63, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7
+; SI-NEXT: v_mov_b32_e32 v43, v21
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_mov_b32_e32 v54, v29
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16
-; SI-NEXT: v_mul_f32_e32 v58, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v56, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v44, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v41, v23
+; SI-NEXT: v_mov_b32_e32 v29, v20
+; SI-NEXT: v_mul_f32_e32 v57, 1.0, v3
; SI-NEXT: v_mul_f32_e32 v59, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v40
-; SI-NEXT: v_mul_f32_e32 v45, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v40, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v53
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v52
+; SI-NEXT: v_mul_f32_e32 v61, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v44, 1.0, v17
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v41
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v25
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v27
+; SI-NEXT: v_mul_f32_e64 v25, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v3, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v5, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v7, 1.0, s29
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v54, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v56, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v58, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v60, 1.0, v14
+; SI-NEXT: v_mul_f32_e32 v62, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v47, 1.0, v22
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v28
+; SI-NEXT: v_mul_f32_e64 v19, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v0, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s16
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s28
+; SI-NEXT: v_mul_f32_e32 v39, 1.0, v0
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v48
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v45
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v37
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v38
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v49
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v39
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v31
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v60
-; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_mul_f32_e64 v35, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v33, 1.0, s27
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v18
+; SI-NEXT: v_mul_f32_e32 v34, 1.0, v29
+; SI-NEXT: v_mul_f32_e32 v36, 1.0, v24
+; SI-NEXT: v_mul_f32_e32 v38, 1.0, v26
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v30
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v41, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v43, 1.0, v40
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v42
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v62
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v63
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v33
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v34
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v35
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_mul_f32_e32 v42, 1.0, v36
-; SI-NEXT: v_mul_f32_e64 v12, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v34, 1.0, s24
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50
+; SI-NEXT: v_mul_f32_e32 v53, 1.0, v52
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v46
+; SI-NEXT: v_mul_f32_e64 v48, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v18, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v29, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v45, 1.0, s28
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB79_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_waitcnt expcnt(6)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v0, v3, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_alignbit_b32 v2, v2, v8, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v9, 16
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v58
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v56
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_alignbit_b32 v5, v5, v11, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v14, 16
-; SI-NEXT: v_alignbit_b32 v8, v8, v54, 16
-; SI-NEXT: v_alignbit_b32 v9, v9, v46, 16
-; SI-NEXT: v_mov_b32_e32 v62, v61
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v61
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v60, v59
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v59
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v56, v47
-; SI-NEXT: v_alignbit_b32 v13, v13, v47, 16
-; SI-NEXT: v_mov_b32_e32 v46, v45
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v45
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_alignbit_b32 v30, v30, v31, 16
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v33
-; SI-NEXT: v_alignbit_b32 v4, v4, v34, 16
-; SI-NEXT: v_mov_b32_e32 v63, v44
-; SI-NEXT: v_mov_b32_e32 v58, v57
-; SI-NEXT: v_mov_b32_e32 v44, v43
-; SI-NEXT: v_alignbit_b32 v16, v16, v43, 16
-; SI-NEXT: v_mov_b32_e32 v43, v41
-; SI-NEXT: v_alignbit_b32 v17, v17, v41, 16
-; SI-NEXT: v_alignbit_b32 v18, v18, v40, 16
-; SI-NEXT: v_mov_b32_e32 v40, v55
-; SI-NEXT: v_alignbit_b32 v19, v19, v55, 16
-; SI-NEXT: v_alignbit_b32 v20, v20, v48, 16
-; SI-NEXT: v_mov_b32_e32 v48, v53
-; SI-NEXT: v_alignbit_b32 v21, v21, v53, 16
-; SI-NEXT: v_alignbit_b32 v22, v22, v52, 16
-; SI-NEXT: v_mov_b32_e32 v52, v51
-; SI-NEXT: v_alignbit_b32 v23, v23, v51, 16
-; SI-NEXT: v_alignbit_b32 v24, v24, v50, 16
-; SI-NEXT: v_mov_b32_e32 v50, v49
-; SI-NEXT: v_alignbit_b32 v25, v25, v49, 16
-; SI-NEXT: v_mov_b32_e32 v36, v39
-; SI-NEXT: v_alignbit_b32 v26, v26, v39, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v34, v38
-; SI-NEXT: v_alignbit_b32 v27, v27, v38, 16
-; SI-NEXT: v_mov_b32_e32 v35, v37
-; SI-NEXT: v_alignbit_b32 v28, v28, v37, 16
-; SI-NEXT: v_mov_b32_e32 v37, v32
-; SI-NEXT: v_alignbit_b32 v29, v29, v32, 16
-; SI-NEXT: v_alignbit_b32 v31, v31, v42, 16
+; SI-NEXT: v_mov_b32_e32 v0, v19
+; SI-NEXT: v_mov_b32_e32 v37, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v33
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v63
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v21
; SI-NEXT: s_mov_b64 s[4:5], 0
-; SI-NEXT: v_mov_b32_e32 v32, v33
-; SI-NEXT: v_mov_b32_e32 v33, v42
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_alignbit_b32 v10, v10, v61, 16
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_alignbit_b32 v12, v12, v54, 16
-; SI-NEXT: v_mov_b32_e32 v41, v61
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_alignbit_b32 v11, v11, v59, 16
-; SI-NEXT: v_mov_b32_e32 v55, v59
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_alignbit_b32 v14, v14, v45, 16
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[0:1], v[19:20], 16
+; SI-NEXT: v_mov_b32_e32 v1, v48
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 16
+; SI-NEXT: v_mov_b32_e32 v2, v14
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v49, v15
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v3
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[2:3], v[14:15], 16
+; SI-NEXT: v_mov_b32_e32 v3, v16
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v20, v17
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v35
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[3:4], v[16:17], 16
+; SI-NEXT: v_mov_b32_e32 v4, v18
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v5
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[4:5], v[18:19], 16
+; SI-NEXT: v_mov_b32_e32 v5, v29
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[5:6], v[29:30], 16
+; SI-NEXT: v_mov_b32_e32 v6, v45
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[6:7], v[45:46], 16
+; SI-NEXT: v_mov_b32_e32 v7, v39
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[7:8], v[39:40], 16
+; SI-NEXT: v_mov_b32_e32 v8, v9
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v61
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v49
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v52
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[8:9], v[9:10], 16
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v9
+; SI-NEXT: v_mov_b32_e32 v9, v54
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[9:10], v[54:55], 16
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v55, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v10
+; SI-NEXT: v_mov_b32_e32 v10, v11
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[10:11], v[11:12], 16
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v11
+; SI-NEXT: v_mov_b32_e32 v11, v56
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[11:12], v[56:57], 16
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v56, v44
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v50
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v12
+; SI-NEXT: v_lshr_b64 v[12:13], v[13:14], 16
+; SI-NEXT: v_mov_b32_e32 v13, v58
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[13:14], v[58:59], 16
+; SI-NEXT: v_mov_b32_e32 v14, v60
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[14:15], v[60:61], 16
+; SI-NEXT: v_mov_b32_e32 v15, v62
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[62:63], 16
+; SI-NEXT: v_mov_b32_e32 v16, v32
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[16:17], v[32:33], 16
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v27
+; SI-NEXT: v_mov_b32_e32 v33, v34
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v17
+; SI-NEXT: v_mov_b32_e32 v40, v17
+; SI-NEXT: v_lshr_b64 v[17:18], v[34:35], 16
+; SI-NEXT: v_lshr_b64 v[18:19], v[47:48], 16
+; SI-NEXT: v_lshr_b64 v[19:20], v[36:37], 16
+; SI-NEXT: v_mov_b32_e32 v20, v38
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[20:21], v[38:39], 16
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v34, v47
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v21
+; SI-NEXT: v_mov_b32_e32 v21, v22
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[21:22], v[22:23], 16
+; SI-NEXT: v_mov_b32_e32 v22, v31
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[22:23], v[31:32], 16
+; SI-NEXT: v_mov_b32_e32 v23, v24
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[23:24], v[24:25], 16
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v24
+; SI-NEXT: v_mov_b32_e32 v24, v41
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[24:25], v[41:42], 16
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v41, v26
+; SI-NEXT: v_mov_b32_e32 v42, v51
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v25
+; SI-NEXT: v_lshr_b64 v[25:26], v[26:27], 16
+; SI-NEXT: v_mov_b32_e32 v26, v43
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[26:27], v[43:44], 16
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v43, v28
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v27
+; SI-NEXT: v_lshr_b64 v[27:28], v[28:29], 16
+; SI-NEXT: v_lshr_b64 v[28:29], v[51:52], 16
+; SI-NEXT: v_lshr_b64 v[29:30], v[53:54], 16
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v52, v53
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v15, v15, v47, 16
-; SI-NEXT: v_mov_b32_e32 v51, v47
-; SI-NEXT: v_mov_b32_e32 v53, v45
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v30
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshr_b64 v[30:31], v[31:32], 16
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v57
+; SI-NEXT: v_mov_b32_e32 v53, v31
+; SI-NEXT: v_lshr_b64 v[31:32], v[31:32], 16
; SI-NEXT: s_branch .LBB79_3
; SI-NEXT: .LBB79_2:
-; SI-NEXT: v_mov_b32_e32 v63, v44
-; SI-NEXT: v_mov_b32_e32 v44, v43
-; SI-NEXT: v_mov_b32_e32 v43, v41
-; SI-NEXT: v_mov_b32_e32 v40, v55
-; SI-NEXT: v_mov_b32_e32 v48, v53
-; SI-NEXT: v_mov_b32_e32 v52, v51
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v62, v61
-; SI-NEXT: v_mov_b32_e32 v60, v59
-; SI-NEXT: v_mov_b32_e32 v58, v57
-; SI-NEXT: v_mov_b32_e32 v56, v47
-; SI-NEXT: v_mov_b32_e32 v46, v45
-; SI-NEXT: v_mov_b32_e32 v50, v49
-; SI-NEXT: v_mov_b32_e32 v36, v39
+; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v56, v44
+; SI-NEXT: v_mov_b32_e32 v55, v13
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v34, v38
-; SI-NEXT: v_mov_b32_e32 v35, v37
-; SI-NEXT: v_mov_b32_e32 v37, v32
+; SI-NEXT: v_mov_b32_e32 v33, v34
+; SI-NEXT: v_mov_b32_e32 v34, v47
+; SI-NEXT: v_mov_b32_e32 v52, v53
+; SI-NEXT: v_mov_b32_e32 v53, v0
; SI-NEXT: s_mov_b64 s[4:5], -1
-; SI-NEXT: v_mov_b32_e32 v32, v33
-; SI-NEXT: v_mov_b32_e32 v33, v42
+; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_mov_b32_e32 v41, v26
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v43, v28
+; SI-NEXT: v_mov_b32_e32 v42, v51
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: .LBB79_3: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v38, v50
-; SI-NEXT: v_mov_b32_e32 v39, v52
-; SI-NEXT: v_mov_b32_e32 v49, v40
-; SI-NEXT: v_mov_b32_e32 v50, v43
-; SI-NEXT: v_mov_b32_e32 v43, v44
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mov_b32_e32 v32, v40
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v37, v34
+; SI-NEXT: v_mov_b32_e32 v34, v33
+; SI-NEXT: v_mov_b32_e32 v35, v56
; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5]
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v33, v38
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v51, v46
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v54, v46
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v44, v46
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v45, v56
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v47, v56
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mov_b32_e32 v58, v60
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; SI-NEXT: s_cbranch_vccnz .LBB79_5
; SI-NEXT: ; %bb.4: ; %cmp.true
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v57
+; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v61
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v49
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v40
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v39
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v63
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v62
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v60
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v59
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v58
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v46
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v40
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v35
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v32
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v53
; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v60
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v58
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v56
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v47
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v45
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v46
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v54
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v51
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v50
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v55
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v48
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v38
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v33
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_lshr_b64 v[16:17], v[16:17], 16
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v34
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_lshr_b64 v[17:18], v[17:18], 16
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v37
; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshr_b64 v[18:19], v[18:19], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v36
; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshr_b64 v[19:20], v[19:20], 16
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshr_b64 v[20:21], v[20:21], 16
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshr_b64 v[21:22], v[21:22], 16
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshr_b64 v[22:23], v[22:23], 16
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshr_b64 v[23:24], v[23:24], 16
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshr_b64 v[24:25], v[24:25], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v41
; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshr_b64 v[25:26], v[25:26], 16
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshr_b64 v[26:27], v[26:27], 16
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v43
; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshr_b64 v[27:28], v[27:28], 16
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v42
; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshr_b64 v[28:29], v[28:29], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v52
; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v45
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v42
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v52
-; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v41
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v55
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v54
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v56
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v53
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v51
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v43
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v16, v17, v16, 16
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v50
-; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_alignbit_b32 v17, v18, v17, 16
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_alignbit_b32 v18, v19, v18, 16
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; SI-NEXT: v_alignbit_b32 v19, v20, v19, 16
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_alignbit_b32 v20, v21, v20, 16
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v48
-; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; SI-NEXT: v_alignbit_b32 v21, v22, v21, 16
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; SI-NEXT: v_alignbit_b32 v22, v23, v22, 16
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v39
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; SI-NEXT: v_alignbit_b32 v23, v24, v23, 16
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; SI-NEXT: v_alignbit_b32 v24, v25, v24, 16
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v38
-; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; SI-NEXT: v_alignbit_b32 v25, v26, v25, 16
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v36
-; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; SI-NEXT: v_alignbit_b32 v26, v27, v26, 16
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v34
-; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; SI-NEXT: v_alignbit_b32 v27, v28, v27, 16
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v35
-; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; SI-NEXT: v_alignbit_b32 v28, v29, v28, 16
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v37
; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; SI-NEXT: v_alignbit_b32 v29, v30, v29, 16
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_lshr_b64 v[29:30], v[29:30], 16
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_alignbit_b32 v30, v31, v30, 16
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v33
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; SI-NEXT: v_alignbit_b32 v31, v32, v31, 16
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v33
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_lshr_b64 v[32:33], v[32:33], 16
+; SI-NEXT: v_lshr_b64 v[30:31], v[30:31], 16
+; SI-NEXT: v_mov_b32_e32 v31, v32
; SI-NEXT: .LBB79_5: ; %end
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
@@ -137847,36 +138655,39 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; VI-NEXT: v_mov_b32_e32 v31, v17
; VI-NEXT: v_mov_b32_e32 v30, v16
; VI-NEXT: v_mov_b32_e32 v29, v15
-; VI-NEXT: v_mov_b32_e32 v28, v14
; VI-NEXT: v_mov_b32_e32 v27, v13
-; VI-NEXT: v_mov_b32_e32 v26, v12
; VI-NEXT: v_mov_b32_e32 v25, v11
-; VI-NEXT: v_mov_b32_e32 v24, v10
; VI-NEXT: v_mov_b32_e32 v23, v9
-; VI-NEXT: v_mov_b32_e32 v22, v8
; VI-NEXT: v_mov_b32_e32 v21, v7
-; VI-NEXT: v_mov_b32_e32 v20, v6
; VI-NEXT: v_mov_b32_e32 v19, v5
-; VI-NEXT: v_mov_b32_e32 v32, v4
; VI-NEXT: v_mov_b32_e32 v17, v3
-; VI-NEXT: v_mov_b32_e32 v16, v2
; VI-NEXT: v_mov_b32_e32 v15, v1
+; VI-NEXT: v_mov_b32_e32 v28, v14
+; VI-NEXT: v_mov_b32_e32 v26, v12
+; VI-NEXT: v_mov_b32_e32 v24, v10
+; VI-NEXT: v_mov_b32_e32 v22, v8
+; VI-NEXT: v_mov_b32_e32 v20, v6
+; VI-NEXT: v_mov_b32_e32 v32, v4
+; VI-NEXT: v_mov_b32_e32 v16, v2
; VI-NEXT: v_mov_b32_e32 v14, v0
-; VI-NEXT: v_mov_b32_e32 v0, s16
-; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-NEXT: v_mov_b32_e32 v2, s18
+; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v3, s19
-; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v5, s21
-; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v7, s23
-; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v9, s25
-; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v11, s27
-; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v13, s29
+; VI-NEXT: v_mov_b32_e32 v0, s16
+; VI-NEXT: v_mov_b32_e32 v2, s18
+; VI-NEXT: v_mov_b32_e32 v4, s20
+; VI-NEXT: v_mov_b32_e32 v6, s22
+; VI-NEXT: v_mov_b32_e32 v8, s24
+; VI-NEXT: v_mov_b32_e32 v10, s26
+; VI-NEXT: v_mov_b32_e32 v12, s28
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB79_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB79_3
@@ -137885,580 +138696,600 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v15, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v15
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
-; VI-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_alignbit_b32 v15, v15, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v15, v18, v34, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v15
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v14, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v14
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v14
+; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[33:34]
+; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_bfe_u32 v15, v14, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
-; VI-NEXT: v_cndmask_b32_e32 v14, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; VI-NEXT: v_alignbit_b32 v14, v14, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v13
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v14, v15, v18, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v14
+; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[35:36]
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v13
+; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v13, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v13
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v13
+; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
-; VI-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; VI-NEXT: v_alignbit_b32 v13, v13, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v13, v15, v18, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v12
+; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v12, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v12
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v12
+; VI-NEXT: v_lshrrev_b64 v[35:36], 16, v[35:36]
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_bfe_u32 v13, v12, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
-; VI-NEXT: v_cndmask_b32_e32 v12, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_alignbit_b32 v12, v12, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v11
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v12, v13, v15, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v12
+; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[36:37]
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v11, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v11
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v11
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
-; VI-NEXT: v_cndmask_b32_e32 v11, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; VI-NEXT: v_alignbit_b32 v11, v11, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v11, v13, v15, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v11
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v10
+; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v10, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v10
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v10
+; VI-NEXT: v_lshrrev_b64 v[36:37], 16, v[36:37]
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: v_bfe_u32 v11, v10, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
-; VI-NEXT: v_cndmask_b32_e32 v10, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_alignbit_b32 v10, v10, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v9
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v10, v11, v13, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v10
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[37:38]
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v9
+; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v9, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v9
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v9
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
-; VI-NEXT: v_cndmask_b32_e32 v9, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_alignbit_b32 v9, v9, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v8
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v8
+; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v8, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v8
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v8
+; VI-NEXT: v_lshrrev_b64 v[37:38], 16, v[37:38]
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
-; VI-NEXT: v_cndmask_b32_e32 v8, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_alignbit_b32 v8, v8, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v7
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[38:39]
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v7
+; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v7, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v7
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v7
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; VI-NEXT: v_cndmask_b32_e32 v7, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_alignbit_b32 v7, v7, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v6, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v6
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v6
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_bfe_u32 v7, v6, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
-; VI-NEXT: v_cndmask_b32_e32 v6, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_alignbit_b32 v6, v6, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v6, v7, v9, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[48:49]
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v5, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v5
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v5
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: v_cndmask_b32_e32 v5, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_alignbit_b32 v5, v5, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v4
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v4
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v4
+; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[48:49]
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_alignbit_b32 v4, v4, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v3
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v4
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[49:50]
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v3
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v3
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v3, v3, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v2
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v2
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v2
+; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50]
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_alignbit_b32 v2, v2, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v1
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v2
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[50:51]
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v1
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_alignbit_b32 v1, v1, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v0
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0
+; VI-NEXT: v_lshrrev_b64 v[50:51], 16, v[50:51]
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v31
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v31, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v31
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v31
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
-; VI-NEXT: v_cndmask_b32_e32 v31, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_alignbit_b32 v31, v31, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v30
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v30, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v30
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v30
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
-; VI-NEXT: v_cndmask_b32_e32 v30, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_alignbit_b32 v30, v30, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v29
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v29, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v29
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v29
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
-; VI-NEXT: v_cndmask_b32_e32 v29, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_alignbit_b32 v29, v29, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v28
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v28, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v28
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v28
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
-; VI-NEXT: v_cndmask_b32_e32 v28, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_alignbit_b32 v28, v28, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v27
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v27, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v27
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v27
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
-; VI-NEXT: v_cndmask_b32_e32 v27, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; VI-NEXT: v_alignbit_b32 v27, v27, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v26
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v26, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v26
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v26
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
-; VI-NEXT: v_cndmask_b32_e32 v26, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_alignbit_b32 v26, v26, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v25, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v25
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v25
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
-; VI-NEXT: v_cndmask_b32_e32 v25, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; VI-NEXT: v_alignbit_b32 v25, v25, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v24
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v24, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v24
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v24
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
-; VI-NEXT: v_cndmask_b32_e32 v24, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_alignbit_b32 v24, v24, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v23
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v23, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v23
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v23
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
-; VI-NEXT: v_cndmask_b32_e32 v23, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_alignbit_b32 v23, v23, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v22
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v22, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v22
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v22
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
-; VI-NEXT: v_cndmask_b32_e32 v22, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_alignbit_b32 v22, v22, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v21
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v21, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v21
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v21
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
-; VI-NEXT: v_cndmask_b32_e32 v21, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_alignbit_b32 v21, v21, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v20
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v20, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v20
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v20
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
-; VI-NEXT: v_cndmask_b32_e32 v20, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_alignbit_b32 v20, v20, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v19, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v19
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v19
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
-; VI-NEXT: v_cndmask_b32_e32 v19, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_alignbit_b32 v19, v19, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v32
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
-; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; VI-NEXT: v_alignbit_b32 v32, v32, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v17
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v17, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v17
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v17
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
-; VI-NEXT: v_cndmask_b32_e32 v17, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_alignbit_b32 v17, v17, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v16
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v16
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_cndmask_b32_e32 v16, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_alignbit_b32 v16, v16, v18, 16
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v0
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[51:52]
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v31
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v30
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v30
+; VI-NEXT: v_lshrrev_b64 v[51:52], 16, v[51:52]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v29
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v29
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[30:31], 16, v[52:53]
+; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v28
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
+; VI-NEXT: v_lshrrev_b64 v[52:53], 16, v[52:53]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v27
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v27
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[28:29], 16, v[53:54]
+; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v26
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v26
+; VI-NEXT: v_lshrrev_b64 v[53:54], 16, v[53:54]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v25
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[26:27], 16, v[54:55]
+; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v24
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v24
+; VI-NEXT: v_lshrrev_b64 v[38:39], 16, v[38:39]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v23
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v23
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[24:25], 16, v[39:40]
+; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v22
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
+; VI-NEXT: v_lshrrev_b64 v[39:40], 16, v[39:40]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v21
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[22:23], 16, v[40:41]
+; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v20
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v20
+; VI-NEXT: v_lshrrev_b64 v[40:41], 16, v[40:41]
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v19
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v18, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v32
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v31, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v17
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v17
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[41:42]
+; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v16
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16
+; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; VI-NEXT: v_cndmask_b32_e32 v15, v3, v5, vcc
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b64 v[54:55], 16, v[54:55]
+; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19]
+; VI-NEXT: v_lshrrev_b64 v[41:42], 16, v[41:42]
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[31:32]
+; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[15:16]
+; VI-NEXT: v_mov_b32_e32 v1, v50
+; VI-NEXT: v_mov_b32_e32 v3, v49
+; VI-NEXT: v_mov_b32_e32 v5, v48
+; VI-NEXT: v_mov_b32_e32 v7, v38
+; VI-NEXT: v_mov_b32_e32 v9, v37
+; VI-NEXT: v_mov_b32_e32 v11, v36
+; VI-NEXT: v_mov_b32_e32 v13, v35
+; VI-NEXT: v_mov_b32_e32 v15, v34
+; VI-NEXT: v_mov_b32_e32 v17, v41
+; VI-NEXT: v_mov_b32_e32 v19, v18
+; VI-NEXT: v_mov_b32_e32 v21, v40
+; VI-NEXT: v_mov_b32_e32 v23, v39
+; VI-NEXT: v_mov_b32_e32 v25, v54
+; VI-NEXT: v_mov_b32_e32 v27, v53
+; VI-NEXT: v_mov_b32_e32 v29, v52
+; VI-NEXT: v_mov_b32_e32 v31, v51
; VI-NEXT: .LBB79_3: ; %end
+; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v18, v32
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB79_4:
; VI-NEXT: s_branch .LBB79_2
@@ -154017,6 +154848,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:332
@@ -154027,14 +154859,13 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:312
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:308
; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:304
-; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
-; SI-NEXT: s_mov_b32 s72, s21
+; SI-NEXT: ; implicit-def: $vgpr44 : SGPR spill to VGPR lane
+; SI-NEXT: s_mov_b32 s73, s21
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_writelane_b32 v43, s19, 0
-; SI-NEXT: v_writelane_b32 v43, s18, 1
-; SI-NEXT: v_writelane_b32 v43, s17, 2
-; SI-NEXT: v_writelane_b32 v43, s16, 3
-; SI-NEXT: s_mov_b32 s60, s24
+; SI-NEXT: v_writelane_b32 v44, s19, 0
+; SI-NEXT: v_writelane_b32 v44, s18, 1
+; SI-NEXT: v_writelane_b32 v44, s17, 2
+; SI-NEXT: v_writelane_b32 v44, s16, 3
; SI-NEXT: v_writelane_b32 v41, s30, 0
; SI-NEXT: v_writelane_b32 v41, s31, 1
; SI-NEXT: v_writelane_b32 v41, s34, 2
@@ -154059,7 +154890,8 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: v_writelane_b32 v41, s69, 21
; SI-NEXT: v_writelane_b32 v41, s70, 22
; SI-NEXT: v_writelane_b32 v41, s71, 23
-; SI-NEXT: s_mov_b32 s77, s28
+; SI-NEXT: s_mov_b32 s74, s29
+; SI-NEXT: s_mov_b32 s78, s28
; SI-NEXT: s_mov_b32 s76, s27
; SI-NEXT: v_writelane_b32 v41, s80, 24
; SI-NEXT: v_writelane_b32 v41, s81, 25
@@ -154073,35 +154905,35 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: v_writelane_b32 v41, s97, 33
; SI-NEXT: v_writelane_b32 v41, s98, 34
; SI-NEXT: v_writelane_b32 v41, s99, 35
-; SI-NEXT: s_mov_b32 s79, s26
+; SI-NEXT: s_mov_b32 s47, s26
+; SI-NEXT: v_readfirstlane_b32 s37, v22
+; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
; SI-NEXT: v_readfirstlane_b32 s38, v20
-; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
+; SI-NEXT: v_writelane_b32 v43, s37, 0
; SI-NEXT: v_readfirstlane_b32 s39, v19
-; SI-NEXT: v_writelane_b32 v42, s38, 0
+; SI-NEXT: v_writelane_b32 v43, s38, 1
; SI-NEXT: v_readfirstlane_b32 s48, v25
-; SI-NEXT: v_writelane_b32 v42, s39, 1
+; SI-NEXT: v_writelane_b32 v43, s39, 2
; SI-NEXT: v_readfirstlane_b32 s49, v26
-; SI-NEXT: v_writelane_b32 v42, s48, 2
+; SI-NEXT: v_writelane_b32 v43, s48, 3
; SI-NEXT: v_readfirstlane_b32 s50, v24
-; SI-NEXT: v_writelane_b32 v42, s49, 3
+; SI-NEXT: v_writelane_b32 v43, s49, 4
; SI-NEXT: v_readfirstlane_b32 s51, v23
-; SI-NEXT: v_writelane_b32 v42, s50, 4
+; SI-NEXT: v_writelane_b32 v43, s50, 5
; SI-NEXT: v_readfirstlane_b32 s52, v29
-; SI-NEXT: v_writelane_b32 v42, s51, 5
+; SI-NEXT: v_writelane_b32 v43, s51, 6
; SI-NEXT: v_readfirstlane_b32 s53, v30
-; SI-NEXT: v_writelane_b32 v42, s52, 6
+; SI-NEXT: v_writelane_b32 v43, s52, 7
; SI-NEXT: v_readfirstlane_b32 s54, v28
-; SI-NEXT: v_writelane_b32 v42, s53, 7
+; SI-NEXT: v_writelane_b32 v43, s53, 8
; SI-NEXT: v_readfirstlane_b32 s55, v27
-; SI-NEXT: v_writelane_b32 v42, s54, 8
-; SI-NEXT: v_writelane_b32 v42, s55, 9
+; SI-NEXT: v_writelane_b32 v43, s54, 9
+; SI-NEXT: v_writelane_b32 v43, s55, 10
+; SI-NEXT: s_mov_b32 s57, s24
; SI-NEXT: v_readfirstlane_b32 s16, v1
; SI-NEXT: v_readfirstlane_b32 s17, v2
; SI-NEXT: v_readfirstlane_b32 s18, v5
; SI-NEXT: v_readfirstlane_b32 s19, v6
-; SI-NEXT: v_readfirstlane_b32 s88, v4
-; SI-NEXT: v_readfirstlane_b32 s89, v3
-; SI-NEXT: v_readfirstlane_b32 s90, v9
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_readfirstlane_b32 s6, v31
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:300
@@ -154112,31 +154944,34 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:280
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s4, v32
-; SI-NEXT: v_writelane_b32 v43, s4, 4
+; SI-NEXT: v_writelane_b32 v44, s4, 4
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_readfirstlane_b32 s4, v33
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:276
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:272
-; SI-NEXT: v_writelane_b32 v43, s4, 5
+; SI-NEXT: v_writelane_b32 v44, s4, 5
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s4, v34
-; SI-NEXT: v_writelane_b32 v43, s4, 6
+; SI-NEXT: v_writelane_b32 v44, s4, 6
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_readfirstlane_b32 s4, v35
-; SI-NEXT: v_writelane_b32 v43, s4, 7
+; SI-NEXT: v_writelane_b32 v44, s4, 7
; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_readfirstlane_b32 s4, v36
-; SI-NEXT: v_writelane_b32 v43, s4, 8
+; SI-NEXT: v_writelane_b32 v44, s4, 8
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_readfirstlane_b32 s4, v37
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:268
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:264
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:260
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:256
-; SI-NEXT: v_writelane_b32 v43, s4, 9
+; SI-NEXT: v_writelane_b32 v44, s4, 9
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s4, v38
-; SI-NEXT: v_writelane_b32 v43, s4, 10
+; SI-NEXT: v_writelane_b32 v44, s4, 10
+; SI-NEXT: v_readfirstlane_b32 s77, v4
+; SI-NEXT: v_readfirstlane_b32 s89, v3
+; SI-NEXT: v_readfirstlane_b32 s90, v9
; SI-NEXT: v_readfirstlane_b32 s91, v10
; SI-NEXT: v_readfirstlane_b32 s92, v8
; SI-NEXT: v_readfirstlane_b32 s93, v7
@@ -154147,22 +154982,21 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: v_readfirstlane_b32 s34, v16
; SI-NEXT: v_readfirstlane_b32 s35, v15
; SI-NEXT: v_readfirstlane_b32 s36, v21
-; SI-NEXT: v_readfirstlane_b32 s37, v22
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_readfirstlane_b32 s4, v31
-; SI-NEXT: v_writelane_b32 v43, s4, 11
+; SI-NEXT: v_writelane_b32 v44, s4, 11
; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_readfirstlane_b32 s4, v39
-; SI-NEXT: v_writelane_b32 v43, s4, 12
+; SI-NEXT: v_writelane_b32 v44, s4, 12
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_readfirstlane_b32 s4, v48
-; SI-NEXT: v_writelane_b32 v43, s4, 13
+; SI-NEXT: v_writelane_b32 v44, s4, 13
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_readfirstlane_b32 s4, v49
-; SI-NEXT: v_writelane_b32 v43, s4, 14
+; SI-NEXT: v_writelane_b32 v44, s4, 14
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_readfirstlane_b32 s4, v50
-; SI-NEXT: v_writelane_b32 v43, s4, 15
+; SI-NEXT: v_writelane_b32 v44, s4, 15
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_readfirstlane_b32 s4, v51
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:252
@@ -154175,33 +155009,33 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s75, v32
; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_readfirstlane_b32 s61, v33
+; SI-NEXT: v_readfirstlane_b32 s21, v33
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:224
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:220
-; SI-NEXT: v_writelane_b32 v43, s4, 16
+; SI-NEXT: v_writelane_b32 v44, s4, 16
; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_readfirstlane_b32 s43, v34
+; SI-NEXT: v_readfirstlane_b32 s4, v34
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_readfirstlane_b32 s40, v35
; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_readfirstlane_b32 s4, v36
+; SI-NEXT: v_readfirstlane_b32 s61, v36
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_readfirstlane_b32 s63, v37
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:216
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:212
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:208
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:204
-; SI-NEXT: v_writelane_b32 v43, s4, 17
+; SI-NEXT: v_writelane_b32 v44, s4, 17
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s59, v31
; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_readfirstlane_b32 s42, v38
+; SI-NEXT: v_readfirstlane_b32 s56, v38
; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_readfirstlane_b32 s73, v39
+; SI-NEXT: v_readfirstlane_b32 s43, v39
; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_readfirstlane_b32 s21, v48
+; SI-NEXT: v_readfirstlane_b32 s46, v48
; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_readfirstlane_b32 s57, v49
+; SI-NEXT: v_readfirstlane_b32 s42, v49
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_readfirstlane_b32 s13, v50
; SI-NEXT: s_waitcnt vmcnt(6)
@@ -154214,9 +155048,9 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:180
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:176
; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_readfirstlane_b32 s47, v32
+; SI-NEXT: v_readfirstlane_b32 s88, v32
; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_readfirstlane_b32 s24, v33
+; SI-NEXT: v_readfirstlane_b32 s79, v33
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:172
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:168
; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:164
@@ -154225,35 +155059,36 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:152
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_readfirstlane_b32 s78, v34
+; SI-NEXT: v_readfirstlane_b32 s4, v34
+; SI-NEXT: v_writelane_b32 v44, s4, 18
; SI-NEXT: v_readfirstlane_b32 s4, v35
-; SI-NEXT: v_writelane_b32 v43, s4, 18
+; SI-NEXT: v_writelane_b32 v44, s4, 19
; SI-NEXT: v_readfirstlane_b32 s4, v36
-; SI-NEXT: v_writelane_b32 v43, s4, 19
+; SI-NEXT: v_writelane_b32 v44, s4, 20
; SI-NEXT: s_waitcnt vmcnt(13)
; SI-NEXT: v_readfirstlane_b32 s4, v37
-; SI-NEXT: v_writelane_b32 v43, s4, 20
+; SI-NEXT: v_writelane_b32 v44, s4, 21
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s4, v31
-; SI-NEXT: v_writelane_b32 v43, s4, 21
+; SI-NEXT: v_writelane_b32 v44, s4, 22
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_readfirstlane_b32 s4, v38
-; SI-NEXT: v_writelane_b32 v43, s4, 22
+; SI-NEXT: v_writelane_b32 v44, s4, 23
; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_readfirstlane_b32 s4, v39
-; SI-NEXT: v_writelane_b32 v43, s4, 23
+; SI-NEXT: v_writelane_b32 v44, s4, 24
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_readfirstlane_b32 s4, v48
-; SI-NEXT: v_writelane_b32 v43, s4, 24
+; SI-NEXT: v_writelane_b32 v44, s4, 25
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_readfirstlane_b32 s4, v49
-; SI-NEXT: v_writelane_b32 v43, s4, 25
+; SI-NEXT: v_writelane_b32 v44, s4, 26
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_readfirstlane_b32 s4, v50
-; SI-NEXT: v_writelane_b32 v43, s4, 26
+; SI-NEXT: v_writelane_b32 v44, s4, 27
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_readfirstlane_b32 s4, v51
-; SI-NEXT: v_writelane_b32 v43, s4, 27
+; SI-NEXT: v_writelane_b32 v44, s4, 28
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:148
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:144
; SI-NEXT: s_waitcnt vmcnt(7)
@@ -154269,43 +155104,43 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:112
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:108
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:104
-; SI-NEXT: v_writelane_b32 v43, s4, 28
+; SI-NEXT: v_writelane_b32 v44, s4, 29
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_readfirstlane_b32 s4, v52
-; SI-NEXT: v_writelane_b32 v43, s4, 29
+; SI-NEXT: v_writelane_b32 v44, s4, 30
; SI-NEXT: v_readfirstlane_b32 s4, v53
-; SI-NEXT: v_writelane_b32 v43, s4, 30
+; SI-NEXT: v_writelane_b32 v44, s4, 31
; SI-NEXT: v_readfirstlane_b32 s4, v54
-; SI-NEXT: v_writelane_b32 v43, s4, 31
+; SI-NEXT: v_writelane_b32 v44, s4, 32
; SI-NEXT: v_readfirstlane_b32 s4, v55
-; SI-NEXT: v_writelane_b32 v43, s4, 32
+; SI-NEXT: v_writelane_b32 v44, s4, 33
+; SI-NEXT: v_writelane_b32 v44, s22, 34
+; SI-NEXT: v_writelane_b32 v44, s23, 35
+; SI-NEXT: v_writelane_b32 v44, s73, 36
+; SI-NEXT: v_writelane_b32 v44, s20, 37
+; SI-NEXT: v_writelane_b32 v44, s47, 38
+; SI-NEXT: v_writelane_b32 v44, s76, 39
+; SI-NEXT: v_writelane_b32 v44, s25, 40
+; SI-NEXT: v_writelane_b32 v44, s57, 41
+; SI-NEXT: v_writelane_b32 v44, s74, 42
; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_readfirstlane_b32 s4, v40
-; SI-NEXT: v_writelane_b32 v43, s4, 33
-; SI-NEXT: v_writelane_b32 v43, s22, 34
-; SI-NEXT: v_writelane_b32 v43, s23, 35
-; SI-NEXT: v_writelane_b32 v43, s72, 36
-; SI-NEXT: v_writelane_b32 v43, s20, 37
-; SI-NEXT: v_writelane_b32 v43, s79, 38
-; SI-NEXT: v_writelane_b32 v43, s76, 39
-; SI-NEXT: v_writelane_b32 v43, s25, 40
-; SI-NEXT: v_writelane_b32 v43, s60, 41
-; SI-NEXT: v_writelane_b32 v43, s29, 42
-; SI-NEXT: v_writelane_b32 v43, s77, 43
-; SI-NEXT: v_writelane_b32 v43, s16, 44
-; SI-NEXT: v_writelane_b32 v43, s17, 45
-; SI-NEXT: v_writelane_b32 v43, s18, 46
-; SI-NEXT: v_writelane_b32 v43, s19, 47
-; SI-NEXT: v_writelane_b32 v43, s88, 48
-; SI-NEXT: v_writelane_b32 v43, s89, 49
-; SI-NEXT: v_writelane_b32 v43, s90, 50
-; SI-NEXT: v_writelane_b32 v43, s91, 51
-; SI-NEXT: v_writelane_b32 v43, s92, 52
-; SI-NEXT: v_writelane_b32 v43, s93, 53
-; SI-NEXT: v_writelane_b32 v43, s94, 54
-; SI-NEXT: v_writelane_b32 v43, s95, 55
+; SI-NEXT: v_readfirstlane_b32 s24, v40
+; SI-NEXT: v_writelane_b32 v44, s78, 43
+; SI-NEXT: v_writelane_b32 v44, s24, 44
+; SI-NEXT: v_writelane_b32 v44, s16, 45
+; SI-NEXT: v_writelane_b32 v44, s17, 46
+; SI-NEXT: v_writelane_b32 v44, s18, 47
+; SI-NEXT: v_writelane_b32 v44, s19, 48
+; SI-NEXT: v_writelane_b32 v44, s77, 49
+; SI-NEXT: v_writelane_b32 v44, s89, 50
+; SI-NEXT: v_writelane_b32 v44, s90, 51
+; SI-NEXT: v_writelane_b32 v44, s91, 52
+; SI-NEXT: v_writelane_b32 v44, s92, 53
+; SI-NEXT: v_writelane_b32 v44, s93, 54
+; SI-NEXT: v_writelane_b32 v44, s94, 55
+; SI-NEXT: v_writelane_b32 v44, s95, 56
; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_readfirstlane_b32 s62, v33
+; SI-NEXT: v_readfirstlane_b32 s58, v33
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_readfirstlane_b32 s10, v34
; SI-NEXT: s_waitcnt vmcnt(8)
@@ -154313,7 +155148,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: v_readfirstlane_b32 s28, v31
; SI-NEXT: v_readfirstlane_b32 s27, v32
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_readfirstlane_b32 s58, v36
+; SI-NEXT: v_readfirstlane_b32 s29, v36
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_readfirstlane_b32 s69, v37
; SI-NEXT: s_waitcnt vmcnt(5)
@@ -154344,32 +155179,31 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 vcc_lo, v12
; SI-NEXT: v_readfirstlane_b32 vcc_hi, v11
-; SI-NEXT: v_writelane_b32 v43, vcc_lo, 56
-; SI-NEXT: v_writelane_b32 v43, vcc_hi, 57
-; SI-NEXT: v_writelane_b32 v43, s30, 58
-; SI-NEXT: v_writelane_b32 v43, s31, 59
-; SI-NEXT: v_writelane_b32 v43, s34, 60
-; SI-NEXT: v_writelane_b32 v43, s35, 61
-; SI-NEXT: v_writelane_b32 v43, s36, 62
-; SI-NEXT: v_writelane_b32 v43, s37, 63
+; SI-NEXT: v_writelane_b32 v44, vcc_lo, 57
+; SI-NEXT: v_writelane_b32 v44, vcc_hi, 58
+; SI-NEXT: v_writelane_b32 v44, s30, 59
+; SI-NEXT: v_writelane_b32 v44, s31, 60
+; SI-NEXT: v_writelane_b32 v44, s34, 61
+; SI-NEXT: v_writelane_b32 v44, s35, 62
+; SI-NEXT: v_writelane_b32 v44, s36, 63
; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_readfirstlane_b32 s74, v31
+; SI-NEXT: v_readfirstlane_b32 s60, v31
; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_readfirstlane_b32 s46, v32
+; SI-NEXT: v_readfirstlane_b32 s62, v32
; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_readfirstlane_b32 s96, v33
+; SI-NEXT: v_readfirstlane_b32 s83, v33
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_readfirstlane_b32 s98, v34
; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_readfirstlane_b32 s41, v35
+; SI-NEXT: v_readfirstlane_b32 s81, v35
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_readfirstlane_b32 s56, v36
+; SI-NEXT: v_readfirstlane_b32 s72, v36
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_readfirstlane_b32 s87, v37
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_readfirstlane_b32 s99, v38
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_readfirstlane_b32 s81, v39
+; SI-NEXT: v_readfirstlane_b32 s82, v39
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:48
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:44
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:40
@@ -154381,9 +155215,9 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_readfirstlane_b32 s26, v48
; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_readfirstlane_b32 s83, v49
+; SI-NEXT: v_readfirstlane_b32 s15, v49
; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_readfirstlane_b32 s82, v50
+; SI-NEXT: v_readfirstlane_b32 s96, v50
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_readfirstlane_b32 s7, v51
; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:16
@@ -154392,7 +155226,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_readfirstlane_b32 s15, v31
+; SI-NEXT: v_readfirstlane_b32 s41, v31
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_readfirstlane_b32 s97, v32
; SI-NEXT: s_waitcnt vmcnt(10)
@@ -154413,144 +155247,146 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: v_readfirstlane_b32 s65, v48
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_readfirstlane_b32 s64, v49
-; SI-NEXT: v_writelane_b32 v42, s64, 10
+; SI-NEXT: v_writelane_b32 v43, s64, 11
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_readfirstlane_b32 s67, v50
-; SI-NEXT: v_writelane_b32 v42, s65, 11
+; SI-NEXT: v_writelane_b32 v43, s65, 12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s84, v51
-; SI-NEXT: v_writelane_b32 v42, s67, 12
-; SI-NEXT: v_writelane_b32 v42, s84, 13
-; SI-NEXT: v_writelane_b32 v42, s85, 14
-; SI-NEXT: v_writelane_b32 v42, s86, 15
-; SI-NEXT: v_writelane_b32 v42, s87, 16
-; SI-NEXT: v_writelane_b32 v42, s8, 17
-; SI-NEXT: v_writelane_b32 v42, s99, 18
-; SI-NEXT: v_writelane_b32 v42, s12, 19
-; SI-NEXT: v_writelane_b32 v42, s44, 20
-; SI-NEXT: v_writelane_b32 v42, s97, 21
-; SI-NEXT: v_writelane_b32 v42, s83, 22
-; SI-NEXT: v_writelane_b32 v42, s82, 23
-; SI-NEXT: v_writelane_b32 v42, s98, 24
-; SI-NEXT: v_writelane_b32 v42, s96, 25
-; SI-NEXT: v_writelane_b32 v42, s81, 26
-; SI-NEXT: v_writelane_b32 v42, s9, 27
-; SI-NEXT: v_writelane_b32 v42, s41, 28
-; SI-NEXT: v_writelane_b32 v42, s80, 29
-; SI-NEXT: v_writelane_b32 v42, s7, 30
-; SI-NEXT: v_writelane_b32 v42, s56, 31
-; SI-NEXT: v_writelane_b32 v42, s26, 32
-; SI-NEXT: v_writelane_b32 v42, s15, 33
-; SI-NEXT: v_writelane_b32 v42, s14, 34
-; SI-NEXT: v_writelane_b32 v42, s69, 35
-; SI-NEXT: v_writelane_b32 v42, s71, 36
-; SI-NEXT: v_writelane_b32 v42, s70, 37
-; SI-NEXT: v_writelane_b32 v42, s68, 38
-; SI-NEXT: v_writelane_b32 v42, s74, 39
-; SI-NEXT: v_writelane_b32 v42, s46, 40
-; SI-NEXT: v_writelane_b32 v42, s11, 41
-; SI-NEXT: v_writelane_b32 v42, s10, 42
-; SI-NEXT: v_writelane_b32 v42, s62, 43
-; SI-NEXT: v_writelane_b32 v42, s66, 44
-; SI-NEXT: v_writelane_b32 v42, s58, 45
-; SI-NEXT: v_writelane_b32 v42, s28, 46
-; SI-NEXT: v_writelane_b32 v42, s27, 47
-; SI-NEXT: v_writelane_b32 v42, s78, 48
-; SI-NEXT: v_writelane_b32 v42, s24, 49
+; SI-NEXT: v_writelane_b32 v43, s67, 13
+; SI-NEXT: v_writelane_b32 v43, s84, 14
+; SI-NEXT: v_writelane_b32 v43, s85, 15
+; SI-NEXT: v_writelane_b32 v43, s86, 16
+; SI-NEXT: v_writelane_b32 v43, s87, 17
+; SI-NEXT: v_writelane_b32 v43, s8, 18
+; SI-NEXT: v_writelane_b32 v43, s99, 19
+; SI-NEXT: v_writelane_b32 v43, s12, 20
+; SI-NEXT: v_writelane_b32 v43, s44, 21
+; SI-NEXT: v_writelane_b32 v43, s97, 22
+; SI-NEXT: v_writelane_b32 v43, s15, 23
+; SI-NEXT: v_writelane_b32 v43, s96, 24
+; SI-NEXT: v_writelane_b32 v43, s98, 25
+; SI-NEXT: v_writelane_b32 v43, s83, 26
+; SI-NEXT: v_writelane_b32 v43, s82, 27
+; SI-NEXT: v_writelane_b32 v43, s9, 28
+; SI-NEXT: v_writelane_b32 v43, s81, 29
+; SI-NEXT: v_writelane_b32 v43, s80, 30
+; SI-NEXT: v_writelane_b32 v43, s7, 31
+; SI-NEXT: v_writelane_b32 v43, s72, 32
+; SI-NEXT: v_writelane_b32 v43, s26, 33
+; SI-NEXT: v_writelane_b32 v43, s41, 34
+; SI-NEXT: v_writelane_b32 v43, s14, 35
+; SI-NEXT: v_writelane_b32 v43, s69, 36
+; SI-NEXT: v_writelane_b32 v43, s71, 37
+; SI-NEXT: v_writelane_b32 v43, s70, 38
+; SI-NEXT: v_writelane_b32 v43, s68, 39
+; SI-NEXT: v_writelane_b32 v43, s60, 40
+; SI-NEXT: v_writelane_b32 v43, s62, 41
+; SI-NEXT: v_writelane_b32 v43, s11, 42
+; SI-NEXT: v_writelane_b32 v43, s10, 43
+; SI-NEXT: v_writelane_b32 v43, s58, 44
+; SI-NEXT: v_writelane_b32 v43, s66, 45
+; SI-NEXT: v_writelane_b32 v43, s29, 46
+; SI-NEXT: v_writelane_b32 v43, s28, 47
+; SI-NEXT: v_writelane_b32 v43, s27, 48
; SI-NEXT: s_cbranch_scc0 .LBB89_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_readlane_b32 s4, v43, 3
+; SI-NEXT: v_readlane_b32 s4, v44, 3
; SI-NEXT: s_and_b32 s4, s4, 0xff
-; SI-NEXT: v_readlane_b32 s5, v43, 2
+; SI-NEXT: v_readlane_b32 s5, v44, 2
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_lshl_b32 s5, s5, 24
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: v_writelane_b32 v42, s4, 56
-; SI-NEXT: v_readlane_b32 s4, v43, 1
+; SI-NEXT: v_writelane_b32 v43, s4, 58
+; SI-NEXT: v_readlane_b32 s4, v44, 1
; SI-NEXT: s_and_b32 s4, s4, 0xff
-; SI-NEXT: v_readlane_b32 s5, v43, 0
+; SI-NEXT: v_readlane_b32 s5, v44, 0
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_lshl_b32 s5, s5, 24
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: v_writelane_b32 v42, s4, 57
+; SI-NEXT: v_writelane_b32 v43, s4, 59
; SI-NEXT: s_and_b32 s4, s20, 0xff
-; SI-NEXT: s_lshl_b32 s5, s72, 8
+; SI-NEXT: s_lshl_b32 s5, s73, 8
; SI-NEXT: s_or_b32 s4, s4, s5
; SI-NEXT: s_and_b32 s5, s22, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_mov_b32 s22, s6
; SI-NEXT: s_lshl_b32 s6, s23, 24
-; SI-NEXT: v_writelane_b32 v42, s4, 58
+; SI-NEXT: v_writelane_b32 v43, s4, 60
; SI-NEXT: s_or_b32 s4, s6, s5
-; SI-NEXT: s_and_b32 s5, s60, 0xff
+; SI-NEXT: s_and_b32 s5, s57, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_lshl_b32 s6, s25, 24
-; SI-NEXT: v_writelane_b32 v42, s4, 59
-; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: v_writelane_b32 v42, s5, 60
-; SI-NEXT: s_and_b32 s5, s79, 0xff
+; SI-NEXT: v_writelane_b32 v43, s4, 61
+; SI-NEXT: s_or_b32 s4, s6, s5
+; SI-NEXT: s_and_b32 s5, s47, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_lshl_b32 s6, s76, 24
-; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: v_writelane_b32 v42, s5, 61
-; SI-NEXT: s_and_b32 s5, s77, 0xff
-; SI-NEXT: s_lshl_b32 s6, s29, 8
+; SI-NEXT: v_writelane_b32 v43, s4, 62
+; SI-NEXT: s_or_b32 s4, s6, s5
+; SI-NEXT: s_and_b32 s5, s78, 0xff
+; SI-NEXT: s_lshl_b32 s6, s74, 8
; SI-NEXT: s_or_b32 s5, s5, s6
; SI-NEXT: s_and_b32 s6, s16, 0xff
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s16, s17, 24
-; SI-NEXT: s_or_b32 s6, s16, s6
-; SI-NEXT: v_writelane_b32 v42, s6, 62
+; SI-NEXT: v_writelane_b32 v43, s4, 63
+; SI-NEXT: s_or_b32 s4, s16, s6
; SI-NEXT: s_and_b32 s6, s89, 0xff
+; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: s_lshl_b32 s16, s88, 24
-; SI-NEXT: s_mov_b32 s4, s47
-; SI-NEXT: s_or_b32 s47, s16, s6
+; SI-NEXT: s_lshl_b32 s16, s77, 24
+; SI-NEXT: v_writelane_b32 v42, s4, 0
+; SI-NEXT: s_or_b32 s6, s16, s6
+; SI-NEXT: v_writelane_b32 v42, s6, 1
; SI-NEXT: s_and_b32 s6, s18, 0xff
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s16, s19, 24
-; SI-NEXT: s_or_b32 s25, s16, s6
+; SI-NEXT: s_or_b32 s76, s16, s6
; SI-NEXT: s_and_b32 s6, s93, 0xff
; SI-NEXT: s_lshl_b32 s16, s92, 8
; SI-NEXT: s_or_b32 s6, s6, s16
; SI-NEXT: s_and_b32 s16, s90, 0xff
; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_lshl_b32 s17, s91, 24
-; SI-NEXT: s_or_b32 s92, s17, s16
+; SI-NEXT: s_or_b32 s77, s17, s16
; SI-NEXT: s_and_b32 s16, vcc_hi, 0xff
; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_lshl_b32 s17, vcc_lo, 24
-; SI-NEXT: s_or_b32 s76, s17, s16
+; SI-NEXT: s_or_b32 s25, s17, s16
; SI-NEXT: s_and_b32 s16, s94, 0xff
; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_lshl_b32 s17, s95, 24
-; SI-NEXT: s_or_b32 s91, s17, s16
+; SI-NEXT: s_or_b32 s74, s17, s16
; SI-NEXT: s_and_b32 s16, s35, 0xff
; SI-NEXT: s_lshl_b32 s17, s34, 8
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s30, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s31, 24
-; SI-NEXT: s_or_b32 s77, s18, s17
+; SI-NEXT: s_or_b32 s78, s18, s17
; SI-NEXT: s_and_b32 s17, s39, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s38, 24
-; SI-NEXT: s_or_b32 s79, s18, s17
+; SI-NEXT: s_mov_b32 s31, s88
+; SI-NEXT: s_or_b32 s88, s18, s17
; SI-NEXT: s_and_b32 s17, s36, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s37, 24
-; SI-NEXT: s_or_b32 s93, s18, s17
+; SI-NEXT: s_or_b32 s89, s18, s17
; SI-NEXT: s_and_b32 s17, s51, 0xff
; SI-NEXT: s_lshl_b32 s18, s50, 8
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_and_b32 s18, s48, 0xff
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_lshl_b32 s19, s49, 24
-; SI-NEXT: s_or_b32 s89, s19, s18
+; SI-NEXT: s_or_b32 s18, s19, s18
+; SI-NEXT: v_writelane_b32 v43, s18, 49
; SI-NEXT: s_and_b32 s18, s55, 0xff
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_lshl_b32 s19, s54, 24
-; SI-NEXT: s_or_b32 s31, s19, s18
+; SI-NEXT: s_mov_b32 s73, s79
+; SI-NEXT: s_or_b32 s79, s19, s18
; SI-NEXT: s_and_b32 s18, s52, 0xff
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_lshl_b32 s19, s53, 24
@@ -154561,7 +155397,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_and_b32 s19, s64, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s65, 24
-; SI-NEXT: s_or_b32 s60, s20, s19
+; SI-NEXT: s_or_b32 s95, s20, s19
; SI-NEXT: s_and_b32 s19, s12, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s8, 24
@@ -154577,217 +155413,226 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s97, 24
; SI-NEXT: s_or_b32 s9, s20, s19
-; SI-NEXT: s_and_b32 s19, s15, 0xff
+; SI-NEXT: s_and_b32 s19, s41, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s7, 24
; SI-NEXT: s_or_b32 s7, s20, s19
-; SI-NEXT: s_and_b32 s19, s82, 0xff
+; SI-NEXT: s_and_b32 s19, s96, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_lshl_b32 s20, s83, 24
-; SI-NEXT: s_or_b32 s23, s20, s19
+; SI-NEXT: s_lshl_b32 s20, s15, 24
+; SI-NEXT: v_writelane_b32 v43, s12, 50
+; SI-NEXT: s_or_b32 s12, s20, s19
; SI-NEXT: s_and_b32 s19, s26, 0xff
-; SI-NEXT: s_lshl_b32 s20, s81, 8
+; SI-NEXT: s_lshl_b32 s20, s82, 8
; SI-NEXT: s_or_b32 vcc_hi, s19, s20
; SI-NEXT: s_and_b32 s19, s99, 0xff
-; SI-NEXT: v_writelane_b32 v42, s9, 50
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s87, 24
-; SI-NEXT: v_writelane_b32 v42, s7, 51
-; SI-NEXT: s_or_b32 s7, s20, s19
-; SI-NEXT: s_and_b32 s19, s56, 0xff
+; SI-NEXT: v_writelane_b32 v43, s9, 51
+; SI-NEXT: s_or_b32 s9, s20, s19
+; SI-NEXT: s_and_b32 s19, s72, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_lshl_b32 s20, s41, 24
-; SI-NEXT: v_writelane_b32 v42, s7, 52
-; SI-NEXT: s_or_b32 s7, s20, s19
+; SI-NEXT: s_lshl_b32 s20, s81, 24
+; SI-NEXT: v_writelane_b32 v43, s9, 52
+; SI-NEXT: s_or_b32 s9, s20, s19
; SI-NEXT: s_and_b32 s19, s98, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_lshl_b32 s20, s96, 24
-; SI-NEXT: v_writelane_b32 v42, s7, 54
-; SI-NEXT: s_or_b32 s7, s20, s19
-; SI-NEXT: s_and_b32 s19, s46, 0xff
-; SI-NEXT: s_lshl_b32 s20, s74, 8
+; SI-NEXT: s_lshl_b32 s20, s83, 24
+; SI-NEXT: v_writelane_b32 v43, s9, 54
+; SI-NEXT: s_or_b32 s9, s20, s19
+; SI-NEXT: s_and_b32 s19, s62, 0xff
+; SI-NEXT: s_lshl_b32 s20, s60, 8
; SI-NEXT: s_or_b32 s84, s19, s20
; SI-NEXT: s_and_b32 s19, s71, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s70, 24
-; SI-NEXT: s_or_b32 s72, s20, s19
+; SI-NEXT: v_writelane_b32 v43, s9, 53
+; SI-NEXT: s_or_b32 s9, s20, s19
; SI-NEXT: s_and_b32 s19, s11, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s68, 24
-; SI-NEXT: v_writelane_b32 v42, s7, 53
-; SI-NEXT: s_or_b32 s7, s20, s19
+; SI-NEXT: s_or_b32 s57, s20, s19
; SI-NEXT: s_and_b32 s19, s14, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s69, 24
+; SI-NEXT: v_writelane_b32 v43, s9, 55
; SI-NEXT: s_or_b32 s9, s20, s19
-; SI-NEXT: s_and_b32 s19, s58, 0xff
+; SI-NEXT: s_and_b32 s19, s29, 0xff
; SI-NEXT: s_lshl_b32 s20, s66, 8
; SI-NEXT: s_or_b32 s85, s19, s20
; SI-NEXT: s_and_b32 s19, s10, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_lshl_b32 s20, s62, 24
-; SI-NEXT: s_or_b32 s49, s20, s19
+; SI-NEXT: s_lshl_b32 s20, s58, 24
+; SI-NEXT: v_writelane_b32 v43, s9, 56
+; SI-NEXT: s_or_b32 s9, s20, s19
; SI-NEXT: s_and_b32 s19, s27, 0xff
-; SI-NEXT: v_writelane_b32 v42, s9, 55
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s28, 24
-; SI-NEXT: v_readlane_b32 s9, v43, 33
-; SI-NEXT: s_or_b32 s50, s20, s19
-; SI-NEXT: s_and_b32 s19, s9, 0xff
-; SI-NEXT: v_readlane_b32 s9, v43, 32
+; SI-NEXT: v_writelane_b32 v43, s9, 57
+; SI-NEXT: s_or_b32 s23, s20, s19
+; SI-NEXT: s_and_b32 s19, s24, 0xff
+; SI-NEXT: v_readlane_b32 s9, v44, 33
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s9, 24
-; SI-NEXT: v_readlane_b32 s9, v43, 31
-; SI-NEXT: s_or_b32 s51, s20, s19
+; SI-NEXT: v_readlane_b32 s9, v44, 32
+; SI-NEXT: s_or_b32 s10, s20, s19
; SI-NEXT: s_and_b32 s19, s9, 0xff
-; SI-NEXT: v_readlane_b32 s9, v43, 30
+; SI-NEXT: v_readlane_b32 s9, v44, 31
; SI-NEXT: s_lshl_b32 s20, s9, 8
-; SI-NEXT: v_readlane_b32 s9, v43, 29
+; SI-NEXT: v_readlane_b32 s9, v44, 30
; SI-NEXT: s_or_b32 s86, s19, s20
; SI-NEXT: s_and_b32 s19, s9, 0xff
-; SI-NEXT: v_readlane_b32 s9, v43, 28
+; SI-NEXT: v_readlane_b32 s9, v44, 29
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s9, 24
-; SI-NEXT: v_readlane_b32 s9, v43, 27
-; SI-NEXT: s_or_b32 s52, s20, s19
+; SI-NEXT: v_readlane_b32 s9, v44, 28
+; SI-NEXT: s_or_b32 s47, s20, s19
; SI-NEXT: s_and_b32 s19, s9, 0xff
-; SI-NEXT: v_readlane_b32 s9, v43, 26
+; SI-NEXT: v_readlane_b32 s9, v44, 27
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s9, 24
-; SI-NEXT: v_readlane_b32 s9, v43, 25
-; SI-NEXT: s_or_b32 s53, s20, s19
-; SI-NEXT: s_and_b32 s19, s9, 0xff
-; SI-NEXT: v_readlane_b32 s9, v43, 24
+; SI-NEXT: v_readlane_b32 s11, v44, 26
+; SI-NEXT: s_or_b32 s9, s20, s19
+; SI-NEXT: s_and_b32 s19, s11, 0xff
+; SI-NEXT: v_readlane_b32 s11, v44, 25
; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_lshl_b32 s20, s9, 24
-; SI-NEXT: v_readlane_b32 s9, v43, 23
-; SI-NEXT: s_or_b32 s54, s20, s19
-; SI-NEXT: s_and_b32 s19, s9, 0xff
-; SI-NEXT: v_readlane_b32 s9, v43, 22
-; SI-NEXT: s_lshl_b32 s20, s9, 8
-; SI-NEXT: v_readlane_b32 s9, v43, 21
+; SI-NEXT: s_lshl_b32 s20, s11, 24
+; SI-NEXT: v_readlane_b32 s11, v44, 24
+; SI-NEXT: s_or_b32 s24, s20, s19
+; SI-NEXT: s_mov_b32 s92, s11
+; SI-NEXT: s_and_b32 s19, s11, 0xff
+; SI-NEXT: v_readlane_b32 s11, v44, 23
+; SI-NEXT: s_mov_b32 s36, s11
+; SI-NEXT: s_lshl_b32 s20, s11, 8
+; SI-NEXT: v_readlane_b32 s11, v44, 22
; SI-NEXT: s_or_b32 s87, s19, s20
-; SI-NEXT: s_and_b32 s19, s9, 0xff
-; SI-NEXT: v_readlane_b32 s9, v43, 20
+; SI-NEXT: s_mov_b32 s62, s11
+; SI-NEXT: s_and_b32 s19, s11, 0xff
+; SI-NEXT: v_readlane_b32 s11, v44, 21
; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_lshl_b32 s20, s9, 24
-; SI-NEXT: v_readlane_b32 s9, v43, 19
-; SI-NEXT: s_or_b32 s55, s20, s19
-; SI-NEXT: s_mov_b32 s58, s9
-; SI-NEXT: s_and_b32 s19, s9, 0xff
-; SI-NEXT: v_readlane_b32 s9, v43, 18
+; SI-NEXT: s_mov_b32 s30, s11
+; SI-NEXT: s_lshl_b32 s20, s11, 24
+; SI-NEXT: v_readlane_b32 s11, v44, 20
+; SI-NEXT: s_or_b32 s58, s20, s19
+; SI-NEXT: s_mov_b32 s91, s11
+; SI-NEXT: s_and_b32 s19, s11, 0xff
+; SI-NEXT: v_readlane_b32 s11, v44, 19
; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_lshl_b32 s20, s9, 24
-; SI-NEXT: s_or_b32 s64, s20, s19
-; SI-NEXT: s_and_b32 s19, s78, 0xff
+; SI-NEXT: s_mov_b32 s35, s11
+; SI-NEXT: s_lshl_b32 s20, s11, 24
+; SI-NEXT: v_readlane_b32 s11, v44, 18
+; SI-NEXT: s_mov_b32 s4, s46
+; SI-NEXT: s_or_b32 s46, s20, s19
+; SI-NEXT: s_and_b32 s19, s11, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_lshl_b32 s20, s24, 24
-; SI-NEXT: s_or_b32 s65, s20, s19
-; SI-NEXT: s_and_b32 s19, s4, 0xff
+; SI-NEXT: s_lshl_b32 s20, s73, 24
+; SI-NEXT: s_mov_b32 s52, s73
+; SI-NEXT: s_or_b32 s73, s20, s19
+; SI-NEXT: s_and_b32 s19, s31, 0xff
; SI-NEXT: s_lshl_b32 s20, s45, 8
; SI-NEXT: s_or_b32 s26, s19, s20
; SI-NEXT: s_and_b32 s19, s13, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_lshl_b32 s20, s57, 24
-; SI-NEXT: s_or_b32 s66, s20, s19
-; SI-NEXT: s_and_b32 s19, s21, 0xff
-; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_lshl_b32 s20, s73, 24
+; SI-NEXT: s_lshl_b32 s20, s42, 24
; SI-NEXT: s_or_b32 s67, s20, s19
-; SI-NEXT: s_and_b32 s19, s42, 0xff
-; SI-NEXT: v_readlane_b32 s88, v43, 17
+; SI-NEXT: s_and_b32 s19, s4, 0xff
+; SI-NEXT: s_lshl_b32 s19, s19, 16
+; SI-NEXT: s_lshl_b32 s20, s43, 24
+; SI-NEXT: s_mov_b32 s53, s42
+; SI-NEXT: s_or_b32 s42, s20, s19
+; SI-NEXT: s_and_b32 s19, s56, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s59, 24
; SI-NEXT: s_or_b32 s68, s20, s19
; SI-NEXT: s_and_b32 s19, s63, 0xff
-; SI-NEXT: s_lshl_b32 s20, s88, 8
+; SI-NEXT: s_lshl_b32 s20, s61, 8
+; SI-NEXT: v_readlane_b32 s93, v44, 17
; SI-NEXT: s_or_b32 s27, s19, s20
; SI-NEXT: s_and_b32 s19, s40, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_lshl_b32 s20, s43, 24
-; SI-NEXT: s_or_b32 s69, s20, s19
-; SI-NEXT: s_and_b32 s19, s61, 0xff
-; SI-NEXT: s_mov_b32 s39, s57
-; SI-NEXT: s_mov_b32 s57, s7
+; SI-NEXT: s_lshl_b32 s20, s93, 24
+; SI-NEXT: s_or_b32 s70, s20, s19
+; SI-NEXT: s_and_b32 s19, s21, 0xff
+; SI-NEXT: s_mov_b32 s51, s59
+; SI-NEXT: s_mov_b32 s59, s7
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s75, 24
-; SI-NEXT: v_readlane_b32 s7, v43, 16
-; SI-NEXT: s_or_b32 s70, s20, s19
+; SI-NEXT: v_readlane_b32 s7, v44, 16
+; SI-NEXT: s_mov_b32 s48, s56
+; SI-NEXT: s_mov_b32 s56, s10
+; SI-NEXT: s_or_b32 s69, s20, s19
; SI-NEXT: s_mov_b32 s10, s7
; SI-NEXT: s_and_b32 s19, s7, 0xff
-; SI-NEXT: v_readlane_b32 s7, v43, 15
+; SI-NEXT: v_readlane_b32 s7, v44, 15
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_mov_b32 s71, s7
; SI-NEXT: s_lshl_b32 s20, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v43, 14
-; SI-NEXT: s_or_b32 s62, s20, s19
-; SI-NEXT: s_mov_b32 s15, s7
-; SI-NEXT: s_and_b32 s19, s7, 0xff
-; SI-NEXT: v_readlane_b32 s7, v43, 13
+; SI-NEXT: v_readlane_b32 s7, v44, 14
+; SI-NEXT: s_mov_b32 s39, s75
+; SI-NEXT: s_mov_b32 s75, s94
+; SI-NEXT: s_or_b32 s94, s20, s19
; SI-NEXT: s_mov_b32 s41, s7
+; SI-NEXT: s_and_b32 s19, s7, 0xff
+; SI-NEXT: v_readlane_b32 s7, v44, 13
+; SI-NEXT: s_mov_b32 s14, s7
; SI-NEXT: s_lshl_b32 s20, s7, 8
-; SI-NEXT: v_readlane_b32 s7, v43, 12
+; SI-NEXT: v_readlane_b32 s7, v44, 12
; SI-NEXT: s_or_b32 s29, s19, s20
-; SI-NEXT: s_mov_b32 s14, s7
+; SI-NEXT: s_mov_b32 s81, s7
; SI-NEXT: s_and_b32 s19, s7, 0xff
-; SI-NEXT: v_readlane_b32 s7, v43, 11
+; SI-NEXT: v_readlane_b32 s7, v44, 11
+; SI-NEXT: s_mov_b32 s55, s45
+; SI-NEXT: s_mov_b32 s45, s9
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_mov_b32 s9, s7
; SI-NEXT: s_lshl_b32 s20, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v43, 10
-; SI-NEXT: s_or_b32 s80, s20, s19
-; SI-NEXT: s_mov_b32 s56, s7
+; SI-NEXT: v_readlane_b32 s7, v44, 10
+; SI-NEXT: s_mov_b32 s38, s11
+; SI-NEXT: s_or_b32 s11, s20, s19
+; SI-NEXT: s_mov_b32 s72, s7
; SI-NEXT: s_and_b32 s19, s7, 0xff
-; SI-NEXT: v_readlane_b32 s7, v43, 9
+; SI-NEXT: v_readlane_b32 s7, v44, 9
; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_mov_b32 s81, s7
-; SI-NEXT: s_lshl_b32 s20, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v43, 8
-; SI-NEXT: s_or_b32 s11, s20, s19
; SI-NEXT: s_mov_b32 s82, s7
+; SI-NEXT: s_lshl_b32 s20, s7, 24
+; SI-NEXT: v_readlane_b32 s7, v44, 8
+; SI-NEXT: s_or_b32 s80, s20, s19
+; SI-NEXT: s_mov_b32 s83, s7
; SI-NEXT: s_and_b32 s19, s7, 0xff
-; SI-NEXT: v_readlane_b32 s7, v43, 7
+; SI-NEXT: v_readlane_b32 s7, v44, 7
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_mov_b32 s96, s7
; SI-NEXT: s_lshl_b32 s20, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v43, 6
-; SI-NEXT: s_mov_b32 s36, s63
-; SI-NEXT: s_mov_b32 s63, s93
-; SI-NEXT: s_mov_b32 s93, s61
-; SI-NEXT: s_mov_b32 s61, s91
-; SI-NEXT: s_mov_b32 s91, s75
-; SI-NEXT: s_mov_b32 s75, s92
-; SI-NEXT: s_or_b32 s92, s20, s19
+; SI-NEXT: v_readlane_b32 s7, v44, 6
+; SI-NEXT: s_mov_b32 s90, s31
+; SI-NEXT: s_or_b32 s31, s20, s19
; SI-NEXT: s_mov_b32 s98, s7
; SI-NEXT: s_and_b32 s19, s7, 0xff
-; SI-NEXT: v_readlane_b32 s7, v43, 5
+; SI-NEXT: v_readlane_b32 s7, v44, 5
; SI-NEXT: s_mov_b32 s44, s7
; SI-NEXT: s_lshl_b32 s20, s7, 8
-; SI-NEXT: v_readlane_b32 s7, v43, 4
-; SI-NEXT: s_mov_b32 s48, s13
-; SI-NEXT: s_mov_b32 s13, s94
-; SI-NEXT: s_mov_b32 s94, s21
+; SI-NEXT: v_readlane_b32 s7, v44, 4
+; SI-NEXT: s_mov_b32 s37, s43
+; SI-NEXT: s_mov_b32 s43, s93
+; SI-NEXT: s_mov_b32 s93, s21
; SI-NEXT: s_or_b32 s21, s19, s20
; SI-NEXT: s_and_b32 s19, s7, 0xff
-; SI-NEXT: s_mov_b32 s95, s4
+; SI-NEXT: s_mov_b32 s34, s4
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_lshl_b32 s20, s22, 24
-; SI-NEXT: v_readlane_b32 s4, v42, 58
-; SI-NEXT: s_mov_b32 s46, s45
-; SI-NEXT: s_mov_b32 s34, s73
-; SI-NEXT: s_mov_b32 s73, s12
-; SI-NEXT: s_mov_b32 s37, s42
-; SI-NEXT: s_mov_b32 s38, s59
-; SI-NEXT: s_mov_b32 s59, s8
-; SI-NEXT: s_mov_b32 s30, s88
-; SI-NEXT: s_mov_b32 s88, s31
-; SI-NEXT: s_mov_b32 s78, s40
-; SI-NEXT: s_mov_b32 s31, s43
+; SI-NEXT: v_readlane_b32 s4, v43, 60
+; SI-NEXT: s_mov_b32 s54, s13
+; SI-NEXT: s_mov_b32 s13, s12
+; SI-NEXT: s_mov_b32 s50, s63
+; SI-NEXT: s_mov_b32 s63, s95
+; SI-NEXT: s_mov_b32 s49, s61
+; SI-NEXT: s_mov_b32 s61, s8
+; SI-NEXT: s_mov_b32 s60, s40
; SI-NEXT: s_mov_b32 s12, s7
; SI-NEXT: s_mov_b32 s7, s22
-; SI-NEXT: s_or_b32 s83, s20, s19
+; SI-NEXT: s_or_b32 s15, s20, s19
; SI-NEXT: s_lshl_b32 s20, s4, 16
-; SI-NEXT: s_lshl_b32 s74, s5, 16
+; SI-NEXT: s_lshl_b32 s95, s5, 16
; SI-NEXT: s_lshl_b32 s22, s6, 16
; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_lshl_b32 s19, s17, 16
@@ -154799,16 +155644,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_lshl_b32 s97, s86, 16
; SI-NEXT: s_lshl_b32 s28, s87, 16
; SI-NEXT: s_lshl_b32 s87, s26, 16
-; SI-NEXT: v_readlane_b32 s26, v42, 56
+; SI-NEXT: v_readlane_b32 s26, v43, 58
; SI-NEXT: s_lshl_b32 s86, s27, 16
-; SI-NEXT: v_readlane_b32 s27, v42, 57
-; SI-NEXT: v_readlane_b32 s35, v42, 61
+; SI-NEXT: v_readlane_b32 s27, v43, 59
+; SI-NEXT: v_readlane_b32 s66, v43, 63
; SI-NEXT: s_lshl_b32 s85, s29, 16
-; SI-NEXT: v_readlane_b32 s29, v42, 60
-; SI-NEXT: v_readlane_b32 s24, v42, 59
-; SI-NEXT: v_readlane_b32 s90, v42, 62
+; SI-NEXT: v_readlane_b32 s29, v43, 62
+; SI-NEXT: v_readlane_b32 s65, v43, 61
+; SI-NEXT: v_readlane_b32 s64, v42, 0
; SI-NEXT: s_lshl_b32 s84, s21, 16
-; SI-NEXT: s_mov_b32 s21, s47
+; SI-NEXT: v_readlane_b32 s21, v42, 1
; SI-NEXT: s_cbranch_execnz .LBB89_3
; SI-NEXT: .LBB89_2: ; %cmp.true
; SI-NEXT: s_add_i32 s4, s98, 3
@@ -154823,10 +155668,10 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_or_b32 s5, s5, s6
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: s_add_i32 s5, s56, 3
+; SI-NEXT: s_add_i32 s5, s72, 3
; SI-NEXT: s_and_b32 s5, s5, 0xff
-; SI-NEXT: s_lshl_b32 s6, s81, 8
-; SI-NEXT: s_add_i32 s16, s82, 3
+; SI-NEXT: s_lshl_b32 s6, s82, 8
+; SI-NEXT: s_add_i32 s16, s83, 3
; SI-NEXT: s_or_b32 s5, s6, s5
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s6, s96, 24
@@ -154835,10 +155680,10 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_or_b32 s6, s6, s16
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: s_add_i32 s6, s15, 3
+; SI-NEXT: s_add_i32 s6, s41, 3
; SI-NEXT: s_and_b32 s6, s6, 0xff
-; SI-NEXT: s_lshl_b32 s16, s41, 8
-; SI-NEXT: s_add_i32 s17, s14, 3
+; SI-NEXT: s_lshl_b32 s16, s14, 8
+; SI-NEXT: s_add_i32 s17, s81, 3
; SI-NEXT: s_or_b32 s6, s16, s6
; SI-NEXT: s_and_b32 s17, s17, 0xff
; SI-NEXT: s_lshl_b32 s16, s9, 24
@@ -154849,7 +155694,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_or_b32 s6, s16, s6
; SI-NEXT: s_add_i32 s16, s93, 3
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s91, 8
+; SI-NEXT: s_lshl_b32 s17, s39, 8
; SI-NEXT: s_add_i32 s18, s10, 3
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_and_b32 s18, s18, 0xff
@@ -154859,150 +155704,143 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s17, s36, 3
+; SI-NEXT: s_add_i32 s17, s50, 3
; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: s_lshl_b32 s18, s30, 8
-; SI-NEXT: s_add_i32 s19, s78, 3
+; SI-NEXT: s_lshl_b32 s18, s49, 8
+; SI-NEXT: s_add_i32 s19, s60, 3
; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: s_and_b32 s19, s19, 0xff
-; SI-NEXT: s_lshl_b32 s18, s31, 24
+; SI-NEXT: s_lshl_b32 s18, s43, 24
; SI-NEXT: s_lshl_b32 s19, s19, 16
; SI-NEXT: s_addk_i32 s17, 0x300
; SI-NEXT: s_or_b32 s18, s18, s19
; SI-NEXT: s_and_b32 s17, s17, 0xffff
; SI-NEXT: s_or_b32 s17, s18, s17
-; SI-NEXT: s_add_i32 s18, s94, 3
+; SI-NEXT: s_add_i32 s18, s34, 3
; SI-NEXT: s_and_b32 s18, s18, 0xff
-; SI-NEXT: s_lshl_b32 s19, s34, 8
-; SI-NEXT: s_add_i32 s20, s37, 3
+; SI-NEXT: s_lshl_b32 s19, s37, 8
+; SI-NEXT: s_add_i32 s20, s48, 3
; SI-NEXT: s_or_b32 s18, s19, s18
; SI-NEXT: s_and_b32 s20, s20, 0xff
-; SI-NEXT: s_lshl_b32 s19, s38, 24
+; SI-NEXT: s_lshl_b32 s19, s51, 24
; SI-NEXT: s_lshl_b32 s20, s20, 16
; SI-NEXT: s_addk_i32 s18, 0x300
; SI-NEXT: s_or_b32 s19, s19, s20
; SI-NEXT: s_and_b32 s18, s18, 0xffff
; SI-NEXT: s_or_b32 s18, s19, s18
-; SI-NEXT: s_add_i32 s19, s95, 3
+; SI-NEXT: s_add_i32 s19, s90, 3
; SI-NEXT: s_and_b32 s19, s19, 0xff
-; SI-NEXT: s_lshl_b32 s20, s46, 8
-; SI-NEXT: s_add_i32 s22, s48, 3
+; SI-NEXT: s_lshl_b32 s20, s55, 8
+; SI-NEXT: s_add_i32 s22, s54, 3
; SI-NEXT: s_or_b32 s19, s20, s19
; SI-NEXT: s_and_b32 s22, s22, 0xff
-; SI-NEXT: s_lshl_b32 s20, s39, 24
+; SI-NEXT: s_lshl_b32 s20, s53, 24
; SI-NEXT: s_lshl_b32 s22, s22, 16
; SI-NEXT: s_addk_i32 s19, 0x300
; SI-NEXT: s_or_b32 s20, s20, s22
; SI-NEXT: s_and_b32 s19, s19, 0xffff
; SI-NEXT: s_or_b32 s19, s20, s19
-; SI-NEXT: s_add_i32 s20, s58, 3
-; SI-NEXT: v_readlane_b32 s7, v43, 18
+; SI-NEXT: s_add_i32 s20, s91, 3
; SI-NEXT: s_and_b32 s20, s20, 0xff
-; SI-NEXT: s_lshl_b32 s22, s7, 8
-; SI-NEXT: v_readlane_b32 s7, v42, 49
+; SI-NEXT: s_lshl_b32 s22, s35, 8
+; SI-NEXT: s_add_i32 s23, s38, 3
; SI-NEXT: s_or_b32 s20, s22, s20
-; SI-NEXT: s_lshl_b32 s22, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v42, 48
-; SI-NEXT: s_add_i32 s23, s7, 3
; SI-NEXT: s_and_b32 s23, s23, 0xff
+; SI-NEXT: s_lshl_b32 s22, s52, 24
; SI-NEXT: s_lshl_b32 s23, s23, 16
; SI-NEXT: s_addk_i32 s20, 0x300
; SI-NEXT: s_or_b32 s22, s22, s23
; SI-NEXT: s_and_b32 s20, s20, 0xffff
-; SI-NEXT: v_readlane_b32 s7, v43, 23
; SI-NEXT: s_or_b32 s20, s22, s20
-; SI-NEXT: s_add_i32 s22, s7, 3
-; SI-NEXT: v_readlane_b32 s7, v43, 22
+; SI-NEXT: s_add_i32 s22, s92, 3
; SI-NEXT: s_and_b32 s22, s22, 0xff
-; SI-NEXT: s_lshl_b32 s23, s7, 8
-; SI-NEXT: v_readlane_b32 s7, v43, 20
+; SI-NEXT: s_lshl_b32 s23, s36, 8
+; SI-NEXT: s_add_i32 s60, s62, 3
; SI-NEXT: s_or_b32 s22, s23, s22
-; SI-NEXT: s_lshl_b32 s23, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v43, 21
-; SI-NEXT: s_add_i32 s60, s7, 3
; SI-NEXT: s_and_b32 s60, s60, 0xff
+; SI-NEXT: s_lshl_b32 s23, s30, 24
; SI-NEXT: s_lshl_b32 s60, s60, 16
; SI-NEXT: s_addk_i32 s22, 0x300
; SI-NEXT: s_or_b32 s23, s23, s60
; SI-NEXT: s_and_b32 s22, s22, 0xffff
-; SI-NEXT: v_readlane_b32 s7, v43, 27
+; SI-NEXT: v_readlane_b32 s7, v44, 28
; SI-NEXT: s_or_b32 s22, s23, s22
; SI-NEXT: s_add_i32 s23, s7, 3
-; SI-NEXT: v_readlane_b32 s7, v43, 26
+; SI-NEXT: v_readlane_b32 s7, v44, 27
; SI-NEXT: s_and_b32 s23, s23, 0xff
; SI-NEXT: s_lshl_b32 s60, s7, 8
-; SI-NEXT: v_readlane_b32 s7, v43, 24
+; SI-NEXT: v_readlane_b32 s7, v44, 25
; SI-NEXT: s_or_b32 s23, s60, s23
; SI-NEXT: s_lshl_b32 s60, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v43, 25
+; SI-NEXT: v_readlane_b32 s7, v44, 26
; SI-NEXT: s_add_i32 s61, s7, 3
; SI-NEXT: s_and_b32 s61, s61, 0xff
; SI-NEXT: s_lshl_b32 s61, s61, 16
; SI-NEXT: s_addk_i32 s23, 0x300
; SI-NEXT: s_or_b32 s60, s60, s61
; SI-NEXT: s_and_b32 s23, s23, 0xffff
-; SI-NEXT: v_readlane_b32 s7, v43, 31
+; SI-NEXT: v_readlane_b32 s7, v44, 32
; SI-NEXT: s_or_b32 s23, s60, s23
; SI-NEXT: s_add_i32 s60, s7, 3
-; SI-NEXT: v_readlane_b32 s7, v43, 30
+; SI-NEXT: v_readlane_b32 s7, v44, 31
; SI-NEXT: s_and_b32 s60, s60, 0xff
; SI-NEXT: s_lshl_b32 s61, s7, 8
-; SI-NEXT: v_readlane_b32 s7, v43, 28
+; SI-NEXT: v_readlane_b32 s7, v44, 29
; SI-NEXT: s_or_b32 s60, s61, s60
; SI-NEXT: s_lshl_b32 s61, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v43, 29
+; SI-NEXT: v_readlane_b32 s7, v44, 30
; SI-NEXT: s_add_i32 s62, s7, 3
-; SI-NEXT: v_readlane_b32 s7, v42, 47
+; SI-NEXT: v_readlane_b32 s7, v43, 48
; SI-NEXT: s_and_b32 s62, s62, 0xff
; SI-NEXT: s_add_i32 s59, s7, 3
-; SI-NEXT: v_readlane_b32 s7, v42, 46
+; SI-NEXT: v_readlane_b32 s7, v43, 47
; SI-NEXT: s_lshl_b32 s62, s62, 16
; SI-NEXT: s_addk_i32 s60, 0x300
; SI-NEXT: s_and_b32 s59, s59, 0xff
; SI-NEXT: s_lshl_b32 s58, s7, 8
-; SI-NEXT: v_readlane_b32 s7, v43, 32
+; SI-NEXT: v_readlane_b32 s7, v44, 33
; SI-NEXT: s_or_b32 s61, s61, s62
; SI-NEXT: s_and_b32 s60, s60, 0xffff
; SI-NEXT: s_or_b32 s58, s58, s59
; SI-NEXT: s_lshl_b32 s59, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v43, 33
+; SI-NEXT: v_readlane_b32 s7, v44, 44
; SI-NEXT: s_or_b32 s60, s61, s60
; SI-NEXT: s_add_i32 s61, s7, 3
-; SI-NEXT: v_readlane_b32 s7, v42, 45
+; SI-NEXT: v_readlane_b32 s7, v43, 46
; SI-NEXT: s_add_i32 s57, s7, 3
-; SI-NEXT: v_readlane_b32 s7, v42, 44
+; SI-NEXT: v_readlane_b32 s7, v43, 45
; SI-NEXT: s_lshl_b32 s56, s7, 8
-; SI-NEXT: v_readlane_b32 s7, v42, 43
+; SI-NEXT: v_readlane_b32 s7, v43, 44
; SI-NEXT: s_lshl_b32 s47, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v42, 42
+; SI-NEXT: v_readlane_b32 s7, v43, 43
; SI-NEXT: s_add_i32 s46, s7, 3
-; SI-NEXT: v_readlane_b32 s7, v42, 41
+; SI-NEXT: v_readlane_b32 s7, v43, 42
; SI-NEXT: s_add_i32 s45, s7, 3
-; SI-NEXT: v_readlane_b32 s7, v42, 38
+; SI-NEXT: v_readlane_b32 s7, v43, 39
; SI-NEXT: s_lshl_b32 s42, s7, 8
-; SI-NEXT: v_readlane_b32 s7, v42, 35
+; SI-NEXT: v_readlane_b32 s7, v43, 36
; SI-NEXT: s_lshl_b32 s15, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v42, 34
+; SI-NEXT: v_readlane_b32 s7, v43, 35
; SI-NEXT: s_and_b32 s45, s45, 0xff
; SI-NEXT: s_add_i32 s14, s7, 3
; SI-NEXT: s_or_b32 s42, s42, s45
; SI-NEXT: s_and_b32 s14, s14, 0xff
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_addk_i32 s42, 0x300
-; SI-NEXT: v_readlane_b32 s7, v42, 40
+; SI-NEXT: v_readlane_b32 s7, v43, 41
; SI-NEXT: s_and_b32 s57, s57, 0xff
; SI-NEXT: s_or_b32 s14, s15, s14
; SI-NEXT: s_and_b32 s15, s42, 0xffff
; SI-NEXT: s_add_i32 s44, s7, 3
-; SI-NEXT: v_readlane_b32 s7, v42, 39
+; SI-NEXT: v_readlane_b32 s7, v43, 40
; SI-NEXT: s_or_b32 s56, s56, s57
; SI-NEXT: s_or_b32 s57, s14, s15
; SI-NEXT: s_and_b32 s14, s44, 0xff
; SI-NEXT: s_lshl_b32 s15, s7, 8
-; SI-NEXT: v_readlane_b32 s7, v42, 37
+; SI-NEXT: v_readlane_b32 s7, v43, 38
; SI-NEXT: s_or_b32 s14, s15, s14
; SI-NEXT: s_lshl_b32 s15, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v42, 36
+; SI-NEXT: v_readlane_b32 s7, v43, 37
; SI-NEXT: s_add_i32 s40, s7, 3
; SI-NEXT: s_and_b32 s61, s61, 0xff
; SI-NEXT: s_and_b32 s40, s40, 0xff
@@ -155017,15 +155855,15 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_or_b32 s58, s59, s58
; SI-NEXT: s_or_b32 s59, s15, s14
; SI-NEXT: s_add_i32 s14, s6, 0x3000000
-; SI-NEXT: v_readlane_b32 s6, v42, 31
+; SI-NEXT: v_readlane_b32 s6, v43, 32
; SI-NEXT: s_add_i32 s11, s6, 3
-; SI-NEXT: v_readlane_b32 s7, v42, 28
+; SI-NEXT: v_readlane_b32 s7, v43, 29
; SI-NEXT: s_and_b32 s6, s11, 0xff
; SI-NEXT: s_lshl_b32 s8, s7, 8
-; SI-NEXT: v_readlane_b32 s7, v42, 25
+; SI-NEXT: v_readlane_b32 s7, v43, 26
; SI-NEXT: s_or_b32 s6, s8, s6
; SI-NEXT: s_lshl_b32 s8, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v42, 24
+; SI-NEXT: v_readlane_b32 s7, v43, 25
; SI-NEXT: s_add_i32 s24, s7, 3
; SI-NEXT: s_and_b32 s11, s24, 0xff
; SI-NEXT: s_addk_i32 s6, 0x300
@@ -155033,47 +155871,47 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_or_b32 s8, s8, s11
; SI-NEXT: s_or_b32 s8, s8, s6
-; SI-NEXT: v_readlane_b32 s6, v42, 32
+; SI-NEXT: v_readlane_b32 s6, v43, 33
; SI-NEXT: s_add_i32 s12, s6, 3
-; SI-NEXT: v_readlane_b32 s7, v42, 26
+; SI-NEXT: v_readlane_b32 s7, v43, 27
; SI-NEXT: s_and_b32 s6, s12, 0xff
; SI-NEXT: s_lshl_b32 s11, s7, 8
-; SI-NEXT: v_readlane_b32 s7, v42, 16
+; SI-NEXT: v_readlane_b32 s7, v43, 17
; SI-NEXT: s_or_b32 s6, s11, s6
; SI-NEXT: s_lshl_b32 s11, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v42, 18
+; SI-NEXT: v_readlane_b32 s7, v43, 19
; SI-NEXT: s_add_i32 s12, s7, 3
; SI-NEXT: s_and_b32 s12, s12, 0xff
; SI-NEXT: s_addk_i32 s6, 0x300
; SI-NEXT: s_lshl_b32 s12, s12, 16
-; SI-NEXT: v_readlane_b32 s7, v42, 33
+; SI-NEXT: v_readlane_b32 s7, v43, 34
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_or_b32 s11, s11, s12
; SI-NEXT: s_add_i32 s13, s7, 3
-; SI-NEXT: v_readlane_b32 s7, v42, 30
+; SI-NEXT: v_readlane_b32 s7, v43, 31
; SI-NEXT: s_or_b32 s6, s11, s6
; SI-NEXT: s_and_b32 s11, s13, 0xff
; SI-NEXT: s_lshl_b32 s10, s7, 8
-; SI-NEXT: v_readlane_b32 s7, v42, 22
+; SI-NEXT: v_readlane_b32 s7, v43, 23
; SI-NEXT: s_or_b32 s10, s10, s11
; SI-NEXT: s_lshl_b32 s11, s7, 24
-; SI-NEXT: v_readlane_b32 s7, v42, 23
+; SI-NEXT: v_readlane_b32 s7, v43, 24
; SI-NEXT: s_add_i32 s25, s7, 3
; SI-NEXT: s_and_b32 s12, s25, 0xff
; SI-NEXT: s_addk_i32 s10, 0x300
; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: s_or_b32 s11, s11, s12
-; SI-NEXT: v_readlane_b32 s7, v42, 29
+; SI-NEXT: v_readlane_b32 s7, v43, 30
; SI-NEXT: s_or_b32 s10, s11, s10
; SI-NEXT: s_add_i32 s9, s7, 3
-; SI-NEXT: v_readlane_b32 s7, v42, 27
-; SI-NEXT: v_readlane_b32 s11, v42, 20
+; SI-NEXT: v_readlane_b32 s7, v43, 28
+; SI-NEXT: v_readlane_b32 s11, v43, 21
; SI-NEXT: s_and_b32 s9, s9, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 8
; SI-NEXT: s_add_i32 s11, s11, 3
; SI-NEXT: s_or_b32 s7, s7, s9
-; SI-NEXT: v_readlane_b32 s9, v42, 21
+; SI-NEXT: v_readlane_b32 s9, v43, 22
; SI-NEXT: s_and_b32 s11, s11, 0xff
; SI-NEXT: s_addk_i32 s7, 0x300
; SI-NEXT: s_lshl_b32 s9, s9, 24
@@ -155081,15 +155919,15 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_or_b32 s9, s9, s11
; SI-NEXT: s_or_b32 s7, s9, s7
-; SI-NEXT: v_readlane_b32 s9, v42, 19
+; SI-NEXT: v_readlane_b32 s9, v43, 20
; SI-NEXT: s_add_i32 s21, s9, 3
-; SI-NEXT: v_readlane_b32 s11, v42, 17
-; SI-NEXT: v_readlane_b32 s12, v42, 14
+; SI-NEXT: v_readlane_b32 s11, v43, 18
+; SI-NEXT: v_readlane_b32 s12, v43, 15
; SI-NEXT: s_and_b32 s9, s21, 0xff
; SI-NEXT: s_lshl_b32 s11, s11, 8
; SI-NEXT: s_add_i32 s12, s12, 3
; SI-NEXT: s_or_b32 s9, s11, s9
-; SI-NEXT: v_readlane_b32 s11, v42, 15
+; SI-NEXT: v_readlane_b32 s11, v43, 16
; SI-NEXT: s_and_b32 s12, s12, 0xff
; SI-NEXT: s_addk_i32 s9, 0x300
; SI-NEXT: s_lshl_b32 s11, s11, 24
@@ -155097,15 +155935,15 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_and_b32 s9, s9, 0xffff
; SI-NEXT: s_or_b32 s11, s11, s12
; SI-NEXT: s_or_b32 s9, s11, s9
-; SI-NEXT: v_readlane_b32 s11, v42, 13
+; SI-NEXT: v_readlane_b32 s11, v43, 14
; SI-NEXT: s_add_i32 s11, s11, 3
-; SI-NEXT: v_readlane_b32 s12, v42, 12
-; SI-NEXT: v_readlane_b32 s13, v42, 10
+; SI-NEXT: v_readlane_b32 s12, v43, 13
+; SI-NEXT: v_readlane_b32 s13, v43, 11
; SI-NEXT: s_and_b32 s11, s11, 0xff
; SI-NEXT: s_lshl_b32 s12, s12, 8
; SI-NEXT: s_add_i32 s13, s13, 3
; SI-NEXT: s_or_b32 s11, s12, s11
-; SI-NEXT: v_readlane_b32 s12, v42, 11
+; SI-NEXT: v_readlane_b32 s12, v43, 12
; SI-NEXT: s_and_b32 s13, s13, 0xff
; SI-NEXT: s_addk_i32 s11, 0x300
; SI-NEXT: s_lshl_b32 s12, s12, 24
@@ -155113,16 +155951,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_and_b32 s11, s11, 0xffff
; SI-NEXT: s_or_b32 s12, s12, s13
; SI-NEXT: s_or_b32 s11, s12, s11
-; SI-NEXT: v_readlane_b32 s12, v42, 9
+; SI-NEXT: v_readlane_b32 s12, v43, 10
; SI-NEXT: s_add_i32 s15, s16, 0x3000000
; SI-NEXT: s_add_i32 s12, s12, 3
-; SI-NEXT: v_readlane_b32 s13, v42, 8
-; SI-NEXT: v_readlane_b32 s16, v42, 6
+; SI-NEXT: v_readlane_b32 s13, v43, 9
+; SI-NEXT: v_readlane_b32 s16, v43, 7
; SI-NEXT: s_and_b32 s12, s12, 0xff
; SI-NEXT: s_lshl_b32 s13, s13, 8
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_or_b32 s12, s13, s12
-; SI-NEXT: v_readlane_b32 s13, v42, 7
+; SI-NEXT: v_readlane_b32 s13, v43, 8
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_addk_i32 s12, 0x300
; SI-NEXT: s_lshl_b32 s13, s13, 24
@@ -155130,16 +155968,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_and_b32 s12, s12, 0xffff
; SI-NEXT: s_or_b32 s13, s13, s16
; SI-NEXT: s_or_b32 s12, s13, s12
-; SI-NEXT: v_readlane_b32 s13, v42, 5
+; SI-NEXT: v_readlane_b32 s13, v43, 6
; SI-NEXT: s_add_i32 s40, s17, 0x3000000
; SI-NEXT: s_add_i32 s13, s13, 3
-; SI-NEXT: v_readlane_b32 s16, v42, 4
-; SI-NEXT: v_readlane_b32 s17, v42, 2
+; SI-NEXT: v_readlane_b32 s16, v43, 5
+; SI-NEXT: v_readlane_b32 s17, v43, 3
; SI-NEXT: s_and_b32 s13, s13, 0xff
; SI-NEXT: s_lshl_b32 s16, s16, 8
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_or_b32 s13, s16, s13
-; SI-NEXT: v_readlane_b32 s16, v42, 3
+; SI-NEXT: v_readlane_b32 s16, v43, 4
; SI-NEXT: s_and_b32 s17, s17, 0xff
; SI-NEXT: s_addk_i32 s13, 0x300
; SI-NEXT: s_lshl_b32 s16, s16, 24
@@ -155147,16 +155985,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_or_b32 s13, s16, s13
-; SI-NEXT: v_readlane_b32 s16, v42, 1
+; SI-NEXT: v_readlane_b32 s16, v43, 2
; SI-NEXT: s_add_i32 s41, s18, 0x3000000
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 0
-; SI-NEXT: v_readlane_b32 s18, v43, 62
+; SI-NEXT: v_readlane_b32 s17, v43, 1
+; SI-NEXT: v_readlane_b32 s18, v44, 63
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v43, 63
+; SI-NEXT: v_readlane_b32 s17, v43, 0
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -155165,16 +156003,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s17, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v43, 61
+; SI-NEXT: v_readlane_b32 s16, v44, 62
; SI-NEXT: s_add_i32 s42, s19, 0x3000000
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s18, v43, 60
-; SI-NEXT: v_readlane_b32 s19, v43, 58
+; SI-NEXT: v_readlane_b32 s18, v44, 61
+; SI-NEXT: v_readlane_b32 s19, v44, 59
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s18, s18, 8
; SI-NEXT: s_add_i32 s19, s19, 3
; SI-NEXT: s_or_b32 s16, s18, s16
-; SI-NEXT: v_readlane_b32 s18, v43, 59
+; SI-NEXT: v_readlane_b32 s18, v44, 60
; SI-NEXT: s_and_b32 s19, s19, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s18, s18, 24
@@ -155182,16 +156020,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s18, s18, s19
; SI-NEXT: s_or_b32 s16, s18, s16
-; SI-NEXT: v_readlane_b32 s18, v43, 57
+; SI-NEXT: v_readlane_b32 s18, v44, 58
; SI-NEXT: s_add_i32 s43, s20, 0x3000000
; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: v_readlane_b32 s19, v43, 56
-; SI-NEXT: v_readlane_b32 s20, v43, 54
+; SI-NEXT: v_readlane_b32 s19, v44, 57
+; SI-NEXT: v_readlane_b32 s20, v44, 55
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 8
; SI-NEXT: s_add_i32 s20, s20, 3
; SI-NEXT: s_or_b32 s18, s19, s18
-; SI-NEXT: v_readlane_b32 s19, v43, 55
+; SI-NEXT: v_readlane_b32 s19, v44, 56
; SI-NEXT: s_and_b32 s20, s20, 0xff
; SI-NEXT: s_addk_i32 s18, 0x300
; SI-NEXT: s_lshl_b32 s19, s19, 24
@@ -155199,15 +156037,15 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_and_b32 s18, s18, 0xffff
; SI-NEXT: s_or_b32 s19, s19, s20
; SI-NEXT: s_or_b32 s18, s19, s18
-; SI-NEXT: v_readlane_b32 s19, v43, 53
+; SI-NEXT: v_readlane_b32 s19, v44, 54
; SI-NEXT: s_add_i32 s19, s19, 3
-; SI-NEXT: v_readlane_b32 s20, v43, 52
-; SI-NEXT: v_readlane_b32 s21, v43, 50
+; SI-NEXT: v_readlane_b32 s20, v44, 53
+; SI-NEXT: v_readlane_b32 s21, v44, 51
; SI-NEXT: s_and_b32 s19, s19, 0xff
; SI-NEXT: s_lshl_b32 s20, s20, 8
; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_or_b32 s19, s20, s19
-; SI-NEXT: v_readlane_b32 s20, v43, 51
+; SI-NEXT: v_readlane_b32 s20, v44, 52
; SI-NEXT: s_and_b32 s21, s21, 0xff
; SI-NEXT: s_addk_i32 s19, 0x300
; SI-NEXT: s_lshl_b32 s20, s20, 24
@@ -155215,16 +156053,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_and_b32 s19, s19, 0xffff
; SI-NEXT: s_or_b32 s20, s20, s21
; SI-NEXT: s_or_b32 s19, s20, s19
-; SI-NEXT: v_readlane_b32 s20, v43, 49
+; SI-NEXT: v_readlane_b32 s20, v44, 50
; SI-NEXT: s_add_i32 s44, s22, 0x3000000
; SI-NEXT: s_add_i32 s20, s20, 3
-; SI-NEXT: v_readlane_b32 s21, v43, 48
-; SI-NEXT: v_readlane_b32 s22, v43, 46
+; SI-NEXT: v_readlane_b32 s21, v44, 49
+; SI-NEXT: v_readlane_b32 s22, v44, 47
; SI-NEXT: s_and_b32 s20, s20, 0xff
; SI-NEXT: s_lshl_b32 s21, s21, 8
; SI-NEXT: s_add_i32 s22, s22, 3
; SI-NEXT: s_or_b32 s20, s21, s20
-; SI-NEXT: v_readlane_b32 s21, v43, 47
+; SI-NEXT: v_readlane_b32 s21, v44, 48
; SI-NEXT: s_and_b32 s22, s22, 0xff
; SI-NEXT: s_addk_i32 s20, 0x300
; SI-NEXT: s_lshl_b32 s21, s21, 24
@@ -155233,16 +156071,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_or_b32 s21, s21, s22
; SI-NEXT: s_or_b32 s20, s21, s20
; SI-NEXT: s_add_i32 s21, s20, 0x3000000
-; SI-NEXT: v_readlane_b32 s20, v43, 43
+; SI-NEXT: v_readlane_b32 s20, v44, 43
; SI-NEXT: s_add_i32 s45, s23, 0x3000000
; SI-NEXT: s_add_i32 s20, s20, 3
-; SI-NEXT: v_readlane_b32 s22, v43, 42
-; SI-NEXT: v_readlane_b32 s23, v43, 44
+; SI-NEXT: v_readlane_b32 s22, v44, 42
+; SI-NEXT: v_readlane_b32 s23, v44, 45
; SI-NEXT: s_and_b32 s20, s20, 0xff
; SI-NEXT: s_lshl_b32 s22, s22, 8
; SI-NEXT: s_add_i32 s23, s23, 3
; SI-NEXT: s_or_b32 s20, s22, s20
-; SI-NEXT: v_readlane_b32 s22, v43, 45
+; SI-NEXT: v_readlane_b32 s22, v44, 46
; SI-NEXT: s_and_b32 s23, s23, 0xff
; SI-NEXT: s_addk_i32 s20, 0x300
; SI-NEXT: s_lshl_b32 s22, s22, 24
@@ -155251,15 +156089,15 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_or_b32 s22, s22, s23
; SI-NEXT: s_or_b32 s20, s22, s20
; SI-NEXT: s_add_i32 s22, s20, 0x3000000
-; SI-NEXT: v_readlane_b32 s20, v43, 41
+; SI-NEXT: v_readlane_b32 s20, v44, 41
; SI-NEXT: s_add_i32 s20, s20, 3
-; SI-NEXT: v_readlane_b32 s23, v43, 40
-; SI-NEXT: v_readlane_b32 s24, v43, 38
+; SI-NEXT: v_readlane_b32 s23, v44, 40
+; SI-NEXT: v_readlane_b32 s24, v44, 38
; SI-NEXT: s_and_b32 s20, s20, 0xff
; SI-NEXT: s_lshl_b32 s23, s23, 8
; SI-NEXT: s_add_i32 s24, s24, 3
; SI-NEXT: s_or_b32 s20, s23, s20
-; SI-NEXT: v_readlane_b32 s23, v43, 39
+; SI-NEXT: v_readlane_b32 s23, v44, 39
; SI-NEXT: s_and_b32 s24, s24, 0xff
; SI-NEXT: s_addk_i32 s20, 0x300
; SI-NEXT: s_lshl_b32 s23, s23, 24
@@ -155268,361 +156106,367 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_or_b32 s23, s23, s24
; SI-NEXT: s_or_b32 s20, s23, s20
; SI-NEXT: s_add_i32 s23, s20, 0x3000000
-; SI-NEXT: v_readlane_b32 s20, v43, 37
+; SI-NEXT: v_readlane_b32 s20, v44, 37
; SI-NEXT: s_add_i32 s20, s20, 3
-; SI-NEXT: v_readlane_b32 s24, v43, 36
-; SI-NEXT: v_readlane_b32 s25, v43, 34
+; SI-NEXT: v_readlane_b32 s24, v44, 36
+; SI-NEXT: v_readlane_b32 s25, v44, 34
; SI-NEXT: s_and_b32 s20, s20, 0xff
; SI-NEXT: s_lshl_b32 s24, s24, 8
; SI-NEXT: s_add_i32 s25, s25, 3
; SI-NEXT: s_or_b32 s20, s24, s20
-; SI-NEXT: v_readlane_b32 s24, v43, 35
+; SI-NEXT: v_readlane_b32 s24, v44, 35
; SI-NEXT: s_and_b32 s25, s25, 0xff
; SI-NEXT: s_addk_i32 s20, 0x300
; SI-NEXT: s_lshl_b32 s24, s24, 24
; SI-NEXT: s_lshl_b32 s25, s25, 16
; SI-NEXT: s_and_b32 s20, s20, 0xffff
; SI-NEXT: s_or_b32 s24, s24, s25
-; SI-NEXT: s_and_b32 s46, s46, 0xff
; SI-NEXT: s_or_b32 s20, s24, s20
-; SI-NEXT: v_readlane_b32 s24, v43, 3
-; SI-NEXT: s_lshl_b32 s46, s46, 16
-; SI-NEXT: s_addk_i32 s56, 0x300
+; SI-NEXT: v_readlane_b32 s24, v44, 3
; SI-NEXT: s_add_i32 s24, s24, 3
-; SI-NEXT: v_readlane_b32 s25, v43, 2
-; SI-NEXT: v_readlane_b32 s26, v43, 1
-; SI-NEXT: s_or_b32 s46, s47, s46
-; SI-NEXT: s_and_b32 s47, s56, 0xffff
-; SI-NEXT: s_add_i32 s7, s7, 0x3000000
-; SI-NEXT: s_add_i32 s9, s9, 0x3000000
+; SI-NEXT: v_readlane_b32 s25, v44, 2
+; SI-NEXT: v_readlane_b32 s26, v44, 1
; SI-NEXT: s_and_b32 s24, s24, 0xff
; SI-NEXT: s_lshl_b32 s25, s25, 8
; SI-NEXT: s_add_i32 s26, s26, 3
-; SI-NEXT: s_or_b32 s56, s46, s47
-; SI-NEXT: s_add_i32 s47, s58, 0x3000000
-; SI-NEXT: s_add_i32 s58, s59, 0x3000000
-; SI-NEXT: s_add_i32 s10, s10, 0x3000000
; SI-NEXT: s_or_b32 s24, s25, s24
-; SI-NEXT: v_readlane_b32 s25, v43, 0
+; SI-NEXT: v_readlane_b32 s25, v44, 0
; SI-NEXT: s_and_b32 s26, s26, 0xff
-; SI-NEXT: s_and_b32 s73, s9, 0xffff0000
-; SI-NEXT: s_lshl_b32 s59, s9, 16
-; SI-NEXT: s_and_b32 s9, s7, 0xffff0000
-; SI-NEXT: s_add_i32 s6, s6, 0x3000000
+; SI-NEXT: s_add_i32 s13, s13, 0x3000000
; SI-NEXT: s_addk_i32 s24, 0x300
; SI-NEXT: s_lshl_b32 s25, s25, 24
; SI-NEXT: s_lshl_b32 s26, s26, 16
-; SI-NEXT: s_and_b32 s63, s17, 0xffff0000
-; SI-NEXT: s_lshl_b32 s79, s17, 16
-; SI-NEXT: v_writelane_b32 v42, s9, 50
-; SI-NEXT: s_lshl_b32 s17, s7, 16
-; SI-NEXT: s_lshl_b32 s7, s10, 16
-; SI-NEXT: s_add_i32 s8, s8, 0x3000000
+; SI-NEXT: s_add_i32 s9, s9, 0x3000000
+; SI-NEXT: s_add_i32 s11, s11, 0x3000000
+; SI-NEXT: s_add_i32 s18, s18, 0x3000000
; SI-NEXT: s_and_b32 s24, s24, 0xffff
; SI-NEXT: s_or_b32 s25, s25, s26
-; SI-NEXT: v_writelane_b32 v42, s7, 51
-; SI-NEXT: s_and_b32 s7, s6, 0xffff0000
+; SI-NEXT: s_and_b32 s89, s17, 0xffff0000
+; SI-NEXT: s_lshl_b32 s88, s17, 16
+; SI-NEXT: s_and_b32 s17, s13, 0xffff0000
+; SI-NEXT: s_add_i32 s7, s7, 0x3000000
; SI-NEXT: s_or_b32 s24, s25, s24
-; SI-NEXT: v_writelane_b32 v42, s7, 52
+; SI-NEXT: s_and_b32 s74, s18, 0xffff0000
+; SI-NEXT: s_lshl_b32 s25, s18, 16
+; SI-NEXT: v_writelane_b32 v43, s17, 49
+; SI-NEXT: s_and_b32 s63, s11, 0xffff0000
+; SI-NEXT: s_lshl_b32 s18, s11, 16
+; SI-NEXT: s_and_b32 s11, s9, 0xffff0000
+; SI-NEXT: s_and_b32 s46, s46, 0xff
+; SI-NEXT: s_add_i32 s6, s6, 0x3000000
+; SI-NEXT: v_writelane_b32 v43, s11, 50
+; SI-NEXT: s_lshl_b32 s61, s9, 16
+; SI-NEXT: s_and_b32 s9, s7, 0xffff0000
+; SI-NEXT: s_lshl_b32 s46, s46, 16
+; SI-NEXT: s_addk_i32 s56, 0x300
+; SI-NEXT: s_add_i32 s8, s8, 0x3000000
+; SI-NEXT: v_writelane_b32 v43, s9, 51
+; SI-NEXT: s_lshl_b32 s17, s7, 16
+; SI-NEXT: s_and_b32 s7, s6, 0xffff0000
+; SI-NEXT: s_or_b32 s46, s47, s46
+; SI-NEXT: s_and_b32 s47, s56, 0xffff
+; SI-NEXT: v_writelane_b32 v43, s7, 52
; SI-NEXT: s_and_b32 s7, s8, 0xffff0000
+; SI-NEXT: s_or_b32 s56, s46, s47
+; SI-NEXT: s_add_i32 s47, s58, 0x3000000
+; SI-NEXT: s_add_i32 s58, s59, 0x3000000
+; SI-NEXT: v_writelane_b32 v43, s7, 53
+; SI-NEXT: s_lshl_b32 s7, s8, 16
+; SI-NEXT: s_add_i32 s57, s57, 0x3000000
+; SI-NEXT: v_writelane_b32 v43, s7, 54
+; SI-NEXT: s_and_b32 s7, s58, 0xffff0000
; SI-NEXT: s_add_i32 s4, s4, 0x3000000
; SI-NEXT: s_add_i32 s5, s5, 0x3000000
; SI-NEXT: s_add_i32 s46, s60, 0x3000000
; SI-NEXT: s_add_i32 s56, s56, 0x3000000
-; SI-NEXT: s_add_i32 s57, s57, 0x3000000
-; SI-NEXT: s_add_i32 s11, s11, 0x3000000
+; SI-NEXT: s_add_i32 s10, s10, 0x3000000
; SI-NEXT: s_add_i32 s12, s12, 0x3000000
-; SI-NEXT: s_add_i32 s13, s13, 0x3000000
; SI-NEXT: s_add_i32 s16, s16, 0x3000000
-; SI-NEXT: s_add_i32 s18, s18, 0x3000000
; SI-NEXT: s_add_i32 s19, s19, 0x3000000
; SI-NEXT: s_add_i32 s20, s20, 0x3000000
; SI-NEXT: s_add_i32 s24, s24, 0x3000000
-; SI-NEXT: v_writelane_b32 v42, s7, 53
-; SI-NEXT: s_lshl_b32 s7, s8, 16
+; SI-NEXT: v_writelane_b32 v43, s7, 55
+; SI-NEXT: s_and_b32 s7, s57, 0xffff0000
; SI-NEXT: s_and_b32 s27, s24, 0xffff0000
; SI-NEXT: s_lshl_b32 s26, s24, 16
-; SI-NEXT: s_and_b32 s24, s20, 0xffff0000
+; SI-NEXT: s_and_b32 s65, s20, 0xffff0000
; SI-NEXT: s_lshl_b32 s20, s20, 16
-; SI-NEXT: s_and_b32 s35, s23, 0xffff0000
+; SI-NEXT: s_and_b32 s66, s23, 0xffff0000
; SI-NEXT: s_lshl_b32 s29, s23, 16
-; SI-NEXT: s_and_b32 s90, s22, 0xffff0000
-; SI-NEXT: s_lshl_b32 s74, s22, 16
-; SI-NEXT: s_and_b32 s25, s21, 0xffff0000
+; SI-NEXT: s_and_b32 s64, s22, 0xffff0000
+; SI-NEXT: s_lshl_b32 s95, s22, 16
+; SI-NEXT: s_and_b32 s76, s21, 0xffff0000
; SI-NEXT: s_lshl_b32 s21, s21, 16
-; SI-NEXT: s_and_b32 s75, s19, 0xffff0000
+; SI-NEXT: s_and_b32 s77, s19, 0xffff0000
; SI-NEXT: s_lshl_b32 s22, s19, 16
-; SI-NEXT: s_and_b32 s61, s18, 0xffff0000
-; SI-NEXT: s_lshl_b32 s76, s18, 16
-; SI-NEXT: s_and_b32 s77, s16, 0xffff0000
+; SI-NEXT: s_and_b32 s78, s16, 0xffff0000
; SI-NEXT: s_lshl_b32 s16, s16, 16
-; SI-NEXT: s_and_b32 s89, s13, 0xffff0000
; SI-NEXT: s_lshl_b32 s19, s13, 16
-; SI-NEXT: s_and_b32 s13, s12, 0xffff0000
-; SI-NEXT: s_lshl_b32 s88, s12, 16
-; SI-NEXT: s_and_b32 s60, s11, 0xffff0000
-; SI-NEXT: s_lshl_b32 s18, s11, 16
-; SI-NEXT: s_and_b32 s23, s10, 0xffff0000
+; SI-NEXT: s_and_b32 s75, s12, 0xffff0000
+; SI-NEXT: s_lshl_b32 s79, s12, 16
+; SI-NEXT: s_and_b32 s13, s10, 0xffff0000
+; SI-NEXT: s_lshl_b32 s59, s10, 16
; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: v_writelane_b32 v42, s7, 54
-; SI-NEXT: s_and_b32 s72, s58, 0xffff0000
; SI-NEXT: s_lshl_b32 s99, s58, 16
-; SI-NEXT: s_and_b32 s7, s57, 0xffff0000
+; SI-NEXT: v_writelane_b32 v43, s7, 56
; SI-NEXT: s_lshl_b32 s57, s57, 16
-; SI-NEXT: s_and_b32 s49, s56, 0xffff0000
+; SI-NEXT: s_and_b32 s7, s56, 0xffff0000
; SI-NEXT: s_lshl_b32 s8, s56, 16
-; SI-NEXT: s_and_b32 s51, s47, 0xffff0000
-; SI-NEXT: s_lshl_b32 s50, s47, 16
-; SI-NEXT: s_and_b32 s52, s46, 0xffff0000
+; SI-NEXT: s_and_b32 s56, s47, 0xffff0000
+; SI-NEXT: s_lshl_b32 s23, s47, 16
+; SI-NEXT: s_and_b32 s47, s46, 0xffff0000
; SI-NEXT: s_lshl_b32 s97, s46, 16
-; SI-NEXT: s_and_b32 s54, s45, 0xffff0000
-; SI-NEXT: s_lshl_b32 s53, s45, 16
-; SI-NEXT: s_and_b32 s55, s44, 0xffff0000
+; SI-NEXT: s_and_b32 s24, s45, 0xffff0000
+; SI-NEXT: s_lshl_b32 s45, s45, 16
+; SI-NEXT: s_and_b32 s58, s44, 0xffff0000
; SI-NEXT: s_lshl_b32 s28, s44, 16
-; SI-NEXT: s_and_b32 s65, s43, 0xffff0000
-; SI-NEXT: s_lshl_b32 s64, s43, 16
-; SI-NEXT: s_and_b32 s66, s42, 0xffff0000
+; SI-NEXT: s_and_b32 s73, s43, 0xffff0000
+; SI-NEXT: s_lshl_b32 s46, s43, 16
+; SI-NEXT: s_and_b32 s67, s42, 0xffff0000
; SI-NEXT: s_lshl_b32 s87, s42, 16
; SI-NEXT: s_and_b32 s68, s41, 0xffff0000
-; SI-NEXT: s_lshl_b32 s67, s41, 16
-; SI-NEXT: s_and_b32 s69, s40, 0xffff0000
+; SI-NEXT: s_lshl_b32 s42, s41, 16
+; SI-NEXT: s_and_b32 s70, s40, 0xffff0000
; SI-NEXT: s_lshl_b32 s86, s40, 16
-; SI-NEXT: s_and_b32 s62, s15, 0xffff0000
-; SI-NEXT: s_lshl_b32 s70, s15, 16
-; SI-NEXT: s_and_b32 s80, s14, 0xffff0000
+; SI-NEXT: s_and_b32 s94, s15, 0xffff0000
+; SI-NEXT: s_lshl_b32 s69, s15, 16
+; SI-NEXT: s_and_b32 s11, s14, 0xffff0000
; SI-NEXT: s_lshl_b32 s85, s14, 16
-; SI-NEXT: s_and_b32 s92, s5, 0xffff0000
-; SI-NEXT: s_lshl_b32 s11, s5, 16
-; SI-NEXT: s_and_b32 s83, s4, 0xffff0000
+; SI-NEXT: s_and_b32 s31, s5, 0xffff0000
+; SI-NEXT: s_lshl_b32 s80, s5, 16
+; SI-NEXT: s_and_b32 s15, s4, 0xffff0000
; SI-NEXT: s_lshl_b32 s84, s4, 16
-; SI-NEXT: v_writelane_b32 v42, s7, 55
+; SI-NEXT: v_writelane_b32 v43, s7, 57
; SI-NEXT: .LBB89_3: ; %end
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s27
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s26
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s26
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_readlane_b32 s4, v43, 49
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s24
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s20
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s65
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s20
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s35
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s29
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s66
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s29
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s90
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s74
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s64
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s95
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s25
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s21
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s76
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s21
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s75
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s22
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s77
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s22
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s61
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s76
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s74
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s25
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s77
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s16
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s78
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s16
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s63
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s79
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s89
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s88
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s89
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s19
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s13
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s88
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s75
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s79
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s60
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s63
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s18
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
+; SI-NEXT: v_readlane_b32 s4, v43, 50
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s73
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s59
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s61
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
-; SI-NEXT: v_readlane_b32 s4, v42, 50
+; SI-NEXT: v_readlane_b32 s4, v43, 51
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s17
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s17
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s23
-; SI-NEXT: v_readlane_b32 s4, v42, 51
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s13
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s59
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
-; SI-NEXT: v_readlane_b32 s4, v42, 52
+; SI-NEXT: v_readlane_b32 s4, v43, 52
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s6
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0
-; SI-NEXT: v_readlane_b32 s4, v42, 53
+; SI-NEXT: v_readlane_b32 s4, v43, 53
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
-; SI-NEXT: v_readlane_b32 s4, v42, 54
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_readlane_b32 s4, v43, 54
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0
+; SI-NEXT: v_readlane_b32 s4, v43, 55
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s72
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s99
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s99
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0
-; SI-NEXT: v_readlane_b32 s4, v42, 55
+; SI-NEXT: v_readlane_b32 s4, v43, 56
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s57
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s57
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0
+; SI-NEXT: v_readlane_b32 s4, v43, 57
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s49
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s8
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s8
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s51
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s50
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s56
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s23
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s52
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s97
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s47
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s97
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s54
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s53
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s24
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s45
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s55
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s28
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s58
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s28
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s65
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s64
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s73
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s46
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s66
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s87
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s67
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s87
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s68
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s67
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s42
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s69
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s86
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s70
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s86
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s62
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s70
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s94
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s69
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s80
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s85
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s11
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s85
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s92
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s11
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s31
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s80
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s83
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s84
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s15
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s84
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
@@ -155666,6 +156510,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -155676,99 +156521,109 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: ; implicit-def: $sgpr8
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr8
-; SI-NEXT: v_readlane_b32 s58, v43, 19
+; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; implicit-def: $sgpr8
-; SI-NEXT: s_mov_b32 s95, s47
-; SI-NEXT: s_mov_b32 s94, s21
-; SI-NEXT: s_mov_b32 s93, s61
-; SI-NEXT: s_mov_b32 s34, s73
-; SI-NEXT: s_mov_b32 s91, s75
-; SI-NEXT: v_readlane_b32 s56, v43, 10
-; SI-NEXT: s_mov_b32 s36, s63
-; SI-NEXT: s_mov_b32 s38, s59
-; SI-NEXT: s_mov_b32 s37, s42
-; SI-NEXT: v_readlane_b32 s30, v43, 17
-; SI-NEXT: v_readlane_b32 s98, v43, 6
-; SI-NEXT: s_mov_b32 s46, s45
-; SI-NEXT: s_mov_b32 s31, s43
-; SI-NEXT: s_mov_b32 s78, s40
-; SI-NEXT: v_readlane_b32 s15, v43, 14
-; SI-NEXT: s_mov_b32 s39, s57
-; SI-NEXT: s_mov_b32 s48, s13
-; SI-NEXT: v_readlane_b32 s41, v43, 13
-; SI-NEXT: v_readlane_b32 s44, v43, 5
-; SI-NEXT: v_readlane_b32 s9, v43, 11
-; SI-NEXT: v_readlane_b32 s14, v43, 12
-; SI-NEXT: v_readlane_b32 s81, v43, 9
-; SI-NEXT: v_readlane_b32 s10, v43, 16
-; SI-NEXT: v_readlane_b32 s12, v43, 4
-; SI-NEXT: v_readlane_b32 s96, v43, 7
-; SI-NEXT: v_readlane_b32 s82, v43, 8
-; SI-NEXT: v_readlane_b32 s71, v43, 15
+; SI-NEXT: ; kill: killed $sgpr8
+; SI-NEXT: v_readlane_b32 s92, v44, 24
+; SI-NEXT: ; implicit-def: $sgpr8
+; SI-NEXT: v_readlane_b32 s91, v44, 20
+; SI-NEXT: s_mov_b32 s90, s88
+; SI-NEXT: v_readlane_b32 s36, v44, 23
+; SI-NEXT: v_readlane_b32 s35, v44, 19
+; SI-NEXT: v_readlane_b32 s62, v44, 22
+; SI-NEXT: v_readlane_b32 s38, v44, 18
+; SI-NEXT: s_mov_b32 s34, s46
+; SI-NEXT: s_mov_b32 s93, s21
+; SI-NEXT: s_mov_b32 s37, s43
+; SI-NEXT: s_mov_b32 s39, s75
+; SI-NEXT: v_readlane_b32 s72, v44, 10
+; SI-NEXT: s_mov_b32 s50, s63
+; SI-NEXT: s_mov_b32 s51, s59
+; SI-NEXT: s_mov_b32 s48, s56
+; SI-NEXT: v_readlane_b32 s30, v44, 21
+; SI-NEXT: s_mov_b32 s49, s61
+; SI-NEXT: s_mov_b32 s52, s79
+; SI-NEXT: v_readlane_b32 s98, v44, 6
+; SI-NEXT: s_mov_b32 s55, s45
+; SI-NEXT: v_readlane_b32 s43, v44, 17
+; SI-NEXT: s_mov_b32 s60, s40
+; SI-NEXT: v_readlane_b32 s41, v44, 14
+; SI-NEXT: s_mov_b32 s53, s42
+; SI-NEXT: s_mov_b32 s54, s13
+; SI-NEXT: v_readlane_b32 s14, v44, 13
+; SI-NEXT: v_readlane_b32 s44, v44, 5
+; SI-NEXT: v_readlane_b32 s9, v44, 11
+; SI-NEXT: v_readlane_b32 s81, v44, 12
+; SI-NEXT: v_readlane_b32 s82, v44, 9
+; SI-NEXT: v_readlane_b32 s10, v44, 16
+; SI-NEXT: v_readlane_b32 s12, v44, 4
+; SI-NEXT: v_readlane_b32 s96, v44, 7
+; SI-NEXT: v_readlane_b32 s83, v44, 8
+; SI-NEXT: v_readlane_b32 s71, v44, 15
; SI-NEXT: ; kill: killed $sgpr6
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr8
; SI-NEXT: ; implicit-def: $sgpr8
+; SI-NEXT: ; implicit-def: $sgpr11
; SI-NEXT: ; implicit-def: $sgpr26
; SI-NEXT: ; implicit-def: $sgpr27
; SI-NEXT: ; implicit-def: $sgpr20
-; SI-NEXT: ; implicit-def: $sgpr24
+; SI-NEXT: ; implicit-def: $sgpr65
; SI-NEXT: ; implicit-def: $sgpr29
-; SI-NEXT: ; implicit-def: $sgpr35
-; SI-NEXT: ; implicit-def: $sgpr74
-; SI-NEXT: ; implicit-def: $sgpr90
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr95
+; SI-NEXT: ; implicit-def: $sgpr64
; SI-NEXT: ; implicit-def: $sgpr21
-; SI-NEXT: ; implicit-def: $sgpr25
-; SI-NEXT: ; implicit-def: $sgpr22
-; SI-NEXT: ; implicit-def: $sgpr75
; SI-NEXT: ; implicit-def: $sgpr76
-; SI-NEXT: ; implicit-def: $sgpr61
-; SI-NEXT: ; implicit-def: $sgpr16
+; SI-NEXT: ; implicit-def: $sgpr22
; SI-NEXT: ; implicit-def: $sgpr77
-; SI-NEXT: ; implicit-def: $sgpr79
-; SI-NEXT: ; implicit-def: $sgpr63
-; SI-NEXT: ; implicit-def: $sgpr19
-; SI-NEXT: ; implicit-def: $sgpr89
+; SI-NEXT: ; implicit-def: $sgpr25
+; SI-NEXT: ; implicit-def: $sgpr74
+; SI-NEXT: ; implicit-def: $sgpr16
+; SI-NEXT: ; implicit-def: $sgpr78
; SI-NEXT: ; implicit-def: $sgpr88
-; SI-NEXT: ; implicit-def: $sgpr13
+; SI-NEXT: ; implicit-def: $sgpr89
+; SI-NEXT: ; implicit-def: $sgpr19
+; SI-NEXT: ; implicit-def: $sgpr79
+; SI-NEXT: ; implicit-def: $sgpr75
; SI-NEXT: ; implicit-def: $sgpr18
-; SI-NEXT: ; implicit-def: $sgpr60
-; SI-NEXT: ; implicit-def: $sgpr59
-; SI-NEXT: ; implicit-def: $sgpr73
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr61
; SI-NEXT: ; implicit-def: $sgpr17
; SI-NEXT: ; kill: killed $sgpr6
-; SI-NEXT: ; implicit-def: $sgpr23
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr13
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; implicit-def: $sgpr99
-; SI-NEXT: ; implicit-def: $sgpr72
; SI-NEXT: ; implicit-def: $sgpr57
; SI-NEXT: ; kill: killed $sgpr8
; SI-NEXT: ; implicit-def: $sgpr8
-; SI-NEXT: ; implicit-def: $sgpr49
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; implicit-def: $sgpr51
+; SI-NEXT: ; kill: killed $sgpr11
+; SI-NEXT: ; implicit-def: $sgpr23
+; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr97
-; SI-NEXT: ; implicit-def: $sgpr52
-; SI-NEXT: ; implicit-def: $sgpr53
-; SI-NEXT: ; implicit-def: $sgpr54
+; SI-NEXT: ; implicit-def: $sgpr47
+; SI-NEXT: ; implicit-def: $sgpr45
+; SI-NEXT: ; implicit-def: $sgpr24
; SI-NEXT: ; implicit-def: $sgpr28
-; SI-NEXT: ; implicit-def: $sgpr55
-; SI-NEXT: ; implicit-def: $sgpr64
-; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: ; implicit-def: $sgpr73
; SI-NEXT: ; implicit-def: $sgpr87
-; SI-NEXT: ; implicit-def: $sgpr66
; SI-NEXT: ; implicit-def: $sgpr67
+; SI-NEXT: ; implicit-def: $sgpr42
; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; implicit-def: $sgpr86
-; SI-NEXT: ; implicit-def: $sgpr69
; SI-NEXT: ; implicit-def: $sgpr70
-; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr69
+; SI-NEXT: ; implicit-def: $sgpr94
; SI-NEXT: ; implicit-def: $sgpr85
-; SI-NEXT: ; implicit-def: $sgpr80
; SI-NEXT: ; implicit-def: $sgpr11
-; SI-NEXT: ; implicit-def: $sgpr92
+; SI-NEXT: ; implicit-def: $sgpr80
+; SI-NEXT: ; implicit-def: $sgpr31
; SI-NEXT: ; implicit-def: $sgpr84
-; SI-NEXT: ; implicit-def: $sgpr83
+; SI-NEXT: ; implicit-def: $sgpr15
; SI-NEXT: s_branch .LBB89_2
;
; VI-LABEL: bitcast_v128i8_to_v64bf16_scalar:
@@ -167038,40 +167893,43 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:80
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:16
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:28
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:24
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:44
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:40
; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:52
; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:68
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:64
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76
@@ -167104,1627 +167962,1841 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: v_writelane_b32 v63, s81, 25
; SI-NEXT: v_writelane_b32 v63, s82, 26
; SI-NEXT: v_writelane_b32 v63, s83, 27
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_mul_f32_e32 v56, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
; SI-NEXT: v_writelane_b32 v63, s84, 28
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9
; SI-NEXT: v_writelane_b32 v63, s85, 29
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v14
; SI-NEXT: v_writelane_b32 v63, s86, 30
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15
; SI-NEXT: v_writelane_b32 v63, s87, 31
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v18
+; SI-NEXT: v_mul_f32_e32 v39, 1.0, v10
; SI-NEXT: v_writelane_b32 v63, s96, 32
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v26
; SI-NEXT: v_writelane_b32 v63, s97, 33
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
; SI-NEXT: v_writelane_b32 v63, s98, 34
-; SI-NEXT: v_mov_b32_e32 v46, v21
; SI-NEXT: v_writelane_b32 v63, s99, 35
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v58, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v59, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v60, 1.0, v11
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v16
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v46
+; SI-NEXT: v_mul_f32_e32 v35, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v51, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v47, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v46, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v7
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v48
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v60, 1.0, v9
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v14
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v55, 1.0, v18
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v17
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v22
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v21
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v24
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v23
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v32
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v26
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v38
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v33
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v34
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v48
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v30
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v29
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v33
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v34
+; SI-NEXT: s_waitcnt vmcnt(8) expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v54
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v35
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v36
-; SI-NEXT: v_mul_f32_e32 v35, 1.0, v37
-; SI-NEXT: v_mul_f32_e32 v34, 1.0, v38
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v39
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v49
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v50
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v51
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v53
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v54
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v55
-; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: s_waitcnt vmcnt(6) expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v42
+; SI-NEXT: v_mul_f32_e32 v33, 1.0, v36
+; SI-NEXT: v_mul_f32_e32 v37, 1.0, v37
+; SI-NEXT: v_mul_f32_e32 v57, 1.0, v57
+; SI-NEXT: v_mul_f32_e32 v36, 1.0, v58
+; SI-NEXT: v_mul_f32_e32 v58, 1.0, v59
+; SI-NEXT: v_mul_f32_e32 v59, 1.0, v49
+; SI-NEXT: v_mul_f32_e32 v50, 1.0, v50
+; SI-NEXT: v_mul_f32_e32 v49, 1.0, v52
+; SI-NEXT: v_mul_f32_e32 v53, 1.0, v53
; SI-NEXT: v_mul_f32_e32 v38, 1.0, v40
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v42
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v43
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v44
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v45
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v14, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v15, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v18, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v19, 1.0, s24
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v23, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v25, 1.0, s28
+; SI-NEXT: v_mul_f32_e32 v40, 1.0, v41
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(6) expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v43
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_mul_f32_e32 v56, 1.0, v44
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v45
+; SI-NEXT: v_mul_f32_e64 v13, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v15, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v52, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v11, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v30, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v34, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v54, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v41, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v42, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v45, 1.0, s27
+; SI-NEXT: v_mul_f32_e64 v48, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v43, 1.0, s29
+; SI-NEXT: v_mul_f32_e64 v44, 1.0, s28
; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr61 : SGPR spill to VGPR lane
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB91_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v3
-; SI-NEXT: v_mov_b32_e32 v42, v37
-; SI-NEXT: v_alignbit_b32 v37, v2, v11, 16
-; SI-NEXT: v_alignbit_b32 v11, v44, v4, 16
-; SI-NEXT: v_readfirstlane_b32 s4, v37
-; SI-NEXT: v_readfirstlane_b32 s5, v11
-; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v14
-; SI-NEXT: v_writelane_b32 v62, s6, 0
-; SI-NEXT: v_alignbit_b32 v2, v2, v15, 16
-; SI-NEXT: v_writelane_b32 v62, s7, 1
-; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[10:11], s[4:5], 8
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v14, v52, v6, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; SI-NEXT: v_readfirstlane_b32 s5, v14
-; SI-NEXT: v_alignbit_b32 v2, v2, v19, 16
-; SI-NEXT: s_lshr_b64 s[8:9], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[12:13], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 8
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v10
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v19, v2, v8, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v23
-; SI-NEXT: v_readfirstlane_b32 s5, v19
-; SI-NEXT: v_alignbit_b32 v2, v2, v25, 16
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v56
-; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[18:19], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[22:23], s[4:5], 8
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: v_alignbit_b32 v47, v45, v47, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v32
-; SI-NEXT: v_readfirstlane_b32 s5, v47
-; SI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v58
-; SI-NEXT: s_lshr_b64 s[20:21], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[24:25], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[28:29], s[4:5], 8
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: v_mov_b32_e32 v4, v58
-; SI-NEXT: v_alignbit_b32 v58, v8, v41, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v59
-; SI-NEXT: v_readfirstlane_b32 s5, v58
-; SI-NEXT: v_alignbit_b32 v2, v2, v61, 16
-; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[40:41], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[44:45], s[4:5], 8
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v5
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v2, v2, v60, 16
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v23, v22
-; SI-NEXT: v_mov_b32_e32 v40, v36
-; SI-NEXT: s_mov_b64 vcc, 0
-; SI-NEXT: v_lshrrev_b32_e32 v56, 24, v56
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v18
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_alignbit_b32 v41, v15, v6, 16
-; SI-NEXT: v_readfirstlane_b32 s5, v41
-; SI-NEXT: s_lshr_b64 s[42:43], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[58:59], s[4:5], 8
-; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v32
-; SI-NEXT: v_alignbit_b32 v59, v1, v13, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s5, v59
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; SI-NEXT: s_lshr_b64 s[56:57], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[60:61], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[72:73], s[4:5], 8
-; SI-NEXT: v_alignbit_b32 v61, v1, v17, 16
-; SI-NEXT: v_readfirstlane_b32 s5, v61
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v13, 8, v58
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_alignbit_b32 v2, v2, v21, 16
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v9
-; SI-NEXT: v_alignbit_b32 v2, v2, v12, 16
-; SI-NEXT: s_lshr_b64 s[62:63], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[74:75], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[78:79], s[4:5], 8
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v22
-; SI-NEXT: v_alignbit_b32 v60, v2, v20, 16
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v24
-; SI-NEXT: v_alignbit_b32 v1, v2, v46, 16
-; SI-NEXT: v_readfirstlane_b32 s5, v60
-; SI-NEXT: s_lshr_b64 s[76:77], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[88:89], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[92:93], s[4:5], 8
+; SI-NEXT: v_readfirstlane_b32 s4, v13
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v15
+; SI-NEXT: s_lshr_b64 s[8:9], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v52
+; SI-NEXT: s_lshr_b32 s7, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v30
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v34
+; SI-NEXT: s_lshr_b64 s[86:87], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v54
+; SI-NEXT: s_lshr_b32 s65, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v41
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v42
+; SI-NEXT: s_lshr_b64 s[80:81], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v45
+; SI-NEXT: s_lshr_b32 s69, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v43
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v44
+; SI-NEXT: v_mov_b32_e32 v34, v35
+; SI-NEXT: s_lshr_b64 s[66:67], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v34
+; SI-NEXT: s_lshr_b32 s91, s4, 16
+; SI-NEXT: v_mov_b32_e32 v30, v51
+; SI-NEXT: v_readfirstlane_b32 s4, v47
+; SI-NEXT: v_mov_b32_e32 v51, v46
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v51
+; SI-NEXT: v_mov_b32_e32 v35, v6
+; SI-NEXT: s_lshr_b64 s[52:53], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v35
+; SI-NEXT: s_lshr_b32 s37, s4, 16
; SI-NEXT: v_readfirstlane_b32 s4, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v1, v5
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v23
-; SI-NEXT: v_mov_b32_e32 v5, v28
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v24, 24, v10
-; SI-NEXT: v_lshrrev_b32_e32 v9, 8, v47
-; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v41
-; SI-NEXT: v_lshrrev_b32_e32 v10, 8, v61
-; SI-NEXT: v_lshrrev_b32_e32 v23, 8, v60
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v20
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v25, v2, v26, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v57
-; SI-NEXT: v_readfirstlane_b32 s5, v25
-; SI-NEXT: v_alignbit_b32 v2, v2, v16, 16
-; SI-NEXT: s_lshr_b64 s[90:91], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[94:95], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[34:35], s[4:5], 8
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v28
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v22, v2, v30, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v31
-; SI-NEXT: v_readfirstlane_b32 s5, v22
-; SI-NEXT: v_alignbit_b32 v2, v2, v27, 16
-; SI-NEXT: s_lshr_b64 s[30:31], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[36:37], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[38:39], s[4:5], 8
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v29
-; SI-NEXT: v_alignbit_b32 v17, v2, v36, 16
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v35
-; SI-NEXT: v_readfirstlane_b32 s5, v17
-; SI-NEXT: v_alignbit_b32 v2, v2, v34, 16
-; SI-NEXT: s_lshr_b64 s[48:49], s[4:5], 24
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_mov_b32_e32 v41, v5
+; SI-NEXT: v_readfirstlane_b32 s4, v5
+; SI-NEXT: v_mov_b32_e32 v5, v39
+; SI-NEXT: s_lshr_b64 s[30:31], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v5
+; SI-NEXT: s_lshr_b32 s89, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v9
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v31
; SI-NEXT: s_lshr_b64 s[50:51], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[52:53], s[4:5], 8
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v42
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v20
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v5
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v22
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v29
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v29, v37
-; SI-NEXT: v_mov_b32_e32 v37, v42
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v17
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v37
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v33
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v34, 24, v4
+; SI-NEXT: s_lshr_b32 s57, s4, 16
+; SI-NEXT: v_mov_b32_e32 v42, v32
+; SI-NEXT: v_readfirstlane_b32 s4, v32
+; SI-NEXT: v_mov_b32_e32 v32, v4
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v32
+; SI-NEXT: v_mov_b32_e32 v6, v55
+; SI-NEXT: s_lshr_b64 s[92:93], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v6
+; SI-NEXT: s_lshr_b32 s79, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v20
+; SI-NEXT: v_mov_b32_e32 v39, v12
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v39
+; SI-NEXT: v_mov_b32_e32 v9, v8
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: v_mov_b32_e32 v43, v20
+; SI-NEXT: s_lshr_b64 s[76:77], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v9
+; SI-NEXT: v_mov_b32_e32 v20, v21
+; SI-NEXT: v_readfirstlane_b32 s78, v18
+; SI-NEXT: s_lshr_b32 s73, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v20
+; SI-NEXT: v_mov_b32_e32 v18, v22
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v18
+; SI-NEXT: s_lshr_b64 s[62:63], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v23
+; SI-NEXT: s_lshr_b32 s59, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v28
+; SI-NEXT: v_mov_b32_e32 v21, v25
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v27
+; SI-NEXT: v_mov_b32_e32 v25, v26
+; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v25
+; SI-NEXT: v_mov_b32_e32 v12, v29
+; SI-NEXT: s_lshr_b32 s45, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v12
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: v_mov_b32_e32 v44, v1
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_mov_b32_e32 v1, v52
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: v_mov_b32_e32 v52, v17
+; SI-NEXT: v_readfirstlane_b32 s4, v17
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v29, v33
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v22, v24
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: s_lshr_b64 s[40:41], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v29
+; SI-NEXT: s_lshr_b32 s29, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s6, v11
+; SI-NEXT: v_readfirstlane_b32 s12, v40
+; SI-NEXT: s_lshr_b64 s[96:97], s[6:7], 16
+; SI-NEXT: s_mov_b32 s9, s96
+; SI-NEXT: v_readfirstlane_b32 s88, v60
+; SI-NEXT: s_lshr_b64 s[82:83], s[88:89], 16
+; SI-NEXT: v_readfirstlane_b32 s64, v16
+; SI-NEXT: s_lshr_b64 s[84:85], s[64:65], 16
+; SI-NEXT: s_mov_b32 s87, s84
+; SI-NEXT: v_readfirstlane_b32 s68, v48
+; SI-NEXT: s_lshr_b64 s[70:71], s[68:69], 16
+; SI-NEXT: s_mov_b32 s81, s70
+; SI-NEXT: v_readfirstlane_b32 s90, v30
+; SI-NEXT: s_lshr_b64 s[38:39], s[90:91], 16
+; SI-NEXT: s_mov_b32 s67, s38
+; SI-NEXT: v_readfirstlane_b32 s36, v3
+; SI-NEXT: s_lshr_b64 s[98:99], s[36:37], 16
+; SI-NEXT: s_mov_b32 s53, s98
+; SI-NEXT: s_mov_b32 s31, s82
+; SI-NEXT: v_readfirstlane_b32 s56, v7
+; SI-NEXT: s_lshr_b64 s[94:95], s[56:57], 16
+; SI-NEXT: s_mov_b32 s51, s94
+; SI-NEXT: s_lshr_b64 s[74:75], s[78:79], 16
+; SI-NEXT: s_mov_b32 s93, s74
+; SI-NEXT: v_readfirstlane_b32 s72, v19
+; SI-NEXT: s_lshr_b64 s[60:61], s[72:73], 16
+; SI-NEXT: s_mov_b32 s77, s60
+; SI-NEXT: v_readfirstlane_b32 s58, v21
+; SI-NEXT: s_lshr_b64 s[54:55], s[58:59], 16
+; SI-NEXT: s_mov_b32 s63, s54
+; SI-NEXT: v_readfirstlane_b32 s44, v22
+; SI-NEXT: s_lshr_b64 s[42:43], s[44:45], 16
+; SI-NEXT: s_mov_b32 s47, s42
+; SI-NEXT: v_mov_b32_e32 v26, v37
+; SI-NEXT: v_readfirstlane_b32 s28, v26
+; SI-NEXT: s_lshr_b64 s[26:27], s[28:29], 16
+; SI-NEXT: s_mov_b32 s41, s26
+; SI-NEXT: v_readfirstlane_b32 s22, v36
+; SI-NEXT: v_readfirstlane_b32 s18, v49
+; SI-NEXT: v_lshrrev_b32_e32 v48, 24, v1
+; SI-NEXT: v_mov_b32_e32 v1, v56
+; SI-NEXT: v_mov_b32_e32 v3, v54
+; SI-NEXT: v_lshrrev_b32_e32 v37, 24, v6
+; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v50
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v38
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v1
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_mov_b32_e32 v54, v59
+; SI-NEXT: s_lshr_b32 s78, s96, 8
+; SI-NEXT: s_lshr_b32 s61, s84, 8
+; SI-NEXT: s_lshr_b32 s72, s70, 8
+; SI-NEXT: s_lshr_b32 s75, s38, 8
+; SI-NEXT: s_lshr_b32 s58, s98, 8
+; SI-NEXT: s_lshr_b32 s43, s82, 8
+; SI-NEXT: s_lshr_b32 s44, s94, 8
+; SI-NEXT: s_mov_b32 s64, s74
+; SI-NEXT: s_lshr_b32 s27, s74, 8
+; SI-NEXT: s_mov_b32 s90, s60
+; SI-NEXT: s_lshr_b32 s28, s60, 8
+; SI-NEXT: s_lshr_b32 s74, s54, 8
+; SI-NEXT: s_mov_b32 s68, s42
+; SI-NEXT: s_mov_b32 s56, s26
; SI-NEXT: v_lshrrev_b32_e32 v16, 24, v3
-; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v11
-; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v7
-; SI-NEXT: v_lshrrev_b32_e32 v7, 8, v14
-; SI-NEXT: v_lshrrev_b32_e32 v27, 8, v19
-; SI-NEXT: v_lshrrev_b32_e32 v4, 8, v59
-; SI-NEXT: v_lshrrev_b32_e32 v35, 24, v43
-; SI-NEXT: v_mov_b32_e32 v31, v20
-; SI-NEXT: v_mov_b32_e32 v20, v34
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_alignbit_b32 v30, v2, v36, 16
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v48
-; SI-NEXT: v_alignbit_b32 v2, v2, v39, 16
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; SI-NEXT: v_readfirstlane_b32 s5, v30
-; SI-NEXT: s_lshr_b64 s[54:55], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[64:65], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[68:69], s[4:5], 8
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v33
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v28, v36
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_alignbit_b32 v57, v2, v39, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v51
-; SI-NEXT: v_readfirstlane_b32 s5, v57
-; SI-NEXT: v_alignbit_b32 v2, v2, v50, 16
-; SI-NEXT: s_lshr_b64 s[66:67], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[70:71], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[82:83], s[4:5], 8
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v49
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v46, v2, v38, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v55
-; SI-NEXT: v_readfirstlane_b32 s5, v46
-; SI-NEXT: v_alignbit_b32 v2, v2, v54, 16
-; SI-NEXT: s_lshr_b64 s[80:81], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[84:85], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[96:97], s[4:5], 8
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v57
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v38, v2, v53, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 24, v18
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v49
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v2, v32
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v46
-; SI-NEXT: v_readfirstlane_b32 s5, v38
-; SI-NEXT: v_lshrrev_b32_e32 v2, 24, v2
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v38
-; SI-NEXT: s_lshr_b64 s[86:87], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[98:99], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 8
-; SI-NEXT: v_mov_b32_e32 v32, v8
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v18, 8, v25
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v30
-; SI-NEXT: v_mov_b32_e32 v55, v49
-; SI-NEXT: v_mov_b32_e32 v49, v15
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v8, v6
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v45
+; SI-NEXT: v_lshrrev_b32_e32 v13, 24, v34
+; SI-NEXT: v_lshrrev_b32_e32 v11, 24, v35
+; SI-NEXT: v_lshrrev_b32_e32 v47, 24, v5
+; SI-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; SI-NEXT: v_lshrrev_b32_e32 v55, 24, v9
+; SI-NEXT: v_lshrrev_b32_e32 v4, 24, v25
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_readfirstlane_b32 s4, v17
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_readfirstlane_b32 s4, v33
+; SI-NEXT: s_lshr_b64 s[24:25], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v57
+; SI-NEXT: s_lshr_b32 s23, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v58
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v59
+; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v50
+; SI-NEXT: s_lshr_b32 s19, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v53
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_readfirstlane_b32 s4, v24
+; SI-NEXT: s_lshr_b64 s[10:11], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v38
+; SI-NEXT: s_lshr_b32 s13, s4, 16
+; SI-NEXT: s_mov_b32 s5, s13
+; SI-NEXT: v_writelane_b32 v61, s4, 26
+; SI-NEXT: v_writelane_b32 v61, s5, 27
+; SI-NEXT: v_readfirstlane_b32 s4, v46
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v10
+; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s5, v56
+; SI-NEXT: s_lshr_b64 s[20:21], s[12:13], 16
+; SI-NEXT: s_lshr_b32 s13, s5, 16
+; SI-NEXT: v_readfirstlane_b32 s12, v14
+; SI-NEXT: s_lshr_b64 vcc, s[12:13], 16
+; SI-NEXT: s_mov_b32 s5, vcc_lo
+; SI-NEXT: s_mov_b32 s88, vcc_lo
+; SI-NEXT: s_lshr_b32 s6, vcc_lo, 8
+; SI-NEXT: s_lshr_b64 vcc, s[8:9], 24
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 4
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 5
+; SI-NEXT: s_lshr_b64 vcc, s[8:9], 16
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 2
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 3
+; SI-NEXT: s_lshr_b64 vcc, s[8:9], 8
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 0
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 1
+; SI-NEXT: s_lshr_b64 vcc, s[86:87], 24
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 10
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 11
+; SI-NEXT: s_lshr_b64 vcc, s[86:87], 16
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 8
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 9
+; SI-NEXT: s_lshr_b64 vcc, s[86:87], 8
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 6
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 7
+; SI-NEXT: s_lshr_b64 vcc, s[80:81], 24
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 16
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 17
+; SI-NEXT: s_lshr_b64 vcc, s[80:81], 16
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 14
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 15
+; SI-NEXT: s_lshr_b64 vcc, s[80:81], 8
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 12
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 13
+; SI-NEXT: s_lshr_b64 vcc, s[66:67], 24
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 22
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 23
+; SI-NEXT: s_lshr_b64 vcc, s[66:67], 16
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 20
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 21
+; SI-NEXT: s_lshr_b64 vcc, s[66:67], 8
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 18
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 19
+; SI-NEXT: s_lshr_b64 vcc, s[52:53], 24
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 28
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 29
+; SI-NEXT: s_lshr_b64 vcc, s[52:53], 16
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 26
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 27
+; SI-NEXT: s_lshr_b64 vcc, s[52:53], 8
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 24
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 25
+; SI-NEXT: s_lshr_b64 vcc, s[30:31], 24
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 34
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 35
+; SI-NEXT: s_lshr_b64 vcc, s[30:31], 16
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 32
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 33
+; SI-NEXT: s_lshr_b64 vcc, s[30:31], 8
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 30
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 31
+; SI-NEXT: s_lshr_b64 vcc, s[50:51], 24
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 40
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 41
+; SI-NEXT: s_lshr_b64 vcc, s[50:51], 16
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 38
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 39
+; SI-NEXT: s_lshr_b64 vcc, s[50:51], 8
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 36
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 37
+; SI-NEXT: s_lshr_b64 vcc, s[92:93], 24
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 46
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 47
+; SI-NEXT: s_lshr_b64 vcc, s[92:93], 16
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 44
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 45
+; SI-NEXT: s_lshr_b64 vcc, s[92:93], 8
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 42
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 43
+; SI-NEXT: s_lshr_b64 vcc, s[76:77], 24
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 52
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 53
+; SI-NEXT: s_lshr_b64 vcc, s[76:77], 16
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 50
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 51
+; SI-NEXT: s_lshr_b64 vcc, s[76:77], 8
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 48
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 49
+; SI-NEXT: s_lshr_b64 vcc, s[62:63], 24
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 58
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 59
+; SI-NEXT: s_lshr_b64 vcc, s[62:63], 16
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 56
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 57
+; SI-NEXT: s_lshr_b64 vcc, s[62:63], 8
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 54
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 55
+; SI-NEXT: s_lshr_b64 vcc, s[46:47], 24
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 0
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 1
+; SI-NEXT: s_lshr_b64 vcc, s[46:47], 16
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 62
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 63
+; SI-NEXT: s_lshr_b64 vcc, s[46:47], 8
+; SI-NEXT: v_writelane_b32 v62, vcc_lo, 60
+; SI-NEXT: v_writelane_b32 v62, vcc_hi, 61
+; SI-NEXT: s_lshr_b64 vcc, s[40:41], 24
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 6
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 7
+; SI-NEXT: s_lshr_b64 vcc, s[40:41], 16
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 4
+; SI-NEXT: s_lshr_b64 s[34:35], s[22:23], 16
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 5
+; SI-NEXT: s_lshr_b64 vcc, s[40:41], 8
+; SI-NEXT: s_mov_b32 s25, s34
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 2
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 3
+; SI-NEXT: s_lshr_b64 vcc, s[24:25], 24
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 12
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 13
+; SI-NEXT: s_lshr_b64 vcc, s[24:25], 16
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 10
+; SI-NEXT: s_lshr_b64 s[14:15], s[18:19], 16
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 11
+; SI-NEXT: s_lshr_b64 vcc, s[24:25], 8
+; SI-NEXT: s_mov_b32 s17, s14
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 8
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 9
+; SI-NEXT: s_lshr_b64 vcc, s[16:17], 24
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 18
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 19
+; SI-NEXT: s_lshr_b64 vcc, s[16:17], 16
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 16
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 17
+; SI-NEXT: s_lshr_b64 vcc, s[16:17], 8
+; SI-NEXT: s_mov_b32 s11, s20
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 14
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 15
+; SI-NEXT: s_lshr_b64 vcc, s[10:11], 24
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 24
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 25
+; SI-NEXT: s_lshr_b64 vcc, s[10:11], 16
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 22
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 23
+; SI-NEXT: s_lshr_b64 vcc, s[10:11], 8
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 20
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 21
+; SI-NEXT: s_lshr_b64 vcc, s[4:5], 24
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 32
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 33
+; SI-NEXT: s_lshr_b64 vcc, s[4:5], 16
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 30
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 31
+; SI-NEXT: s_lshr_b64 vcc, s[4:5], 8
+; SI-NEXT: v_writelane_b32 v61, vcc_lo, 28
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: v_lshrrev_b32_e32 v10, 24, v23
+; SI-NEXT: s_lshr_b32 s22, s42, 8
+; SI-NEXT: s_lshr_b32 s21, s26, 8
+; SI-NEXT: s_lshr_b32 s18, s34, 8
+; SI-NEXT: s_mov_b32 s36, s14
+; SI-NEXT: s_lshr_b32 s15, s14, 8
+; SI-NEXT: s_mov_b32 s14, s20
+; SI-NEXT: s_lshr_b32 s12, s20, 8
+; SI-NEXT: v_writelane_b32 v61, vcc_hi, 29
+; SI-NEXT: s_mov_b64 vcc, 0
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v29
+; SI-NEXT: v_lshrrev_b32_e32 v56, 24, v57
+; SI-NEXT: v_mov_b32_e32 v59, v30
+; SI-NEXT: v_mov_b32_e32 v31, v51
+; SI-NEXT: v_mov_b32_e32 v60, v34
+; SI-NEXT: v_mov_b32_e32 v30, v39
+; SI-NEXT: v_mov_b32_e32 v19, v5
+; SI-NEXT: v_mov_b32_e32 v39, v21
+; SI-NEXT: v_mov_b32_e32 v21, v20
+; SI-NEXT: v_mov_b32_e32 v34, v18
+; SI-NEXT: v_mov_b32_e32 v18, v37
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: v_mov_b32_e32 v7, v26
+; SI-NEXT: v_mov_b32_e32 v20, v2
+; SI-NEXT: v_mov_b32_e32 v37, v17
+; SI-NEXT: v_mov_b32_e32 v51, v33
+; SI-NEXT: v_mov_b32_e32 v17, v9
+; SI-NEXT: v_mov_b32_e32 v9, v10
+; SI-NEXT: v_mov_b32_e32 v26, v25
; SI-NEXT: s_branch .LBB91_3
; SI-NEXT: .LBB91_2:
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; kill: killed $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_mov_b32_e32 v55, v49
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; kill: killed $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_mov_b32_e32 v54, v59
; SI-NEXT: v_writelane_b32 v62, s4, 0
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; kill: killed $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: v_mov_b32_e32 v40, v36
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: v_writelane_b32 v62, s5, 1
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v59, v51
+; SI-NEXT: v_writelane_b32 v62, s4, 2
+; SI-NEXT: v_writelane_b32 v62, s5, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v31, v46
+; SI-NEXT: v_writelane_b32 v62, s4, 4
+; SI-NEXT: v_writelane_b32 v62, s5, 5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v34, v22
+; SI-NEXT: v_writelane_b32 v62, s4, 6
+; SI-NEXT: v_writelane_b32 v62, s5, 7
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v22, v24
+; SI-NEXT: v_writelane_b32 v62, s4, 8
+; SI-NEXT: v_writelane_b32 v62, s5, 9
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v7, v37
+; SI-NEXT: v_writelane_b32 v62, s4, 10
+; SI-NEXT: v_writelane_b32 v62, s5, 11
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: v_writelane_b32 v62, s4, 12
+; SI-NEXT: v_writelane_b32 v62, s5, 13
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: v_writelane_b32 v62, s4, 14
+; SI-NEXT: v_writelane_b32 v62, s5, 15
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr21
+; SI-NEXT: ; implicit-def: $sgpr20
+; SI-NEXT: ; implicit-def: $sgpr89
+; SI-NEXT: ; implicit-def: $sgpr88
+; SI-NEXT: v_mov_b32_e32 v44, v1
+; SI-NEXT: v_writelane_b32 v62, s4, 16
+; SI-NEXT: v_writelane_b32 v62, s5, 17
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: v_mov_b32_e32 v52, v17
+; SI-NEXT: v_writelane_b32 v62, s4, 18
+; SI-NEXT: v_writelane_b32 v62, s5, 19
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v43, v20
+; SI-NEXT: v_writelane_b32 v62, s4, 20
+; SI-NEXT: v_writelane_b32 v62, s5, 21
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v42, v32
+; SI-NEXT: v_writelane_b32 v62, s4, 22
+; SI-NEXT: v_writelane_b32 v62, s5, 23
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v41, v5
+; SI-NEXT: v_writelane_b32 v62, s4, 24
+; SI-NEXT: v_writelane_b32 v62, s5, 25
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_mov_b64 vcc, -1
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; kill: killed $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: v_writelane_b32 v62, s4, 26
+; SI-NEXT: v_writelane_b32 v62, s5, 27
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v60, v35
+; SI-NEXT: v_writelane_b32 v62, s4, 28
+; SI-NEXT: v_writelane_b32 v62, s5, 29
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: v_writelane_b32 v62, s5, 1
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: v_mov_b32_e32 v35, v6
+; SI-NEXT: v_writelane_b32 v62, s4, 30
+; SI-NEXT: v_writelane_b32 v62, s5, 31
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v32, v4
+; SI-NEXT: v_writelane_b32 v62, s4, 32
+; SI-NEXT: v_writelane_b32 v62, s5, 33
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v30, v12
+; SI-NEXT: v_writelane_b32 v62, s4, 34
+; SI-NEXT: v_writelane_b32 v62, s5, 35
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v19, v39
+; SI-NEXT: v_writelane_b32 v62, s4, 36
+; SI-NEXT: v_writelane_b32 v62, s5, 37
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $sgpr10
-; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: v_mov_b32_e32 v39, v25
+; SI-NEXT: v_writelane_b32 v62, s4, 38
+; SI-NEXT: v_writelane_b32 v62, s5, 39
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v12, v29
+; SI-NEXT: v_writelane_b32 v62, s4, 40
+; SI-NEXT: v_writelane_b32 v62, s5, 41
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v20, v2
+; SI-NEXT: v_writelane_b32 v62, s4, 42
+; SI-NEXT: v_writelane_b32 v62, s5, 43
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v6, v55
+; SI-NEXT: v_writelane_b32 v62, s4, 44
+; SI-NEXT: v_writelane_b32 v62, s5, 45
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v17, v8
+; SI-NEXT: v_writelane_b32 v62, s4, 46
+; SI-NEXT: v_writelane_b32 v62, s5, 47
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_mov_b32_e32 v29, v33
+; SI-NEXT: v_writelane_b32 v62, s4, 48
+; SI-NEXT: v_writelane_b32 v62, s5, 49
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr8
+; SI-NEXT: ; implicit-def: $sgpr96
+; SI-NEXT: ; implicit-def: $sgpr78
+; SI-NEXT: ; implicit-def: $sgpr7
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $sgpr86
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $sgpr80
+; SI-NEXT: ; implicit-def: $sgpr70
+; SI-NEXT: ; implicit-def: $sgpr72
+; SI-NEXT: ; implicit-def: $sgpr69
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr38
+; SI-NEXT: ; implicit-def: $sgpr75
+; SI-NEXT: ; implicit-def: $sgpr91
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $sgpr52
+; SI-NEXT: ; implicit-def: $sgpr98
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr37
; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $sgpr30
+; SI-NEXT: ; implicit-def: $sgpr82
+; SI-NEXT: ; implicit-def: $sgpr43
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $sgpr16
-; SI-NEXT: ; implicit-def: $sgpr12
-; SI-NEXT: ; implicit-def: $sgpr8
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $sgpr22
-; SI-NEXT: ; implicit-def: $sgpr18
-; SI-NEXT: ; implicit-def: $sgpr14
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $sgpr27
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $sgpr28
-; SI-NEXT: ; implicit-def: $sgpr24
-; SI-NEXT: ; implicit-def: $sgpr20
-; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $sgpr74
; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $sgpr22
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $sgpr18
; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $sgpr44
-; SI-NEXT: ; implicit-def: $sgpr40
-; SI-NEXT: ; implicit-def: $sgpr26
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $sgpr58
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr42
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $sgpr72
-; SI-NEXT: ; implicit-def: $sgpr60
-; SI-NEXT: ; implicit-def: $sgpr56
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $sgpr78
-; SI-NEXT: ; implicit-def: $sgpr74
-; SI-NEXT: ; implicit-def: $sgpr62
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $sgpr15
+; SI-NEXT: ; implicit-def: $sgpr12
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: ; implicit-def: $sgpr50
+; SI-NEXT: ; implicit-def: $sgpr94
+; SI-NEXT: ; implicit-def: $sgpr57
; SI-NEXT: ; implicit-def: $sgpr92
-; SI-NEXT: ; implicit-def: $sgpr88
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr79
; SI-NEXT: ; implicit-def: $sgpr76
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $sgpr34
-; SI-NEXT: ; implicit-def: $sgpr94
; SI-NEXT: ; implicit-def: $sgpr90
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $sgpr38
-; SI-NEXT: ; implicit-def: $sgpr36
-; SI-NEXT: ; implicit-def: $sgpr30
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $sgpr52
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; implicit-def: $sgpr48
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $sgpr68
-; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr73
+; SI-NEXT: ; implicit-def: $sgpr62
; SI-NEXT: ; implicit-def: $sgpr54
-; SI-NEXT: ; implicit-def: $sgpr82
-; SI-NEXT: ; implicit-def: $sgpr70
-; SI-NEXT: ; implicit-def: $sgpr66
-; SI-NEXT: ; implicit-def: $sgpr96
-; SI-NEXT: ; implicit-def: $sgpr84
-; SI-NEXT: ; implicit-def: $sgpr80
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: ; implicit-def: $sgpr98
-; SI-NEXT: ; implicit-def: $sgpr86
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; kill: killed $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: ; implicit-def: $sgpr68
+; SI-NEXT: ; implicit-def: $sgpr45
+; SI-NEXT: ; implicit-def: $sgpr40
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr29
+; SI-NEXT: ; implicit-def: $sgpr24
+; SI-NEXT: ; implicit-def: $sgpr34
+; SI-NEXT: ; implicit-def: $sgpr23
+; SI-NEXT: ; implicit-def: $sgpr16
+; SI-NEXT: ; implicit-def: $sgpr36
+; SI-NEXT: ; implicit-def: $sgpr19
+; SI-NEXT: ; implicit-def: $sgpr10
+; SI-NEXT: ; implicit-def: $sgpr14
+; SI-NEXT: ; implicit-def: $sgpr13
+; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: v_writelane_b32 v62, s4, 50
+; SI-NEXT: v_writelane_b32 v62, s5, 51
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v62, s4, 52
+; SI-NEXT: v_writelane_b32 v62, s5, 53
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v62, s4, 54
+; SI-NEXT: v_writelane_b32 v62, s5, 55
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v62, s4, 56
+; SI-NEXT: v_writelane_b32 v62, s5, 57
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v62, s4, 58
+; SI-NEXT: v_writelane_b32 v62, s5, 59
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v62, s4, 60
+; SI-NEXT: v_writelane_b32 v62, s5, 61
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v62, s4, 62
+; SI-NEXT: v_writelane_b32 v62, s5, 63
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v61, s4, 0
+; SI-NEXT: v_writelane_b32 v61, s5, 1
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v61, s4, 2
+; SI-NEXT: v_writelane_b32 v61, s5, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v61, s4, 4
+; SI-NEXT: v_writelane_b32 v61, s5, 5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v61, s4, 6
+; SI-NEXT: v_writelane_b32 v61, s5, 7
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v61, s4, 8
+; SI-NEXT: v_writelane_b32 v61, s5, 9
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v61, s4, 10
+; SI-NEXT: v_writelane_b32 v61, s5, 11
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v61, s4, 12
+; SI-NEXT: v_writelane_b32 v61, s5, 13
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v61, s4, 14
+; SI-NEXT: v_writelane_b32 v61, s5, 15
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v61, s4, 16
+; SI-NEXT: v_writelane_b32 v61, s5, 17
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v61, s4, 18
+; SI-NEXT: v_writelane_b32 v61, s5, 19
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v61, s4, 20
+; SI-NEXT: v_writelane_b32 v61, s5, 21
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v61, s4, 22
+; SI-NEXT: v_writelane_b32 v61, s5, 23
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v61, s4, 24
+; SI-NEXT: v_writelane_b32 v61, s5, 25
+; SI-NEXT: ; implicit-def: $sgpr5
+; SI-NEXT: v_writelane_b32 v61, s4, 26
+; SI-NEXT: v_writelane_b32 v61, s5, 27
+; SI-NEXT: v_writelane_b32 v61, s20, 28
+; SI-NEXT: v_writelane_b32 v61, s21, 29
+; SI-NEXT: ; implicit-def: $sgpr20
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v61, s20, 30
+; SI-NEXT: v_writelane_b32 v61, s21, 31
+; SI-NEXT: v_writelane_b32 v61, s88, 32
+; SI-NEXT: v_writelane_b32 v61, s89, 33
+; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: .LBB91_3: ; %Flow
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; SI-NEXT: s_andn2_b64 vcc, exec, vcc
; SI-NEXT: s_cbranch_vccnz .LBB91_5
; SI-NEXT: ; %bb.4: ; %cmp.true
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v43
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v46
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_alignbit_b32 v7, v3, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s4, v7
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v37
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_alignbit_b32 v10, v6, v4, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v33
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s52, v10
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v51
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_readfirstlane_b32 s4, v11
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v3
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_readfirstlane_b32 s12, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v24
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v53
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v9, v3, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s86, v9
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v50
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v38
+; SI-NEXT: v_readfirstlane_b32 s6, v9
+; SI-NEXT: v_readfirstlane_b32 s8, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v40
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: s_lshr_b32 s9, s6, 16
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v12, v3, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s80, v12
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_readfirstlane_b32 s6, v8
+; SI-NEXT: s_lshr_b64 s[10:11], s[8:9], 16
+; SI-NEXT: s_lshr_b32 s9, s6, 16
+; SI-NEXT: v_readfirstlane_b32 s8, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v54
+; SI-NEXT: s_mov_b32 s7, s9
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v58
+; SI-NEXT: v_writelane_b32 v61, s6, 26
+; SI-NEXT: s_lshr_b64 s[20:21], s[8:9], 16
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_readfirstlane_b32 s8, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v49
+; SI-NEXT: v_writelane_b32 v61, s7, 27
+; SI-NEXT: v_readfirstlane_b32 s6, v5
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v50
+; SI-NEXT: s_lshr_b32 s9, s6, 16
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v13, v3, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s66, v13
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v38, v4, v3, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v55
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v15
+; SI-NEXT: v_readfirstlane_b32 s18, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v37
+; SI-NEXT: s_lshr_b64 s[16:17], s[8:9], 16
+; SI-NEXT: v_readfirstlane_b32 s6, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: s_lshr_b32 s19, s6, 16
+; SI-NEXT: v_readfirstlane_b32 s6, v3
+; SI-NEXT: s_lshr_b32 s9, s6, 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v12
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v21
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v43
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v44
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v35
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: s_lshr_b64 s[26:27], s[18:19], 16
+; SI-NEXT: s_mov_b32 s17, s26
+; SI-NEXT: s_mov_b32 s11, s20
+; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v51
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_readfirstlane_b32 s8, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v36
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v1
+; SI-NEXT: v_readfirstlane_b32 s22, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v57
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_alignbit_b32 v15, v7, v6, 16
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v42
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v46, v6, v3, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v48
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v39
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: s_lshr_b64 s[24:25], s[8:9], 16
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_readfirstlane_b32 s8, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v7
+; SI-NEXT: v_readfirstlane_b32 s6, v1
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_alignbit_b32 v23, v7, v6, 16
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v53
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v57, v6, v3, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v54
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v28
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: s_lshr_b32 s23, s6, 16
+; SI-NEXT: v_readfirstlane_b32 s6, v5
+; SI-NEXT: v_readfirstlane_b32 s28, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v27
+; SI-NEXT: s_lshr_b32 s9, s6, 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v29
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_alignbit_b32 v16, v7, v6, 16
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v30, v6, v3, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v21
+; SI-NEXT: s_lshr_b64 s[40:41], s[8:9], 16
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v28
+; SI-NEXT: v_readfirstlane_b32 s8, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v22
+; SI-NEXT: v_readfirstlane_b32 s6, v5
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v40
-; SI-NEXT: v_alignbit_b32 v18, v9, v7, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v34
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; SI-NEXT: v_alignbit_b32 v20, v10, v9, 16
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s38, v15
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s90, v16
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s30, v23
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s76, v18
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s62, v20
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v5
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v4
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s5, v38
-; SI-NEXT: v_readfirstlane_b32 s87, v46
-; SI-NEXT: v_readfirstlane_b32 s81, v57
-; SI-NEXT: v_readfirstlane_b32 s67, v30
-; SI-NEXT: s_lshr_b64 s[54:55], s[66:67], 24
-; SI-NEXT: s_lshr_b64 s[64:65], s[66:67], 16
-; SI-NEXT: s_lshr_b64 s[68:69], s[66:67], 8
-; SI-NEXT: s_lshr_b64 s[66:67], s[80:81], 24
-; SI-NEXT: s_lshr_b64 s[70:71], s[80:81], 16
-; SI-NEXT: s_lshr_b64 s[82:83], s[80:81], 8
-; SI-NEXT: s_lshr_b64 s[80:81], s[86:87], 24
-; SI-NEXT: s_lshr_b64 s[84:85], s[86:87], 16
-; SI-NEXT: s_lshr_b64 s[96:97], s[86:87], 8
-; SI-NEXT: s_lshr_b64 s[86:87], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[98:99], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 8
-; SI-NEXT: v_lshrrev_b32_e32 v35, 24, v2
-; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v30
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v17, v7, v3, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; SI-NEXT: v_readfirstlane_b32 s53, v17
-; SI-NEXT: s_lshr_b64 s[48:49], s[52:53], 24
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_alignbit_b32 v21, v12, v10, 16
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_readfirstlane_b32 s56, v21
-; SI-NEXT: s_lshr_b64 s[50:51], s[52:53], 16
-; SI-NEXT: s_lshr_b64 s[52:53], s[52:53], 8
-; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v6
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: s_lshr_b32 s29, s6, 16
+; SI-NEXT: v_readfirstlane_b32 s6, v7
+; SI-NEXT: v_readfirstlane_b32 s44, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v34
+; SI-NEXT: s_lshr_b32 s9, s6, 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v26
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 16
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_readfirstlane_b32 s8, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v39
+; SI-NEXT: v_readfirstlane_b32 s6, v7
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v7
-; SI-NEXT: v_alignbit_b32 v22, v9, v3, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; SI-NEXT: v_alignbit_b32 v23, v13, v12, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v31
+; SI-NEXT: s_lshr_b32 s45, s6, 16
+; SI-NEXT: v_readfirstlane_b32 s6, v9
+; SI-NEXT: v_readfirstlane_b32 s58, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v30
+; SI-NEXT: s_lshr_b32 s9, s6, 16
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: s_lshr_b64 s[62:63], s[8:9], 16
+; SI-NEXT: v_readfirstlane_b32 s8, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v23
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v9
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s42, v23
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v22
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v17
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v57
-; SI-NEXT: v_readfirstlane_b32 s39, v22
+; SI-NEXT: v_readfirstlane_b32 s6, v9
+; SI-NEXT: s_lshr_b32 s59, s6, 16
+; SI-NEXT: v_readfirstlane_b32 s6, v10
+; SI-NEXT: s_lshr_b32 s9, s6, 16
+; SI-NEXT: s_lshr_b64 s[76:77], s[8:9], 16
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v17
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v11
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v42
+; SI-NEXT: v_readfirstlane_b32 s6, v10
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: s_lshr_b32 s73, s6, 16
+; SI-NEXT: v_readfirstlane_b32 s6, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v11
+; SI-NEXT: s_lshr_b32 s9, s6, 16
+; SI-NEXT: v_readfirstlane_b32 s6, v18
+; SI-NEXT: s_lshr_b32 s79, s6, 16
+; SI-NEXT: s_lshr_b64 s[54:55], s[58:59], 16
+; SI-NEXT: s_mov_b32 s63, s54
+; SI-NEXT: s_lshr_b64 s[60:61], s[44:45], 16
+; SI-NEXT: s_mov_b32 s47, s60
+; SI-NEXT: s_lshr_b64 s[42:43], s[28:29], 16
+; SI-NEXT: s_mov_b32 s41, s42
+; SI-NEXT: s_lshr_b64 s[34:35], s[22:23], 16
+; SI-NEXT: s_mov_b32 s25, s34
+; SI-NEXT: v_readfirstlane_b32 s5, v14
+; SI-NEXT: s_lshr_b32 s13, s5, 16
+; SI-NEXT: s_lshr_b64 vcc, s[12:13], 16
+; SI-NEXT: s_mov_b32 s5, vcc_lo
+; SI-NEXT: v_lshrrev_b32_e32 v56, 24, v1
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v2
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v8
+; SI-NEXT: s_lshr_b32 s22, s60, 8
+; SI-NEXT: s_lshr_b32 s21, s42, 8
+; SI-NEXT: s_lshr_b32 s18, s34, 8
+; SI-NEXT: s_lshr_b32 s12, s20, 8
+; SI-NEXT: v_lshrrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_lshrrev_b32_e32 v55, 24, v10
; SI-NEXT: v_lshrrev_b32_e32 v9, 24, v9
-; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v46
-; SI-NEXT: s_lshr_b64 s[36:37], s[38:39], 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v38
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v21
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_alignbit_b32 v24, v15, v13, 16
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v14
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_alignbit_b32 v25, v10, v3, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; SI-NEXT: v_readfirstlane_b32 s31, v25
-; SI-NEXT: v_readfirstlane_b32 s26, v24
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: s_lshr_b64 s[94:95], s[30:31], 16
-; SI-NEXT: s_lshr_b64 s[34:35], s[30:31], 8
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v23
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_alignbit_b32 v26, v16, v15, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_readfirstlane_b32 s72, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v32
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_readfirstlane_b32 s20, v26
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v21
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v27, v18, v16, 16
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v10
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v60, v12, v3, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
-; SI-NEXT: v_readfirstlane_b32 s91, v60
-; SI-NEXT: v_readfirstlane_b32 s14, v27
-; SI-NEXT: v_lshrrev_b32_e32 v10, 24, v10
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: s_lshr_b64 s[88:89], s[90:91], 16
-; SI-NEXT: s_lshr_b64 s[92:93], s[90:91], 8
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_alignbit_b32 v29, v20, v18, 16
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: v_readfirstlane_b32 s8, v29
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_readfirstlane_b32 s8, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: s_lshr_b64 s[92:93], s[8:9], 16
+; SI-NEXT: s_lshr_b64 s[74:75], s[72:73], 16
+; SI-NEXT: s_mov_b32 s77, s74
+; SI-NEXT: s_lshr_b32 s28, s74, 8
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v12
-; SI-NEXT: v_alignbit_b32 v61, v11, v3, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: v_readfirstlane_b32 s77, v61
-; SI-NEXT: v_lshrrev_b32_e32 v12, 24, v12
-; SI-NEXT: s_lshr_b64 s[74:75], s[76:77], 16
-; SI-NEXT: s_lshr_b64 s[78:79], s[76:77], 8
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_lshrrev_b32_e32 v10, 8, v61
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v13, 24, v13
-; SI-NEXT: v_lshrrev_b32_e32 v56, 24, v18
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_readfirstlane_b32 s78, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: s_lshr_b64 s[48:49], s[78:79], 16
+; SI-NEXT: s_mov_b32 s93, s48
+; SI-NEXT: s_lshr_b32 s27, s48, 8
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_alignbit_b32 v59, v36, v3, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v8
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: v_readfirstlane_b32 s63, v59
-; SI-NEXT: s_lshr_b64 s[60:61], s[62:63], 16
-; SI-NEXT: s_lshr_b64 s[72:73], s[62:63], 8
-; SI-NEXT: v_lshrrev_b32_e32 v4, 8, v59
-; SI-NEXT: v_lshrrev_b32_e32 v18, 8, v25
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v24, 24, v20
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_readfirstlane_b32 s8, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_readfirstlane_b32 s6, v11
+; SI-NEXT: s_lshr_b32 s9, s6, 16
+; SI-NEXT: s_lshr_b64 s[50:51], s[8:9], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v3
+; SI-NEXT: v_readfirstlane_b32 s56, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v41
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_readfirstlane_b32 s8, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v3
-; SI-NEXT: v_alignbit_b32 v41, v49, v15, 16
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
-; SI-NEXT: v_readfirstlane_b32 s57, v41
+; SI-NEXT: v_readfirstlane_b32 s6, v3
+; SI-NEXT: s_lshr_b32 s57, s6, 16
+; SI-NEXT: v_readfirstlane_b32 s6, v13
+; SI-NEXT: s_lshr_b32 s9, s6, 16
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v19
+; SI-NEXT: s_lshr_b64 s[30:31], s[8:9], 16
+; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: v_readfirstlane_b32 s6, v24
+; SI-NEXT: s_lshr_b32 s89, s6, 16
+; SI-NEXT: s_lshr_b64 s[94:95], s[56:57], 16
+; SI-NEXT: s_mov_b32 s51, s94
+; SI-NEXT: s_lshr_b32 s44, s94, 8
+; SI-NEXT: s_mov_b32 s56, s42
+; SI-NEXT: v_lshrrev_b32_e32 v47, 24, v24
; SI-NEXT: v_lshrrev_b32_e32 v3, 24, v3
-; SI-NEXT: s_lshr_b64 s[46:47], s[56:57], 16
-; SI-NEXT: s_lshr_b64 s[58:59], s[56:57], 8
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v41
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; SI-NEXT: v_alignbit_b32 v58, v32, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
-; SI-NEXT: v_readfirstlane_b32 s43, v58
-; SI-NEXT: s_lshr_b64 s[40:41], s[42:43], 16
-; SI-NEXT: s_lshr_b64 s[44:45], s[42:43], 8
-; SI-NEXT: v_lshrrev_b32_e32 v20, 24, v15
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_lshrrev_b32_e32 v13, 8, v58
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_readfirstlane_b32 s88, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v31
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_readfirstlane_b32 s8, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: s_lshr_b64 s[82:83], s[88:89], 16
+; SI-NEXT: s_mov_b32 s31, s82
+; SI-NEXT: s_lshr_b32 s43, s82, 8
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_readfirstlane_b32 s6, v13
+; SI-NEXT: s_lshr_b32 s9, s6, 16
+; SI-NEXT: s_lshr_b64 s[52:53], s[8:9], 16
+; SI-NEXT: v_readfirstlane_b32 s6, v4
+; SI-NEXT: s_lshr_b32 s37, s6, 16
+; SI-NEXT: s_mov_b32 s88, vcc_lo
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v47, v45, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; SI-NEXT: v_readfirstlane_b32 s27, v47
-; SI-NEXT: v_lshrrev_b32_e32 v9, 8, v47
-; SI-NEXT: s_lshr_b64 s[24:25], s[26:27], 16
-; SI-NEXT: s_lshr_b64 s[28:29], s[26:27], 8
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_readfirstlane_b32 s36, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_readfirstlane_b32 s8, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v59
+; SI-NEXT: s_lshr_b64 s[98:99], s[36:37], 16
+; SI-NEXT: s_mov_b32 s53, s98
+; SI-NEXT: s_lshr_b32 s58, s98, 8
+; SI-NEXT: s_mov_b32 s36, s26
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_readfirstlane_b32 s6, v13
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v11
+; SI-NEXT: v_readfirstlane_b32 s90, v13
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v60
+; SI-NEXT: s_lshr_b32 s9, s6, 16
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: s_lshr_b64 s[66:67], s[8:9], 16
+; SI-NEXT: v_readfirstlane_b32 s6, v11
+; SI-NEXT: s_lshr_b32 s91, s6, 16
+; SI-NEXT: s_lshr_b64 s[38:39], s[90:91], 16
+; SI-NEXT: s_mov_b32 s67, s38
+; SI-NEXT: s_lshr_b32 s75, s38, 8
+; SI-NEXT: s_mov_b32 s90, s74
+; SI-NEXT: s_lshr_b32 s74, s54, 8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_readfirstlane_b32 s8, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v19, v11, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
-; SI-NEXT: v_readfirstlane_b32 s21, v19
-; SI-NEXT: v_lshrrev_b32_e32 v27, 8, v19
-; SI-NEXT: s_lshr_b64 s[18:19], s[20:21], 16
-; SI-NEXT: s_lshr_b64 s[22:23], s[20:21], 8
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_readfirstlane_b32 s6, v15
+; SI-NEXT: s_lshr_b32 s9, s6, 16
+; SI-NEXT: s_lshr_b64 s[80:81], s[8:9], 16
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v13
+; SI-NEXT: v_readfirstlane_b32 s68, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v45
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_readfirstlane_b32 s6, v13
+; SI-NEXT: s_lshr_b32 s69, s6, 16
+; SI-NEXT: s_lshr_b64 s[70:71], s[68:69], 16
+; SI-NEXT: s_mov_b32 s81, s70
+; SI-NEXT: s_lshr_b32 s72, s70, 8
+; SI-NEXT: s_mov_b32 s68, s60
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_readfirstlane_b32 s8, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_readfirstlane_b32 s64, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v14, v52, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
-; SI-NEXT: v_readfirstlane_b32 s15, v14
-; SI-NEXT: v_lshrrev_b32_e32 v7, 8, v14
-; SI-NEXT: s_lshr_b64 s[12:13], s[14:15], 16
-; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 8
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_readfirstlane_b32 s6, v16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: s_lshr_b32 s9, s6, 16
+; SI-NEXT: s_lshr_b64 s[86:87], s[8:9], 16
+; SI-NEXT: v_readfirstlane_b32 s6, v12
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: s_lshr_b32 s65, s6, 16
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: s_lshr_b64 s[84:85], s[64:65], 16
+; SI-NEXT: s_mov_b32 s87, s84
+; SI-NEXT: v_lshrrev_b32_e32 v48, 24, v6
+; SI-NEXT: s_lshr_b32 s61, s84, 8
+; SI-NEXT: s_mov_b32 s64, s48
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_readfirstlane_b32 s8, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v11, v44, v16, 16
-; SI-NEXT: v_lshrrev_b32_e32 v16, 24, v23
-; SI-NEXT: v_lshrrev_b32_e32 v23, 8, v60
-; SI-NEXT: v_readfirstlane_b32 s9, v11
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v11
-; SI-NEXT: s_lshr_b64 s[6:7], s[8:9], 24
-; SI-NEXT: s_lshr_b64 s[10:11], s[8:9], 8
-; SI-NEXT: v_writelane_b32 v62, s6, 0
-; SI-NEXT: v_writelane_b32 v62, s7, 1
-; SI-NEXT: s_lshr_b64 s[6:7], s[8:9], 16
-; SI-NEXT: s_lshr_b64 s[8:9], s[14:15], 24
-; SI-NEXT: s_lshr_b64 s[14:15], s[20:21], 24
-; SI-NEXT: s_lshr_b64 s[20:21], s[26:27], 24
-; SI-NEXT: s_lshr_b64 s[26:27], s[42:43], 24
-; SI-NEXT: s_lshr_b64 s[42:43], s[56:57], 24
-; SI-NEXT: s_lshr_b64 s[56:57], s[62:63], 24
-; SI-NEXT: s_lshr_b64 s[62:63], s[76:77], 24
-; SI-NEXT: s_lshr_b64 s[76:77], s[90:91], 24
-; SI-NEXT: s_lshr_b64 s[90:91], s[30:31], 24
-; SI-NEXT: s_lshr_b64 s[30:31], s[38:39], 24
-; SI-NEXT: s_lshr_b64 s[38:39], s[38:39], 8
+; SI-NEXT: v_readfirstlane_b32 s6, v16
+; SI-NEXT: s_lshr_b32 s9, s6, 16
+; SI-NEXT: v_readfirstlane_b32 s6, v6
+; SI-NEXT: s_lshr_b32 s7, s6, 16
+; SI-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
+; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v7
+; SI-NEXT: v_lshrrev_b32_e32 v16, 24, v12
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_readfirstlane_b32 s6, v15
+; SI-NEXT: s_lshr_b64 s[96:97], s[6:7], 16
+; SI-NEXT: s_mov_b32 s9, s96
+; SI-NEXT: s_lshr_b64 s[14:15], s[8:9], 24
+; SI-NEXT: v_writelane_b32 v62, s14, 4
+; SI-NEXT: v_writelane_b32 v62, s15, 5
+; SI-NEXT: s_lshr_b64 s[14:15], s[8:9], 16
+; SI-NEXT: v_writelane_b32 v62, s14, 2
+; SI-NEXT: v_writelane_b32 v62, s15, 3
+; SI-NEXT: s_lshr_b64 s[14:15], s[8:9], 8
+; SI-NEXT: v_writelane_b32 v62, s14, 0
+; SI-NEXT: v_writelane_b32 v62, s15, 1
+; SI-NEXT: s_lshr_b64 s[14:15], s[86:87], 24
+; SI-NEXT: v_writelane_b32 v62, s14, 10
+; SI-NEXT: v_writelane_b32 v62, s15, 11
+; SI-NEXT: s_lshr_b64 s[14:15], s[86:87], 16
+; SI-NEXT: v_writelane_b32 v62, s14, 8
+; SI-NEXT: v_writelane_b32 v62, s15, 9
+; SI-NEXT: s_lshr_b64 s[14:15], s[86:87], 8
+; SI-NEXT: v_writelane_b32 v62, s14, 6
+; SI-NEXT: v_writelane_b32 v62, s15, 7
+; SI-NEXT: s_lshr_b64 s[14:15], s[80:81], 24
+; SI-NEXT: v_writelane_b32 v62, s14, 16
+; SI-NEXT: v_writelane_b32 v62, s15, 17
+; SI-NEXT: s_lshr_b64 s[14:15], s[80:81], 16
+; SI-NEXT: v_writelane_b32 v62, s14, 14
+; SI-NEXT: v_writelane_b32 v62, s15, 15
+; SI-NEXT: s_lshr_b64 s[14:15], s[80:81], 8
+; SI-NEXT: v_writelane_b32 v62, s14, 12
+; SI-NEXT: v_writelane_b32 v62, s15, 13
+; SI-NEXT: s_lshr_b64 s[14:15], s[66:67], 24
+; SI-NEXT: v_writelane_b32 v62, s14, 22
+; SI-NEXT: v_writelane_b32 v62, s15, 23
+; SI-NEXT: s_lshr_b64 s[14:15], s[66:67], 16
+; SI-NEXT: v_writelane_b32 v62, s14, 20
+; SI-NEXT: v_writelane_b32 v62, s15, 21
+; SI-NEXT: s_lshr_b64 s[14:15], s[66:67], 8
+; SI-NEXT: v_writelane_b32 v62, s14, 18
+; SI-NEXT: v_writelane_b32 v62, s15, 19
+; SI-NEXT: s_lshr_b64 s[14:15], s[52:53], 24
+; SI-NEXT: v_writelane_b32 v62, s14, 28
+; SI-NEXT: v_writelane_b32 v62, s15, 29
+; SI-NEXT: s_lshr_b64 s[14:15], s[52:53], 16
+; SI-NEXT: v_writelane_b32 v62, s14, 26
+; SI-NEXT: v_writelane_b32 v62, s15, 27
+; SI-NEXT: s_lshr_b64 s[14:15], s[52:53], 8
+; SI-NEXT: v_writelane_b32 v62, s14, 24
+; SI-NEXT: v_writelane_b32 v62, s15, 25
+; SI-NEXT: s_lshr_b64 s[14:15], s[30:31], 24
+; SI-NEXT: v_writelane_b32 v62, s14, 34
+; SI-NEXT: v_writelane_b32 v62, s15, 35
+; SI-NEXT: s_lshr_b64 s[14:15], s[30:31], 16
+; SI-NEXT: v_writelane_b32 v62, s14, 32
+; SI-NEXT: v_writelane_b32 v62, s15, 33
+; SI-NEXT: s_lshr_b64 s[14:15], s[30:31], 8
+; SI-NEXT: v_writelane_b32 v62, s14, 30
+; SI-NEXT: v_writelane_b32 v62, s15, 31
+; SI-NEXT: s_lshr_b64 s[14:15], s[50:51], 24
+; SI-NEXT: v_writelane_b32 v62, s14, 40
+; SI-NEXT: v_writelane_b32 v62, s15, 41
+; SI-NEXT: s_lshr_b64 s[14:15], s[50:51], 16
+; SI-NEXT: v_writelane_b32 v62, s14, 38
+; SI-NEXT: v_writelane_b32 v62, s15, 39
+; SI-NEXT: s_lshr_b64 s[14:15], s[50:51], 8
+; SI-NEXT: v_writelane_b32 v62, s14, 36
+; SI-NEXT: v_writelane_b32 v62, s15, 37
+; SI-NEXT: s_lshr_b64 s[14:15], s[92:93], 24
+; SI-NEXT: v_writelane_b32 v62, s14, 46
+; SI-NEXT: v_writelane_b32 v62, s15, 47
+; SI-NEXT: s_lshr_b64 s[14:15], s[92:93], 16
+; SI-NEXT: v_writelane_b32 v62, s14, 44
+; SI-NEXT: v_writelane_b32 v62, s15, 45
+; SI-NEXT: s_lshr_b64 s[14:15], s[92:93], 8
+; SI-NEXT: v_writelane_b32 v62, s14, 42
+; SI-NEXT: v_writelane_b32 v62, s15, 43
+; SI-NEXT: s_lshr_b64 s[14:15], s[76:77], 24
+; SI-NEXT: v_writelane_b32 v62, s14, 52
+; SI-NEXT: v_writelane_b32 v62, s15, 53
+; SI-NEXT: s_lshr_b64 s[14:15], s[76:77], 16
+; SI-NEXT: v_writelane_b32 v62, s14, 50
+; SI-NEXT: v_writelane_b32 v62, s15, 51
+; SI-NEXT: s_lshr_b64 s[14:15], s[76:77], 8
+; SI-NEXT: v_writelane_b32 v62, s14, 48
+; SI-NEXT: v_writelane_b32 v62, s15, 49
+; SI-NEXT: s_lshr_b64 s[14:15], s[62:63], 24
+; SI-NEXT: v_writelane_b32 v62, s14, 58
+; SI-NEXT: v_writelane_b32 v62, s15, 59
+; SI-NEXT: s_lshr_b64 s[14:15], s[62:63], 16
+; SI-NEXT: v_writelane_b32 v62, s14, 56
+; SI-NEXT: v_writelane_b32 v62, s15, 57
+; SI-NEXT: s_lshr_b64 s[14:15], s[62:63], 8
+; SI-NEXT: v_writelane_b32 v62, s14, 54
+; SI-NEXT: v_writelane_b32 v62, s15, 55
+; SI-NEXT: s_lshr_b64 s[14:15], s[46:47], 24
+; SI-NEXT: v_writelane_b32 v61, s14, 0
+; SI-NEXT: v_writelane_b32 v61, s15, 1
+; SI-NEXT: s_lshr_b64 s[14:15], s[46:47], 16
+; SI-NEXT: v_writelane_b32 v62, s14, 62
+; SI-NEXT: v_writelane_b32 v62, s15, 63
+; SI-NEXT: s_lshr_b64 s[14:15], s[46:47], 8
+; SI-NEXT: v_writelane_b32 v62, s14, 60
+; SI-NEXT: v_writelane_b32 v62, s15, 61
+; SI-NEXT: s_lshr_b64 s[14:15], s[40:41], 24
+; SI-NEXT: v_writelane_b32 v61, s14, 6
+; SI-NEXT: v_writelane_b32 v61, s15, 7
+; SI-NEXT: s_lshr_b64 s[14:15], s[40:41], 16
+; SI-NEXT: v_writelane_b32 v61, s14, 4
+; SI-NEXT: v_writelane_b32 v61, s15, 5
+; SI-NEXT: s_lshr_b64 s[14:15], s[40:41], 8
+; SI-NEXT: v_writelane_b32 v61, s14, 2
+; SI-NEXT: v_writelane_b32 v61, s15, 3
+; SI-NEXT: s_lshr_b64 s[14:15], s[24:25], 24
+; SI-NEXT: v_writelane_b32 v61, s14, 12
+; SI-NEXT: v_writelane_b32 v61, s15, 13
+; SI-NEXT: s_lshr_b64 s[14:15], s[24:25], 16
+; SI-NEXT: v_writelane_b32 v61, s14, 10
+; SI-NEXT: v_writelane_b32 v61, s15, 11
+; SI-NEXT: s_lshr_b64 s[14:15], s[24:25], 8
+; SI-NEXT: v_writelane_b32 v61, s14, 8
+; SI-NEXT: v_writelane_b32 v61, s15, 9
+; SI-NEXT: s_lshr_b64 s[14:15], s[16:17], 24
+; SI-NEXT: v_writelane_b32 v61, s14, 18
+; SI-NEXT: v_writelane_b32 v61, s15, 19
+; SI-NEXT: s_lshr_b64 s[14:15], s[16:17], 16
+; SI-NEXT: v_writelane_b32 v61, s14, 16
+; SI-NEXT: v_writelane_b32 v61, s15, 17
+; SI-NEXT: s_lshr_b64 s[14:15], s[16:17], 8
+; SI-NEXT: v_writelane_b32 v61, s14, 14
+; SI-NEXT: v_writelane_b32 v61, s15, 15
+; SI-NEXT: s_lshr_b64 s[14:15], s[10:11], 24
+; SI-NEXT: v_writelane_b32 v61, s14, 24
+; SI-NEXT: v_writelane_b32 v61, s15, 25
+; SI-NEXT: s_lshr_b64 s[14:15], s[10:11], 16
+; SI-NEXT: v_writelane_b32 v61, s14, 22
+; SI-NEXT: v_writelane_b32 v61, s15, 23
+; SI-NEXT: s_lshr_b64 s[14:15], s[10:11], 8
+; SI-NEXT: v_writelane_b32 v61, s14, 20
+; SI-NEXT: v_writelane_b32 v61, s15, 21
+; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 24
+; SI-NEXT: v_writelane_b32 v61, s14, 32
+; SI-NEXT: v_writelane_b32 v61, s15, 33
+; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 16
+; SI-NEXT: v_writelane_b32 v61, s14, 30
+; SI-NEXT: v_writelane_b32 v61, s15, 31
+; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 8
+; SI-NEXT: v_writelane_b32 v61, s14, 28
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v13
+; SI-NEXT: v_lshrrev_b32_e32 v13, 24, v11
+; SI-NEXT: v_lshrrev_b32_e32 v11, 24, v4
+; SI-NEXT: v_lshrrev_b32_e32 v4, 24, v5
+; SI-NEXT: v_writelane_b32 v61, s15, 29
+; SI-NEXT: s_lshr_b32 s78, s96, 8
+; SI-NEXT: s_lshr_b32 s15, s26, 8
+; SI-NEXT: s_mov_b32 s14, s20
+; SI-NEXT: s_lshr_b32 s6, vcc_lo, 8
+; SI-NEXT: v_mov_b32_e32 v14, v4
+; SI-NEXT: v_mov_b32_e32 v4, v6
; SI-NEXT: .LBB91_5: ; %end
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v29
-; SI-NEXT: s_lshl_b32 s5, s10, 8
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s6, 0xff
-; SI-NEXT: v_readlane_b32 s6, v62, 0
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_lshl_b32 s6, s6, 24
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
+; SI-NEXT: s_and_b32 s5, s8, 0xff
+; SI-NEXT: v_readlane_b32 s8, v62, 0
+; SI-NEXT: v_readlane_b32 s9, v62, 1
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v62, 2
+; SI-NEXT: v_readlane_b32 s9, v62, 3
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 vcc_lo, v62, 4
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, vcc_lo, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s5
+; SI-NEXT: s_and_b32 s5, s96, 0xff
+; SI-NEXT: s_lshl_b32 s8, s78, 8
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_and_b32 s8, s7, 0xff
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v11
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v44
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v16
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, 4, v0
-; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: s_lshl_b32 s5, s16, 8
-; SI-NEXT: s_lshl_b32 s6, s8, 24
-; SI-NEXT: v_add_i32_e32 v5, vcc, 8, v0
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v26
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: s_lshl_b32 s4, s4, 8
-; SI-NEXT: v_readlane_b32 s7, v62, 1
-; SI-NEXT: v_readlane_b32 s99, v63, 35
-; SI-NEXT: v_readlane_b32 s97, v63, 33
-; SI-NEXT: v_readlane_b32 s87, v63, 31
-; SI-NEXT: v_readlane_b32 s85, v63, 29
-; SI-NEXT: v_readlane_b32 s83, v63, 27
-; SI-NEXT: v_readlane_b32 s81, v63, 25
-; SI-NEXT: v_readlane_b32 s71, v63, 23
-; SI-NEXT: v_readlane_b32 s69, v63, 21
-; SI-NEXT: v_readlane_b32 s67, v63, 19
-; SI-NEXT: v_readlane_b32 s65, v63, 17
-; SI-NEXT: v_readlane_b32 s55, v63, 15
-; SI-NEXT: v_readlane_b32 s53, v63, 13
-; SI-NEXT: v_readlane_b32 s51, v63, 11
-; SI-NEXT: v_readlane_b32 s49, v63, 9
-; SI-NEXT: v_readlane_b32 s39, v63, 7
-; SI-NEXT: v_readlane_b32 s37, v63, 5
-; SI-NEXT: v_readlane_b32 s35, v63, 3
-; SI-NEXT: v_readlane_b32 s31, v63, 1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v48
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v62, 6
+; SI-NEXT: v_readlane_b32 vcc_hi, v62, 5
; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s12, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: s_and_b32 s5, s86, 0xff
+; SI-NEXT: v_readlane_b32 s9, v62, 7
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v62, 8
+; SI-NEXT: v_readlane_b32 s9, v62, 9
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 vcc_lo, v62, 10
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, vcc_lo, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_readlane_b32 vcc_hi, v62, 11
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: s_and_b32 s5, s84, 0xff
+; SI-NEXT: s_lshl_b32 s8, s61, 8
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_and_b32 s8, s65, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v16
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v62, 12
; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
+; SI-NEXT: s_and_b32 s5, s80, 0xff
+; SI-NEXT: v_readlane_b32 s9, v62, 13
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v62, 14
+; SI-NEXT: v_readlane_b32 s9, v62, 15
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 s60, v62, 16
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, s60, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v7
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v52
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, 12, v0
-; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: s_and_b32 s5, s70, 0xff
+; SI-NEXT: s_lshl_b32 s8, s72, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: s_lshl_b32 s5, s22, 8
-; SI-NEXT: s_lshl_b32 s6, s14, 24
-; SI-NEXT: v_add_i32_e32 v5, vcc, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v24
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s18, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_and_b32 s8, s69, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v15
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v62, 18
; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
+; SI-NEXT: s_and_b32 s5, s66, 0xff
+; SI-NEXT: v_readlane_b32 s9, v62, 19
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: v_readlane_b32 s61, v62, 17
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v62, 20
+; SI-NEXT: v_readlane_b32 s9, v62, 21
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 s60, v62, 22
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, s60, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v27
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_lshl_b32 s5, s28, 8
-; SI-NEXT: s_lshl_b32 s6, s20, 24
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, 20, v0
-; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: s_and_b32 s5, s38, 0xff
+; SI-NEXT: s_lshl_b32 s8, s75, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, 24, v0
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v56
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s24, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_and_b32 s8, s91, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v13
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v62, 24
; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
+; SI-NEXT: s_and_b32 s5, s52, 0xff
+; SI-NEXT: v_readlane_b32 s9, v62, 25
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: v_readlane_b32 s61, v62, 23
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v62, 26
+; SI-NEXT: v_readlane_b32 s9, v62, 27
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 s60, v62, 28
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, s60, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v47
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v9
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v45
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, 28, v0
-; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: s_and_b32 s5, s98, 0xff
+; SI-NEXT: s_lshl_b32 s8, s58, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: s_lshl_b32 s5, s44, 8
-; SI-NEXT: s_lshl_b32 s6, s26, 24
-; SI-NEXT: v_add_i32_e32 v5, vcc, 32, v0
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s40, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_and_b32 s8, s37, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v11
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v62, 30
; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
+; SI-NEXT: s_and_b32 s5, s30, 0xff
+; SI-NEXT: v_readlane_b32 s9, v62, 31
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: v_readlane_b32 s61, v62, 29
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v62, 32
+; SI-NEXT: v_readlane_b32 s9, v62, 33
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 s60, v62, 34
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, s60, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v58
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v13
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v32
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, 36, v0
-; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: s_and_b32 s5, s82, 0xff
+; SI-NEXT: s_lshl_b32 s8, s43, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: s_lshl_b32 s5, s58, 8
-; SI-NEXT: s_lshl_b32 s6, s42, 24
-; SI-NEXT: v_add_i32_e32 v5, vcc, 40, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s46, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_and_b32 s8, s89, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v47
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v62, 36
; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: s_and_b32 s5, s50, 0xff
+; SI-NEXT: v_readlane_b32 s9, v62, 37
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v62, 38
+; SI-NEXT: v_readlane_b32 s9, v62, 39
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 s42, v62, 40
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, s42, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v41
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v12
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v49
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_lshl_b32 s5, s72, 8
-; SI-NEXT: s_lshl_b32 s6, s56, 24
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: v_or_b32_e32 v3, v3, v5
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 44, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: s_and_b32 s5, s94, 0xff
+; SI-NEXT: s_lshl_b32 s8, s44, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, 48, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s60, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_and_b32 s8, s57, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v62, 42
; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: s_and_b32 s5, s92, 0xff
+; SI-NEXT: v_readlane_b32 s9, v62, 43
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: v_readlane_b32 s43, v62, 41
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v62, 44
+; SI-NEXT: v_readlane_b32 s9, v62, 45
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 s42, v62, 46
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, s42, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v59
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v36
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_lshl_b32 s5, s78, 8
-; SI-NEXT: s_lshl_b32 s6, s62, 24
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 52, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: s_and_b32 s5, s64, 0xff
+; SI-NEXT: s_lshl_b32 s8, s27, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, 56, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s74, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_and_b32 s8, s79, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v18
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v62, 48
; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: s_and_b32 s5, s76, 0xff
+; SI-NEXT: v_readlane_b32 s9, v62, 49
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v62, 50
+; SI-NEXT: v_readlane_b32 s9, v62, 51
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 s26, v62, 52
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, s26, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v61
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v10
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_lshl_b32 s5, s92, 8
-; SI-NEXT: s_lshl_b32 s6, s76, 24
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 60, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: s_and_b32 s5, s90, 0xff
+; SI-NEXT: s_lshl_b32 s8, s28, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, 64, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s88, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: v_add_i32_e32 v1, vcc, 64, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_and_b32 s8, s73, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v55
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v62, 54
; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: s_and_b32 s5, s62, 0xff
+; SI-NEXT: v_readlane_b32 s9, v62, 55
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: v_readlane_b32 s27, v62, 53
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v62, 56
+; SI-NEXT: v_readlane_b32 s9, v62, 57
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 s26, v62, 58
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, s26, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v60
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v23
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_lshl_b32 s5, s34, 8
-; SI-NEXT: s_lshl_b32 s6, s90, 24
-; SI-NEXT: v_readlane_b32 s34, v63, 2
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x44, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: s_and_b32 s5, s54, 0xff
+; SI-NEXT: s_lshl_b32 s8, s74, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x48, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s94, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x48, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_and_b32 s8, s59, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v9
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v62, 60
; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: s_and_b32 s5, s46, 0xff
+; SI-NEXT: v_readlane_b32 s9, v62, 61
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: v_readlane_b32 s27, v62, 59
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v62, 62
+; SI-NEXT: v_readlane_b32 s9, v62, 63
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 s26, v61, 0
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, s26, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v25
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v18
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_lshl_b32 s5, s38, 8
-; SI-NEXT: s_lshl_b32 s6, s30, 24
-; SI-NEXT: v_readlane_b32 s38, v63, 6
-; SI-NEXT: v_readlane_b32 s30, v63, 0
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x4c, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: s_and_b32 s5, s68, 0xff
+; SI-NEXT: s_lshl_b32 s8, s22, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x50, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s36, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x50, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_and_b32 s8, s45, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v4
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v61, 2
; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: s_and_b32 s5, s40, 0xff
+; SI-NEXT: v_readlane_b32 s9, v61, 3
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: v_readlane_b32 s27, v61, 1
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v61, 4
+; SI-NEXT: v_readlane_b32 s9, v61, 5
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 s26, v61, 6
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, s26, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v22
-; SI-NEXT: s_lshl_b32 s5, s52, 8
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: s_lshl_b32 s6, s48, 24
-; SI-NEXT: v_readlane_b32 s52, v63, 12
-; SI-NEXT: v_readlane_b32 s48, v63, 8
-; SI-NEXT: v_readlane_b32 s36, v63, 4
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x54, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: s_and_b32 s5, s56, 0xff
+; SI-NEXT: s_lshl_b32 s8, s21, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x58, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s50, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x58, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_and_b32 s8, s29, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v14
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v61, 8
; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: s_and_b32 s5, s24, 0xff
+; SI-NEXT: v_readlane_b32 s9, v61, 9
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v61, 10
+; SI-NEXT: v_readlane_b32 s9, v61, 11
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 s20, v61, 12
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, s20, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v17
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: s_lshl_b32 s5, s68, 8
-; SI-NEXT: s_lshl_b32 s6, s54, 24
-; SI-NEXT: v_readlane_b32 s68, v63, 20
-; SI-NEXT: v_readlane_b32 s54, v63, 14
-; SI-NEXT: v_readlane_b32 s50, v63, 10
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x5c, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: s_and_b32 s5, s34, 0xff
+; SI-NEXT: s_lshl_b32 s8, s18, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x60, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s64, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x60, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_and_b32 s8, s23, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v56
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v61, 14
; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: s_and_b32 s5, s16, 0xff
+; SI-NEXT: v_readlane_b32 s9, v61, 15
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v61, 16
+; SI-NEXT: v_readlane_b32 s9, v61, 17
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 s16, v61, 18
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, s16, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v30
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_lshl_b32 s5, s82, 8
-; SI-NEXT: s_lshl_b32 s6, s66, 24
-; SI-NEXT: v_readlane_b32 s82, v63, 26
-; SI-NEXT: v_readlane_b32 s66, v63, 18
-; SI-NEXT: v_readlane_b32 s64, v63, 16
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0
+; SI-NEXT: s_or_b32 s5, s5, s8
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s70, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x68, v0
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: s_and_b32 s5, s36, 0xff
+; SI-NEXT: s_lshl_b32 s8, s15, 8
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: s_and_b32 s8, s19, 0xff
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v57
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: s_lshl_b32 s5, s96, 8
-; SI-NEXT: s_lshl_b32 s6, s80, 24
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0
+; SI-NEXT: s_and_b32 s4, s4, 0xff
+; SI-NEXT: v_readlane_b32 s61, v62, 35
+; SI-NEXT: v_readlane_b32 s43, v62, 47
+; SI-NEXT: v_readlane_b32 s27, v61, 7
+; SI-NEXT: v_readlane_b32 s21, v61, 13
+; SI-NEXT: v_readlane_b32 s17, v61, 19
+; SI-NEXT: v_readlane_b32 s99, v63, 35
+; SI-NEXT: v_readlane_b32 s98, v63, 34
+; SI-NEXT: v_readlane_b32 s97, v63, 33
; SI-NEXT: v_readlane_b32 s96, v63, 32
+; SI-NEXT: v_readlane_b32 s87, v63, 31
+; SI-NEXT: v_readlane_b32 s86, v63, 30
+; SI-NEXT: v_readlane_b32 s85, v63, 29
+; SI-NEXT: v_readlane_b32 s84, v63, 28
+; SI-NEXT: v_readlane_b32 s83, v63, 27
+; SI-NEXT: v_readlane_b32 s82, v63, 26
+; SI-NEXT: v_readlane_b32 s81, v63, 25
; SI-NEXT: v_readlane_b32 s80, v63, 24
+; SI-NEXT: v_readlane_b32 s71, v63, 23
; SI-NEXT: v_readlane_b32 s70, v63, 22
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_readlane_b32 s69, v63, 21
+; SI-NEXT: v_readlane_b32 s68, v63, 20
+; SI-NEXT: v_readlane_b32 s67, v63, 19
+; SI-NEXT: v_readlane_b32 s66, v63, 18
+; SI-NEXT: v_readlane_b32 s65, v63, 17
+; SI-NEXT: v_readlane_b32 s64, v63, 16
+; SI-NEXT: v_readlane_b32 s55, v63, 15
+; SI-NEXT: v_readlane_b32 s54, v63, 14
+; SI-NEXT: v_readlane_b32 s53, v63, 13
+; SI-NEXT: v_readlane_b32 s52, v63, 12
+; SI-NEXT: v_readlane_b32 s51, v63, 11
+; SI-NEXT: v_readlane_b32 s50, v63, 10
+; SI-NEXT: v_readlane_b32 s49, v63, 9
+; SI-NEXT: v_readlane_b32 s48, v63, 8
+; SI-NEXT: v_readlane_b32 s39, v63, 7
+; SI-NEXT: v_readlane_b32 s38, v63, 6
+; SI-NEXT: v_readlane_b32 s37, v63, 5
+; SI-NEXT: v_readlane_b32 s36, v63, 4
+; SI-NEXT: v_readlane_b32 s35, v63, 3
+; SI-NEXT: v_readlane_b32 s34, v63, 2
+; SI-NEXT: v_readlane_b32 s31, v63, 1
+; SI-NEXT: v_readlane_b32 s30, v63, 0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v61, 20
+; SI-NEXT: v_or_b32_e32 v1, s5, v1
+; SI-NEXT: s_and_b32 s5, s10, 0xff
+; SI-NEXT: v_readlane_b32 s9, v61, 21
+; SI-NEXT: s_lshl_b32 s8, s8, 8
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v61, 22
+; SI-NEXT: v_readlane_b32 s9, v61, 23
+; SI-NEXT: s_and_b32 s8, s8, 0xff
+; SI-NEXT: v_readlane_b32 s10, v61, 24
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s9, s10, 24
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_or_b32 s8, s9, s8
+; SI-NEXT: s_or_b32 s5, s5, s8
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x70, v0
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: s_and_b32 s5, s14, 0xff
+; SI-NEXT: s_lshl_b32 s8, s12, 8
+; SI-NEXT: s_or_b32 s5, s5, s8
+; SI-NEXT: v_readlane_b32 s8, v61, 26
+; SI-NEXT: v_readlane_b32 s9, v61, 27
+; SI-NEXT: s_and_b32 s8, s9, 0xff
+; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0
+; SI-NEXT: v_readlane_b32 s11, v61, 25
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, s8, v1
+; SI-NEXT: v_readlane_b32 s8, v61, 28
+; SI-NEXT: v_readlane_b32 s9, v61, 29
; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: s_and_b32 s5, s84, 0xff
+; SI-NEXT: s_lshl_b32 s5, s8, 8
+; SI-NEXT: v_readlane_b32 s8, v61, 30
+; SI-NEXT: v_readlane_b32 s9, v61, 31
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: s_and_b32 s5, s8, 0xff
+; SI-NEXT: v_readlane_b32 s8, v61, 32
; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
-; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v46
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: s_lshl_b32 s5, s86, 24
-; SI-NEXT: v_readlane_b32 s86, v63, 30
-; SI-NEXT: v_readlane_b32 s84, v63, 28
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0
+; SI-NEXT: s_lshl_b32 s8, s8, 24
+; SI-NEXT: s_and_b32 s4, s4, 0xffff
+; SI-NEXT: s_or_b32 s5, s8, s5
+; SI-NEXT: s_or_b32 s4, s4, s5
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x78, v0
+; SI-NEXT: v_mov_b32_e32 v2, s4
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v35
+; SI-NEXT: s_and_b32 s4, s88, 0xff
+; SI-NEXT: s_lshl_b32 s5, s6, 8
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: s_and_b32 s5, s13, 0xff
+; SI-NEXT: s_lshl_b32 s5, s5, 16
+; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
+; SI-NEXT: v_readlane_b32 s9, v61, 33
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, s4, v1
-; SI-NEXT: s_and_b32 s4, s98, 0xff
-; SI-NEXT: s_lshl_b32 s4, s4, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_or_b32 s4, s5, s4
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, s5, v1
; SI-NEXT: v_or_b32_e32 v1, s4, v1
-; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v38
-; SI-NEXT: v_readlane_b32 s98, v63, 34
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -168733,8 +169805,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v63, s30, 0
; VI-NEXT: v_writelane_b32 v63, s31, 1
@@ -168769,209 +169842,225 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_writelane_b32 v63, s86, 30
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_writelane_b32 v63, s87, 31
-; VI-NEXT: v_readfirstlane_b32 s44, v3
-; VI-NEXT: v_readfirstlane_b32 s45, v4
-; VI-NEXT: v_readfirstlane_b32 s42, v5
-; VI-NEXT: v_readfirstlane_b32 s43, v6
-; VI-NEXT: v_readfirstlane_b32 s40, v7
-; VI-NEXT: v_readfirstlane_b32 s41, v8
-; VI-NEXT: v_readfirstlane_b32 s14, v9
-; VI-NEXT: v_readfirstlane_b32 s15, v10
-; VI-NEXT: v_readfirstlane_b32 s12, v11
-; VI-NEXT: v_readfirstlane_b32 s13, v12
-; VI-NEXT: v_readfirstlane_b32 s10, v13
-; VI-NEXT: v_readfirstlane_b32 s11, v14
-; VI-NEXT: v_readfirstlane_b32 s8, v15
-; VI-NEXT: v_readfirstlane_b32 s9, v16
-; VI-NEXT: v_readfirstlane_b32 s6, v17
-; VI-NEXT: v_readfirstlane_b32 s7, v18
+; VI-NEXT: v_readfirstlane_b32 s48, v3
+; VI-NEXT: v_readfirstlane_b32 s49, v4
+; VI-NEXT: v_readfirstlane_b32 s38, v5
+; VI-NEXT: v_readfirstlane_b32 s39, v6
+; VI-NEXT: v_readfirstlane_b32 s36, v7
+; VI-NEXT: v_readfirstlane_b32 s37, v8
+; VI-NEXT: v_readfirstlane_b32 s34, v9
+; VI-NEXT: v_readfirstlane_b32 s35, v10
+; VI-NEXT: v_readfirstlane_b32 s30, v11
+; VI-NEXT: v_readfirstlane_b32 s31, v12
+; VI-NEXT: v_readfirstlane_b32 s90, v13
+; VI-NEXT: v_readfirstlane_b32 s91, v14
+; VI-NEXT: v_readfirstlane_b32 s88, v15
+; VI-NEXT: v_readfirstlane_b32 s89, v16
+; VI-NEXT: v_readfirstlane_b32 s76, v17
+; VI-NEXT: v_readfirstlane_b32 s77, v18
; VI-NEXT: v_readfirstlane_b32 s4, v1
-; VI-NEXT: s_and_b64 s[46:47], vcc, exec
+; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr61 : SGPR spill to VGPR lane
; VI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; VI-NEXT: s_cbranch_scc0 .LBB91_3
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: s_lshr_b32 s46, s5, 24
-; VI-NEXT: v_writelane_b32 v62, s46, 57
-; VI-NEXT: s_lshr_b32 s46, s5, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 56
-; VI-NEXT: s_lshr_b32 s46, s5, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 55
-; VI-NEXT: s_lshr_b32 s46, s4, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 54
-; VI-NEXT: s_lshr_b32 s46, s4, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 53
-; VI-NEXT: s_lshr_b32 s46, s29, 24
-; VI-NEXT: v_writelane_b32 v62, s46, 52
-; VI-NEXT: s_lshr_b32 s46, s29, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 51
-; VI-NEXT: s_lshr_b32 s46, s29, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 50
-; VI-NEXT: s_lshr_b32 s46, s28, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 49
-; VI-NEXT: s_lshr_b32 s46, s28, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 48
-; VI-NEXT: s_lshr_b32 s46, s27, 24
-; VI-NEXT: v_writelane_b32 v62, s46, 47
-; VI-NEXT: s_lshr_b32 s46, s27, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 46
-; VI-NEXT: s_lshr_b32 s46, s27, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 45
-; VI-NEXT: s_lshr_b32 s46, s26, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 44
-; VI-NEXT: s_lshr_b32 s46, s26, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 43
-; VI-NEXT: s_lshr_b32 s46, s25, 24
-; VI-NEXT: v_writelane_b32 v62, s46, 42
-; VI-NEXT: s_lshr_b32 s46, s25, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 41
-; VI-NEXT: s_lshr_b32 s46, s25, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 40
-; VI-NEXT: s_lshr_b32 s46, s24, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 39
-; VI-NEXT: s_lshr_b32 s46, s24, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 38
-; VI-NEXT: s_lshr_b32 s46, s23, 24
-; VI-NEXT: v_writelane_b32 v62, s46, 37
-; VI-NEXT: s_lshr_b32 s46, s23, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 36
-; VI-NEXT: s_lshr_b32 s46, s23, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 35
-; VI-NEXT: s_lshr_b32 s46, s22, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 34
-; VI-NEXT: s_lshr_b32 s46, s22, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 33
-; VI-NEXT: s_lshr_b32 s46, s21, 24
-; VI-NEXT: v_writelane_b32 v62, s46, 32
-; VI-NEXT: s_lshr_b32 s46, s21, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 31
-; VI-NEXT: s_lshr_b32 s46, s21, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 30
-; VI-NEXT: s_lshr_b32 s46, s20, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 29
-; VI-NEXT: s_lshr_b32 s46, s20, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 28
-; VI-NEXT: s_lshr_b32 s46, s19, 24
-; VI-NEXT: v_writelane_b32 v62, s46, 27
-; VI-NEXT: s_lshr_b32 s46, s19, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 26
-; VI-NEXT: s_lshr_b32 s46, s19, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 25
-; VI-NEXT: s_lshr_b32 s46, s18, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 24
-; VI-NEXT: s_lshr_b32 s46, s18, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 23
-; VI-NEXT: s_lshr_b32 s46, s17, 24
-; VI-NEXT: v_writelane_b32 v62, s46, 22
-; VI-NEXT: s_lshr_b32 s46, s17, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 21
-; VI-NEXT: s_lshr_b32 s46, s17, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 20
-; VI-NEXT: s_lshr_b32 s46, s16, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 19
-; VI-NEXT: s_lshr_b32 s46, s16, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 18
-; VI-NEXT: s_lshr_b32 s46, s7, 24
-; VI-NEXT: v_writelane_b32 v62, s46, 17
-; VI-NEXT: s_lshr_b32 s46, s7, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 16
-; VI-NEXT: s_lshr_b32 s46, s7, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 15
-; VI-NEXT: s_lshr_b32 s46, s6, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 14
-; VI-NEXT: s_lshr_b32 s46, s6, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 13
-; VI-NEXT: s_lshr_b32 s46, s9, 24
-; VI-NEXT: v_writelane_b32 v62, s46, 12
-; VI-NEXT: s_lshr_b32 s46, s9, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 11
-; VI-NEXT: s_lshr_b32 s46, s9, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 10
-; VI-NEXT: s_lshr_b32 s46, s8, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 9
-; VI-NEXT: s_lshr_b32 s46, s8, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 8
-; VI-NEXT: s_lshr_b32 s46, s11, 24
-; VI-NEXT: v_writelane_b32 v62, s46, 7
-; VI-NEXT: s_lshr_b32 s46, s11, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 6
-; VI-NEXT: s_lshr_b32 s46, s11, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 5
-; VI-NEXT: s_lshr_b32 s46, s10, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 4
-; VI-NEXT: s_lshr_b32 s46, s10, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 3
-; VI-NEXT: s_lshr_b32 s46, s13, 24
-; VI-NEXT: v_writelane_b32 v62, s46, 2
-; VI-NEXT: s_lshr_b32 s46, s13, 16
-; VI-NEXT: v_writelane_b32 v62, s46, 1
-; VI-NEXT: s_lshr_b32 s46, s12, 16
-; VI-NEXT: s_lshr_b32 s80, s13, 8
-; VI-NEXT: v_writelane_b32 v62, s46, 0
-; VI-NEXT: s_lshr_b32 s81, s12, 8
-; VI-NEXT: s_lshr_b32 s82, s15, 24
-; VI-NEXT: s_lshr_b32 s83, s15, 16
-; VI-NEXT: s_lshr_b32 s85, s15, 8
-; VI-NEXT: s_lshr_b32 s84, s14, 16
-; VI-NEXT: s_lshr_b32 s86, s14, 8
-; VI-NEXT: s_lshr_b32 s87, s41, 24
-; VI-NEXT: s_lshr_b32 s50, s41, 16
-; VI-NEXT: s_lshr_b32 s52, s41, 8
-; VI-NEXT: s_lshr_b32 s51, s40, 16
-; VI-NEXT: s_lshr_b32 s53, s40, 8
-; VI-NEXT: s_lshr_b32 s54, s43, 24
-; VI-NEXT: s_lshr_b32 s55, s43, 16
-; VI-NEXT: s_lshr_b32 s65, s43, 8
-; VI-NEXT: s_lshr_b32 s64, s42, 16
-; VI-NEXT: s_lshr_b32 s66, s42, 8
-; VI-NEXT: s_lshr_b32 s67, s45, 24
-; VI-NEXT: s_lshr_b32 s68, s45, 16
-; VI-NEXT: s_lshr_b32 s70, s45, 8
-; VI-NEXT: s_lshr_b32 s69, s44, 16
-; VI-NEXT: s_lshr_b32 s71, s44, 8
-; VI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24
-; VI-NEXT: s_lshr_b64 s[56:57], s[28:29], 24
-; VI-NEXT: s_lshr_b64 s[58:59], s[26:27], 24
-; VI-NEXT: s_lshr_b64 s[60:61], s[24:25], 24
-; VI-NEXT: s_lshr_b64 s[62:63], s[22:23], 24
-; VI-NEXT: s_lshr_b64 s[72:73], s[20:21], 24
-; VI-NEXT: s_lshr_b64 s[74:75], s[18:19], 24
-; VI-NEXT: s_lshr_b64 s[76:77], s[16:17], 24
-; VI-NEXT: s_lshr_b64 s[78:79], s[6:7], 24
-; VI-NEXT: s_lshr_b64 s[88:89], s[8:9], 24
-; VI-NEXT: s_lshr_b64 s[90:91], s[10:11], 24
-; VI-NEXT: s_lshr_b64 s[30:31], s[12:13], 24
-; VI-NEXT: s_lshr_b64 s[34:35], s[14:15], 24
-; VI-NEXT: s_lshr_b64 s[36:37], s[40:41], 24
-; VI-NEXT: s_lshr_b64 s[38:39], s[42:43], 24
-; VI-NEXT: s_lshr_b64 s[48:49], s[44:45], 24
+; VI-NEXT: s_lshr_b32 s6, s5, 24
+; VI-NEXT: v_writelane_b32 v61, s6, 26
+; VI-NEXT: s_lshr_b32 s6, s5, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 27
+; VI-NEXT: s_lshr_b32 s6, s5, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 28
+; VI-NEXT: s_lshr_b32 s6, s4, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 29
+; VI-NEXT: s_lshr_b32 s6, s4, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 30
+; VI-NEXT: s_lshr_b32 s6, s29, 24
+; VI-NEXT: v_writelane_b32 v61, s6, 31
+; VI-NEXT: s_lshr_b32 s6, s29, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 32
+; VI-NEXT: s_lshr_b32 s6, s29, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 33
+; VI-NEXT: s_lshr_b32 s6, s28, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 34
+; VI-NEXT: s_lshr_b32 s6, s28, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 35
+; VI-NEXT: s_lshr_b32 s6, s27, 24
+; VI-NEXT: v_writelane_b32 v61, s6, 36
+; VI-NEXT: s_lshr_b32 s6, s27, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 37
+; VI-NEXT: s_lshr_b32 s6, s27, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 38
+; VI-NEXT: s_lshr_b32 s6, s26, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 39
+; VI-NEXT: s_lshr_b32 s6, s26, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 40
+; VI-NEXT: s_lshr_b32 s6, s25, 24
+; VI-NEXT: v_writelane_b32 v61, s6, 41
+; VI-NEXT: s_lshr_b32 s6, s25, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 42
+; VI-NEXT: s_lshr_b32 s6, s25, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 43
+; VI-NEXT: s_lshr_b32 s6, s24, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 44
+; VI-NEXT: s_lshr_b32 s6, s24, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 45
+; VI-NEXT: s_lshr_b32 s6, s23, 24
+; VI-NEXT: v_writelane_b32 v61, s6, 46
+; VI-NEXT: s_lshr_b32 s6, s23, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 47
+; VI-NEXT: s_lshr_b32 s6, s23, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 48
+; VI-NEXT: s_lshr_b32 s6, s22, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 49
+; VI-NEXT: s_lshr_b32 s6, s22, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 50
+; VI-NEXT: s_lshr_b32 s6, s21, 24
+; VI-NEXT: v_writelane_b32 v61, s6, 51
+; VI-NEXT: s_lshr_b32 s6, s21, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 52
+; VI-NEXT: s_lshr_b32 s6, s21, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 53
+; VI-NEXT: s_lshr_b32 s6, s20, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 54
+; VI-NEXT: s_lshr_b32 s6, s20, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 55
+; VI-NEXT: s_lshr_b32 s6, s19, 24
+; VI-NEXT: v_writelane_b32 v61, s6, 56
+; VI-NEXT: s_lshr_b32 s6, s19, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 57
+; VI-NEXT: s_lshr_b32 s6, s19, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 58
+; VI-NEXT: s_lshr_b32 s6, s18, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 59
+; VI-NEXT: s_lshr_b32 s6, s18, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 60
+; VI-NEXT: s_lshr_b32 s6, s17, 24
+; VI-NEXT: v_writelane_b32 v61, s6, 61
+; VI-NEXT: s_lshr_b32 s6, s17, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 62
+; VI-NEXT: s_lshr_b32 s6, s17, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 63
+; VI-NEXT: s_lshr_b32 s6, s16, 16
+; VI-NEXT: v_writelane_b32 v62, s6, 0
+; VI-NEXT: s_lshr_b32 s6, s16, 8
+; VI-NEXT: v_writelane_b32 v62, s6, 1
+; VI-NEXT: s_lshr_b32 s6, s39, 24
+; VI-NEXT: v_writelane_b32 v61, s6, 18
+; VI-NEXT: s_lshr_b32 s6, s39, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 19
+; VI-NEXT: s_lshr_b32 s6, s39, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 20
+; VI-NEXT: s_lshr_b32 s6, s38, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 16
+; VI-NEXT: s_lshr_b32 s6, s38, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 17
+; VI-NEXT: s_lshr_b32 s6, s49, 24
+; VI-NEXT: v_writelane_b32 v61, s6, 23
+; VI-NEXT: s_lshr_b32 s6, s49, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 24
+; VI-NEXT: s_lshr_b32 s6, s49, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 25
+; VI-NEXT: s_lshr_b32 s6, s48, 16
+; VI-NEXT: v_writelane_b32 v61, s6, 21
+; VI-NEXT: s_lshr_b32 s6, s48, 8
+; VI-NEXT: v_writelane_b32 v61, s6, 22
+; VI-NEXT: s_lshr_b64 vcc, s[4:5], 24
+; VI-NEXT: v_writelane_b32 v61, vcc_lo, 14
+; VI-NEXT: v_writelane_b32 v61, vcc_hi, 15
+; VI-NEXT: s_lshr_b64 vcc, s[28:29], 24
+; VI-NEXT: v_writelane_b32 v61, vcc_lo, 12
+; VI-NEXT: v_writelane_b32 v61, vcc_hi, 13
+; VI-NEXT: s_lshr_b64 vcc, s[26:27], 24
+; VI-NEXT: v_writelane_b32 v61, vcc_lo, 10
+; VI-NEXT: v_writelane_b32 v61, vcc_hi, 11
+; VI-NEXT: s_lshr_b64 vcc, s[24:25], 24
+; VI-NEXT: v_writelane_b32 v61, vcc_lo, 8
+; VI-NEXT: v_writelane_b32 v61, vcc_hi, 9
+; VI-NEXT: s_lshr_b64 vcc, s[22:23], 24
+; VI-NEXT: v_writelane_b32 v61, vcc_lo, 6
+; VI-NEXT: v_writelane_b32 v61, vcc_hi, 7
+; VI-NEXT: s_lshr_b64 vcc, s[20:21], 24
+; VI-NEXT: v_writelane_b32 v61, vcc_lo, 4
+; VI-NEXT: v_writelane_b32 v61, vcc_hi, 5
+; VI-NEXT: s_lshr_b64 vcc, s[18:19], 24
+; VI-NEXT: v_writelane_b32 v61, vcc_lo, 2
+; VI-NEXT: v_writelane_b32 v61, vcc_hi, 3
+; VI-NEXT: s_lshr_b64 vcc, s[16:17], 24
+; VI-NEXT: v_writelane_b32 v61, vcc_lo, 0
+; VI-NEXT: s_lshr_b32 s87, s77, 24
+; VI-NEXT: s_lshr_b32 s43, s77, 16
+; VI-NEXT: s_lshr_b32 s42, s77, 8
+; VI-NEXT: s_lshr_b32 s13, s76, 16
+; VI-NEXT: s_lshr_b32 s11, s76, 8
+; VI-NEXT: s_lshr_b32 s86, s89, 24
+; VI-NEXT: s_lshr_b32 s85, s89, 16
+; VI-NEXT: s_lshr_b32 s84, s89, 8
+; VI-NEXT: s_lshr_b32 s9, s88, 16
+; VI-NEXT: s_lshr_b32 s7, s88, 8
+; VI-NEXT: s_lshr_b32 s75, s91, 24
+; VI-NEXT: s_lshr_b32 s74, s91, 16
+; VI-NEXT: s_lshr_b32 s73, s91, 8
+; VI-NEXT: s_lshr_b32 s79, s90, 16
+; VI-NEXT: s_lshr_b32 s78, s90, 8
+; VI-NEXT: s_lshr_b32 s60, s31, 24
+; VI-NEXT: s_lshr_b32 s15, s31, 16
+; VI-NEXT: s_lshr_b32 s14, s31, 8
+; VI-NEXT: s_lshr_b32 s72, s30, 16
+; VI-NEXT: s_lshr_b32 s61, s30, 8
+; VI-NEXT: s_lshr_b32 s63, s35, 24
+; VI-NEXT: s_lshr_b32 s57, s35, 16
+; VI-NEXT: s_lshr_b32 s56, s35, 8
+; VI-NEXT: s_lshr_b32 s83, s34, 16
+; VI-NEXT: s_lshr_b32 s82, s34, 8
+; VI-NEXT: s_lshr_b32 s41, s37, 24
+; VI-NEXT: s_lshr_b32 s47, s37, 16
+; VI-NEXT: s_lshr_b32 s46, s37, 8
+; VI-NEXT: s_lshr_b32 s59, s36, 16
+; VI-NEXT: s_lshr_b32 s45, s36, 8
+; VI-NEXT: v_writelane_b32 v61, vcc_hi, 1
+; VI-NEXT: s_lshr_b64 s[50:51], s[76:77], 24
+; VI-NEXT: s_lshr_b64 s[52:53], s[88:89], 24
+; VI-NEXT: s_lshr_b64 s[54:55], s[90:91], 24
+; VI-NEXT: s_lshr_b64 s[64:65], s[30:31], 24
+; VI-NEXT: s_lshr_b64 s[66:67], s[34:35], 24
+; VI-NEXT: s_lshr_b64 s[68:69], s[36:37], 24
+; VI-NEXT: s_lshr_b64 s[70:71], s[38:39], 24
+; VI-NEXT: s_lshr_b64 s[80:81], s[48:49], 24
+; VI-NEXT: s_mov_b32 s6, s17
+; VI-NEXT: s_mov_b32 s8, s19
+; VI-NEXT: s_mov_b32 s10, s21
+; VI-NEXT: s_mov_b32 s12, s23
+; VI-NEXT: s_mov_b32 s40, s25
+; VI-NEXT: s_mov_b32 s44, s27
+; VI-NEXT: s_mov_b32 s58, s29
+; VI-NEXT: s_mov_b32 s62, s5
; VI-NEXT: s_cbranch_execnz .LBB91_4
; VI-NEXT: .LBB91_2: ; %cmp.true
-; VI-NEXT: s_lshl_b32 s46, s45, 16
-; VI-NEXT: v_mov_b32_e32 v31, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s46, v31
+; VI-NEXT: s_lshl_b32 s6, s49, 16
+; VI-NEXT: v_mov_b32_e32 v25, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v1, s6, v25
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s45, s45, 0xffff0000
+; VI-NEXT: s_and_b32 s6, s49, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s45, v31
+; VI-NEXT: v_add_f32_e32 v2, s6, v25
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
@@ -168979,53 +170068,33 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s45, s44, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s45, v31
-; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_lshrrev_b64 v[1:2], 16, v[1:2]
+; VI-NEXT: s_lshl_b32 s6, s48, 16
+; VI-NEXT: v_add_f32_e32 v2, s6, v25
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s44, s44, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s44, v31
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: s_lshl_b32 s44, s43, 16
-; VI-NEXT: v_alignbit_b32 v1, v3, v1, 16
-; VI-NEXT: v_add_f32_e32 v3, s44, v31
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b32 s6, s48, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; VI-NEXT: v_add_f32_e32 v3, s6, v25
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_and_b32 s43, s43, 0xffff0000
+; VI-NEXT: s_lshl_b32 s6, s39, 16
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s43, v31
+; VI-NEXT: v_add_f32_e32 v4, s6, v25
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; VI-NEXT: s_and_b32 s6, s39, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; VI-NEXT: s_lshl_b32 s43, s42, 16
-; VI-NEXT: v_alignbit_b32 v4, v4, v3, 16
-; VI-NEXT: v_add_f32_e32 v3, s43, v31
-; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_and_b32 s42, s42, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
-; VI-NEXT: v_add_f32_e32 v5, s42, v31
+; VI-NEXT: v_add_f32_e32 v5, s6, v25
; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
@@ -169033,53 +170102,33 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; VI-NEXT: s_lshl_b32 s42, s41, 16
-; VI-NEXT: v_alignbit_b32 v3, v5, v3, 16
-; VI-NEXT: v_add_f32_e32 v5, s42, v31
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[4:5]
+; VI-NEXT: s_lshl_b32 s6, s38, 16
+; VI-NEXT: v_add_f32_e32 v5, s6, v25
; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: s_and_b32 s41, s41, 0xffff0000
+; VI-NEXT: s_and_b32 s6, s38, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
-; VI-NEXT: v_add_f32_e32 v6, s41, v31
+; VI-NEXT: v_add_f32_e32 v6, s6, v25
; VI-NEXT: v_bfe_u32 v7, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT: v_or_b32_e32 v8, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
+; VI-NEXT: s_lshl_b32 s6, s37, 16
; VI-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; VI-NEXT: s_lshl_b32 s41, s40, 16
-; VI-NEXT: v_alignbit_b32 v6, v6, v5, 16
-; VI-NEXT: v_add_f32_e32 v5, s41, v31
-; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
-; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
-; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
-; VI-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: s_and_b32 s40, s40, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc
-; VI-NEXT: v_add_f32_e32 v7, s40, v31
-; VI-NEXT: v_bfe_u32 v8, v7, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v7
-; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; VI-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; VI-NEXT: s_lshl_b32 s40, s15, 16
-; VI-NEXT: v_alignbit_b32 v5, v7, v5, 16
-; VI-NEXT: v_add_f32_e32 v7, s40, v31
+; VI-NEXT: v_add_f32_e32 v7, s6, v25
; VI-NEXT: v_bfe_u32 v8, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v7
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; VI-NEXT: s_and_b32 s15, s15, 0xffff0000
+; VI-NEXT: s_and_b32 s6, s37, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; VI-NEXT: v_add_f32_e32 v8, s15, v31
+; VI-NEXT: v_add_f32_e32 v8, s6, v25
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
@@ -169087,53 +170136,33 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; VI-NEXT: s_lshl_b32 s15, s14, 16
-; VI-NEXT: v_alignbit_b32 v8, v8, v7, 16
-; VI-NEXT: v_add_f32_e32 v7, s15, v31
-; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: v_lshrrev_b64 v[7:8], 16, v[7:8]
+; VI-NEXT: s_lshl_b32 s6, s36, 16
+; VI-NEXT: v_add_f32_e32 v8, s6, v25
+; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v7
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; VI-NEXT: s_and_b32 s14, s14, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
-; VI-NEXT: v_add_f32_e32 v9, s14, v31
-; VI-NEXT: v_bfe_u32 v10, v9, 16, 1
-; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v9
-; VI-NEXT: v_add_u32_e32 v10, vcc, 0x7fff, v10
-; VI-NEXT: v_or_b32_e32 v11, 0x400000, v9
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
-; VI-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; VI-NEXT: s_lshl_b32 s14, s13, 16
-; VI-NEXT: v_alignbit_b32 v7, v9, v7, 16
-; VI-NEXT: v_add_f32_e32 v9, s14, v31
+; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
+; VI-NEXT: s_and_b32 s6, s36, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
+; VI-NEXT: v_add_f32_e32 v9, s6, v25
; VI-NEXT: v_bfe_u32 v10, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v9
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x7fff, v10
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
-; VI-NEXT: s_and_b32 s13, s13, 0xffff0000
+; VI-NEXT: s_lshl_b32 s6, s35, 16
; VI-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc
-; VI-NEXT: v_add_f32_e32 v10, s13, v31
+; VI-NEXT: v_add_f32_e32 v10, s6, v25
; VI-NEXT: v_bfe_u32 v11, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
; VI-NEXT: v_or_b32_e32 v12, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
+; VI-NEXT: s_and_b32 s6, s35, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; VI-NEXT: s_lshl_b32 s13, s12, 16
-; VI-NEXT: v_alignbit_b32 v10, v10, v9, 16
-; VI-NEXT: v_add_f32_e32 v9, s13, v31
-; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
-; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
-; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
-; VI-NEXT: v_or_b32_e32 v12, 0x400000, v9
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
-; VI-NEXT: s_and_b32 s12, s12, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc
-; VI-NEXT: v_add_f32_e32 v11, s12, v31
+; VI-NEXT: v_add_f32_e32 v11, s6, v25
; VI-NEXT: v_bfe_u32 v12, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v11
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x7fff, v12
@@ -169141,53 +170170,33 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc
; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; VI-NEXT: s_lshl_b32 s12, s11, 16
-; VI-NEXT: v_alignbit_b32 v9, v11, v9, 16
-; VI-NEXT: v_add_f32_e32 v11, s12, v31
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[10:11]
+; VI-NEXT: s_lshl_b32 s6, s34, 16
+; VI-NEXT: v_add_f32_e32 v11, s6, v25
; VI-NEXT: v_bfe_u32 v12, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v11
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x7fff, v12
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
-; VI-NEXT: s_and_b32 s11, s11, 0xffff0000
+; VI-NEXT: s_and_b32 s6, s34, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc
-; VI-NEXT: v_add_f32_e32 v12, s11, v31
+; VI-NEXT: v_add_f32_e32 v12, s6, v25
; VI-NEXT: v_bfe_u32 v13, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_or_b32_e32 v14, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
+; VI-NEXT: s_lshl_b32 s6, s31, 16
; VI-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; VI-NEXT: s_lshl_b32 s11, s10, 16
-; VI-NEXT: v_alignbit_b32 v12, v12, v11, 16
-; VI-NEXT: v_add_f32_e32 v11, s11, v31
-; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
-; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
-; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
-; VI-NEXT: v_or_b32_e32 v14, 0x400000, v11
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
-; VI-NEXT: s_and_b32 s10, s10, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
-; VI-NEXT: v_add_f32_e32 v13, s10, v31
-; VI-NEXT: v_bfe_u32 v14, v13, 16, 1
-; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13
-; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
-; VI-NEXT: v_or_b32_e32 v15, 0x400000, v13
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
-; VI-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; VI-NEXT: s_lshl_b32 s10, s9, 16
-; VI-NEXT: v_alignbit_b32 v11, v13, v11, 16
-; VI-NEXT: v_add_f32_e32 v13, s10, v31
+; VI-NEXT: v_add_f32_e32 v13, s6, v25
; VI-NEXT: v_bfe_u32 v14, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
-; VI-NEXT: s_and_b32 s9, s9, 0xffff0000
+; VI-NEXT: s_and_b32 s6, s31, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc
-; VI-NEXT: v_add_f32_e32 v14, s9, v31
+; VI-NEXT: v_add_f32_e32 v14, s6, v25
; VI-NEXT: v_bfe_u32 v15, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
@@ -169195,53 +170204,33 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; VI-NEXT: s_lshl_b32 s9, s8, 16
-; VI-NEXT: v_alignbit_b32 v14, v14, v13, 16
-; VI-NEXT: v_add_f32_e32 v13, s9, v31
-; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
-; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_lshrrev_b64 v[13:14], 16, v[13:14]
+; VI-NEXT: s_lshl_b32 s6, s30, 16
+; VI-NEXT: v_add_f32_e32 v14, s6, v25
+; VI-NEXT: v_bfe_u32 v15, v14, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v13
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
-; VI-NEXT: s_and_b32 s8, s8, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v13, v15, v16, vcc
-; VI-NEXT: v_add_f32_e32 v15, s8, v31
-; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v15
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
-; VI-NEXT: v_cndmask_b32_e32 v15, v16, v17, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; VI-NEXT: s_lshl_b32 s8, s7, 16
-; VI-NEXT: v_alignbit_b32 v13, v15, v13, 16
-; VI-NEXT: v_add_f32_e32 v15, s8, v31
+; VI-NEXT: v_or_b32_e32 v16, 0x400000, v14
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
+; VI-NEXT: s_and_b32 s6, s30, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
+; VI-NEXT: v_add_f32_e32 v15, s6, v25
; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
-; VI-NEXT: s_and_b32 s7, s7, 0xffff0000
+; VI-NEXT: s_lshl_b32 s6, s91, 16
; VI-NEXT: v_cndmask_b32_e32 v15, v16, v17, vcc
-; VI-NEXT: v_add_f32_e32 v16, s7, v31
+; VI-NEXT: v_add_f32_e32 v16, s6, v25
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
+; VI-NEXT: s_and_b32 s6, s91, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; VI-NEXT: s_lshl_b32 s7, s6, 16
-; VI-NEXT: v_alignbit_b32 v16, v16, v15, 16
-; VI-NEXT: v_add_f32_e32 v15, s7, v31
-; VI-NEXT: v_bfe_u32 v17, v15, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v15
-; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v15
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
-; VI-NEXT: s_and_b32 s6, s6, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc
-; VI-NEXT: v_add_f32_e32 v17, s6, v31
+; VI-NEXT: v_add_f32_e32 v17, s6, v25
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
@@ -169249,53 +170238,33 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; VI-NEXT: s_lshl_b32 s6, s17, 16
-; VI-NEXT: v_alignbit_b32 v15, v17, v15, 16
-; VI-NEXT: v_add_f32_e32 v17, s6, v31
+; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[16:17]
+; VI-NEXT: s_lshl_b32 s6, s90, 16
+; VI-NEXT: v_add_f32_e32 v17, s6, v25
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
-; VI-NEXT: s_and_b32 s6, s17, 0xffff0000
+; VI-NEXT: s_and_b32 s6, s90, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
-; VI-NEXT: v_add_f32_e32 v18, s6, v31
+; VI-NEXT: v_add_f32_e32 v18, s6, v25
; VI-NEXT: v_bfe_u32 v19, v18, 16, 1
; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v18
; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19
; VI-NEXT: v_or_b32_e32 v20, 0x400000, v18
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: s_lshl_b32 s6, s89, 16
; VI-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; VI-NEXT: s_lshl_b32 s6, s16, 16
-; VI-NEXT: v_alignbit_b32 v18, v18, v17, 16
-; VI-NEXT: v_add_f32_e32 v17, s6, v31
-; VI-NEXT: v_bfe_u32 v19, v17, 16, 1
-; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v17
-; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19
-; VI-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
-; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc
-; VI-NEXT: v_add_f32_e32 v19, s6, v31
-; VI-NEXT: v_bfe_u32 v20, v19, 16, 1
-; VI-NEXT: v_add_u32_e32 v20, vcc, v20, v19
-; VI-NEXT: v_add_u32_e32 v20, vcc, 0x7fff, v20
-; VI-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
-; VI-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; VI-NEXT: s_lshl_b32 s6, s19, 16
-; VI-NEXT: v_alignbit_b32 v17, v19, v17, 16
-; VI-NEXT: v_add_f32_e32 v19, s6, v31
+; VI-NEXT: v_add_f32_e32 v19, s6, v25
; VI-NEXT: v_bfe_u32 v20, v19, 16, 1
; VI-NEXT: v_add_u32_e32 v20, vcc, v20, v19
; VI-NEXT: v_add_u32_e32 v20, vcc, 0x7fff, v20
; VI-NEXT: v_or_b32_e32 v21, 0x400000, v19
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
-; VI-NEXT: s_and_b32 s6, s19, 0xffff0000
+; VI-NEXT: s_and_b32 s6, s89, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc
-; VI-NEXT: v_add_f32_e32 v20, s6, v31
+; VI-NEXT: v_add_f32_e32 v20, s6, v25
; VI-NEXT: v_bfe_u32 v21, v20, 16, 1
; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v20
; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
@@ -169303,863 +170272,1089 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
; VI-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc
; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; VI-NEXT: s_lshl_b32 s6, s18, 16
-; VI-NEXT: v_alignbit_b32 v20, v20, v19, 16
-; VI-NEXT: v_add_f32_e32 v19, s6, v31
-; VI-NEXT: v_bfe_u32 v21, v19, 16, 1
-; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v19
+; VI-NEXT: v_lshrrev_b64 v[19:20], 16, v[19:20]
+; VI-NEXT: s_lshl_b32 s6, s88, 16
+; VI-NEXT: v_add_f32_e32 v20, s6, v25
+; VI-NEXT: v_bfe_u32 v21, v20, 16, 1
+; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v20
; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
-; VI-NEXT: v_or_b32_e32 v22, 0x400000, v19
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
-; VI-NEXT: s_and_b32 s6, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v19, v21, v22, vcc
-; VI-NEXT: v_add_f32_e32 v21, s6, v31
-; VI-NEXT: v_bfe_u32 v22, v21, 16, 1
-; VI-NEXT: v_add_u32_e32 v22, vcc, v22, v21
-; VI-NEXT: v_add_u32_e32 v22, vcc, 0x7fff, v22
-; VI-NEXT: v_or_b32_e32 v23, 0x400000, v21
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
-; VI-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; VI-NEXT: s_lshl_b32 s6, s21, 16
-; VI-NEXT: v_alignbit_b32 v19, v21, v19, 16
-; VI-NEXT: v_add_f32_e32 v21, s6, v31
+; VI-NEXT: v_or_b32_e32 v22, 0x400000, v20
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
+; VI-NEXT: s_and_b32 s6, s88, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc
+; VI-NEXT: v_add_f32_e32 v21, s6, v25
; VI-NEXT: v_bfe_u32 v22, v21, 16, 1
; VI-NEXT: v_add_u32_e32 v22, vcc, v22, v21
; VI-NEXT: v_add_u32_e32 v22, vcc, 0x7fff, v22
; VI-NEXT: v_or_b32_e32 v23, 0x400000, v21
; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
-; VI-NEXT: s_and_b32 s6, s21, 0xffff0000
+; VI-NEXT: s_lshl_b32 s6, s77, 16
; VI-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc
-; VI-NEXT: v_add_f32_e32 v22, s6, v31
+; VI-NEXT: v_add_f32_e32 v22, s6, v25
; VI-NEXT: v_bfe_u32 v23, v22, 16, 1
; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v22
; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23
; VI-NEXT: v_or_b32_e32 v24, 0x400000, v22
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
+; VI-NEXT: s_and_b32 s6, s77, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; VI-NEXT: s_lshl_b32 s6, s20, 16
-; VI-NEXT: v_alignbit_b32 v22, v22, v21, 16
-; VI-NEXT: v_add_f32_e32 v21, s6, v31
-; VI-NEXT: v_bfe_u32 v23, v21, 16, 1
-; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v21
-; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23
-; VI-NEXT: v_or_b32_e32 v24, 0x400000, v21
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
-; VI-NEXT: s_and_b32 s6, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v21, v23, v24, vcc
-; VI-NEXT: v_add_f32_e32 v23, s6, v31
+; VI-NEXT: v_add_f32_e32 v23, s6, v25
; VI-NEXT: v_bfe_u32 v24, v23, 16, 1
; VI-NEXT: v_add_u32_e32 v24, vcc, v24, v23
; VI-NEXT: v_add_u32_e32 v24, vcc, 0x7fff, v24
-; VI-NEXT: v_or_b32_e32 v25, 0x400000, v23
+; VI-NEXT: v_or_b32_e32 v26, 0x400000, v23
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
-; VI-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc
+; VI-NEXT: v_cndmask_b32_e32 v23, v24, v26, vcc
; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; VI-NEXT: s_lshl_b32 s6, s23, 16
-; VI-NEXT: v_alignbit_b32 v21, v23, v21, 16
-; VI-NEXT: v_add_f32_e32 v23, s6, v31
+; VI-NEXT: v_lshrrev_b64 v[22:23], 16, v[22:23]
+; VI-NEXT: s_lshl_b32 s6, s76, 16
+; VI-NEXT: v_add_f32_e32 v23, s6, v25
; VI-NEXT: v_bfe_u32 v24, v23, 16, 1
; VI-NEXT: v_add_u32_e32 v24, vcc, v24, v23
; VI-NEXT: v_add_u32_e32 v24, vcc, 0x7fff, v24
-; VI-NEXT: v_or_b32_e32 v25, 0x400000, v23
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
-; VI-NEXT: s_and_b32 s6, s23, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc
-; VI-NEXT: v_add_f32_e32 v24, s6, v31
-; VI-NEXT: v_bfe_u32 v25, v24, 16, 1
-; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v24
-; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
-; VI-NEXT: v_or_b32_e32 v26, 0x400000, v24
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
-; VI-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; VI-NEXT: s_lshl_b32 s6, s22, 16
-; VI-NEXT: v_alignbit_b32 v24, v24, v23, 16
-; VI-NEXT: v_add_f32_e32 v23, s6, v31
-; VI-NEXT: v_bfe_u32 v25, v23, 16, 1
-; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v23
-; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
; VI-NEXT: v_or_b32_e32 v26, 0x400000, v23
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
-; VI-NEXT: s_and_b32 s6, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v23, v25, v26, vcc
-; VI-NEXT: v_add_f32_e32 v25, s6, v31
-; VI-NEXT: v_bfe_u32 v26, v25, 16, 1
-; VI-NEXT: v_add_u32_e32 v26, vcc, v26, v25
-; VI-NEXT: v_add_u32_e32 v26, vcc, 0x7fff, v26
-; VI-NEXT: v_or_b32_e32 v27, 0x400000, v25
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
-; VI-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; VI-NEXT: s_lshl_b32 s6, s25, 16
-; VI-NEXT: v_alignbit_b32 v23, v25, v23, 16
-; VI-NEXT: v_add_f32_e32 v25, s6, v31
-; VI-NEXT: v_bfe_u32 v26, v25, 16, 1
-; VI-NEXT: v_add_u32_e32 v26, vcc, v26, v25
+; VI-NEXT: s_and_b32 s6, s76, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v23, v24, v26, vcc
+; VI-NEXT: v_add_f32_e32 v24, s6, v25
+; VI-NEXT: v_bfe_u32 v26, v24, 16, 1
+; VI-NEXT: v_add_u32_e32 v26, vcc, v26, v24
; VI-NEXT: v_add_u32_e32 v26, vcc, 0x7fff, v26
-; VI-NEXT: v_or_b32_e32 v27, 0x400000, v25
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
-; VI-NEXT: s_and_b32 s6, s25, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc
-; VI-NEXT: v_add_f32_e32 v26, s6, v31
-; VI-NEXT: v_bfe_u32 v27, v26, 16, 1
-; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v26
-; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27
-; VI-NEXT: v_or_b32_e32 v28, 0x400000, v26
+; VI-NEXT: v_or_b32_e32 v27, 0x400000, v24
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
+; VI-NEXT: s_lshl_b32 s6, s17, 16
+; VI-NEXT: v_cndmask_b32_e32 v24, v26, v27, vcc
+; VI-NEXT: v_add_f32_e32 v26, s6, v25
+; VI-NEXT: v_readfirstlane_b32 s6, v26
+; VI-NEXT: s_bfe_u32 s7, s6, 0x10010
+; VI-NEXT: s_add_i32 s7, s7, s6
+; VI-NEXT: s_add_i32 s8, s7, 0x7fff
+; VI-NEXT: s_or_b32 s9, s6, 0x400000
; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
-; VI-NEXT: v_cndmask_b32_e32 v26, v27, v28, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; VI-NEXT: s_lshl_b32 s6, s24, 16
-; VI-NEXT: v_alignbit_b32 v26, v26, v25, 16
-; VI-NEXT: v_add_f32_e32 v25, s6, v31
-; VI-NEXT: v_bfe_u32 v27, v25, 16, 1
-; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v25
-; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27
-; VI-NEXT: v_or_b32_e32 v28, 0x400000, v25
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
-; VI-NEXT: s_and_b32 s6, s24, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v25, v27, v28, vcc
-; VI-NEXT: v_add_f32_e32 v27, s6, v31
-; VI-NEXT: v_bfe_u32 v28, v27, 16, 1
-; VI-NEXT: v_add_u32_e32 v28, vcc, v28, v27
-; VI-NEXT: v_add_u32_e32 v28, vcc, 0x7fff, v28
-; VI-NEXT: v_or_b32_e32 v29, 0x400000, v27
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
-; VI-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; VI-NEXT: s_lshl_b32 s6, s27, 16
-; VI-NEXT: v_alignbit_b32 v25, v27, v25, 16
-; VI-NEXT: v_add_f32_e32 v27, s6, v31
-; VI-NEXT: v_bfe_u32 v28, v27, 16, 1
-; VI-NEXT: v_add_u32_e32 v28, vcc, v28, v27
-; VI-NEXT: v_add_u32_e32 v28, vcc, 0x7fff, v28
-; VI-NEXT: v_or_b32_e32 v29, 0x400000, v27
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
-; VI-NEXT: s_and_b32 s6, s27, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc
-; VI-NEXT: v_add_f32_e32 v28, s6, v31
-; VI-NEXT: v_bfe_u32 v29, v28, 16, 1
-; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v28
-; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29
-; VI-NEXT: v_or_b32_e32 v30, 0x400000, v28
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
-; VI-NEXT: v_cndmask_b32_e32 v28, v29, v30, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; VI-NEXT: s_lshl_b32 s6, s26, 16
-; VI-NEXT: v_alignbit_b32 v28, v28, v27, 16
-; VI-NEXT: v_add_f32_e32 v27, s6, v31
-; VI-NEXT: v_bfe_u32 v29, v27, 16, 1
-; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v27
-; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29
-; VI-NEXT: v_or_b32_e32 v30, 0x400000, v27
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
-; VI-NEXT: s_and_b32 s6, s26, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v27, v29, v30, vcc
-; VI-NEXT: v_add_f32_e32 v29, s6, v31
-; VI-NEXT: v_bfe_u32 v30, v29, 16, 1
-; VI-NEXT: v_add_u32_e32 v30, vcc, v30, v29
-; VI-NEXT: v_add_u32_e32 v30, vcc, 0x7fff, v30
-; VI-NEXT: v_or_b32_e32 v32, 0x400000, v29
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
-; VI-NEXT: v_cndmask_b32_e32 v29, v30, v32, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; VI-NEXT: s_lshl_b32 s6, s29, 16
-; VI-NEXT: v_alignbit_b32 v27, v29, v27, 16
-; VI-NEXT: v_add_f32_e32 v29, s6, v31
-; VI-NEXT: v_bfe_u32 v30, v29, 16, 1
-; VI-NEXT: v_add_u32_e32 v30, vcc, v30, v29
-; VI-NEXT: v_add_u32_e32 v30, vcc, 0x7fff, v30
-; VI-NEXT: v_or_b32_e32 v32, 0x400000, v29
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
-; VI-NEXT: s_and_b32 s6, s29, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v29, v30, v32, vcc
-; VI-NEXT: v_add_f32_e32 v30, s6, v31
-; VI-NEXT: v_bfe_u32 v32, v30, 16, 1
-; VI-NEXT: v_add_u32_e32 v32, vcc, v32, v30
-; VI-NEXT: v_add_u32_e32 v32, vcc, 0x7fff, v32
-; VI-NEXT: v_or_b32_e32 v33, 0x400000, v30
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
-; VI-NEXT: v_cndmask_b32_e32 v30, v32, v33, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; VI-NEXT: s_lshl_b32 s6, s28, 16
-; VI-NEXT: v_alignbit_b32 v30, v30, v29, 16
-; VI-NEXT: v_add_f32_e32 v29, s6, v31
-; VI-NEXT: v_bfe_u32 v32, v29, 16, 1
-; VI-NEXT: v_add_u32_e32 v32, vcc, v32, v29
-; VI-NEXT: v_add_u32_e32 v32, vcc, 0x7fff, v32
-; VI-NEXT: v_or_b32_e32 v33, 0x400000, v29
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
-; VI-NEXT: s_and_b32 s6, s28, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v29, v32, v33, vcc
-; VI-NEXT: v_add_f32_e32 v32, s6, v31
-; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
-; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; VI-NEXT: s_lshl_b32 s6, s5, 16
-; VI-NEXT: v_alignbit_b32 v29, v32, v29, 16
-; VI-NEXT: v_add_f32_e32 v32, s6, v31
-; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
+; VI-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-NEXT: s_cselect_b32 s6, s9, s8
+; VI-NEXT: s_and_b32 s7, s17, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s8, s7, 0x10010
+; VI-NEXT: s_add_i32 s8, s8, s7
+; VI-NEXT: s_add_i32 s10, s8, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[8:9], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s10
+; VI-NEXT: s_lshr_b32 s7, s7, 16
+; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
+; VI-NEXT: s_lshl_b32 s7, s16, 16
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s8, s7, 0x10010
+; VI-NEXT: s_add_i32 s8, s8, s7
+; VI-NEXT: s_add_i32 s10, s8, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[8:9], vcc, exec
+; VI-NEXT: s_cselect_b32 s8, s7, s10
+; VI-NEXT: s_and_b32 s7, s16, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[10:11], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s9, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s19, 16
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_lshr_b64 s[16:17], s[8:9], 16
+; VI-NEXT: s_bfe_u32 s8, s7, 0x10010
+; VI-NEXT: s_add_i32 s8, s8, s7
+; VI-NEXT: s_add_i32 s10, s8, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[8:9], vcc, exec
+; VI-NEXT: s_cselect_b32 s8, s7, s10
+; VI-NEXT: s_and_b32 s7, s19, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[10:11], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s9, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s18, 16
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[10:11], vcc, exec
+; VI-NEXT: s_cselect_b32 s10, s7, s9
+; VI-NEXT: s_and_b32 s7, s18, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[12:13], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s11, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s21, 16
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[18:19], s[10:11], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[10:11], vcc, exec
+; VI-NEXT: s_cselect_b32 s10, s7, s9
+; VI-NEXT: s_and_b32 s7, s21, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[12:13], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s11, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s20, 16
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[10:11], s[10:11], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[12:13], vcc, exec
+; VI-NEXT: s_cselect_b32 s12, s7, s9
+; VI-NEXT: s_and_b32 s7, s20, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s13, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s23, 16
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[20:21], s[12:13], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[12:13], vcc, exec
+; VI-NEXT: s_cselect_b32 s12, s7, s9
+; VI-NEXT: s_and_b32 s7, s23, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s13, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s22, 16
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[12:13], s[12:13], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: s_cselect_b32 s14, s7, s9
+; VI-NEXT: s_and_b32 s7, s22, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[22:23], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s15, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s25, 16
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[22:23], s[14:15], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: s_cselect_b32 s14, s7, s9
+; VI-NEXT: s_and_b32 s7, s25, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[40:41], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s15, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s24, 16
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[40:41], s[14:15], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: s_cselect_b32 s14, s7, s9
+; VI-NEXT: s_and_b32 s7, s24, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[24:25], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s15, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s27, 16
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[24:25], s[14:15], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: s_cselect_b32 s14, s7, s9
+; VI-NEXT: s_and_b32 s7, s27, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[42:43], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s15, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s26, 16
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[44:45], s[14:15], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: s_cselect_b32 s14, s7, s9
+; VI-NEXT: s_and_b32 s7, s26, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[26:27], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s15, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s29, 16
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[26:27], s[14:15], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: s_cselect_b32 s14, s7, s9
+; VI-NEXT: s_and_b32 s7, s29, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[42:43], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s15, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s28, 16
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[58:59], s[14:15], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: s_cselect_b32 s14, s7, s9
+; VI-NEXT: s_and_b32 s7, s28, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[28:29], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s15, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s5, 16
+; VI-NEXT: v_add_f32_e32 v26, s7, v25
+; VI-NEXT: v_readfirstlane_b32 s7, v26
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[28:29], s[14:15], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: s_cselect_b32 s14, s7, s9
; VI-NEXT: s_and_b32 s5, s5, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
-; VI-NEXT: v_add_f32_e32 v33, s5, v31
-; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
-; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
-; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
-; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v33
+; VI-NEXT: v_add_f32_e32 v26, s5, v25
+; VI-NEXT: v_readfirstlane_b32 s5, v26
+; VI-NEXT: s_bfe_u32 s7, s5, 0x10010
+; VI-NEXT: s_add_i32 s7, s7, s5
+; VI-NEXT: s_addk_i32 s7, 0x7fff
+; VI-NEXT: s_bitset1_b32 s5, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: s_and_b64 s[42:43], vcc, exec
+; VI-NEXT: s_cselect_b32 s5, s5, s7
+; VI-NEXT: s_lshr_b32 s15, s5, 16
; VI-NEXT: s_lshl_b32 s5, s4, 16
-; VI-NEXT: v_alignbit_b32 v32, v33, v32, 16
-; VI-NEXT: v_add_f32_e32 v33, s5, v31
-; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
-; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
+; VI-NEXT: v_add_f32_e32 v26, s5, v25
+; VI-NEXT: v_readfirstlane_b32 s5, v26
+; VI-NEXT: s_bfe_u32 s7, s5, 0x10010
+; VI-NEXT: s_add_i32 s7, s7, s5
+; VI-NEXT: s_lshr_b64 s[62:63], s[14:15], 16
+; VI-NEXT: s_addk_i32 s7, 0x7fff
+; VI-NEXT: s_bitset1_b32 s5, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: v_lshrrev_b64 v[23:24], 16, v[23:24]
+; VI-NEXT: s_cselect_b32 s14, s5, s7
; VI-NEXT: s_and_b32 s4, s4, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
-; VI-NEXT: v_add_f32_e32 v31, s4, v31
-; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
-; VI-NEXT: v_bfe_u32 v34, v31, 16, 1
-; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v31
-; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
-; VI-NEXT: v_or_b32_e32 v35, 0x400000, v31
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
-; VI-NEXT: v_cndmask_b32_e32 v31, v34, v35, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_alignbit_b32 v31, v31, v33, 16
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[29:30]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[27:28]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[25:26]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[21:22]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[17:18]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[15:16]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[13:14]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[11:12]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[9:10]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[7:8]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[5:6]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[3:4]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[1:2]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v32
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v32
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v32
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v31
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v31
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v30
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v30
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v30
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v29
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v29
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v28
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v28
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v28
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v27
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v26
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v26
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v25
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v25
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v24
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v24
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v24
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v23
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v22
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v22
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v21
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v21
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v20
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v24, v22
+; VI-NEXT: v_add_f32_e32 v25, s4, v25
+; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_readfirstlane_b32 s4, v25
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
+; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[23:24]
+; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[20:21]
+; VI-NEXT: v_mov_b32_e32 v21, v19
+; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[20:21]
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_mov_b32_e32 v18, v16
+; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[17:18]
+; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[14:15]
+; VI-NEXT: v_mov_b32_e32 v15, v13
+; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; VI-NEXT: s_bfe_u32 s5, s4, 0x10010
+; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[14:15]
+; VI-NEXT: v_lshrrev_b64 v[11:12], 16, v[11:12]
+; VI-NEXT: s_add_i32 s5, s5, s4
+; VI-NEXT: v_mov_b32_e32 v12, v10
+; VI-NEXT: s_add_i32 s7, s5, 0x7fff
+; VI-NEXT: s_or_b32 s9, s4, 0x400000
+; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[11:12]
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[8:9]
+; VI-NEXT: s_cselect_b32 s4, s9, s7
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b64 v[5:6], 16, v[5:6]
+; VI-NEXT: v_mov_b32_e32 v9, v7
+; VI-NEXT: s_lshr_b32 s15, s4, 16
+; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3]
+; VI-NEXT: v_mov_b32_e32 v6, v4
+; VI-NEXT: s_lshr_b64 s[4:5], s[14:15], 16
+; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[8:9]
+; VI-NEXT: v_mov_b32_e32 v3, v1
+; VI-NEXT: s_mov_b32 s27, s44
+; VI-NEXT: s_mov_b32 s29, s58
+; VI-NEXT: s_mov_b32 s5, s62
+; VI-NEXT: v_lshrrev_b64 v[30:31], 24, v[5:6]
+; VI-NEXT: s_mov_b32 s17, s6
+; VI-NEXT: s_mov_b32 s19, s8
+; VI-NEXT: s_mov_b32 s21, s10
+; VI-NEXT: s_mov_b32 s23, s12
+; VI-NEXT: s_mov_b32 s25, s40
+; VI-NEXT: s_lshr_b64 s[74:75], s[4:5], 24
+; VI-NEXT: s_lshr_b64 s[78:79], s[28:29], 24
+; VI-NEXT: s_lshr_b64 s[30:31], s[26:27], 24
+; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[31:32], 24, v[2:3]
+; VI-NEXT: s_lshr_b64 s[36:37], s[24:25], 24
+; VI-NEXT: s_lshr_b64 s[38:39], s[22:23], 24
+; VI-NEXT: s_lshr_b64 s[48:49], s[20:21], 24
+; VI-NEXT: s_lshr_b64 s[50:51], s[18:19], 24
+; VI-NEXT: s_lshr_b64 s[52:53], s[16:17], 24
+; VI-NEXT: s_lshr_b32 s11, s62, 24
+; VI-NEXT: s_lshr_b32 s13, s62, 16
+; VI-NEXT: s_lshr_b32 s14, s62, 8
+; VI-NEXT: s_lshr_b32 s15, s4, 16
+; VI-NEXT: s_lshr_b32 s17, s4, 8
+; VI-NEXT: s_lshr_b32 s19, s58, 24
+; VI-NEXT: s_lshr_b32 s21, s58, 16
+; VI-NEXT: s_lshr_b32 s23, s58, 8
+; VI-NEXT: s_lshr_b32 s25, s28, 16
+; VI-NEXT: s_lshr_b32 s27, s28, 8
+; VI-NEXT: s_lshr_b32 s29, s44, 24
+; VI-NEXT: s_lshr_b32 s41, s44, 16
+; VI-NEXT: s_lshr_b32 s42, s44, 8
+; VI-NEXT: s_lshr_b32 s43, s26, 16
+; VI-NEXT: s_lshr_b32 s45, s26, 8
+; VI-NEXT: s_lshr_b32 s46, s40, 24
+; VI-NEXT: s_lshr_b32 s47, s40, 16
+; VI-NEXT: s_lshr_b32 s56, s40, 8
+; VI-NEXT: s_lshr_b32 s57, s24, 16
+; VI-NEXT: s_lshr_b32 s59, s24, 8
+; VI-NEXT: s_lshr_b32 s60, s12, 24
+; VI-NEXT: s_lshr_b32 s61, s12, 16
+; VI-NEXT: s_lshr_b32 s63, s12, 8
+; VI-NEXT: s_lshr_b32 s72, s22, 16
+; VI-NEXT: s_lshr_b32 s73, s22, 8
+; VI-NEXT: s_lshr_b32 s75, s10, 24
+; VI-NEXT: s_lshr_b32 s76, s10, 16
+; VI-NEXT: s_lshr_b32 s77, s10, 8
+; VI-NEXT: s_lshr_b32 s79, s20, 16
+; VI-NEXT: s_lshr_b32 s88, s20, 8
+; VI-NEXT: s_lshr_b32 s89, s8, 24
+; VI-NEXT: s_lshr_b32 s90, s8, 16
+; VI-NEXT: s_lshr_b32 s91, s8, 8
+; VI-NEXT: s_lshr_b32 s31, s18, 16
+; VI-NEXT: s_lshr_b32 s34, s18, 8
+; VI-NEXT: s_lshr_b32 vcc_lo, s6, 24
+; VI-NEXT: s_lshr_b32 vcc_hi, s6, 16
+; VI-NEXT: s_lshr_b32 s35, s6, 8
+; VI-NEXT: s_lshr_b32 s9, s16, 16
+; VI-NEXT: s_lshr_b32 s7, s16, 8
+; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v22
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
+; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v22
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v23
+; VI-NEXT: v_lshrrev_b32_e32 v15, 8, v23
+; VI-NEXT: v_lshrrev_b32_e32 v18, 24, v19
+; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v19
+; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v19
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v20
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v20
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v19
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v18
-; VI-NEXT: v_lshrrev_b32_e32 v34, 24, v2
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v2
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v18
-; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v12
-; VI-NEXT: v_lshrrev_b32_e32 v35, 24, v8
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v2
-; VI-NEXT: v_lshrrev_b64 v[41:42], 24, v[23:24]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v17
-; VI-NEXT: v_lshrrev_b32_e32 v45, 24, v16
-; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v16
-; VI-NEXT: v_lshrrev_b32_e32 v56, 8, v13
-; VI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v51, 8, v12
-; VI-NEXT: v_lshrrev_b32_e32 v57, 16, v9
-; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v7
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v17
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v15
-; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v15
-; VI-NEXT: v_lshrrev_b32_e32 v43, 24, v14
-; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v14
-; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v14
-; VI-NEXT: v_lshrrev_b32_e32 v47, 16, v13
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v12
-; VI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v11
-; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v11
-; VI-NEXT: v_lshrrev_b32_e32 v44, 24, v10
+; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v20
+; VI-NEXT: v_lshrrev_b32_e32 v35, 24, v16
+; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v16
+; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v16
+; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v17
+; VI-NEXT: v_lshrrev_b32_e32 v39, 8, v17
+; VI-NEXT: v_lshrrev_b32_e32 v48, 24, v13
+; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
+; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v13
+; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v14
+; VI-NEXT: v_lshrrev_b32_e32 v52, 8, v14
+; VI-NEXT: v_lshrrev_b32_e32 v53, 24, v10
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v10
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v9
-; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v8
-; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v59, 24, v6
-; VI-NEXT: v_lshrrev_b32_e32 v58, 16, v6
-; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v6
-; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; VI-NEXT: v_lshrrev_b32_e32 v45, 8, v5
-; VI-NEXT: v_lshrrev_b32_e32 v42, 24, v4
-; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; VI-NEXT: v_lshrrev_b32_e32 v61, 8, v4
-; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; VI-NEXT: v_lshrrev_b32_e32 v49, 8, v3
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v1
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v10
+; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v11
+; VI-NEXT: v_lshrrev_b32_e32 v41, 8, v11
+; VI-NEXT: v_lshrrev_b32_e32 v42, 24, v7
+; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v7
+; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v7
+; VI-NEXT: v_lshrrev_b32_e32 v45, 16, v8
+; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v8
+; VI-NEXT: v_lshrrev_b32_e32 v47, 24, v4
+; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v4
+; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v4
+; VI-NEXT: v_lshrrev_b32_e32 v57, 16, v5
+; VI-NEXT: v_lshrrev_b32_e32 v59, 8, v5
+; VI-NEXT: v_lshrrev_b32_e32 v60, 24, v1
+; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v1
+; VI-NEXT: v_lshrrev_b32_e32 v26, 8, v1
+; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v27, 8, v2
; VI-NEXT: s_branch .LBB91_5
; VI-NEXT: .LBB91_3:
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr7
+; VI-NEXT: ; implicit-def: $sgpr9
+; VI-NEXT: ; implicit-def: $sgpr8
+; VI-NEXT: ; implicit-def: $sgpr11
+; VI-NEXT: ; implicit-def: $sgpr10
+; VI-NEXT: ; implicit-def: $sgpr13
+; VI-NEXT: ; implicit-def: $sgpr12
+; VI-NEXT: ; implicit-def: $sgpr41
+; VI-NEXT: ; implicit-def: $sgpr40
+; VI-NEXT: ; implicit-def: $sgpr45
+; VI-NEXT: ; implicit-def: $sgpr44
+; VI-NEXT: ; implicit-def: $sgpr59
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr71
-; VI-NEXT: ; implicit-def: $sgpr69
+; VI-NEXT: ; implicit-def: $sgpr47
+; VI-NEXT: ; implicit-def: $sgpr82
+; VI-NEXT: ; implicit-def: $sgpr83
+; VI-NEXT: ; implicit-def: $sgpr56
+; VI-NEXT: ; implicit-def: $sgpr57
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr72
+; VI-NEXT: ; implicit-def: $sgpr14
+; VI-NEXT: ; implicit-def: $sgpr15
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr78
+; VI-NEXT: ; implicit-def: $sgpr79
+; VI-NEXT: ; implicit-def: $sgpr73
+; VI-NEXT: ; implicit-def: $sgpr74
+; VI-NEXT: ; implicit-def: $sgpr75
+; VI-NEXT: ; implicit-def: $sgpr84
+; VI-NEXT: ; implicit-def: $sgpr85
+; VI-NEXT: ; implicit-def: $sgpr86
+; VI-NEXT: ; implicit-def: $sgpr42
+; VI-NEXT: ; implicit-def: $sgpr43
+; VI-NEXT: ; implicit-def: $sgpr87
+; VI-NEXT: ; implicit-def: $sgpr80
; VI-NEXT: ; implicit-def: $sgpr70
; VI-NEXT: ; implicit-def: $sgpr68
-; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: ; implicit-def: $sgpr66
; VI-NEXT: ; implicit-def: $sgpr64
-; VI-NEXT: ; implicit-def: $sgpr65
-; VI-NEXT: ; implicit-def: $sgpr55
; VI-NEXT: ; implicit-def: $sgpr54
-; VI-NEXT: ; implicit-def: $sgpr53
-; VI-NEXT: ; implicit-def: $sgpr51
; VI-NEXT: ; implicit-def: $sgpr52
; VI-NEXT: ; implicit-def: $sgpr50
-; VI-NEXT: ; implicit-def: $sgpr87
-; VI-NEXT: ; implicit-def: $sgpr86
-; VI-NEXT: ; implicit-def: $sgpr84
-; VI-NEXT: ; implicit-def: $sgpr85
-; VI-NEXT: ; implicit-def: $sgpr83
-; VI-NEXT: ; implicit-def: $sgpr82
-; VI-NEXT: ; implicit-def: $sgpr81
-; VI-NEXT: ; implicit-def: $sgpr80
-; VI-NEXT: ; implicit-def: $sgpr76
-; VI-NEXT: ; implicit-def: $sgpr74
-; VI-NEXT: ; implicit-def: $sgpr72
-; VI-NEXT: ; implicit-def: $sgpr62
-; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; kill: killed $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: v_writelane_b32 v61, s6, 0
+; VI-NEXT: v_writelane_b32 v61, s7, 1
+; VI-NEXT: v_writelane_b32 v61, s8, 2
+; VI-NEXT: v_writelane_b32 v61, s9, 3
+; VI-NEXT: v_writelane_b32 v61, s10, 4
+; VI-NEXT: v_writelane_b32 v61, s11, 5
+; VI-NEXT: v_writelane_b32 v61, s12, 6
+; VI-NEXT: v_writelane_b32 v61, s13, 7
+; VI-NEXT: v_writelane_b32 v61, s40, 8
+; VI-NEXT: v_writelane_b32 v61, s41, 9
+; VI-NEXT: v_writelane_b32 v61, s44, 10
+; VI-NEXT: v_writelane_b32 v61, s45, 11
+; VI-NEXT: v_writelane_b32 v61, s58, 12
+; VI-NEXT: v_writelane_b32 v61, s59, 13
+; VI-NEXT: v_writelane_b32 v61, s62, 14
+; VI-NEXT: v_writelane_b32 v61, s63, 15
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr8
+; VI-NEXT: ; implicit-def: $sgpr10
+; VI-NEXT: ; implicit-def: $sgpr12
+; VI-NEXT: ; implicit-def: $sgpr40
+; VI-NEXT: ; implicit-def: $sgpr44
; VI-NEXT: ; implicit-def: $sgpr58
-; VI-NEXT: ; implicit-def: $sgpr56
-; VI-NEXT: ; implicit-def: $sgpr48
-; VI-NEXT: ; implicit-def: $sgpr38
-; VI-NEXT: ; implicit-def: $sgpr36
-; VI-NEXT: ; implicit-def: $sgpr34
-; VI-NEXT: ; implicit-def: $sgpr30
-; VI-NEXT: ; implicit-def: $sgpr90
-; VI-NEXT: ; implicit-def: $sgpr88
-; VI-NEXT: ; implicit-def: $sgpr78
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; kill: killed $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr46
+; VI-NEXT: ; implicit-def: $sgpr62
; VI-NEXT: s_branch .LBB91_2
; VI-NEXT: .LBB91_4:
-; VI-NEXT: v_mov_b32_e32 v33, s71
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s69
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s70
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s68
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s67
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s86
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s83
-; VI-NEXT: v_mov_b32_e32 v31, s4
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s82
-; VI-NEXT: v_readlane_b32 s4, v62, 0
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 1
-; VI-NEXT: v_mov_b32_e32 v40, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 2
-; VI-NEXT: v_mov_b32_e32 v44, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 3
-; VI-NEXT: v_mov_b32_e32 v54, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 4
-; VI-NEXT: v_mov_b32_e32 v53, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 5
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 6
-; VI-NEXT: v_mov_b32_e32 v51, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 7
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 8
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 9
-; VI-NEXT: v_mov_b32_e32 v56, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 10
-; VI-NEXT: v_mov_b32_e32 v47, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 11
-; VI-NEXT: v_mov_b32_e32 v48, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 12
-; VI-NEXT: v_mov_b32_e32 v43, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 13
-; VI-NEXT: v_mov_b32_e32 v46, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 14
-; VI-NEXT: v_mov_b32_e32 v50, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 15
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 16
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 17
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 18
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v33, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 19
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 20
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 21
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 22
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 23
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 24
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 25
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 26
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 27
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 28
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 29
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 30
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 31
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 32
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 33
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 34
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 35
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 36
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 37
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 38
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 39
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 40
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 41
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 42
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 43
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 44
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 45
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 46
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 47
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 48
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 49
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 50
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 51
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 52
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 53
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 54
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 55
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 56
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_readlane_b32 s4, v62, 57
-; VI-NEXT: v_mov_b32_e32 v42, s54
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v55, s4
-; VI-NEXT: v_mov_b32_e32 v41, s46
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v41, s56
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v41, s58
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v41, s60
-; VI-NEXT: v_mov_b32_e32 v45, s72
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v45, s74
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v45, s76
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v45, s78
-; VI-NEXT: v_mov_b32_e32 v55, s88
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v36, s66
-; VI-NEXT: v_mov_b32_e32 v52, s64
-; VI-NEXT: v_mov_b32_e32 v55, v50
-; VI-NEXT: v_mov_b32_e32 v35, s30
-; VI-NEXT: v_mov_b32_e32 v59, s87
-; VI-NEXT: v_mov_b32_e32 v58, s34
-; VI-NEXT: v_mov_b32_e32 v45, s36
-; VI-NEXT: v_mov_b32_e32 v34, s38
-; VI-NEXT: v_mov_b32_e32 v1, s44
-; VI-NEXT: v_mov_b32_e32 v2, s45
-; VI-NEXT: v_mov_b32_e32 v3, s42
-; VI-NEXT: v_mov_b32_e32 v4, s43
-; VI-NEXT: v_mov_b32_e32 v5, s40
-; VI-NEXT: v_mov_b32_e32 v6, s41
-; VI-NEXT: v_mov_b32_e32 v7, s14
-; VI-NEXT: v_mov_b32_e32 v8, s15
-; VI-NEXT: v_mov_b32_e32 v9, s12
-; VI-NEXT: v_mov_b32_e32 v10, s13
-; VI-NEXT: v_mov_b32_e32 v11, s10
-; VI-NEXT: v_mov_b32_e32 v12, s11
-; VI-NEXT: v_mov_b32_e32 v13, s8
-; VI-NEXT: v_mov_b32_e32 v14, s9
-; VI-NEXT: v_mov_b32_e32 v15, s6
-; VI-NEXT: v_mov_b32_e32 v16, s7
-; VI-NEXT: v_mov_b32_e32 v17, s16
-; VI-NEXT: v_mov_b32_e32 v18, s17
-; VI-NEXT: v_mov_b32_e32 v19, s18
-; VI-NEXT: v_mov_b32_e32 v20, s19
-; VI-NEXT: v_mov_b32_e32 v21, s20
-; VI-NEXT: v_mov_b32_e32 v22, s21
-; VI-NEXT: v_mov_b32_e32 v23, s22
-; VI-NEXT: v_mov_b32_e32 v24, s23
-; VI-NEXT: v_mov_b32_e32 v25, s24
-; VI-NEXT: v_mov_b32_e32 v26, s25
-; VI-NEXT: v_mov_b32_e32 v27, s26
-; VI-NEXT: v_mov_b32_e32 v28, s27
-; VI-NEXT: v_mov_b32_e32 v29, s28
-; VI-NEXT: v_mov_b32_e32 v30, s29
-; VI-NEXT: v_mov_b32_e32 v32, s5
-; VI-NEXT: v_mov_b32_e32 v41, s62
-; VI-NEXT: v_mov_b32_e32 v57, s81
-; VI-NEXT: v_mov_b32_e32 v37, s84
-; VI-NEXT: v_mov_b32_e32 v60, s52
-; VI-NEXT: v_mov_b32_e32 v38, s51
-; VI-NEXT: v_mov_b32_e32 v61, s65
-; VI-NEXT: v_mov_b32_e32 v49, s66
-; VI-NEXT: v_mov_b32_e32 v39, s55
-; VI-NEXT: v_mov_b32_e32 v50, v46
-; VI-NEXT: v_mov_b32_e32 v46, v48
-; VI-NEXT: v_mov_b32_e32 v48, v47
-; VI-NEXT: v_mov_b32_e32 v47, v56
-; VI-NEXT: v_mov_b32_e32 v56, v51
-; VI-NEXT: v_mov_b32_e32 v51, s90
-; VI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v35, s85
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v34, s48
-; VI-NEXT: v_mov_b32_e32 v51, v53
-; VI-NEXT: v_mov_b32_e32 v53, v54
-; VI-NEXT: v_mov_b32_e32 v54, v40
-; VI-NEXT: v_mov_b32_e32 v40, s80
-; VI-NEXT: v_mov_b32_e32 v58, s50
-; VI-NEXT: v_mov_b32_e32 v45, s53
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v28, s50
+; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v28, s52
+; VI-NEXT: v_readlane_b32 s5, v61, 16
+; VI-NEXT: v_mov_b32_e32 v57, s5
+; VI-NEXT: v_readlane_b32 s5, v61, 17
+; VI-NEXT: v_mov_b32_e32 v59, s5
+; VI-NEXT: v_readlane_b32 s5, v61, 18
+; VI-NEXT: v_mov_b32_e32 v47, s5
+; VI-NEXT: v_readlane_b32 s5, v61, 19
+; VI-NEXT: v_mov_b32_e32 v56, s5
+; VI-NEXT: v_readlane_b32 s5, v61, 20
+; VI-NEXT: v_mov_b32_e32 v58, s5
+; VI-NEXT: v_readlane_b32 s5, v61, 21
+; VI-NEXT: v_mov_b32_e32 v25, s5
+; VI-NEXT: v_readlane_b32 s5, v61, 22
+; VI-NEXT: v_mov_b32_e32 v27, s5
+; VI-NEXT: v_readlane_b32 s5, v61, 23
+; VI-NEXT: v_mov_b32_e32 v38, s79
+; VI-NEXT: v_mov_b32_e32 v39, s78
+; VI-NEXT: v_mov_b32_e32 v35, s75
+; VI-NEXT: v_mov_b32_e32 v36, s74
+; VI-NEXT: v_mov_b32_e32 v60, s5
+; VI-NEXT: v_readlane_b32 s5, v61, 24
+; VI-NEXT: v_mov_b32_e32 v14, s30
+; VI-NEXT: v_mov_b32_e32 v13, s31
+; VI-NEXT: v_readlane_b32 s74, v61, 14
+; VI-NEXT: v_readlane_b32 s78, v61, 12
+; VI-NEXT: v_readlane_b32 s30, v61, 10
+; VI-NEXT: v_mov_b32_e32 v24, s5
+; VI-NEXT: v_readlane_b32 s5, v61, 25
+; VI-NEXT: v_mov_b32_e32 v8, s36
+; VI-NEXT: v_mov_b32_e32 v7, s37
+; VI-NEXT: v_mov_b32_e32 v5, s38
+; VI-NEXT: v_mov_b32_e32 v4, s39
+; VI-NEXT: v_mov_b32_e32 v2, s48
+; VI-NEXT: v_mov_b32_e32 v1, s49
+; VI-NEXT: v_readlane_b32 s75, v61, 15
+; VI-NEXT: v_readlane_b32 s79, v61, 13
+; VI-NEXT: v_readlane_b32 s31, v61, 11
+; VI-NEXT: v_readlane_b32 s36, v61, 8
+; VI-NEXT: v_readlane_b32 s38, v61, 6
+; VI-NEXT: v_readlane_b32 s48, v61, 4
+; VI-NEXT: v_readlane_b32 s50, v61, 2
+; VI-NEXT: v_readlane_b32 s52, v61, 0
+; VI-NEXT: v_mov_b32_e32 v12, s13
+; VI-NEXT: v_mov_b32_e32 v15, s11
+; VI-NEXT: v_mov_b32_e32 v3, s87
+; VI-NEXT: v_mov_b32_e32 v6, s43
+; VI-NEXT: v_mov_b32_e32 v9, s42
+; VI-NEXT: v_mov_b32_e32 v33, s9
+; VI-NEXT: v_mov_b32_e32 v34, s7
+; VI-NEXT: v_mov_b32_e32 v18, s86
+; VI-NEXT: v_mov_b32_e32 v21, s85
+; VI-NEXT: v_mov_b32_e32 v32, s84
+; VI-NEXT: v_mov_b32_e32 v37, s73
+; VI-NEXT: v_mov_b32_e32 v51, s72
+; VI-NEXT: v_mov_b32_e32 v52, s61
+; VI-NEXT: v_mov_b32_e32 v48, s60
+; VI-NEXT: v_mov_b32_e32 v49, s15
+; VI-NEXT: v_mov_b32_e32 v50, s14
+; VI-NEXT: v_mov_b32_e32 v40, s83
+; VI-NEXT: v_mov_b32_e32 v41, s82
+; VI-NEXT: v_mov_b32_e32 v53, s63
+; VI-NEXT: v_mov_b32_e32 v54, s57
+; VI-NEXT: v_mov_b32_e32 v55, s56
+; VI-NEXT: v_mov_b32_e32 v45, s59
+; VI-NEXT: v_mov_b32_e32 v46, s45
+; VI-NEXT: v_mov_b32_e32 v42, s41
+; VI-NEXT: v_mov_b32_e32 v43, s47
+; VI-NEXT: v_mov_b32_e32 v44, s46
+; VI-NEXT: v_mov_b32_e32 v26, s5
+; VI-NEXT: v_mov_b32_e32 v23, s76
+; VI-NEXT: v_mov_b32_e32 v22, s77
+; VI-NEXT: v_mov_b32_e32 v20, s88
+; VI-NEXT: v_mov_b32_e32 v19, s89
+; VI-NEXT: v_mov_b32_e32 v17, s90
+; VI-NEXT: v_mov_b32_e32 v16, s91
+; VI-NEXT: v_mov_b32_e32 v11, s34
+; VI-NEXT: v_mov_b32_e32 v10, s35
+; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v28, s54
+; VI-NEXT: v_mov_b32_e32 v30, s70
+; VI-NEXT: v_mov_b32_e32 v31, s80
+; VI-NEXT: v_readlane_b32 s11, v61, 26
+; VI-NEXT: v_readlane_b32 s13, v61, 27
+; VI-NEXT: v_readlane_b32 s14, v61, 28
+; VI-NEXT: v_readlane_b32 s15, v61, 29
+; VI-NEXT: v_readlane_b32 s17, v61, 30
+; VI-NEXT: v_readlane_b32 s19, v61, 31
+; VI-NEXT: v_readlane_b32 s21, v61, 32
+; VI-NEXT: v_readlane_b32 s23, v61, 33
+; VI-NEXT: v_readlane_b32 s25, v61, 34
+; VI-NEXT: v_readlane_b32 s27, v61, 35
+; VI-NEXT: v_readlane_b32 s29, v61, 36
+; VI-NEXT: v_readlane_b32 s41, v61, 37
+; VI-NEXT: v_readlane_b32 s42, v61, 38
+; VI-NEXT: v_readlane_b32 s43, v61, 39
+; VI-NEXT: v_readlane_b32 s45, v61, 40
+; VI-NEXT: v_readlane_b32 s46, v61, 41
+; VI-NEXT: v_readlane_b32 s47, v61, 42
+; VI-NEXT: v_readlane_b32 s56, v61, 43
+; VI-NEXT: v_readlane_b32 s57, v61, 44
+; VI-NEXT: v_readlane_b32 s59, v61, 45
+; VI-NEXT: v_readlane_b32 s60, v61, 46
+; VI-NEXT: v_readlane_b32 s61, v61, 47
+; VI-NEXT: v_readlane_b32 s63, v61, 48
+; VI-NEXT: v_readlane_b32 s72, v61, 49
+; VI-NEXT: v_readlane_b32 s73, v61, 50
+; VI-NEXT: v_readlane_b32 s75, v61, 51
+; VI-NEXT: v_readlane_b32 s76, v61, 52
+; VI-NEXT: v_readlane_b32 s77, v61, 53
+; VI-NEXT: v_readlane_b32 s79, v61, 54
+; VI-NEXT: v_readlane_b32 s88, v61, 55
+; VI-NEXT: v_readlane_b32 s89, v61, 56
+; VI-NEXT: v_readlane_b32 s90, v61, 57
+; VI-NEXT: v_readlane_b32 s91, v61, 58
+; VI-NEXT: v_readlane_b32 s31, v61, 59
+; VI-NEXT: v_readlane_b32 s34, v61, 60
+; VI-NEXT: v_readlane_b32 s37, v61, 9
+; VI-NEXT: v_readlane_b32 vcc_lo, v61, 61
+; VI-NEXT: v_readlane_b32 vcc_hi, v61, 62
+; VI-NEXT: v_readlane_b32 s35, v61, 63
+; VI-NEXT: v_readlane_b32 s9, v62, 0
+; VI-NEXT: v_readlane_b32 s7, v62, 1
+; VI-NEXT: v_readlane_b32 s39, v61, 7
+; VI-NEXT: v_readlane_b32 s49, v61, 5
+; VI-NEXT: v_readlane_b32 s51, v61, 3
+; VI-NEXT: v_readlane_b32 s53, v61, 1
+; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v28, s64
+; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v28, s66
+; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v28, s68
+; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; VI-NEXT: .LBB91_5: ; %end
-; VI-NEXT: v_lshlrev_b32_e32 v36, 8, v33
-; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
-; VI-NEXT: v_or_b32_sdwa v17, v17, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: s_and_b32 s5, s16, 0xff
+; VI-NEXT: s_lshl_b32 s7, s7, 8
+; VI-NEXT: s_or_b32 s5, s5, s7
+; VI-NEXT: s_and_b32 s7, s9, 0xff
+; VI-NEXT: s_lshl_b32 s9, s52, 8
+; VI-NEXT: s_or_b32 s7, s7, s9
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s7, s7, 16
+; VI-NEXT: s_or_b32 s5, s5, s7
+; VI-NEXT: v_mov_b32_e32 v28, s5
+; VI-NEXT: s_and_b32 s5, s6, 0xff
+; VI-NEXT: s_lshl_b32 s6, s35, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, vcc_hi, 0xff
+; VI-NEXT: s_lshl_b32 s7, vcc_lo, 8
+; VI-NEXT: s_or_b32 s6, s6, s7
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: v_mov_b32_e32 v29, s5
+; VI-NEXT: s_and_b32 s5, s18, 0xff
+; VI-NEXT: s_lshl_b32 s6, s34, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s31, 0xff
+; VI-NEXT: s_lshl_b32 s7, s50, 8
+; VI-NEXT: s_or_b32 s6, s6, s7
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: buffer_store_dword v28, v0, s[0:3], 0 offen
+; VI-NEXT: v_add_u32_e32 v28, vcc, 4, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v29, s5
+; VI-NEXT: s_and_b32 s5, s8, 0xff
+; VI-NEXT: s_lshl_b32 s6, s91, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s90, 0xff
+; VI-NEXT: s_lshl_b32 s7, s89, 8
+; VI-NEXT: s_or_b32 s6, s6, s7
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v28, vcc, 8, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v29, s5
+; VI-NEXT: s_and_b32 s5, s20, 0xff
+; VI-NEXT: s_lshl_b32 s6, s88, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s79, 0xff
+; VI-NEXT: s_lshl_b32 s7, s48, 8
+; VI-NEXT: s_or_b32 s6, s6, s7
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v28, vcc, 12, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v29, s5
+; VI-NEXT: s_and_b32 s5, s10, 0xff
+; VI-NEXT: s_lshl_b32 s6, s77, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s76, 0xff
+; VI-NEXT: s_lshl_b32 s7, s75, 8
+; VI-NEXT: s_or_b32 s6, s6, s7
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v28, vcc, 16, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v29, s5
+; VI-NEXT: s_and_b32 s5, s22, 0xff
+; VI-NEXT: s_lshl_b32 s6, s73, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s72, 0xff
+; VI-NEXT: s_lshl_b32 s7, s38, 8
+; VI-NEXT: s_or_b32 s6, s6, s7
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v28, vcc, 20, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v29, s5
+; VI-NEXT: s_and_b32 s5, s12, 0xff
+; VI-NEXT: s_lshl_b32 s6, s63, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s61, 0xff
+; VI-NEXT: s_lshl_b32 s7, s60, 8
+; VI-NEXT: s_or_b32 s6, s6, s7
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v28, vcc, 24, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v29, s5
+; VI-NEXT: s_and_b32 s5, s24, 0xff
+; VI-NEXT: s_lshl_b32 s6, s59, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s57, 0xff
+; VI-NEXT: s_lshl_b32 s7, s36, 8
+; VI-NEXT: s_or_b32 s6, s6, s7
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v28, vcc, 28, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v29, s5
+; VI-NEXT: s_and_b32 s5, s40, 0xff
+; VI-NEXT: s_lshl_b32 s6, s56, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s47, 0xff
+; VI-NEXT: s_lshl_b32 s7, s46, 8
+; VI-NEXT: s_or_b32 s6, s6, s7
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v28, vcc, 32, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v29, s5
+; VI-NEXT: s_and_b32 s5, s26, 0xff
+; VI-NEXT: s_lshl_b32 s6, s45, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s43, 0xff
+; VI-NEXT: s_lshl_b32 s7, s30, 8
+; VI-NEXT: s_or_b32 s6, s6, s7
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v28, vcc, 36, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v29, s5
+; VI-NEXT: s_and_b32 s5, s44, 0xff
+; VI-NEXT: s_lshl_b32 s6, s42, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s41, 0xff
+; VI-NEXT: s_lshl_b32 s7, s29, 8
+; VI-NEXT: s_or_b32 s6, s6, s7
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v28, vcc, 40, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v29, s5
+; VI-NEXT: s_and_b32 s5, s28, 0xff
+; VI-NEXT: s_lshl_b32 s6, s27, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s25, 0xff
+; VI-NEXT: s_lshl_b32 s7, s78, 8
+; VI-NEXT: s_or_b32 s6, s6, s7
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v28, vcc, 44, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v29, s5
+; VI-NEXT: s_and_b32 s5, s58, 0xff
+; VI-NEXT: s_lshl_b32 s6, s23, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s21, 0xff
+; VI-NEXT: s_lshl_b32 s7, s19, 8
+; VI-NEXT: s_or_b32 s6, s6, s7
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v28, vcc, 48, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v29, s5
+; VI-NEXT: s_and_b32 s4, s4, 0xff
+; VI-NEXT: s_lshl_b32 s5, s17, 8
+; VI-NEXT: s_or_b32 s4, s4, s5
+; VI-NEXT: s_and_b32 s5, s15, 0xff
+; VI-NEXT: s_lshl_b32 s6, s74, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s4, s4, 0xffff
+; VI-NEXT: s_lshl_b32 s5, s5, 16
+; VI-NEXT: v_add_u32_e32 v28, vcc, 52, v0
+; VI-NEXT: s_or_b32 s4, s4, s5
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v29, s4
+; VI-NEXT: s_and_b32 s4, s62, 0xff
+; VI-NEXT: s_lshl_b32 s5, s14, 8
+; VI-NEXT: s_or_b32 s4, s4, s5
+; VI-NEXT: s_and_b32 s5, s13, 0xff
+; VI-NEXT: s_lshl_b32 s6, s11, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v27, 8, v27
+; VI-NEXT: s_and_b32 s4, s4, 0xffff
+; VI-NEXT: s_lshl_b32 s5, s5, 16
+; VI-NEXT: v_or_b32_sdwa v2, v2, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v27, 8, v31
+; VI-NEXT: v_add_u32_e32 v28, vcc, 56, v0
+; VI-NEXT: s_or_b32 s4, s4, s5
+; VI-NEXT: v_or_b32_sdwa v25, v25, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: v_add_u32_e32 v28, vcc, 60, v0
+; VI-NEXT: v_mov_b32_e32 v29, s4
+; VI-NEXT: v_or_b32_sdwa v2, v2, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_add_u32_e32 v25, vcc, 64, v0
+; VI-NEXT: buffer_store_dword v29, v28, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v25, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v26
+; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v60
+; VI-NEXT: v_or_b32_sdwa v2, v24, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
+; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v59
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v30
+; VI-NEXT: v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v2, v57, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
+; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v58
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v47
+; VI-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v2, v56, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
+; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v46
+; VI-NEXT: v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_readlane_b32 s87, v63, 31
; VI-NEXT: v_readlane_b32 s86, v63, 30
; VI-NEXT: v_readlane_b32 s85, v63, 29
@@ -170192,393 +171387,121 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_readlane_b32 s34, v63, 2
; VI-NEXT: v_readlane_b32 s31, v63, 1
; VI-NEXT: v_readlane_b32 s30, v63, 0
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v36, 8, v33
-; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
-; VI-NEXT: v_or_b32_sdwa v18, v18, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v36, 8, v33
-; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v34, v33, v36 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v17, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v17, v33, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 4, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 8, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v17, v20, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 12, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v18, v21, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 16, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v17, v22, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 20, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v41
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v18, v23, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 24, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v17, v24, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 28, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v18, v25, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 32, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v17, v26, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 36, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v18, v27, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 40, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v17, v28, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 44, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v18, v29, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 48, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v17, v30, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 52, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v18, v31, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 56, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v17, v32, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v18, vcc, 60, v0
-; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v1, v1, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v17, vcc, 64, v0
-; VI-NEXT: buffer_store_dword v1, v17, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; VI-NEXT: v_or_b32_sdwa v2, v17, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v49
-; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; VI-NEXT: v_or_b32_sdwa v1, v52, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v61
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v42
-; VI-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v39, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v45
-; VI-NEXT: v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; VI-NEXT: v_or_b32_sdwa v2, v38, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; VI-NEXT: v_or_b32_sdwa v2, v45, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v60
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v59
-; VI-NEXT: v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v58, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v44
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v42
+; VI-NEXT: v_or_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v2, v43, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v41
+; VI-NEXT: v_or_b32_sdwa v1, v11, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; VI-NEXT: v_or_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v37, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; VI-NEXT: v_or_b32_sdwa v2, v40, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v35
-; VI-NEXT: v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v55
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v53
+; VI-NEXT: v_or_b32_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v2, v54, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v57
-; VI-NEXT: v_or_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v52
+; VI-NEXT: v_or_b32_sdwa v1, v14, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; VI-NEXT: v_or_b32_sdwa v2, v51, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v40
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v44
-; VI-NEXT: v_or_b32_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v54, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v50
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v48
+; VI-NEXT: v_or_b32_sdwa v1, v13, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v53
-; VI-NEXT: v_or_b32_sdwa v1, v11, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v39
+; VI-NEXT: v_or_b32_sdwa v1, v17, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; VI-NEXT: v_or_b32_sdwa v2, v51, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; VI-NEXT: v_or_b32_sdwa v2, v38, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; VI-NEXT: v_or_b32_sdwa v1, v12, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v56, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v37
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v35
+; VI-NEXT: v_or_b32_sdwa v1, v16, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v2, v36, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v34
+; VI-NEXT: v_or_b32_sdwa v1, v20, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; VI-NEXT: v_or_b32_sdwa v1, v13, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v47, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; VI-NEXT: v_or_b32_sdwa v2, v33, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v48
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v43
-; VI-NEXT: v_or_b32_sdwa v1, v14, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v46, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v32
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v18
+; VI-NEXT: v_or_b32_sdwa v1, v19, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v2, v21, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v50
-; VI-NEXT: v_or_b32_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v15
+; VI-NEXT: v_or_b32_sdwa v1, v23, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; VI-NEXT: v_or_b32_sdwa v2, v55, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; VI-NEXT: v_or_b32_sdwa v2, v12, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; VI-NEXT: v_or_b32_sdwa v1, v16, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v3
+; VI-NEXT: v_or_b32_sdwa v1, v22, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -224996,19 +225919,19 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; VI-NEXT: v_writelane_b32 v42, s31, 1
; VI-NEXT: v_mov_b32_e32 v31, v17
; VI-NEXT: v_mov_b32_e32 v30, v16
-; VI-NEXT: v_mov_b32_e32 v29, v15
+; VI-NEXT: v_mov_b32_e32 v32, v15
+; VI-NEXT: v_mov_b32_e32 v33, v13
+; VI-NEXT: v_mov_b32_e32 v34, v11
+; VI-NEXT: v_mov_b32_e32 v35, v9
+; VI-NEXT: v_mov_b32_e32 v36, v7
+; VI-NEXT: v_mov_b32_e32 v37, v5
+; VI-NEXT: v_mov_b32_e32 v38, v3
; VI-NEXT: v_mov_b32_e32 v28, v14
-; VI-NEXT: v_mov_b32_e32 v27, v13
; VI-NEXT: v_mov_b32_e32 v26, v12
-; VI-NEXT: v_mov_b32_e32 v25, v11
; VI-NEXT: v_mov_b32_e32 v24, v10
-; VI-NEXT: v_mov_b32_e32 v23, v9
; VI-NEXT: v_mov_b32_e32 v22, v8
-; VI-NEXT: v_mov_b32_e32 v21, v7
; VI-NEXT: v_mov_b32_e32 v20, v6
-; VI-NEXT: v_mov_b32_e32 v19, v5
-; VI-NEXT: v_mov_b32_e32 v32, v4
-; VI-NEXT: v_mov_b32_e32 v17, v3
+; VI-NEXT: v_mov_b32_e32 v48, v4
; VI-NEXT: v_mov_b32_e32 v16, v2
; VI-NEXT: v_readfirstlane_b32 s30, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
@@ -225019,583 +225942,595 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB101_4
; VI-NEXT: .LBB101_2: ; %cmp.true
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: s_lshl_b32 s4, s30, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
+; VI-NEXT: v_mov_b32_e32 v17, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: s_lshl_b32 s4, s28, 16
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s30, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_add_f32_e32 v2, s4, v17
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: s_lshl_b32 s4, s30, 16
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_lshl_b32 s4, s31, 16
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
+; VI-NEXT: v_add_f32_e32 v2, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; VI-NEXT: v_bfe_u32 v4, v2, 16, 1
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2
+; VI-NEXT: s_and_b32 s4, s26, 0xffff0000
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_and_b32 s4, s31, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v0
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s29, 16
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_alignbit_b32 v14, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_alignbit_b32 v15, v4, v3, 16
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s28, 16
-; VI-NEXT: v_alignbit_b32 v13, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s27, 16
-; VI-NEXT: v_alignbit_b32 v12, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s27, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
; VI-NEXT: s_lshl_b32 s4, s26, 16
-; VI-NEXT: v_alignbit_b32 v11, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s26, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s25, 16
-; VI-NEXT: v_alignbit_b32 v10, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s25, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s24, 16
-; VI-NEXT: v_alignbit_b32 v9, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[2:3]
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_and_b32 s4, s24, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s23, 16
-; VI-NEXT: v_alignbit_b32 v8, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s22, 16
-; VI-NEXT: v_alignbit_b32 v7, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: s_lshl_b32 s4, s24, 16
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_alignbit_b32 v6, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: s_lshl_b32 s4, s22, 16
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_alignbit_b32 v5, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_alignbit_b32 v4, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: s_lshl_b32 s4, s18, 16
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: s_lshl_b32 s4, s16, 16
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v1, s4, v17
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: s_lshl_b32 s4, s17, 16
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v17
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v1
+; VI-NEXT: v_add_f32_e32 v1, s4, v17
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v18, v5, v7, vcc
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v18, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v18, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v18, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v2
-; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
-; VI-NEXT: v_or_b32_e32 v33, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v18, v33, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v18, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v1
+; VI-NEXT: s_lshl_b32 s4, s19, 16
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v17
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v49, v5, v7, vcc
+; VI-NEXT: v_add_f32_e32 v5, s4, v17
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: s_lshl_b32 s4, s21, 16
+; VI-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc
+; VI-NEXT: v_add_f32_e32 v7, s4, v17
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19]
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v5
+; VI-NEXT: v_add_f32_e32 v5, s4, v17
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v1
+; VI-NEXT: v_mov_b32_e32 v1, v18
+; VI-NEXT: v_cndmask_b32_e32 v18, v9, v11, vcc
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: s_lshl_b32 s4, s23, 16
+; VI-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc
+; VI-NEXT: v_add_f32_e32 v7, s4, v17
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50]
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: s_and_b32 s4, s25, 0xffff0000
+; VI-NEXT: v_mov_b32_e32 v3, v49
+; VI-NEXT: v_cndmask_b32_e32 v49, v9, v11, vcc
+; VI-NEXT: v_add_f32_e32 v9, s4, v17
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: s_lshl_b32 s4, s25, 16
+; VI-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc
+; VI-NEXT: v_add_f32_e32 v11, s4, v17
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19]
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
+; VI-NEXT: s_and_b32 s4, s27, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v9
+; VI-NEXT: v_add_f32_e32 v9, s4, v17
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
+; VI-NEXT: v_mov_b32_e32 v5, v18
+; VI-NEXT: v_cndmask_b32_e32 v18, v13, v15, vcc
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: s_lshl_b32 s4, s27, 16
+; VI-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc
+; VI-NEXT: v_add_f32_e32 v11, s4, v17
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
+; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50]
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
+; VI-NEXT: v_mov_b32_e32 v7, v49
+; VI-NEXT: v_cndmask_b32_e32 v49, v13, v15, vcc
+; VI-NEXT: v_add_f32_e32 v13, s4, v17
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19]
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v9
+; VI-NEXT: v_mov_b32_e32 v9, v18
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: s_lshl_b32 s4, s29, 16
+; VI-NEXT: v_cndmask_b32_e32 v13, v15, v18, vcc
+; VI-NEXT: v_add_f32_e32 v15, s4, v17
+; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
-; VI-NEXT: v_or_b32_e32 v33, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v18, v33, vcc
-; VI-NEXT: v_add_f32_e32 v18, s4, v0
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v18, v1, 16
-; VI-NEXT: v_add_f32_e32 v18, s4, v0
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v16
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: s_and_b32 s4, s31, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v13
+; VI-NEXT: v_add_f32_e32 v13, s4, v17
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19]
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: s_lshl_b32 s4, s31, 16
+; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc
+; VI-NEXT: v_add_f32_e32 v15, s4, v17
+; VI-NEXT: v_bfe_u32 v17, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v15
+; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50]
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_mov_b32_e32 v11, v49
+; VI-NEXT: v_cndmask_b32_e32 v49, v17, v19, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v16
; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v16
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v16
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v13
+; VI-NEXT: v_mov_b32_e32 v13, v18
+; VI-NEXT: v_bfe_u32 v18, v16, 16, 1
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v16
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_cndmask_b32_e32 v16, v33, v34, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v17
-; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
-; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
-; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
-; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
-; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
-; VI-NEXT: v_bfe_u32 v34, v17, 16, 1
-; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v17
-; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
-; VI-NEXT: v_or_b32_e32 v35, 0x400000, v17
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
-; VI-NEXT: v_cndmask_b32_e32 v17, v34, v35, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v32
-; VI-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; VI-NEXT: v_bfe_u32 v35, v34, 16, 1
-; VI-NEXT: v_add_u32_e32 v35, vcc, v35, v34
-; VI-NEXT: v_add_u32_e32 v35, vcc, 0x7fff, v35
-; VI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
-; VI-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v34, v34
-; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; VI-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc
-; VI-NEXT: v_bfe_u32 v35, v32, 16, 1
-; VI-NEXT: v_add_u32_e32 v35, vcc, v35, v32
-; VI-NEXT: v_add_u32_e32 v35, vcc, 0x7fff, v35
-; VI-NEXT: v_or_b32_e32 v36, 0x400000, v32
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
-; VI-NEXT: v_cndmask_b32_e32 v32, v35, v36, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v19
-; VI-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; VI-NEXT: v_bfe_u32 v36, v35, 16, 1
-; VI-NEXT: v_add_u32_e32 v36, vcc, v36, v35
-; VI-NEXT: v_add_u32_e32 v36, vcc, 0x7fff, v36
-; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; VI-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v35, v35
+; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v17
+; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc
+; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v16
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
+; VI-NEXT: v_cndmask_b32_e32 v16, v17, v19, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v18
+; VI-NEXT: v_and_b32_e32 v18, 0xffff0000, v38
+; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; VI-NEXT: v_bfe_u32 v19, v18, 16, 1
+; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v18
+; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19
+; VI-NEXT: v_or_b32_e32 v21, 0x400000, v18
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_cndmask_b32_e32 v18, v19, v21, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v38
; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; VI-NEXT: v_cndmask_b32_e32 v35, v36, v37, vcc
-; VI-NEXT: v_bfe_u32 v36, v19, 16, 1
-; VI-NEXT: v_add_u32_e32 v36, vcc, v36, v19
-; VI-NEXT: v_add_u32_e32 v36, vcc, 0x7fff, v36
-; VI-NEXT: v_or_b32_e32 v37, 0x400000, v19
+; VI-NEXT: v_bfe_u32 v21, v19, 16, 1
+; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v19
+; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
+; VI-NEXT: v_or_b32_e32 v23, 0x400000, v19
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
-; VI-NEXT: v_cndmask_b32_e32 v19, v36, v37, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v20
-; VI-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; VI-NEXT: v_bfe_u32 v37, v36, 16, 1
-; VI-NEXT: v_add_u32_e32 v37, vcc, v37, v36
-; VI-NEXT: v_add_u32_e32 v37, vcc, 0x7fff, v37
+; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v48
+; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
+; VI-NEXT: v_cndmask_b32_e32 v38, v21, v23, vcc
+; VI-NEXT: v_bfe_u32 v21, v19, 16, 1
+; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v19
+; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v48
+; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
+; VI-NEXT: v_or_b32_e32 v23, 0x400000, v19
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
+; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; VI-NEXT: v_cndmask_b32_e32 v19, v21, v23, vcc
+; VI-NEXT: v_bfe_u32 v21, v18, 16, 1
+; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v18
+; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
+; VI-NEXT: v_or_b32_e32 v23, 0x400000, v18
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_cndmask_b32_e32 v18, v21, v23, vcc
+; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v37
+; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; VI-NEXT: v_bfe_u32 v23, v21, 16, 1
+; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v21
+; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23
+; VI-NEXT: v_or_b32_e32 v25, 0x400000, v21
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
+; VI-NEXT: v_cndmask_b32_e32 v21, v23, v25, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v37
+; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50]
+; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; VI-NEXT: v_bfe_u32 v25, v23, 16, 1
+; VI-NEXT: v_mov_b32_e32 v15, v49
+; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v23
+; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v21
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v20
; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; VI-NEXT: v_or_b32_e32 v38, 0x400000, v36
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v36, v36
+; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; VI-NEXT: v_cndmask_b32_e32 v36, v37, v38, vcc
-; VI-NEXT: v_bfe_u32 v37, v20, 16, 1
-; VI-NEXT: v_add_u32_e32 v37, vcc, v37, v20
-; VI-NEXT: v_add_u32_e32 v37, vcc, 0x7fff, v37
-; VI-NEXT: v_or_b32_e32 v38, 0x400000, v20
+; VI-NEXT: v_or_b32_e32 v27, 0x400000, v23
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
+; VI-NEXT: v_bfe_u32 v23, v20, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v48, v25, v27, vcc
+; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v20
+; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23
+; VI-NEXT: v_or_b32_e32 v25, 0x400000, v20
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
-; VI-NEXT: v_cndmask_b32_e32 v20, v37, v38, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v21
-; VI-NEXT: v_add_f32_e32 v37, 0x40c00000, v37
-; VI-NEXT: v_bfe_u32 v38, v37, 16, 1
-; VI-NEXT: v_add_u32_e32 v38, vcc, v38, v37
-; VI-NEXT: v_add_u32_e32 v38, vcc, 0x7fff, v38
-; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; VI-NEXT: v_or_b32_e32 v39, 0x400000, v37
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v37, v37
-; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; VI-NEXT: v_cndmask_b32_e32 v37, v38, v39, vcc
-; VI-NEXT: v_bfe_u32 v38, v21, 16, 1
-; VI-NEXT: v_add_u32_e32 v38, vcc, v38, v21
-; VI-NEXT: v_add_u32_e32 v38, vcc, 0x7fff, v38
-; VI-NEXT: v_or_b32_e32 v39, 0x400000, v21
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
-; VI-NEXT: v_cndmask_b32_e32 v21, v38, v39, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v22
-; VI-NEXT: v_add_f32_e32 v38, 0x40c00000, v38
-; VI-NEXT: v_bfe_u32 v39, v38, 16, 1
-; VI-NEXT: v_add_u32_e32 v39, vcc, v39, v38
-; VI-NEXT: v_add_u32_e32 v39, vcc, 0x7fff, v39
+; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v21
+; VI-NEXT: v_bfe_u32 v21, v20, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc
+; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v20
+; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
+; VI-NEXT: v_or_b32_e32 v25, 0x400000, v20
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
+; VI-NEXT: v_cndmask_b32_e32 v20, v21, v25, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v23
+; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v36
+; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; VI-NEXT: v_bfe_u32 v25, v23, 16, 1
+; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v23
+; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
+; VI-NEXT: v_or_b32_e32 v27, 0x400000, v23
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
+; VI-NEXT: v_cndmask_b32_e32 v23, v25, v27, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v36
+; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; VI-NEXT: v_bfe_u32 v27, v25, 16, 1
+; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v25
+; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v22
; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; VI-NEXT: v_or_b32_e32 v48, 0x400000, v38
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v38, v38
+; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27
; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; VI-NEXT: v_cndmask_b32_e32 v38, v39, v48, vcc
-; VI-NEXT: v_bfe_u32 v39, v22, 16, 1
-; VI-NEXT: v_add_u32_e32 v39, vcc, v39, v22
-; VI-NEXT: v_add_u32_e32 v39, vcc, 0x7fff, v39
-; VI-NEXT: v_or_b32_e32 v48, 0x400000, v22
+; VI-NEXT: v_or_b32_e32 v29, 0x400000, v25
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
+; VI-NEXT: v_bfe_u32 v25, v22, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v36, v27, v29, vcc
+; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v22
+; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
+; VI-NEXT: v_or_b32_e32 v27, 0x400000, v22
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
-; VI-NEXT: v_cndmask_b32_e32 v22, v39, v48, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v23
-; VI-NEXT: v_add_f32_e32 v39, 0x40c00000, v39
-; VI-NEXT: v_bfe_u32 v48, v39, 16, 1
-; VI-NEXT: v_add_u32_e32 v48, vcc, v48, v39
-; VI-NEXT: v_add_u32_e32 v48, vcc, 0x7fff, v48
-; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; VI-NEXT: v_or_b32_e32 v49, 0x400000, v39
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v39, v39
-; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; VI-NEXT: v_cndmask_b32_e32 v39, v48, v49, vcc
-; VI-NEXT: v_bfe_u32 v48, v23, 16, 1
-; VI-NEXT: v_add_u32_e32 v48, vcc, v48, v23
-; VI-NEXT: v_add_u32_e32 v48, vcc, 0x7fff, v48
-; VI-NEXT: v_or_b32_e32 v49, 0x400000, v23
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
-; VI-NEXT: v_cndmask_b32_e32 v23, v48, v49, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v24
-; VI-NEXT: v_add_f32_e32 v48, 0x40c00000, v48
-; VI-NEXT: v_bfe_u32 v49, v48, 16, 1
-; VI-NEXT: v_add_u32_e32 v49, vcc, v49, v48
-; VI-NEXT: v_add_u32_e32 v49, vcc, 0x7fff, v49
+; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v23
+; VI-NEXT: v_bfe_u32 v23, v22, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v25, v25, v27, vcc
+; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v22
+; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23
+; VI-NEXT: v_or_b32_e32 v27, 0x400000, v22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
+; VI-NEXT: v_cndmask_b32_e32 v22, v23, v27, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v25
+; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v35
+; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; VI-NEXT: v_bfe_u32 v27, v25, 16, 1
+; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v25
+; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27
+; VI-NEXT: v_or_b32_e32 v29, 0x400000, v25
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
+; VI-NEXT: v_cndmask_b32_e32 v25, v27, v29, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v35
+; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
+; VI-NEXT: v_bfe_u32 v29, v27, 16, 1
+; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v27
+; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v25
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v24
; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; VI-NEXT: v_or_b32_e32 v50, 0x400000, v48
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v48, v48
+; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29
; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; VI-NEXT: v_cndmask_b32_e32 v48, v49, v50, vcc
-; VI-NEXT: v_bfe_u32 v49, v24, 16, 1
-; VI-NEXT: v_add_u32_e32 v49, vcc, v49, v24
-; VI-NEXT: v_add_u32_e32 v49, vcc, 0x7fff, v49
-; VI-NEXT: v_or_b32_e32 v50, 0x400000, v24
+; VI-NEXT: v_or_b32_e32 v35, 0x400000, v27
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
+; VI-NEXT: v_bfe_u32 v27, v24, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v50, v29, v35, vcc
+; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v24
+; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27
+; VI-NEXT: v_or_b32_e32 v29, 0x400000, v24
; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
-; VI-NEXT: v_cndmask_b32_e32 v24, v49, v50, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v25
-; VI-NEXT: v_add_f32_e32 v49, 0x40c00000, v49
-; VI-NEXT: v_bfe_u32 v50, v49, 16, 1
-; VI-NEXT: v_add_u32_e32 v50, vcc, v50, v49
-; VI-NEXT: v_add_u32_e32 v50, vcc, 0x7fff, v50
-; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; VI-NEXT: v_or_b32_e32 v51, 0x400000, v49
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v49, v49
-; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; VI-NEXT: v_cndmask_b32_e32 v49, v50, v51, vcc
-; VI-NEXT: v_bfe_u32 v50, v25, 16, 1
-; VI-NEXT: v_add_u32_e32 v50, vcc, v50, v25
-; VI-NEXT: v_add_u32_e32 v50, vcc, 0x7fff, v50
-; VI-NEXT: v_or_b32_e32 v51, 0x400000, v25
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
-; VI-NEXT: v_cndmask_b32_e32 v25, v50, v51, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v26
-; VI-NEXT: v_add_f32_e32 v50, 0x40c00000, v50
-; VI-NEXT: v_bfe_u32 v51, v50, 16, 1
-; VI-NEXT: v_add_u32_e32 v51, vcc, v51, v50
-; VI-NEXT: v_add_u32_e32 v51, vcc, 0x7fff, v51
+; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v25
+; VI-NEXT: v_bfe_u32 v25, v24, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v27, v27, v29, vcc
+; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v24
+; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
+; VI-NEXT: v_or_b32_e32 v29, 0x400000, v24
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
+; VI-NEXT: v_cndmask_b32_e32 v24, v25, v29, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v27
+; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v34
+; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
+; VI-NEXT: v_bfe_u32 v29, v27, 16, 1
+; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v27
+; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29
+; VI-NEXT: v_or_b32_e32 v35, 0x400000, v27
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
+; VI-NEXT: v_cndmask_b32_e32 v27, v29, v35, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v34
+; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; VI-NEXT: v_bfe_u32 v34, v29, 16, 1
+; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v29
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
+; VI-NEXT: v_or_b32_e32 v35, 0x400000, v29
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
+; VI-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v27
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v26
; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; VI-NEXT: v_or_b32_e32 v52, 0x400000, v50
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v50, v50
; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; VI-NEXT: v_cndmask_b32_e32 v50, v51, v52, vcc
-; VI-NEXT: v_bfe_u32 v51, v26, 16, 1
-; VI-NEXT: v_add_u32_e32 v51, vcc, v51, v26
-; VI-NEXT: v_add_u32_e32 v51, vcc, 0x7fff, v51
+; VI-NEXT: v_bfe_u32 v29, v26, 16, 1
+; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v26
+; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29
; VI-NEXT: v_or_b32_e32 v52, 0x400000, v26
; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
-; VI-NEXT: v_cndmask_b32_e32 v26, v51, v52, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v27
-; VI-NEXT: v_add_f32_e32 v51, 0x40c00000, v51
-; VI-NEXT: v_bfe_u32 v52, v51, 16, 1
-; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v51
+; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v27
+; VI-NEXT: v_bfe_u32 v27, v26, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v29, v29, v52, vcc
+; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v26
+; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27
+; VI-NEXT: v_or_b32_e32 v52, 0x400000, v26
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: v_cndmask_b32_e32 v26, v27, v52, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v29
+; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v33
+; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; VI-NEXT: v_bfe_u32 v52, v29, 16, 1
+; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v29
; VI-NEXT: v_add_u32_e32 v52, vcc, 0x7fff, v52
-; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; VI-NEXT: v_or_b32_e32 v53, 0x400000, v51
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v51, v51
-; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; VI-NEXT: v_cndmask_b32_e32 v51, v52, v53, vcc
-; VI-NEXT: v_bfe_u32 v52, v27, 16, 1
-; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v27
+; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; VI-NEXT: v_or_b32_e32 v53, 0x400000, v29
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
+; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
+; VI-NEXT: v_cndmask_b32_e32 v29, v52, v53, vcc
+; VI-NEXT: v_bfe_u32 v52, v33, 16, 1
+; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v33
; VI-NEXT: v_add_u32_e32 v52, vcc, 0x7fff, v52
-; VI-NEXT: v_or_b32_e32 v53, 0x400000, v27
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
-; VI-NEXT: v_cndmask_b32_e32 v27, v52, v53, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v28
-; VI-NEXT: v_add_f32_e32 v52, 0x40c00000, v52
-; VI-NEXT: v_bfe_u32 v53, v52, 16, 1
-; VI-NEXT: v_add_u32_e32 v53, vcc, v53, v52
-; VI-NEXT: v_add_u32_e32 v53, vcc, 0x7fff, v53
+; VI-NEXT: v_or_b32_e32 v53, 0x400000, v33
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
+; VI-NEXT: v_cndmask_b32_e32 v52, v52, v53, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v28
; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; VI-NEXT: v_or_b32_e32 v54, 0x400000, v52
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v52, v52
; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; VI-NEXT: v_cndmask_b32_e32 v52, v53, v54, vcc
-; VI-NEXT: v_bfe_u32 v53, v28, 16, 1
-; VI-NEXT: v_add_u32_e32 v53, vcc, v53, v28
-; VI-NEXT: v_add_u32_e32 v53, vcc, 0x7fff, v53
+; VI-NEXT: v_bfe_u32 v33, v28, 16, 1
+; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v28
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v54, 0x400000, v28
; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
-; VI-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v29
-; VI-NEXT: v_add_f32_e32 v53, 0x40c00000, v53
-; VI-NEXT: v_bfe_u32 v54, v53, 16, 1
-; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v53
+; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v29
+; VI-NEXT: v_bfe_u32 v29, v28, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v33, v33, v54, vcc
+; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v28
+; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29
+; VI-NEXT: v_or_b32_e32 v54, 0x400000, v28
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
+; VI-NEXT: v_cndmask_b32_e32 v28, v29, v54, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v33
+; VI-NEXT: v_and_b32_e32 v33, 0xffff0000, v32
+; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
+; VI-NEXT: v_bfe_u32 v54, v33, 16, 1
+; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v33
; VI-NEXT: v_add_u32_e32 v54, vcc, 0x7fff, v54
-; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; VI-NEXT: v_or_b32_e32 v55, 0x400000, v53
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v53, v53
-; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; VI-NEXT: v_cndmask_b32_e32 v53, v54, v55, vcc
-; VI-NEXT: v_bfe_u32 v54, v29, 16, 1
-; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v29
+; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; VI-NEXT: v_or_b32_e32 v55, 0x400000, v33
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
+; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
+; VI-NEXT: v_cndmask_b32_e32 v33, v54, v55, vcc
+; VI-NEXT: v_bfe_u32 v54, v32, 16, 1
+; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v32
; VI-NEXT: v_add_u32_e32 v54, vcc, 0x7fff, v54
-; VI-NEXT: v_or_b32_e32 v55, 0x400000, v29
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
-; VI-NEXT: v_cndmask_b32_e32 v29, v54, v55, vcc
+; VI-NEXT: v_or_b32_e32 v55, 0x400000, v32
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
+; VI-NEXT: v_cndmask_b32_e32 v32, v54, v55, vcc
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v30
-; VI-NEXT: v_add_f32_e32 v54, 0x40c00000, v54
-; VI-NEXT: v_bfe_u32 v55, v54, 16, 1
-; VI-NEXT: v_add_u32_e32 v55, vcc, v55, v54
-; VI-NEXT: v_add_u32_e32 v55, vcc, 0x7fff, v55
; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; VI-NEXT: v_or_b32_e32 v40, 0x400000, v54
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v54, v54
; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; VI-NEXT: v_cndmask_b32_e32 v54, v55, v40, vcc
; VI-NEXT: v_bfe_u32 v55, v30, 16, 1
; VI-NEXT: v_add_u32_e32 v55, vcc, v55, v30
; VI-NEXT: v_add_u32_e32 v55, vcc, 0x7fff, v55
; VI-NEXT: v_or_b32_e32 v40, 0x400000, v30
; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
+; VI-NEXT: v_add_f32_e32 v54, 0x40c00000, v54
; VI-NEXT: v_cndmask_b32_e32 v30, v55, v40, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v31
-; VI-NEXT: v_add_f32_e32 v55, 0x40c00000, v55
-; VI-NEXT: v_bfe_u32 v40, v55, 16, 1
-; VI-NEXT: v_add_u32_e32 v40, vcc, v40, v55
-; VI-NEXT: v_add_u32_e32 v40, vcc, 0x7fff, v40
-; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; VI-NEXT: v_or_b32_e32 v41, 0x400000, v55
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v55, v55
-; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; VI-NEXT: v_cndmask_b32_e32 v55, v40, v41, vcc
-; VI-NEXT: v_bfe_u32 v40, v31, 16, 1
-; VI-NEXT: v_add_u32_e32 v40, vcc, v40, v31
+; VI-NEXT: v_bfe_u32 v55, v54, 16, 1
+; VI-NEXT: v_add_u32_e32 v55, vcc, v55, v54
+; VI-NEXT: v_add_u32_e32 v55, vcc, 0x7fff, v55
+; VI-NEXT: v_or_b32_e32 v40, 0x400000, v54
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v54, v54
+; VI-NEXT: v_cndmask_b32_e32 v54, v55, v40, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v30
+; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v31
+; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; VI-NEXT: v_bfe_u32 v40, v30, 16, 1
+; VI-NEXT: v_add_u32_e32 v40, vcc, v40, v30
; VI-NEXT: v_add_u32_e32 v40, vcc, 0x7fff, v40
-; VI-NEXT: v_or_b32_e32 v41, 0x400000, v31
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
-; VI-NEXT: v_cndmask_b32_e32 v31, v40, v41, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; VI-NEXT: v_or_b32_e32 v41, 0x400000, v30
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v31
+; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; VI-NEXT: v_bfe_u32 v31, v30, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[48:49]
+; VI-NEXT: v_cndmask_b32_e32 v40, v40, v41, vcc
+; VI-NEXT: v_add_u32_e32 v31, vcc, v31, v30
+; VI-NEXT: v_lshrrev_b64 v[36:37], 16, v[36:37]
+; VI-NEXT: v_add_u32_e32 v31, vcc, 0x7fff, v31
+; VI-NEXT: v_mov_b32_e32 v37, v48
+; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[50:51]
+; VI-NEXT: v_or_b32_e32 v41, 0x400000, v30
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
+; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[34:35]
+; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v33
+; VI-NEXT: v_cndmask_b32_e32 v30, v31, v41, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v40
+; VI-NEXT: v_mov_b32_e32 v35, v48
+; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[52:53]
; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_alignbit_b32 v31, v31, v55, 16
-; VI-NEXT: v_alignbit_b32 v30, v30, v54, 16
-; VI-NEXT: v_alignbit_b32 v29, v29, v53, 16
-; VI-NEXT: v_alignbit_b32 v28, v28, v52, 16
-; VI-NEXT: v_alignbit_b32 v27, v27, v51, 16
-; VI-NEXT: v_alignbit_b32 v26, v26, v50, 16
-; VI-NEXT: v_alignbit_b32 v25, v25, v49, 16
-; VI-NEXT: v_alignbit_b32 v24, v24, v48, 16
-; VI-NEXT: v_alignbit_b32 v23, v23, v39, 16
-; VI-NEXT: v_alignbit_b32 v22, v22, v38, 16
-; VI-NEXT: v_alignbit_b32 v21, v21, v37, 16
-; VI-NEXT: v_alignbit_b32 v20, v20, v36, 16
-; VI-NEXT: v_alignbit_b32 v19, v19, v35, 16
-; VI-NEXT: v_alignbit_b32 v32, v32, v34, 16
-; VI-NEXT: v_alignbit_b32 v17, v17, v33, 16
-; VI-NEXT: v_alignbit_b32 v16, v16, v18, 16
+; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[32:33]
+; VI-NEXT: v_lshrrev_b64 v[50:51], 16, v[30:31]
+; VI-NEXT: v_lshrrev_b64 v[38:39], 16, v[38:39]
+; VI-NEXT: v_mov_b32_e32 v33, v48
+; VI-NEXT: v_lshrrev_b64 v[30:31], 16, v[54:55]
+; VI-NEXT: v_lshrrev_b64 v[28:29], 16, v[28:29]
+; VI-NEXT: v_lshrrev_b64 v[26:27], 16, v[26:27]
+; VI-NEXT: v_lshrrev_b64 v[24:25], 16, v[24:25]
+; VI-NEXT: v_lshrrev_b64 v[22:23], 16, v[22:23]
+; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[20:21]
+; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[18:19]
+; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[16:17]
+; VI-NEXT: v_mov_b32_e32 v31, v50
; VI-NEXT: s_branch .LBB101_5
; VI-NEXT: .LBB101_3:
; VI-NEXT: s_branch .LBB101_2
@@ -225619,7 +226554,14 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; VI-NEXT: .LBB101_5: ; %end
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
-; VI-NEXT: v_mov_b32_e32 v18, v32
+; VI-NEXT: v_mov_b32_e32 v17, v38
+; VI-NEXT: v_mov_b32_e32 v18, v48
+; VI-NEXT: v_mov_b32_e32 v19, v37
+; VI-NEXT: v_mov_b32_e32 v21, v36
+; VI-NEXT: v_mov_b32_e32 v23, v35
+; VI-NEXT: v_mov_b32_e32 v25, v34
+; VI-NEXT: v_mov_b32_e32 v27, v33
+; VI-NEXT: v_mov_b32_e32 v29, v32
; VI-NEXT: v_readlane_b32 s31, v42, 1
; VI-NEXT: v_readlane_b32 s30, v42, 0
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
@@ -229236,1105 +230178,1194 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v37, v0
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:40
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:44
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:48
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:52
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:56
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:60
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:64
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:76
-; SI-NEXT: v_cvt_f16_f32_e32 v40, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v9
-; SI-NEXT: v_mov_b32_e32 v46, v28
-; SI-NEXT: v_cvt_f16_f32_e32 v43, v2
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:76
+; SI-NEXT: v_cvt_f16_f32_e32 v34, v1
+; SI-NEXT: v_mov_b32_e32 v37, v20
+; SI-NEXT: v_cvt_f16_f32_e32 v35, v2
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v36, v7
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
-; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
-; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
-; SI-NEXT: v_cvt_f16_f32_e32 v44, v24
-; SI-NEXT: v_cvt_f16_f32_e32 v45, v25
-; SI-NEXT: v_cvt_f16_f32_e32 v26, v26
-; SI-NEXT: v_cvt_f16_f32_e32 v28, v27
-; SI-NEXT: v_cvt_f16_f32_e32 v27, v46
-; SI-NEXT: v_cvt_f16_f32_e32 v46, v29
-; SI-NEXT: v_cvt_f16_f32_e32 v47, v30
-; SI-NEXT: v_cvt_f16_f32_e32 v24, s18
-; SI-NEXT: v_cvt_f16_f32_e32 v25, s19
-; SI-NEXT: v_cvt_f16_f32_e32 v29, s20
-; SI-NEXT: v_cvt_f16_f32_e32 v30, s21
+; SI-NEXT: v_cvt_f16_f32_e32 v20, v16
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v17
+; SI-NEXT: v_cvt_f16_f32_e32 v17, v18
+; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
+; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
+; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
+; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
+; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
+; SI-NEXT: v_cvt_f16_f32_e32 v54, v25
+; SI-NEXT: v_cvt_f16_f32_e32 v48, v26
+; SI-NEXT: v_cvt_f16_f32_e32 v50, v27
+; SI-NEXT: v_cvt_f16_f32_e32 v51, v28
+; SI-NEXT: v_cvt_f16_f32_e32 v55, v29
+; SI-NEXT: v_cvt_f16_f32_e32 v40, v30
+; SI-NEXT: v_cvt_f16_f32_e32 v7, s16
+; SI-NEXT: v_cvt_f16_f32_e32 v18, s17
+; SI-NEXT: v_cvt_f16_f32_e32 v27, s20
+; SI-NEXT: v_cvt_f16_f32_e32 v26, s21
+; SI-NEXT: v_cvt_f16_f32_e32 v25, s22
+; SI-NEXT: v_cvt_f16_f32_e32 v28, s23
+; SI-NEXT: v_cvt_f16_f32_e32 v38, s24
+; SI-NEXT: v_cvt_f16_f32_e32 v30, s27
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; SI-NEXT: v_cvt_f16_f32_e32 v31, v15
-; SI-NEXT: v_cvt_f16_f32_e32 v15, v17
-; SI-NEXT: v_cvt_f16_f32_e32 v17, v19
-; SI-NEXT: v_cvt_f16_f32_e32 v19, v20
-; SI-NEXT: v_cvt_f16_f32_e32 v20, v21
-; SI-NEXT: v_cvt_f16_f32_e32 v21, v22
-; SI-NEXT: v_cvt_f16_f32_e32 v22, v23
-; SI-NEXT: v_cvt_f16_f32_e32 v32, v32
-; SI-NEXT: v_cvt_f16_f32_e32 v56, v33
-; SI-NEXT: v_cvt_f16_f32_e32 v34, v34
-; SI-NEXT: v_cvt_f16_f32_e32 v35, v35
-; SI-NEXT: v_cvt_f16_f32_e32 v57, v36
-; SI-NEXT: v_cvt_f16_f32_e32 v58, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v38, v38
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v32
+; SI-NEXT: v_cvt_f16_f32_e32 v32, v15
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v49
+; SI-NEXT: v_cvt_f16_f32_e32 v15, v37
+; SI-NEXT: v_cvt_f16_f32_e32 v41, v39
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v52
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v29, v53
+; SI-NEXT: v_cvt_f16_f32_e32 v42, v42
+; SI-NEXT: v_cvt_f16_f32_e32 v43, v43
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cvt_f16_f32_e32 v44, v44
; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_cvt_f16_f32_e32 v59, v39
+; SI-NEXT: v_cvt_f16_f32_e32 v45, v45
; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_cvt_f16_f32_e32 v60, v48
+; SI-NEXT: v_cvt_f16_f32_e32 v46, v46
; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_cvt_f16_f32_e32 v61, v49
-; SI-NEXT: s_waitcnt vmcnt(10) expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v52
+; SI-NEXT: v_cvt_f16_f32_e32 v47, v47
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_cvt_f16_f32_e32 v56, v56
; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_cvt_f16_f32_e32 v53, v53
+; SI-NEXT: v_cvt_f16_f32_e32 v57, v57
; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_cvt_f16_f32_e32 v2, v54
+; SI-NEXT: v_cvt_f16_f32_e32 v58, v58
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_cvt_f16_f32_e32 v54, v55
+; SI-NEXT: v_cvt_f16_f32_e32 v59, v59
; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_cvt_f16_f32_e32 v41, v41
+; SI-NEXT: v_cvt_f16_f32_e32 v60, v60
; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_cvt_f16_f32_e32 v42, v42
+; SI-NEXT: v_cvt_f16_f32_e32 v61, v61
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_cvt_f16_f32_e32 v62, v62
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_cvt_f16_f32_e32 v63, v63
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_cvt_f16_f32_e32 v55, v50
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cvt_f16_f32_e32 v9, v51
-; SI-NEXT: v_cvt_f16_f32_e32 v0, s16
-; SI-NEXT: v_cvt_f16_f32_e32 v23, s17
-; SI-NEXT: v_cvt_f16_f32_e32 v36, s22
-; SI-NEXT: v_cvt_f16_f32_e32 v39, s23
-; SI-NEXT: v_cvt_f16_f32_e32 v48, s24
-; SI-NEXT: v_cvt_f16_f32_e32 v49, s25
-; SI-NEXT: v_cvt_f16_f32_e32 v33, s26
-; SI-NEXT: v_cvt_f16_f32_e32 v50, s27
-; SI-NEXT: v_cvt_f16_f32_e32 v51, s28
-; SI-NEXT: v_cvt_f16_f32_e32 v52, s29
+; SI-NEXT: v_cvt_f16_f32_e32 v37, v31
+; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v33
+; SI-NEXT: v_cvt_f16_f32_e32 v31, s18
+; SI-NEXT: v_cvt_f16_f32_e32 v33, s19
+; SI-NEXT: v_cvt_f16_f32_e32 v39, s25
+; SI-NEXT: v_cvt_f16_f32_e32 v49, s26
+; SI-NEXT: v_cvt_f16_f32_e32 v52, s28
+; SI-NEXT: v_cvt_f16_f32_e32 v53, s29
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB103_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v23
-; SI-NEXT: v_mov_b32_e32 v23, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v24
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v36
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v25
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v29
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v30
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v12
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v14
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v32
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v36
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v18
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v18, v20
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v39
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v20
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v48
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v16
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v49
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v17
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v33
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v19
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v50
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v15
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v51
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v22
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v52
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v23
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v40
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v24
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v43
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v31
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v23
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v48
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v33
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v27
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v51
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v26
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v55
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v25
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v40
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v5
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v46
-; SI-NEXT: s_mov_b64 s[4:5], 0
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_mov_b32_e32 v51, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_mov_b32_e32 v36, v22
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v44
-; SI-NEXT: v_mov_b32_e32 v50, v26
-; SI-NEXT: v_mov_b32_e32 v33, v28
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
-; SI-NEXT: v_mov_b32_e32 v38, v7
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v59
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v60
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v61
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v53
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v54
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v41
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v42
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v62
-; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v41
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v11
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v38
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v13
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v39
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v29
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v49
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v42
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v18
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v30
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v19
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v44
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v20
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v52
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v47
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v45
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v56
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v35
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v45
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v57
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v58
-; SI-NEXT: v_mov_b32_e32 v58, v5
-; SI-NEXT: v_mov_b32_e32 v59, v11
-; SI-NEXT: v_mov_b32_e32 v60, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v63
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v55
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v9
-; SI-NEXT: v_mov_b32_e32 v5, v23
-; SI-NEXT: v_mov_b32_e32 v7, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v53
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v46
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v34
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v56
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v35
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v58
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v37
+; SI-NEXT: s_mov_b64 s[4:5], 0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v21
+; SI-NEXT: v_mov_b32_e32 v38, v54
+; SI-NEXT: v_mov_b32_e32 v52, v51
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v20
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v43
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v47
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v57
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v59
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v61
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v62
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v63
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; SI-NEXT: v_mov_b32_e32 v11, v32
+; SI-NEXT: v_mov_b32_e32 v27, v26
+; SI-NEXT: v_mov_b32_e32 v25, v28
+; SI-NEXT: v_mov_b32_e32 v30, v48
+; SI-NEXT: v_mov_b32_e32 v32, v50
+; SI-NEXT: v_mov_b32_e32 v39, v49
+; SI-NEXT: v_mov_b32_e32 v48, v55
+; SI-NEXT: v_mov_b32_e32 v49, v40
+; SI-NEXT: v_mov_b32_e32 v50, v20
; SI-NEXT: s_branch .LBB103_3
; SI-NEXT: .LBB103_2:
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_mov_b32_e32 v33, v28
-; SI-NEXT: v_mov_b32_e32 v50, v26
-; SI-NEXT: v_mov_b32_e32 v36, v22
-; SI-NEXT: v_mov_b32_e32 v51, v21
+; SI-NEXT: v_mov_b32_e32 v11, v32
+; SI-NEXT: v_mov_b32_e32 v32, v50
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_mov_b32_e32 v52, v51
+; SI-NEXT: v_mov_b32_e32 v38, v54
+; SI-NEXT: v_mov_b32_e32 v18, v20
; SI-NEXT: s_mov_b64 s[4:5], -1
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_mov_b32_e32 v5, v6
+; SI-NEXT: ; kill: killed $vgpr3
; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v27, v26
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v25, v28
+; SI-NEXT: v_mov_b32_e32 v30, v48
+; SI-NEXT: v_mov_b32_e32 v39, v49
+; SI-NEXT: v_mov_b32_e32 v48, v55
+; SI-NEXT: v_mov_b32_e32 v49, v40
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: .LBB103_3: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v19, v20
-; SI-NEXT: v_mov_b32_e32 v6, v27
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_mov_b32_e32 v61, v2
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v51, v2
; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5]
; SI-NEXT: s_cbranch_vccnz .LBB103_5
; SI-NEXT: ; %bb.4: ; %cmp.true
-; SI-NEXT: v_cvt_f32_f16_e32 v2, v9
-; SI-NEXT: v_cvt_f32_f16_e32 v8, v55
-; SI-NEXT: v_cvt_f32_f16_e32 v10, v63
-; SI-NEXT: v_cvt_f32_f16_e32 v14, v62
-; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v58
+; SI-NEXT: v_cvt_f32_f16_e32 v33, v46
+; SI-NEXT: v_mov_b32_e32 v28, v38
+; SI-NEXT: v_cvt_f32_f16_e32 v36, v24
+; SI-NEXT: v_add_f32_e32 v58, 0x38000000, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v47
+; SI-NEXT: v_add_f32_e32 v47, 0x38000000, v33
+; SI-NEXT: v_cvt_f32_f16_e32 v33, v43
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v46, 0x38000000, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v44
+; SI-NEXT: v_cvt_f32_f16_e32 v44, v42
+; SI-NEXT: v_add_f32_e32 v43, 0x38000000, v33
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_cvt_f32_f16_e32 v33, v50
+; SI-NEXT: v_add_f32_e32 v42, 0x38000000, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v51
+; SI-NEXT: v_cvt_f32_f16_e32 v51, v32
+; SI-NEXT: v_cvt_f32_f16_e32 v50, v52
+; SI-NEXT: v_add_f32_e32 v55, 0x38000000, v33
+; SI-NEXT: v_add_f32_e32 v54, 0x38000000, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v49
+; SI-NEXT: v_cvt_f32_f16_e32 v33, v48
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v15
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v13
+; SI-NEXT: v_add_f32_e32 v38, 0x38000000, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v30
+; SI-NEXT: v_add_f32_e32 v48, 0x38000000, v33
+; SI-NEXT: v_cvt_f32_f16_e32 v33, v28
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v37
+; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v21
+; SI-NEXT: v_add_f32_e32 v35, 0x38000000, v33
+; SI-NEXT: v_add_f32_e32 v33, 0x38000000, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v17
+; SI-NEXT: v_add_f32_e32 v32, 0x38000000, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; SI-NEXT: v_cvt_f32_f16_e32 v37, v23
+; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v14
+; SI-NEXT: v_cvt_f32_f16_e32 v14, v12
+; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
+; SI-NEXT: v_cvt_f32_f16_e32 v40, v41
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v63
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v62
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v60
+; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v2
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v61
+; SI-NEXT: v_add_f32_e32 v62, 0x38000000, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v10, v59
+; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v9
+; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v57
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v56
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v55, 0x38000000, v14
-; SI-NEXT: v_cvt_f32_f16_e32 v15, v61
-; SI-NEXT: v_cvt_f32_f16_e32 v8, v42
-; SI-NEXT: v_cvt_f32_f16_e32 v10, v41
-; SI-NEXT: v_cvt_f32_f16_e32 v3, v34
-; SI-NEXT: v_add_f32_e32 v29, 0x38000000, v15
-; SI-NEXT: v_add_f32_e32 v54, 0x38000000, v8
-; SI-NEXT: v_cvt_f32_f16_e32 v8, v53
-; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v10
-; SI-NEXT: v_cvt_f32_f16_e32 v10, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v9, v51
-; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v8
-; SI-NEXT: v_cvt_f32_f16_e32 v4, v35
-; SI-NEXT: v_add_f32_e32 v39, 0x38000000, v10
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_cvt_f32_f16_e32 v10, v27
-; SI-NEXT: v_cvt_f32_f16_e32 v11, v19
-; SI-NEXT: v_cvt_f32_f16_e32 v42, v7
-; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
-; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v10
-; SI-NEXT: v_cvt_f32_f16_e32 v10, v32
-; SI-NEXT: v_add_f32_e32 v42, 0x38000000, v42
-; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
-; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
-; SI-NEXT: v_add_f32_e32 v27, 0x38000000, v10
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v14, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v52, 0x38000000, v14
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v14, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v48, 0x38000000, v14
-; SI-NEXT: v_cvt_f32_f16_e32 v14, v20
-; SI-NEXT: v_cvt_f32_f16_e32 v20, v33
-; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v14
-; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v4, v46
-; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
-; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v4, v45
-; SI-NEXT: v_cvt_f32_f16_e32 v45, v5
-; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
-; SI-NEXT: v_add_f32_e32 v45, 0x38000000, v45
-; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v15, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v49, 0x38000000, v15
-; SI-NEXT: v_cvt_f32_f16_e32 v15, v57
-; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v15
-; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v3
-; SI-NEXT: v_cvt_f32_f16_e32 v3, v47
-; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v3
-; SI-NEXT: v_cvt_f32_f16_e32 v3, v50
-; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v8, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v8
-; SI-NEXT: v_cvt_f32_f16_e32 v8, v56
-; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v8
-; SI-NEXT: v_cvt_f32_f16_e32 v8, v6
-; SI-NEXT: v_cvt_f32_f16_e32 v6, v44
-; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v8
-; SI-NEXT: v_cvt_f32_f16_e32 v8, v36
-; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
-; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v21, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v28, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v28, 0x38000000, v28
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v31, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v31, 0x38000000, v31
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v32, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v32, 0x38000000, v32
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v33, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v33, 0x38000000, v33
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v34, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v10
+; SI-NEXT: v_add_f32_e32 v56, 0x38000000, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v45
+; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v34, v19
+; SI-NEXT: v_cvt_f32_f16_e32 v17, v16
+; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v29
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_cvt_f32_f16_e32 v29, v26
+; SI-NEXT: v_cvt_f32_f16_e32 v26, v20
+; SI-NEXT: v_cvt_f32_f16_e32 v18, v18
+; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v17
+; SI-NEXT: v_cvt_f32_f16_e32 v27, v27
+; SI-NEXT: v_cvt_f32_f16_e32 v25, v25
+; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v18
+; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v31
+; SI-NEXT: v_add_f32_e32 v26, 0x38000000, v26
+; SI-NEXT: v_add_f32_e32 v27, 0x38000000, v27
+; SI-NEXT: v_add_f32_e32 v29, 0x38000000, v29
+; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
+; SI-NEXT: v_cvt_f32_f16_e32 v39, v39
+; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
+; SI-NEXT: v_cvt_f32_f16_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v34, 0x38000000, v34
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v36, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v39, 0x38000000, v39
+; SI-NEXT: v_add_f32_e32 v37, 0x38000000, v37
+; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_add_f32_e32 v36, 0x38000000, v36
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v50, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v50, 0x38000000, v50
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v51, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
; SI-NEXT: v_add_f32_e32 v51, 0x38000000, v51
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v40, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v50, 0x38000000, v50
; SI-NEXT: v_add_f32_e32 v40, 0x38000000, v40
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v41, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v41, 0x38000000, v41
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v43, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v43, 0x38000000, v43
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v44, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_add_f32_e32 v44, 0x38000000, v44
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v46, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v46, 0x38000000, v46
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v47, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v47, 0x38000000, v47
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v56, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v56, 0x38000000, v56
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v57, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v57, 0x38000000, v57
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v58, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v58, 0x38000000, v58
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v26, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v26, 0x38000000, v26
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v22, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v19, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_cvt_f32_f16_e32 v53, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v53, 0x38000000, v53
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cvt_f32_f16_e32 v61, v19
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v61, 0x38000000, v61
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cvt_f32_f16_e32 v52, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v52, 0x38000000, v52
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cvt_f32_f16_e32 v63, v19
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v63, 0x38000000, v63
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cvt_f32_f16_e32 v49, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v49, 0x38000000, v49
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cvt_f32_f16_e32 v19, v19
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
+; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v35, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v35, 0x38000000, v35
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v13, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v12, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
+; SI-NEXT: v_cvt_f32_f16_e32 v30, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v30
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
-; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v28, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v28, 0x38000000, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v5, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
-; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v23, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
+; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v59, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
+; SI-NEXT: v_cvt_f32_f16_e32 v21, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; SI-NEXT: v_cvt_f32_f16_e32 v41, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
+; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
+; SI-NEXT: v_add_f32_e32 v41, 0x38000000, v41
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cvt_f32_f16_e32 v20, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cvt_f32_f16_e32 v45, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v8
+; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
+; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
+; SI-NEXT: v_add_f32_e32 v45, 0x38000000, v45
+; SI-NEXT: v_add_f32_e32 v31, 0x38000000, v31
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cvt_f32_f16_e32 v57, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_add_f32_e32 v57, 0x38000000, v57
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v20
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v21
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v23
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v26
+; SI-NEXT: v_cvt_f16_f32_e32 v20, v27
+; SI-NEXT: v_cvt_f16_f32_e32 v21, v29
+; SI-NEXT: v_cvt_f16_f32_e32 v23, v25
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v20
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v21
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v23
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v28
+; SI-NEXT: v_cvt_f16_f32_e32 v20, v30
+; SI-NEXT: v_cvt_f16_f32_e32 v21, v39
+; SI-NEXT: v_cvt_f16_f32_e32 v23, v49
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v20
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v21
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v23
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v52
+; SI-NEXT: v_cvt_f16_f32_e32 v20, v53
+; SI-NEXT: v_cvt_f16_f32_e32 v21, v63
+; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v20
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v19
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v21
+; SI-NEXT: v_cvt_f16_f32_e32 v21, v57
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v31
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v61
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cvt_f32_f16_e32 v59, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
; SI-NEXT: v_add_f32_e32 v59, 0x38000000, v59
-; SI-NEXT: v_cvt_f16_f32_e32 v59, v59
+; SI-NEXT: v_cvt_f16_f32_e32 v20, v59
+; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v60, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; SI-NEXT: v_cvt_f32_f16_e32 v60, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v20
; SI-NEXT: v_add_f32_e32 v60, 0x38000000, v60
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v61, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v61, 0x38000000, v61
-; SI-NEXT: v_cvt_f16_f32_e32 v61, v61
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v62, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v62, 0x38000000, v62
-; SI-NEXT: v_cvt_f16_f32_e32 v62, v62
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v63, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v63, 0x38000000, v63
-; SI-NEXT: v_cvt_f16_f32_e32 v63, v63
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v19, v60
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v63
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v19
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v62
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v21
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v61
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v45
+; SI-NEXT: v_cvt_f16_f32_e32 v19, v41
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v60
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v14
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v59
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v12
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v18
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v17
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v16
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v11
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v15
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v12
-; SI-NEXT: v_cvt_f16_f32_e32 v5, v13
-; SI-NEXT: v_cvt_f16_f32_e32 v7, v35
-; SI-NEXT: v_cvt_f16_f32_e32 v12, v19
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v34
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v33
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v22
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v32
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v22
-; SI-NEXT: v_cvt_f16_f32_e32 v5, v26
-; SI-NEXT: v_cvt_f16_f32_e32 v7, v58
-; SI-NEXT: v_cvt_f16_f32_e32 v12, v57
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v37
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v36
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v8
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v35
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v24
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v56
-; SI-NEXT: v_cvt_f16_f32_e32 v5, v47
-; SI-NEXT: v_cvt_f16_f32_e32 v12, v45
-; SI-NEXT: v_cvt_f16_f32_e32 v7, v46
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v44
-; SI-NEXT: v_cvt_f16_f32_e32 v5, v43
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v7
-; SI-NEXT: v_cvt_f16_f32_e32 v7, v42
-; SI-NEXT: v_cvt_f16_f32_e32 v12, v41
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v51
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v50
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v48
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v38
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v40
-; SI-NEXT: v_cvt_f16_f32_e32 v5, v51
-; SI-NEXT: v_cvt_f16_f32_e32 v7, v50
-; SI-NEXT: v_cvt_f16_f32_e32 v12, v36
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v40
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v54
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v55
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v44
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v42
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v9
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v34
-; SI-NEXT: v_cvt_f16_f32_e32 v5, v33
-; SI-NEXT: v_cvt_f16_f32_e32 v12, v31
-; SI-NEXT: v_cvt_f16_f32_e32 v7, v32
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v43
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v47
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v10
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v46
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v28
-; SI-NEXT: v_cvt_f16_f32_e32 v5, v21
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v7
-; SI-NEXT: v_cvt_f16_f32_e32 v7, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v58
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v4
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v8
-; SI-NEXT: v_cvt_f16_f32_e32 v5, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v4
-; SI-NEXT: v_cvt_f16_f32_e32 v4, v16
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v56
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v20
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v5
-; SI-NEXT: v_cvt_f16_f32_e32 v5, v10
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v17
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v27
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v3
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v18
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
-; SI-NEXT: v_cvt_f16_f32_e32 v4, v15
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v3
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v24
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v4
-; SI-NEXT: v_cvt_f16_f32_e32 v4, v23
-; SI-NEXT: v_cvt_f16_f32_e32 v5, v14
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v3
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v48
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v4
-; SI-NEXT: v_cvt_f16_f32_e32 v4, v39
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v5
-; SI-NEXT: v_cvt_f16_f32_e32 v5, v25
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v4
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v52
-; SI-NEXT: v_cvt_f16_f32_e32 v4, v30
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v49
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v29
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v5
-; SI-NEXT: v_cvt_f16_f32_e32 v5, v54
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v55
-; SI-NEXT: v_mov_b32_e32 v17, v11
-; SI-NEXT: v_mov_b32_e32 v16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; SI-NEXT: v_mov_b32_e32 v3, v19
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v62
+; SI-NEXT: v_mov_b32_e32 v36, v12
+; SI-NEXT: v_mov_b32_e32 v35, v19
+; SI-NEXT: v_mov_b32_e32 v8, v14
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v4
-; SI-NEXT: v_mov_b32_e32 v4, v22
-; SI-NEXT: v_mov_b32_e32 v22, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; SI-NEXT: v_mov_b32_e32 v4, v13
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
; SI-NEXT: .LBB103_5: ; %end
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: buffer_store_dword v1, v37, s[0:3], 0 offen
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v37
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v37
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v37
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v37
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v37
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v37
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v37
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v3
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v37
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v37
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v37
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v37
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v37
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v37
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v37
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v37
-; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v17
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v37
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v37
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v40
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v13
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v37
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v37
-; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v59
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v38
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v37
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v60
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v58
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v37
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v18
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v37
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v31
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v37
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v14
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x60, v37
-; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v24
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
-; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x64, v37
-; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v48
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39
-; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x68, v37
-; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v49
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v25
-; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x6c, v37
-; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v52
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v29
-; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x70, v37
-; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v28
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v30
-; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x74, v37
-; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v31
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v12
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43
-; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x78, v37
-; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v26
-; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x7c, v37
-; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
@@ -234101,1088 +235132,1394 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:12
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:16
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76
; SI-NEXT: s_waitcnt expcnt(6)
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:72
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:76
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v57, v21
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mul_f32_e32 v62, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v57
+; SI-NEXT: v_mov_b32_e32 v63, v23
+; SI-NEXT: v_mov_b32_e32 v46, v20
+; SI-NEXT: v_mov_b32_e32 v41, v18
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v59, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v25
+; SI-NEXT: v_mul_f32_e32 v47, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v61, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v60, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v9
; SI-NEXT: v_mul_f32_e32 v45, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v19
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v63, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v30
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v30, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v22, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v20, 1.0, s19
+; SI-NEXT: v_mul_f32_e32 v56, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v14
+; SI-NEXT: v_mul_f32_e32 v59, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v17
+; SI-NEXT: v_mul_f32_e32 v41, 1.0, v41
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v58, 1.0, v46
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v22
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v63
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v63, 1.0, v26
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v27
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v28
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v29
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v30
+; SI-NEXT: v_mul_f32_e64 v30, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v26, 1.0, s20
; SI-NEXT: v_mul_f32_e64 v29, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v28, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v21, 1.0, s28
+; SI-NEXT: v_mul_f32_e64 v24, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v25, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v19, 1.0, s28
+; SI-NEXT: v_mul_f32_e64 v22, 1.0, s29
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v17
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v62, 1.0, v32
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v33
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v32
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v33
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v34
-; SI-NEXT: v_mul_f32_e32 v35, 1.0, v35
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v36
-; SI-NEXT: v_mul_f32_e32 v60, 1.0, v37
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v39
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v48
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49
-; SI-NEXT: v_mul_f32_e32 v56, 1.0, v51
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v52
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v54
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v34
+; SI-NEXT: v_mul_f32_e32 v34, 1.0, v35
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v36
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v37
+; SI-NEXT: v_mul_f32_e32 v37, 1.0, v38
+; SI-NEXT: v_mul_f32_e32 v36, 1.0, v39
+; SI-NEXT: v_mul_f32_e32 v46, 1.0, v48
; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v49, 1.0, v49
; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v40
+; SI-NEXT: v_mul_f32_e32 v50, 1.0, v50
; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_mul_f32_e32 v42, 1.0, v41
+; SI-NEXT: v_mul_f32_e32 v39, 1.0, v51
; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v43
+; SI-NEXT: v_mul_f32_e32 v38, 1.0, v52
; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v44
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v46
+; SI-NEXT: v_mul_f32_e32 v57, 1.0, v53
+; SI-NEXT: s_waitcnt vmcnt(8) expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v57
+; SI-NEXT: v_mul_f32_e32 v55, 1.0, v55
; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_mul_f32_e32 v58, 1.0, v58
-; SI-NEXT: v_mul_f32_e64 v54, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v26, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v52, 1.0, s24
-; SI-NEXT: v_mul_f32_e64 v34, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v33, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v32, 1.0, s29
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v53, 1.0, v40
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_mul_f32_e32 v42, 1.0, v42
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v43, 1.0, v43
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v44
+; SI-NEXT: v_mul_f32_e64 v32, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v35, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v33, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v51, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v48, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v54, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v52, 1.0, s27
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB105_2
; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v20
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v54
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v26
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v52
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v21
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_mov_b64 s[4:5], 0
+; SI-NEXT: v_mov_b32_e32 v40, v49
+; SI-NEXT: v_mov_b32_e32 v44, v53
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v35
+; SI-NEXT: v_mov_b32_e32 v35, v21
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v33
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v54
+; SI-NEXT: v_mov_b32_e32 v54, v5
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v29
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v51
+; SI-NEXT: v_mov_b32_e32 v51, v56
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v57
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v48
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v49
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v25
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v52
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v22
+; SI-NEXT: v_mov_b32_e32 v52, v7
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v42
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v62
+; SI-NEXT: v_mov_b32_e32 v24, v23
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v41
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v47
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v61
+; SI-NEXT: v_mov_b32_e32 v47, v45
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v36
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v19, v18
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v60
+; SI-NEXT: v_mov_b32_e32 v60, v42
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v7
+; SI-NEXT: v_mov_b32_e32 v30, v20
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v45
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v45, v57
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v56
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v18
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v28
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v6
+; SI-NEXT: v_mov_b32_e32 v11, v6
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v63
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v34
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v26
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v17
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v55
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v15
+; SI-NEXT: v_mov_b32_e32 v42, v4
+; SI-NEXT: v_mov_b32_e32 v15, v63
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v32
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v10
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v27
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v13
+; SI-NEXT: v_mov_b32_e32 v5, v18
+; SI-NEXT: v_mov_b32_e32 v6, v41
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v9
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v31
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v37
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v50
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v45
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v15
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v14
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v38
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v13
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v19
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v24
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v27
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v11
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v62
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v35
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v53
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v25
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v36
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v39
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v51
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v48
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v49
-; SI-NEXT: v_mov_b32_e32 v25, v1
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v30
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v34
-; SI-NEXT: v_mov_b32_e32 v57, v13
-; SI-NEXT: v_mov_b32_e32 v40, v3
-; SI-NEXT: v_mov_b32_e32 v54, v50
-; SI-NEXT: v_mov_b32_e32 v46, v19
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; SI-NEXT: v_mov_b32_e32 v44, v15
-; SI-NEXT: v_mov_b32_e32 v9, v11
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v6
-; SI-NEXT: s_mov_b64 s[4:5], 0
-; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v59
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v10
-; SI-NEXT: v_mov_b32_e32 v41, v27
-; SI-NEXT: v_mov_b32_e32 v52, v62
-; SI-NEXT: v_mov_b32_e32 v21, v58
-; SI-NEXT: v_mov_b32_e32 v58, v20
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v31
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v55
-; SI-NEXT: v_mov_b32_e32 v55, v4
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v42
-; SI-NEXT: v_mov_b32_e32 v56, v47
-; SI-NEXT: v_mov_b32_e32 v53, v5
-; SI-NEXT: v_mov_b32_e32 v42, v43
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v13
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v3
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v50
-; SI-NEXT: s_waitcnt vmcnt(2) expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v19
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v43
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; SI-NEXT: v_mov_b32_e32 v5, v19
-; SI-NEXT: v_mov_b32_e32 v7, v15
+; SI-NEXT: v_mov_b32_e32 v2, v38
+; SI-NEXT: v_mov_b32_e32 v38, v31
+; SI-NEXT: s_branch .LBB105_3
+; SI-NEXT: .LBB105_2:
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: v_mov_b32_e32 v35, v21
+; SI-NEXT: v_mov_b32_e32 v30, v20
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v52, v7
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v63
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v61
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v47
-; SI-NEXT: v_mov_b32_e32 v47, v3
-; SI-NEXT: v_mov_b32_e32 v3, v17
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v43
-; SI-NEXT: v_mov_b32_e32 v1, v13
-; SI-NEXT: s_branch .LBB105_3
-; SI-NEXT: .LBB105_2:
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_mov_b32_e32 v25, v1
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_mov_b32_e32 v21, v58
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_mov_b32_e32 v52, v62
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v54, v50
-; SI-NEXT: v_mov_b32_e32 v56, v47
-; SI-NEXT: v_mov_b32_e32 v9, v11
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v53, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v40, v3
-; SI-NEXT: v_mov_b32_e32 v44, v15
-; SI-NEXT: v_mov_b32_e32 v57, v13
-; SI-NEXT: v_mov_b32_e32 v46, v19
-; SI-NEXT: v_mov_b32_e32 v41, v27
-; SI-NEXT: s_mov_b64 s[4:5], -1
-; SI-NEXT: v_mov_b32_e32 v42, v43
-; SI-NEXT: v_mov_b32_e32 v3, v17
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v54, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v24, v23
+; SI-NEXT: v_mov_b32_e32 v19, v18
+; SI-NEXT: v_mov_b32_e32 v51, v56
+; SI-NEXT: v_mov_b32_e32 v40, v49
+; SI-NEXT: v_mov_b32_e32 v47, v45
+; SI-NEXT: v_mov_b32_e32 v44, v53
+; SI-NEXT: v_mov_b32_e32 v11, v6
+; SI-NEXT: s_mov_b64 s[4:5], -1
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, v38
+; SI-NEXT: v_mov_b32_e32 v60, v42
+; SI-NEXT: v_mov_b32_e32 v45, v57
+; SI-NEXT: v_mov_b32_e32 v38, v31
+; SI-NEXT: v_mov_b32_e32 v42, v4
+; SI-NEXT: v_mov_b32_e32 v6, v41
+; SI-NEXT: v_mov_b32_e32 v15, v63
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: .LBB105_3: ; %Flow
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v18, v3
+; SI-NEXT: v_mov_b32_e32 v57, v9
+; SI-NEXT: v_mov_b32_e32 v23, v1
; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5]
+; SI-NEXT: v_mov_b32_e32 v53, v47
+; SI-NEXT: v_mov_b32_e32 v47, v51
; SI-NEXT: s_cbranch_vccnz .LBB105_5
; SI-NEXT: ; %bb.4: ; %cmp.true
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v30
-; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v4
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v31
-; SI-NEXT: v_mov_b32_e32 v38, v9
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v38
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v31
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_mov_b32_e32 v4, v52
+; SI-NEXT: v_mov_b32_e32 v52, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v13
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v29
-; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v4
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v30
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v43
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_mov_b32_e32 v59, v45
+; SI-NEXT: v_mov_b32_e32 v61, v46
+; SI-NEXT: v_mov_b32_e32 v46, v2
+; SI-NEXT: v_mov_b32_e32 v45, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v55
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v39
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v23
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v36
+; SI-NEXT: v_add_f32_e32 v48, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v50
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v37
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_mov_b32_e32 v37, v42
+; SI-NEXT: v_mov_b32_e32 v42, v2
+; SI-NEXT: v_mov_b32_e32 v41, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v34
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v28
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_mov_b32_e32 v31, v30
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v17
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_mov_b32_e32 v15, v44
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v57
+; SI-NEXT: v_add_f32_e32 v62, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v27
+; SI-NEXT: v_add_f32_e32 v57, 0x40c00000, v1
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v32
+; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v26
+; SI-NEXT: v_mov_b32_e32 v10, v11
+; SI-NEXT: v_mov_b32_e32 v11, v24
+; SI-NEXT: v_add_f32_e32 v43, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v18
+; SI-NEXT: v_add_f32_e32 v55, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v35
+; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54
+; SI-NEXT: v_mov_b32_e32 v12, v19
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v59
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v28
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_mov_b32_e32 v59, v58
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v34
-; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v4
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v29
-; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v30
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v31
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v2
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v32
-; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v4
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v27
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v35, 0x40c00000, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v40
-; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v4
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v50, 0x40c00000, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v26
-; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v11
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v19
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v19
+; SI-NEXT: v_lshr_b64 v[1:2], v[33:34], 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v15
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v50
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v44
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v5
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v57
-; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v17
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v24
+; SI-NEXT: v_lshr_b64 v[1:2], v[33:34], 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v46
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v13
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v63
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
+; SI-NEXT: v_lshr_b64 v[1:2], v[33:34], 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
+; SI-NEXT: v_lshr_b64 v[1:2], v[33:34], 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v41
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v12
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v11
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v61
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v11
+; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v14
+; SI-NEXT: v_mov_b32_e32 v14, v26
+; SI-NEXT: v_lshr_b64 v[25:26], v[25:26], 16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[33:34], 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v52
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v12
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v40
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[33:34], 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v47
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v53
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v9
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v9
+; SI-NEXT: v_lshr_b64 v[1:2], v[33:34], 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v60
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v7
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v10
+; SI-NEXT: v_mov_b32_e32 v47, v46
+; SI-NEXT: v_mov_b32_e32 v46, v45
+; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
+; SI-NEXT: v_lshr_b64 v[1:2], v[33:34], 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v5
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v7
+; SI-NEXT: v_lshr_b64 v[1:2], v[33:34], 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v8
+; SI-NEXT: v_lshr_b64 v[1:2], v[33:34], 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v56
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v5
+; SI-NEXT: v_lshr_b64 v[1:2], v[33:34], 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v21
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v3
+; SI-NEXT: v_lshr_b64 v[1:2], v[33:34], 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v42
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v37
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v38
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v2
+; SI-NEXT: v_lshr_b64 v[33:34], v[33:34], 16
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v61
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_alignbit_b32 v4, v6, v4, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v53
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_alignbit_b32 v6, v8, v6, 16
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_alignbit_b32 v8, v10, v8, 16
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_alignbit_b32 v10, v12, v10, 16
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; SI-NEXT: v_alignbit_b32 v12, v14, v12, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v23
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_alignbit_b32 v14, v18, v14, 16
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_alignbit_b32 v18, v20, v18, 16
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v23
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v47
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; SI-NEXT: v_alignbit_b32 v24, v24, v23, 16
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_alignbit_b32 v22, v21, v20, 16
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v4
+; SI-NEXT: v_lshr_b64 v[33:34], v[33:34], 16
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v52
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; SI-NEXT: v_lshr_b64 v[48:49], v[21:22], 16
-; SI-NEXT: v_lshr_b64 v[49:50], v[7:8], 16
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v26
-; SI-NEXT: v_alignbit_b32 v26, v59, v25, 16
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
-; SI-NEXT: v_lshr_b64 v[51:52], v[25:26], 16
-; SI-NEXT: v_lshr_b64 v[52:53], v[1:2], 16
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v16, v45, v16, 16
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; SI-NEXT: v_alignbit_b32 v28, v58, v27, 16
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_alignbit_b32 v20, v55, v20, 16
-; SI-NEXT: v_lshr_b64 v[36:37], v[19:20], 16
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v29
-; SI-NEXT: v_alignbit_b32 v35, v43, v32, 16
-; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v30
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
-; SI-NEXT: v_lshr_b64 v[62:63], v[34:35], 16
-; SI-NEXT: v_lshr_b64 v[33:34], v[15:16], 16
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v30
-; SI-NEXT: v_alignbit_b32 v39, v29, v32, 16
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: v_lshr_b64 v[31:32], v[38:39], 16
-; SI-NEXT: v_lshr_b64 v[37:38], v[5:6], 16
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[31:32], v[27:28], 16
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[31:32], v[23:24], 16
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[31:32], v[17:18], 16
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[31:32], v[13:14], 16
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v6
+; SI-NEXT: v_lshr_b64 v[33:34], v[33:34], 16
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v60
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v37, 0x40c00000, v33
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v1
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[31:32], v[11:12], 16
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v37
+; SI-NEXT: v_lshr_b64 v[33:34], v[33:34], 16
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[31:32], v[9:10], 16
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: v_lshr_b64 v[33:34], v[46:47], 16
+; SI-NEXT: v_mov_b32_e32 v61, v42
+; SI-NEXT: v_mov_b32_e32 v1, v33
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v53, v33
+; SI-NEXT: v_lshr_b64 v[33:34], v[48:49], 16
+; SI-NEXT: v_mov_b32_e32 v60, v41
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v1, v33
+; SI-NEXT: v_mov_b32_e32 v38, v33
+; SI-NEXT: v_lshr_b64 v[33:34], v[22:23], 16
+; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v37
+; SI-NEXT: v_mov_b32_e32 v40, v33
+; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v41, 0xffff0000, v8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v1, v33
+; SI-NEXT: v_lshr_b64 v[33:34], v[60:61], 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, v33
+; SI-NEXT: v_lshr_b64 v[33:34], v[62:63], 16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v4, v33
+; SI-NEXT: v_lshr_b64 v[33:34], v[57:58], 16
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v6, v33
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: v_lshr_b64 v[33:34], v[29:30], 16
+; SI-NEXT: v_mov_b32_e32 v62, v56
+; SI-NEXT: v_mov_b32_e32 v8, v33
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v42, v33
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v8, v44
+; SI-NEXT: v_lshr_b64 v[33:34], v[43:44], 16
+; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v10
+; SI-NEXT: v_mov_b32_e32 v58, v63
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v8, v33
+; SI-NEXT: v_lshr_b64 v[33:34], v[55:56], 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v10, v33
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v44, v33
+; SI-NEXT: v_lshr_b64 v[33:34], v[27:28], 16
+; SI-NEXT: v_mov_b32_e32 v55, v25
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v10, v33
+; SI-NEXT: v_lshr_b64 v[33:34], v[20:21], 16
+; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v24
+; SI-NEXT: v_mov_b32_e32 v12, v33
+; SI-NEXT: v_mov_b32_e32 v46, v33
+; SI-NEXT: v_lshr_b64 v[33:34], v[31:32], 16
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_mov_b32_e32 v20, v28
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v12, v33
+; SI-NEXT: v_lshr_b64 v[33:34], v[35:36], 16
+; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v19
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v14, v25
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v14, v36
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v15, v51
+; SI-NEXT: v_lshr_b64 v[24:25], v[50:51], 16
+; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
+; SI-NEXT: v_mov_b32_e32 v57, v24
+; SI-NEXT: v_mov_b32_e32 v25, v32
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v14, v33
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v15, v24
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v15, v17
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_lshr_b64 v[31:32], v[3:4], 16
+; SI-NEXT: v_lshr_b64 v[16:17], v[16:17], 16
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v15, v16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
+; SI-NEXT: v_mov_b32_e32 v35, v16
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[34:35], 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[56:57], 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[54:55], 16
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[11:12], v[45:46], 16
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[9:10], v[43:44], 16
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[7:8], v[41:42], 16
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v14, v49
+; SI-NEXT: v_mov_b32_e32 v16, v30
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v7, v23
+; SI-NEXT: v_lshr_b64 v[48:49], v[39:40], 16
+; SI-NEXT: v_lshr_b64 v[29:30], v[37:38], 16
+; SI-NEXT: v_lshr_b64 v[22:23], v[52:53], 16
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v8, v47
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
; SI-NEXT: .LBB105_5: ; %end
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v52
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v39
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 4, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v62
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 8, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v35
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 12, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v29
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 16, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v28
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v58
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 20, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v33
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 24, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v26
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v59
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 28, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v25
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 32, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v24
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 36, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 40, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v25
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v55
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 44, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v33
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 48, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v45
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 52, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v48
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 56, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v22
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 60, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v62
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v15
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 64, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v18
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x44, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v15
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x48, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x4c, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v13
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x50, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x54, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v59
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x58, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x5c, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v58
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x60, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x64, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v61
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v48
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x68, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v6
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x6c, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v31
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x70, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x74, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v14
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x78, v0
-; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v8
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
@@ -235215,19 +236552,19 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_writelane_b32 v42, s31, 1
; VI-NEXT: v_mov_b32_e32 v31, v17
; VI-NEXT: v_mov_b32_e32 v30, v16
-; VI-NEXT: v_mov_b32_e32 v29, v15
+; VI-NEXT: v_mov_b32_e32 v32, v15
+; VI-NEXT: v_mov_b32_e32 v33, v13
+; VI-NEXT: v_mov_b32_e32 v34, v11
+; VI-NEXT: v_mov_b32_e32 v35, v9
+; VI-NEXT: v_mov_b32_e32 v36, v7
+; VI-NEXT: v_mov_b32_e32 v37, v5
+; VI-NEXT: v_mov_b32_e32 v38, v3
; VI-NEXT: v_mov_b32_e32 v28, v14
-; VI-NEXT: v_mov_b32_e32 v27, v13
; VI-NEXT: v_mov_b32_e32 v26, v12
-; VI-NEXT: v_mov_b32_e32 v25, v11
; VI-NEXT: v_mov_b32_e32 v24, v10
-; VI-NEXT: v_mov_b32_e32 v23, v9
; VI-NEXT: v_mov_b32_e32 v22, v8
-; VI-NEXT: v_mov_b32_e32 v21, v7
; VI-NEXT: v_mov_b32_e32 v20, v6
-; VI-NEXT: v_mov_b32_e32 v19, v5
-; VI-NEXT: v_mov_b32_e32 v32, v4
-; VI-NEXT: v_mov_b32_e32 v17, v3
+; VI-NEXT: v_mov_b32_e32 v48, v4
; VI-NEXT: v_mov_b32_e32 v16, v2
; VI-NEXT: v_readfirstlane_b32 s30, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
@@ -235238,583 +236575,595 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB105_4
; VI-NEXT: .LBB105_2: ; %cmp.true
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: s_lshl_b32 s4, s30, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
+; VI-NEXT: v_mov_b32_e32 v17, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: s_lshl_b32 s4, s28, 16
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s30, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_add_f32_e32 v2, s4, v17
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: s_lshl_b32 s4, s30, 16
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_lshl_b32 s4, s31, 16
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
+; VI-NEXT: v_add_f32_e32 v2, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; VI-NEXT: v_bfe_u32 v4, v2, 16, 1
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2
+; VI-NEXT: s_and_b32 s4, s26, 0xffff0000
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_and_b32 s4, s31, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v0
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s29, 16
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_alignbit_b32 v14, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_alignbit_b32 v15, v4, v3, 16
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s28, 16
-; VI-NEXT: v_alignbit_b32 v13, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s27, 16
-; VI-NEXT: v_alignbit_b32 v12, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s27, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
; VI-NEXT: s_lshl_b32 s4, s26, 16
-; VI-NEXT: v_alignbit_b32 v11, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s26, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s25, 16
-; VI-NEXT: v_alignbit_b32 v10, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s25, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s24, 16
-; VI-NEXT: v_alignbit_b32 v9, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[2:3]
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_and_b32 s4, s24, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s23, 16
-; VI-NEXT: v_alignbit_b32 v8, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s22, 16
-; VI-NEXT: v_alignbit_b32 v7, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: s_lshl_b32 s4, s24, 16
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_alignbit_b32 v6, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: s_lshl_b32 s4, s22, 16
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_alignbit_b32 v5, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_alignbit_b32 v4, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: s_lshl_b32 s4, s18, 16
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: s_lshl_b32 s4, s16, 16
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v17
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v1, s4, v17
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: s_lshl_b32 s4, s17, 16
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v17
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v1
+; VI-NEXT: v_add_f32_e32 v1, s4, v17
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v18, v5, v7, vcc
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v18, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v18, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v18, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v2
-; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
-; VI-NEXT: v_or_b32_e32 v33, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v18, v33, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v18, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v1
+; VI-NEXT: s_lshl_b32 s4, s19, 16
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v17
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v49, v5, v7, vcc
+; VI-NEXT: v_add_f32_e32 v5, s4, v17
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: s_lshl_b32 s4, s21, 16
+; VI-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc
+; VI-NEXT: v_add_f32_e32 v7, s4, v17
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19]
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v5
+; VI-NEXT: v_add_f32_e32 v5, s4, v17
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v1
+; VI-NEXT: v_mov_b32_e32 v1, v18
+; VI-NEXT: v_cndmask_b32_e32 v18, v9, v11, vcc
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: s_lshl_b32 s4, s23, 16
+; VI-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc
+; VI-NEXT: v_add_f32_e32 v7, s4, v17
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50]
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: s_and_b32 s4, s25, 0xffff0000
+; VI-NEXT: v_mov_b32_e32 v3, v49
+; VI-NEXT: v_cndmask_b32_e32 v49, v9, v11, vcc
+; VI-NEXT: v_add_f32_e32 v9, s4, v17
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: s_lshl_b32 s4, s25, 16
+; VI-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc
+; VI-NEXT: v_add_f32_e32 v11, s4, v17
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19]
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
+; VI-NEXT: s_and_b32 s4, s27, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v9
+; VI-NEXT: v_add_f32_e32 v9, s4, v17
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
+; VI-NEXT: v_mov_b32_e32 v5, v18
+; VI-NEXT: v_cndmask_b32_e32 v18, v13, v15, vcc
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: s_lshl_b32 s4, s27, 16
+; VI-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc
+; VI-NEXT: v_add_f32_e32 v11, s4, v17
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
+; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50]
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
+; VI-NEXT: v_mov_b32_e32 v7, v49
+; VI-NEXT: v_cndmask_b32_e32 v49, v13, v15, vcc
+; VI-NEXT: v_add_f32_e32 v13, s4, v17
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19]
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v9
+; VI-NEXT: v_mov_b32_e32 v9, v18
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: s_lshl_b32 s4, s29, 16
+; VI-NEXT: v_cndmask_b32_e32 v13, v15, v18, vcc
+; VI-NEXT: v_add_f32_e32 v15, s4, v17
+; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
-; VI-NEXT: v_or_b32_e32 v33, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v18, v33, vcc
-; VI-NEXT: v_add_f32_e32 v18, s4, v0
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v18, v1, 16
-; VI-NEXT: v_add_f32_e32 v18, s4, v0
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v16
-; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: s_and_b32 s4, s31, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v13
+; VI-NEXT: v_add_f32_e32 v13, s4, v17
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19]
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: s_lshl_b32 s4, s31, 16
+; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc
+; VI-NEXT: v_add_f32_e32 v15, s4, v17
+; VI-NEXT: v_bfe_u32 v17, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v15
+; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50]
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_mov_b32_e32 v11, v49
+; VI-NEXT: v_cndmask_b32_e32 v49, v17, v19, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v16
; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
-; VI-NEXT: v_bfe_u32 v33, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v16
-; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
-; VI-NEXT: v_or_b32_e32 v34, 0x400000, v16
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v13
+; VI-NEXT: v_mov_b32_e32 v13, v18
+; VI-NEXT: v_bfe_u32 v18, v16, 16, 1
+; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v16
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_cndmask_b32_e32 v16, v33, v34, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v17
-; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
-; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
-; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
-; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
-; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
-; VI-NEXT: v_bfe_u32 v34, v17, 16, 1
-; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v17
-; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
-; VI-NEXT: v_or_b32_e32 v35, 0x400000, v17
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
-; VI-NEXT: v_cndmask_b32_e32 v17, v34, v35, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v32
-; VI-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; VI-NEXT: v_bfe_u32 v35, v34, 16, 1
-; VI-NEXT: v_add_u32_e32 v35, vcc, v35, v34
-; VI-NEXT: v_add_u32_e32 v35, vcc, 0x7fff, v35
-; VI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
-; VI-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v34, v34
-; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; VI-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc
-; VI-NEXT: v_bfe_u32 v35, v32, 16, 1
-; VI-NEXT: v_add_u32_e32 v35, vcc, v35, v32
-; VI-NEXT: v_add_u32_e32 v35, vcc, 0x7fff, v35
-; VI-NEXT: v_or_b32_e32 v36, 0x400000, v32
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
-; VI-NEXT: v_cndmask_b32_e32 v32, v35, v36, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v19
-; VI-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; VI-NEXT: v_bfe_u32 v36, v35, 16, 1
-; VI-NEXT: v_add_u32_e32 v36, vcc, v36, v35
-; VI-NEXT: v_add_u32_e32 v36, vcc, 0x7fff, v36
-; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; VI-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v35, v35
+; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v17
+; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc
+; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v16
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
+; VI-NEXT: v_cndmask_b32_e32 v16, v17, v19, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v18
+; VI-NEXT: v_and_b32_e32 v18, 0xffff0000, v38
+; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; VI-NEXT: v_bfe_u32 v19, v18, 16, 1
+; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v18
+; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19
+; VI-NEXT: v_or_b32_e32 v21, 0x400000, v18
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_cndmask_b32_e32 v18, v19, v21, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v38
; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; VI-NEXT: v_cndmask_b32_e32 v35, v36, v37, vcc
-; VI-NEXT: v_bfe_u32 v36, v19, 16, 1
-; VI-NEXT: v_add_u32_e32 v36, vcc, v36, v19
-; VI-NEXT: v_add_u32_e32 v36, vcc, 0x7fff, v36
-; VI-NEXT: v_or_b32_e32 v37, 0x400000, v19
+; VI-NEXT: v_bfe_u32 v21, v19, 16, 1
+; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v19
+; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
+; VI-NEXT: v_or_b32_e32 v23, 0x400000, v19
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
-; VI-NEXT: v_cndmask_b32_e32 v19, v36, v37, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v20
-; VI-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; VI-NEXT: v_bfe_u32 v37, v36, 16, 1
-; VI-NEXT: v_add_u32_e32 v37, vcc, v37, v36
-; VI-NEXT: v_add_u32_e32 v37, vcc, 0x7fff, v37
+; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v48
+; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
+; VI-NEXT: v_cndmask_b32_e32 v38, v21, v23, vcc
+; VI-NEXT: v_bfe_u32 v21, v19, 16, 1
+; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v19
+; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v48
+; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
+; VI-NEXT: v_or_b32_e32 v23, 0x400000, v19
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
+; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; VI-NEXT: v_cndmask_b32_e32 v19, v21, v23, vcc
+; VI-NEXT: v_bfe_u32 v21, v18, 16, 1
+; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v18
+; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
+; VI-NEXT: v_or_b32_e32 v23, 0x400000, v18
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
+; VI-NEXT: v_cndmask_b32_e32 v18, v21, v23, vcc
+; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v37
+; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; VI-NEXT: v_bfe_u32 v23, v21, 16, 1
+; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v21
+; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23
+; VI-NEXT: v_or_b32_e32 v25, 0x400000, v21
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
+; VI-NEXT: v_cndmask_b32_e32 v21, v23, v25, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v37
+; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50]
+; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; VI-NEXT: v_bfe_u32 v25, v23, 16, 1
+; VI-NEXT: v_mov_b32_e32 v15, v49
+; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v23
+; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v21
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v20
; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; VI-NEXT: v_or_b32_e32 v38, 0x400000, v36
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v36, v36
+; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; VI-NEXT: v_cndmask_b32_e32 v36, v37, v38, vcc
-; VI-NEXT: v_bfe_u32 v37, v20, 16, 1
-; VI-NEXT: v_add_u32_e32 v37, vcc, v37, v20
-; VI-NEXT: v_add_u32_e32 v37, vcc, 0x7fff, v37
-; VI-NEXT: v_or_b32_e32 v38, 0x400000, v20
+; VI-NEXT: v_or_b32_e32 v27, 0x400000, v23
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
+; VI-NEXT: v_bfe_u32 v23, v20, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v48, v25, v27, vcc
+; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v20
+; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23
+; VI-NEXT: v_or_b32_e32 v25, 0x400000, v20
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
-; VI-NEXT: v_cndmask_b32_e32 v20, v37, v38, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v21
-; VI-NEXT: v_add_f32_e32 v37, 0x40c00000, v37
-; VI-NEXT: v_bfe_u32 v38, v37, 16, 1
-; VI-NEXT: v_add_u32_e32 v38, vcc, v38, v37
-; VI-NEXT: v_add_u32_e32 v38, vcc, 0x7fff, v38
-; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; VI-NEXT: v_or_b32_e32 v39, 0x400000, v37
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v37, v37
-; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; VI-NEXT: v_cndmask_b32_e32 v37, v38, v39, vcc
-; VI-NEXT: v_bfe_u32 v38, v21, 16, 1
-; VI-NEXT: v_add_u32_e32 v38, vcc, v38, v21
-; VI-NEXT: v_add_u32_e32 v38, vcc, 0x7fff, v38
-; VI-NEXT: v_or_b32_e32 v39, 0x400000, v21
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
-; VI-NEXT: v_cndmask_b32_e32 v21, v38, v39, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v22
-; VI-NEXT: v_add_f32_e32 v38, 0x40c00000, v38
-; VI-NEXT: v_bfe_u32 v39, v38, 16, 1
-; VI-NEXT: v_add_u32_e32 v39, vcc, v39, v38
-; VI-NEXT: v_add_u32_e32 v39, vcc, 0x7fff, v39
+; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v21
+; VI-NEXT: v_bfe_u32 v21, v20, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc
+; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v20
+; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
+; VI-NEXT: v_or_b32_e32 v25, 0x400000, v20
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
+; VI-NEXT: v_cndmask_b32_e32 v20, v21, v25, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v23
+; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v36
+; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; VI-NEXT: v_bfe_u32 v25, v23, 16, 1
+; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v23
+; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
+; VI-NEXT: v_or_b32_e32 v27, 0x400000, v23
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
+; VI-NEXT: v_cndmask_b32_e32 v23, v25, v27, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v36
+; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; VI-NEXT: v_bfe_u32 v27, v25, 16, 1
+; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v25
+; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v22
; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; VI-NEXT: v_or_b32_e32 v48, 0x400000, v38
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v38, v38
+; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27
; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; VI-NEXT: v_cndmask_b32_e32 v38, v39, v48, vcc
-; VI-NEXT: v_bfe_u32 v39, v22, 16, 1
-; VI-NEXT: v_add_u32_e32 v39, vcc, v39, v22
-; VI-NEXT: v_add_u32_e32 v39, vcc, 0x7fff, v39
-; VI-NEXT: v_or_b32_e32 v48, 0x400000, v22
+; VI-NEXT: v_or_b32_e32 v29, 0x400000, v25
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
+; VI-NEXT: v_bfe_u32 v25, v22, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v36, v27, v29, vcc
+; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v22
+; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
+; VI-NEXT: v_or_b32_e32 v27, 0x400000, v22
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
-; VI-NEXT: v_cndmask_b32_e32 v22, v39, v48, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v23
-; VI-NEXT: v_add_f32_e32 v39, 0x40c00000, v39
-; VI-NEXT: v_bfe_u32 v48, v39, 16, 1
-; VI-NEXT: v_add_u32_e32 v48, vcc, v48, v39
-; VI-NEXT: v_add_u32_e32 v48, vcc, 0x7fff, v48
-; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; VI-NEXT: v_or_b32_e32 v49, 0x400000, v39
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v39, v39
-; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; VI-NEXT: v_cndmask_b32_e32 v39, v48, v49, vcc
-; VI-NEXT: v_bfe_u32 v48, v23, 16, 1
-; VI-NEXT: v_add_u32_e32 v48, vcc, v48, v23
-; VI-NEXT: v_add_u32_e32 v48, vcc, 0x7fff, v48
-; VI-NEXT: v_or_b32_e32 v49, 0x400000, v23
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
-; VI-NEXT: v_cndmask_b32_e32 v23, v48, v49, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v24
-; VI-NEXT: v_add_f32_e32 v48, 0x40c00000, v48
-; VI-NEXT: v_bfe_u32 v49, v48, 16, 1
-; VI-NEXT: v_add_u32_e32 v49, vcc, v49, v48
-; VI-NEXT: v_add_u32_e32 v49, vcc, 0x7fff, v49
+; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v23
+; VI-NEXT: v_bfe_u32 v23, v22, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v25, v25, v27, vcc
+; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v22
+; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23
+; VI-NEXT: v_or_b32_e32 v27, 0x400000, v22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
+; VI-NEXT: v_cndmask_b32_e32 v22, v23, v27, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v25
+; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v35
+; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; VI-NEXT: v_bfe_u32 v27, v25, 16, 1
+; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v25
+; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27
+; VI-NEXT: v_or_b32_e32 v29, 0x400000, v25
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
+; VI-NEXT: v_cndmask_b32_e32 v25, v27, v29, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v35
+; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
+; VI-NEXT: v_bfe_u32 v29, v27, 16, 1
+; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v27
+; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v25
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v24
; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; VI-NEXT: v_or_b32_e32 v50, 0x400000, v48
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v48, v48
+; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29
; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; VI-NEXT: v_cndmask_b32_e32 v48, v49, v50, vcc
-; VI-NEXT: v_bfe_u32 v49, v24, 16, 1
-; VI-NEXT: v_add_u32_e32 v49, vcc, v49, v24
-; VI-NEXT: v_add_u32_e32 v49, vcc, 0x7fff, v49
-; VI-NEXT: v_or_b32_e32 v50, 0x400000, v24
+; VI-NEXT: v_or_b32_e32 v35, 0x400000, v27
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
+; VI-NEXT: v_bfe_u32 v27, v24, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v50, v29, v35, vcc
+; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v24
+; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27
+; VI-NEXT: v_or_b32_e32 v29, 0x400000, v24
; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
-; VI-NEXT: v_cndmask_b32_e32 v24, v49, v50, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v25
-; VI-NEXT: v_add_f32_e32 v49, 0x40c00000, v49
-; VI-NEXT: v_bfe_u32 v50, v49, 16, 1
-; VI-NEXT: v_add_u32_e32 v50, vcc, v50, v49
-; VI-NEXT: v_add_u32_e32 v50, vcc, 0x7fff, v50
-; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; VI-NEXT: v_or_b32_e32 v51, 0x400000, v49
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v49, v49
-; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; VI-NEXT: v_cndmask_b32_e32 v49, v50, v51, vcc
-; VI-NEXT: v_bfe_u32 v50, v25, 16, 1
-; VI-NEXT: v_add_u32_e32 v50, vcc, v50, v25
-; VI-NEXT: v_add_u32_e32 v50, vcc, 0x7fff, v50
-; VI-NEXT: v_or_b32_e32 v51, 0x400000, v25
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
-; VI-NEXT: v_cndmask_b32_e32 v25, v50, v51, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v26
-; VI-NEXT: v_add_f32_e32 v50, 0x40c00000, v50
-; VI-NEXT: v_bfe_u32 v51, v50, 16, 1
-; VI-NEXT: v_add_u32_e32 v51, vcc, v51, v50
-; VI-NEXT: v_add_u32_e32 v51, vcc, 0x7fff, v51
+; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v25
+; VI-NEXT: v_bfe_u32 v25, v24, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v27, v27, v29, vcc
+; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v24
+; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
+; VI-NEXT: v_or_b32_e32 v29, 0x400000, v24
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
+; VI-NEXT: v_cndmask_b32_e32 v24, v25, v29, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v27
+; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v34
+; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
+; VI-NEXT: v_bfe_u32 v29, v27, 16, 1
+; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v27
+; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29
+; VI-NEXT: v_or_b32_e32 v35, 0x400000, v27
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
+; VI-NEXT: v_cndmask_b32_e32 v27, v29, v35, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v34
+; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; VI-NEXT: v_bfe_u32 v34, v29, 16, 1
+; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v29
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
+; VI-NEXT: v_or_b32_e32 v35, 0x400000, v29
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
+; VI-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v27
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v26
; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; VI-NEXT: v_or_b32_e32 v52, 0x400000, v50
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v50, v50
; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; VI-NEXT: v_cndmask_b32_e32 v50, v51, v52, vcc
-; VI-NEXT: v_bfe_u32 v51, v26, 16, 1
-; VI-NEXT: v_add_u32_e32 v51, vcc, v51, v26
-; VI-NEXT: v_add_u32_e32 v51, vcc, 0x7fff, v51
+; VI-NEXT: v_bfe_u32 v29, v26, 16, 1
+; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v26
+; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29
; VI-NEXT: v_or_b32_e32 v52, 0x400000, v26
; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
-; VI-NEXT: v_cndmask_b32_e32 v26, v51, v52, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v27
-; VI-NEXT: v_add_f32_e32 v51, 0x40c00000, v51
-; VI-NEXT: v_bfe_u32 v52, v51, 16, 1
-; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v51
+; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v27
+; VI-NEXT: v_bfe_u32 v27, v26, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v29, v29, v52, vcc
+; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v26
+; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27
+; VI-NEXT: v_or_b32_e32 v52, 0x400000, v26
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
+; VI-NEXT: v_cndmask_b32_e32 v26, v27, v52, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v29
+; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v33
+; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; VI-NEXT: v_bfe_u32 v52, v29, 16, 1
+; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v29
; VI-NEXT: v_add_u32_e32 v52, vcc, 0x7fff, v52
-; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; VI-NEXT: v_or_b32_e32 v53, 0x400000, v51
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v51, v51
-; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; VI-NEXT: v_cndmask_b32_e32 v51, v52, v53, vcc
-; VI-NEXT: v_bfe_u32 v52, v27, 16, 1
-; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v27
+; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; VI-NEXT: v_or_b32_e32 v53, 0x400000, v29
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
+; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
+; VI-NEXT: v_cndmask_b32_e32 v29, v52, v53, vcc
+; VI-NEXT: v_bfe_u32 v52, v33, 16, 1
+; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v33
; VI-NEXT: v_add_u32_e32 v52, vcc, 0x7fff, v52
-; VI-NEXT: v_or_b32_e32 v53, 0x400000, v27
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
-; VI-NEXT: v_cndmask_b32_e32 v27, v52, v53, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v28
-; VI-NEXT: v_add_f32_e32 v52, 0x40c00000, v52
-; VI-NEXT: v_bfe_u32 v53, v52, 16, 1
-; VI-NEXT: v_add_u32_e32 v53, vcc, v53, v52
-; VI-NEXT: v_add_u32_e32 v53, vcc, 0x7fff, v53
+; VI-NEXT: v_or_b32_e32 v53, 0x400000, v33
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
+; VI-NEXT: v_cndmask_b32_e32 v52, v52, v53, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v28
; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; VI-NEXT: v_or_b32_e32 v54, 0x400000, v52
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v52, v52
; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; VI-NEXT: v_cndmask_b32_e32 v52, v53, v54, vcc
-; VI-NEXT: v_bfe_u32 v53, v28, 16, 1
-; VI-NEXT: v_add_u32_e32 v53, vcc, v53, v28
-; VI-NEXT: v_add_u32_e32 v53, vcc, 0x7fff, v53
+; VI-NEXT: v_bfe_u32 v33, v28, 16, 1
+; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v28
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v54, 0x400000, v28
; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
-; VI-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v29
-; VI-NEXT: v_add_f32_e32 v53, 0x40c00000, v53
-; VI-NEXT: v_bfe_u32 v54, v53, 16, 1
-; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v53
+; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v29
+; VI-NEXT: v_bfe_u32 v29, v28, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v33, v33, v54, vcc
+; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v28
+; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29
+; VI-NEXT: v_or_b32_e32 v54, 0x400000, v28
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
+; VI-NEXT: v_cndmask_b32_e32 v28, v29, v54, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v33
+; VI-NEXT: v_and_b32_e32 v33, 0xffff0000, v32
+; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
+; VI-NEXT: v_bfe_u32 v54, v33, 16, 1
+; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v33
; VI-NEXT: v_add_u32_e32 v54, vcc, 0x7fff, v54
-; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; VI-NEXT: v_or_b32_e32 v55, 0x400000, v53
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v53, v53
-; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; VI-NEXT: v_cndmask_b32_e32 v53, v54, v55, vcc
-; VI-NEXT: v_bfe_u32 v54, v29, 16, 1
-; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v29
+; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; VI-NEXT: v_or_b32_e32 v55, 0x400000, v33
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
+; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
+; VI-NEXT: v_cndmask_b32_e32 v33, v54, v55, vcc
+; VI-NEXT: v_bfe_u32 v54, v32, 16, 1
+; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v32
; VI-NEXT: v_add_u32_e32 v54, vcc, 0x7fff, v54
-; VI-NEXT: v_or_b32_e32 v55, 0x400000, v29
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
-; VI-NEXT: v_cndmask_b32_e32 v29, v54, v55, vcc
+; VI-NEXT: v_or_b32_e32 v55, 0x400000, v32
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
+; VI-NEXT: v_cndmask_b32_e32 v32, v54, v55, vcc
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v30
-; VI-NEXT: v_add_f32_e32 v54, 0x40c00000, v54
-; VI-NEXT: v_bfe_u32 v55, v54, 16, 1
-; VI-NEXT: v_add_u32_e32 v55, vcc, v55, v54
-; VI-NEXT: v_add_u32_e32 v55, vcc, 0x7fff, v55
; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; VI-NEXT: v_or_b32_e32 v40, 0x400000, v54
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v54, v54
; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; VI-NEXT: v_cndmask_b32_e32 v54, v55, v40, vcc
; VI-NEXT: v_bfe_u32 v55, v30, 16, 1
; VI-NEXT: v_add_u32_e32 v55, vcc, v55, v30
; VI-NEXT: v_add_u32_e32 v55, vcc, 0x7fff, v55
; VI-NEXT: v_or_b32_e32 v40, 0x400000, v30
; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
+; VI-NEXT: v_add_f32_e32 v54, 0x40c00000, v54
; VI-NEXT: v_cndmask_b32_e32 v30, v55, v40, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v31
-; VI-NEXT: v_add_f32_e32 v55, 0x40c00000, v55
-; VI-NEXT: v_bfe_u32 v40, v55, 16, 1
-; VI-NEXT: v_add_u32_e32 v40, vcc, v40, v55
-; VI-NEXT: v_add_u32_e32 v40, vcc, 0x7fff, v40
-; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; VI-NEXT: v_or_b32_e32 v41, 0x400000, v55
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v55, v55
-; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; VI-NEXT: v_cndmask_b32_e32 v55, v40, v41, vcc
-; VI-NEXT: v_bfe_u32 v40, v31, 16, 1
-; VI-NEXT: v_add_u32_e32 v40, vcc, v40, v31
+; VI-NEXT: v_bfe_u32 v55, v54, 16, 1
+; VI-NEXT: v_add_u32_e32 v55, vcc, v55, v54
+; VI-NEXT: v_add_u32_e32 v55, vcc, 0x7fff, v55
+; VI-NEXT: v_or_b32_e32 v40, 0x400000, v54
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v54, v54
+; VI-NEXT: v_cndmask_b32_e32 v54, v55, v40, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v30
+; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v31
+; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; VI-NEXT: v_bfe_u32 v40, v30, 16, 1
+; VI-NEXT: v_add_u32_e32 v40, vcc, v40, v30
; VI-NEXT: v_add_u32_e32 v40, vcc, 0x7fff, v40
-; VI-NEXT: v_or_b32_e32 v41, 0x400000, v31
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
-; VI-NEXT: v_cndmask_b32_e32 v31, v40, v41, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; VI-NEXT: v_or_b32_e32 v41, 0x400000, v30
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v31
+; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; VI-NEXT: v_bfe_u32 v31, v30, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[48:49]
+; VI-NEXT: v_cndmask_b32_e32 v40, v40, v41, vcc
+; VI-NEXT: v_add_u32_e32 v31, vcc, v31, v30
+; VI-NEXT: v_lshrrev_b64 v[36:37], 16, v[36:37]
+; VI-NEXT: v_add_u32_e32 v31, vcc, 0x7fff, v31
+; VI-NEXT: v_mov_b32_e32 v37, v48
+; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[50:51]
+; VI-NEXT: v_or_b32_e32 v41, 0x400000, v30
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
+; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[34:35]
+; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v33
+; VI-NEXT: v_cndmask_b32_e32 v30, v31, v41, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v40
+; VI-NEXT: v_mov_b32_e32 v35, v48
+; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[52:53]
; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_alignbit_b32 v31, v31, v55, 16
-; VI-NEXT: v_alignbit_b32 v30, v30, v54, 16
-; VI-NEXT: v_alignbit_b32 v29, v29, v53, 16
-; VI-NEXT: v_alignbit_b32 v28, v28, v52, 16
-; VI-NEXT: v_alignbit_b32 v27, v27, v51, 16
-; VI-NEXT: v_alignbit_b32 v26, v26, v50, 16
-; VI-NEXT: v_alignbit_b32 v25, v25, v49, 16
-; VI-NEXT: v_alignbit_b32 v24, v24, v48, 16
-; VI-NEXT: v_alignbit_b32 v23, v23, v39, 16
-; VI-NEXT: v_alignbit_b32 v22, v22, v38, 16
-; VI-NEXT: v_alignbit_b32 v21, v21, v37, 16
-; VI-NEXT: v_alignbit_b32 v20, v20, v36, 16
-; VI-NEXT: v_alignbit_b32 v19, v19, v35, 16
-; VI-NEXT: v_alignbit_b32 v32, v32, v34, 16
-; VI-NEXT: v_alignbit_b32 v17, v17, v33, 16
-; VI-NEXT: v_alignbit_b32 v16, v16, v18, 16
+; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[32:33]
+; VI-NEXT: v_lshrrev_b64 v[50:51], 16, v[30:31]
+; VI-NEXT: v_lshrrev_b64 v[38:39], 16, v[38:39]
+; VI-NEXT: v_mov_b32_e32 v33, v48
+; VI-NEXT: v_lshrrev_b64 v[30:31], 16, v[54:55]
+; VI-NEXT: v_lshrrev_b64 v[28:29], 16, v[28:29]
+; VI-NEXT: v_lshrrev_b64 v[26:27], 16, v[26:27]
+; VI-NEXT: v_lshrrev_b64 v[24:25], 16, v[24:25]
+; VI-NEXT: v_lshrrev_b64 v[22:23], 16, v[22:23]
+; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[20:21]
+; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[18:19]
+; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[16:17]
+; VI-NEXT: v_mov_b32_e32 v31, v50
; VI-NEXT: s_branch .LBB105_5
; VI-NEXT: .LBB105_3:
; VI-NEXT: s_branch .LBB105_2
@@ -235838,7 +237187,14 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; VI-NEXT: .LBB105_5: ; %end
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
-; VI-NEXT: v_mov_b32_e32 v18, v32
+; VI-NEXT: v_mov_b32_e32 v17, v38
+; VI-NEXT: v_mov_b32_e32 v18, v48
+; VI-NEXT: v_mov_b32_e32 v19, v37
+; VI-NEXT: v_mov_b32_e32 v21, v36
+; VI-NEXT: v_mov_b32_e32 v23, v35
+; VI-NEXT: v_mov_b32_e32 v25, v34
+; VI-NEXT: v_mov_b32_e32 v27, v33
+; VI-NEXT: v_mov_b32_e32 v29, v32
; VI-NEXT: v_readlane_b32 s31, v42, 1
; VI-NEXT: v_readlane_b32 s30, v42, 0
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
@@ -238881,54 +240237,54 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: v_writelane_b32 v40, s85, 29
; SI-NEXT: v_writelane_b32 v40, s86, 30
; SI-NEXT: v_writelane_b32 v40, s87, 31
+; SI-NEXT: s_mov_b32 s74, s23
+; SI-NEXT: s_mov_b32 s72, s21
+; SI-NEXT: s_mov_b32 s61, s18
; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
; SI-NEXT: s_mov_b32 s60, s16
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v41, s17, 0
-; SI-NEXT: s_mov_b32 s61, s19
; SI-NEXT: v_writelane_b32 v41, s60, 1
-; SI-NEXT: s_mov_b32 s63, s18
-; SI-NEXT: v_writelane_b32 v41, s61, 2
-; SI-NEXT: s_mov_b32 s72, s21
-; SI-NEXT: v_writelane_b32 v41, s63, 3
+; SI-NEXT: v_writelane_b32 v41, s19, 2
+; SI-NEXT: v_writelane_b32 v41, s61, 3
; SI-NEXT: v_writelane_b32 v41, s72, 4
-; SI-NEXT: s_mov_b32 s74, s23
; SI-NEXT: v_writelane_b32 v41, s20, 5
; SI-NEXT: v_writelane_b32 v41, s74, 6
-; SI-NEXT: s_mov_b32 s75, s25
+; SI-NEXT: s_mov_b32 s76, s25
; SI-NEXT: v_writelane_b32 v41, s22, 7
-; SI-NEXT: v_writelane_b32 v41, s75, 8
-; SI-NEXT: s_mov_b32 s76, s27
+; SI-NEXT: v_writelane_b32 v41, s76, 8
+; SI-NEXT: s_mov_b32 s78, s27
; SI-NEXT: v_writelane_b32 v41, s24, 9
-; SI-NEXT: v_writelane_b32 v41, s76, 10
-; SI-NEXT: s_mov_b32 s93, s29
+; SI-NEXT: v_writelane_b32 v41, s78, 10
+; SI-NEXT: s_mov_b32 s88, s29
; SI-NEXT: v_writelane_b32 v41, s26, 11
-; SI-NEXT: v_writelane_b32 v41, s93, 12
-; SI-NEXT: v_readfirstlane_b32 s16, v2
+; SI-NEXT: v_writelane_b32 v41, s88, 12
+; SI-NEXT: v_readfirstlane_b32 s77, v2
; SI-NEXT: v_writelane_b32 v41, s28, 13
-; SI-NEXT: v_readfirstlane_b32 s73, v4
-; SI-NEXT: v_writelane_b32 v41, s16, 14
-; SI-NEXT: v_readfirstlane_b32 s89, v3
-; SI-NEXT: v_writelane_b32 v41, s73, 15
-; SI-NEXT: v_readfirstlane_b32 s90, v6
-; SI-NEXT: v_writelane_b32 v41, s89, 16
-; SI-NEXT: v_readfirstlane_b32 s91, v5
-; SI-NEXT: v_writelane_b32 v41, s90, 17
-; SI-NEXT: v_readfirstlane_b32 s34, v8
-; SI-NEXT: v_writelane_b32 v41, s91, 18
-; SI-NEXT: v_readfirstlane_b32 s35, v7
-; SI-NEXT: v_writelane_b32 v41, s34, 19
-; SI-NEXT: v_readfirstlane_b32 s36, v10
-; SI-NEXT: v_writelane_b32 v41, s35, 20
-; SI-NEXT: v_writelane_b32 v40, s96, 32
-; SI-NEXT: v_readfirstlane_b32 s37, v9
-; SI-NEXT: v_writelane_b32 v41, s36, 21
+; SI-NEXT: v_readfirstlane_b32 s79, v4
+; SI-NEXT: v_writelane_b32 v41, s77, 14
+; SI-NEXT: v_readfirstlane_b32 s90, v3
+; SI-NEXT: v_writelane_b32 v41, s79, 15
+; SI-NEXT: v_readfirstlane_b32 s91, v6
+; SI-NEXT: v_writelane_b32 v41, s90, 16
+; SI-NEXT: v_readfirstlane_b32 s92, v5
+; SI-NEXT: v_writelane_b32 v41, s91, 17
+; SI-NEXT: v_readfirstlane_b32 s93, v8
+; SI-NEXT: v_writelane_b32 v41, s92, 18
+; SI-NEXT: v_readfirstlane_b32 s94, v7
+; SI-NEXT: v_writelane_b32 v41, s93, 19
+; SI-NEXT: v_readfirstlane_b32 s95, v10
+; SI-NEXT: v_writelane_b32 v41, s94, 20
+; SI-NEXT: v_readfirstlane_b32 s30, v9
+; SI-NEXT: v_writelane_b32 v41, s95, 21
+; SI-NEXT: v_readfirstlane_b32 s31, v12
+; SI-NEXT: v_writelane_b32 v41, s30, 22
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_readfirstlane_b32 s62, v31
+; SI-NEXT: v_readfirstlane_b32 s21, v31
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_readfirstlane_b32 s80, v32
; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_readfirstlane_b32 s69, v33
+; SI-NEXT: v_readfirstlane_b32 s75, v33
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:36
@@ -238940,20 +240296,25 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s84, v34
; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_readfirstlane_b32 s68, v35
+; SI-NEXT: v_readfirstlane_b32 s23, v35
; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_readfirstlane_b32 s83, v36
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_readfirstlane_b32 s87, v38
; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:80
-; SI-NEXT: v_readfirstlane_b32 s6, v37
+; SI-NEXT: v_readfirstlane_b32 s18, v37
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:8
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:4
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32
+; SI-NEXT: v_writelane_b32 v41, s31, 23
+; SI-NEXT: v_readfirstlane_b32 s34, v11
+; SI-NEXT: v_readfirstlane_b32 s35, v14
+; SI-NEXT: v_readfirstlane_b32 s36, v13
+; SI-NEXT: v_writelane_b32 v40, s96, 32
+; SI-NEXT: v_readfirstlane_b32 s37, v16
; SI-NEXT: v_writelane_b32 v40, s97, 33
-; SI-NEXT: v_readfirstlane_b32 s38, v12
-; SI-NEXT: v_writelane_b32 v41, s37, 22
+; SI-NEXT: v_readfirstlane_b32 s38, v15
; SI-NEXT: v_writelane_b32 v40, s98, 34
; SI-NEXT: v_readfirstlane_b32 s14, v30
; SI-NEXT: v_readfirstlane_b32 s15, v29
@@ -238963,21 +240324,13 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: v_readfirstlane_b32 s11, v25
; SI-NEXT: v_readfirstlane_b32 s8, v24
; SI-NEXT: v_readfirstlane_b32 s9, v23
-; SI-NEXT: v_readfirstlane_b32 s88, v22
-; SI-NEXT: v_readfirstlane_b32 s29, v21
-; SI-NEXT: v_readfirstlane_b32 s79, v20
-; SI-NEXT: v_readfirstlane_b32 s27, v19
-; SI-NEXT: v_readfirstlane_b32 s78, v18
-; SI-NEXT: v_readfirstlane_b32 s25, v17
-; SI-NEXT: v_readfirstlane_b32 s77, v16
-; SI-NEXT: v_readfirstlane_b32 s23, v15
-; SI-NEXT: v_readfirstlane_b32 s39, v14
-; SI-NEXT: v_readfirstlane_b32 s21, v13
-; SI-NEXT: v_readfirstlane_b32 s19, v11
-; SI-NEXT: v_readfirstlane_b32 s18, v1
-; SI-NEXT: v_writelane_b32 v41, s38, 23
+; SI-NEXT: v_readfirstlane_b32 s89, v22
+; SI-NEXT: v_readfirstlane_b32 s7, v21
+; SI-NEXT: v_readfirstlane_b32 s25, v20
+; SI-NEXT: v_readfirstlane_b32 s29, v19
+; SI-NEXT: v_readfirstlane_b32 s39, v18
+; SI-NEXT: v_readfirstlane_b32 s27, v17
; SI-NEXT: v_writelane_b32 v40, s99, 35
-; SI-NEXT: v_writelane_b32 v41, s39, 24
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s58, v31
; SI-NEXT: s_waitcnt vmcnt(11)
@@ -238997,261 +240350,289 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_readfirstlane_b32 s42, v34
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v38
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s5, v1
+; SI-NEXT: v_writelane_b32 v41, s5, 24
+; SI-NEXT: v_writelane_b32 v41, s34, 25
+; SI-NEXT: v_writelane_b32 v41, s35, 26
+; SI-NEXT: v_writelane_b32 v41, s36, 27
+; SI-NEXT: v_writelane_b32 v41, s37, 28
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_readfirstlane_b32 s43, v35
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_readfirstlane_b32 s40, v36
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s41, v37
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_writelane_b32 v41, s38, 29
+; SI-NEXT: v_writelane_b32 v41, s39, 30
; SI-NEXT: s_cbranch_scc0 .LBB107_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshl_b32 s4, s60, 16
-; SI-NEXT: v_writelane_b32 v41, s4, 25
-; SI-NEXT: s_lshl_b32 s4, s63, 16
-; SI-NEXT: v_writelane_b32 v41, s4, 26
-; SI-NEXT: s_lshl_b32 s4, s20, 16
-; SI-NEXT: v_writelane_b32 v41, s4, 27
-; SI-NEXT: s_lshl_b32 s4, s22, 16
-; SI-NEXT: v_writelane_b32 v41, s4, 28
-; SI-NEXT: s_lshl_b32 s4, s24, 16
-; SI-NEXT: v_writelane_b32 v41, s4, 29
-; SI-NEXT: s_lshl_b32 s4, s26, 16
-; SI-NEXT: v_writelane_b32 v41, s4, 30
-; SI-NEXT: s_lshl_b32 s4, s28, 16
-; SI-NEXT: v_writelane_b32 v41, s4, 31
-; SI-NEXT: s_lshl_b32 s4, s18, 16
; SI-NEXT: v_writelane_b32 v41, s4, 32
-; SI-NEXT: s_lshl_b32 s4, s89, 16
-; SI-NEXT: v_writelane_b32 v41, s4, 33
-; SI-NEXT: s_lshl_b32 s4, s91, 16
+; SI-NEXT: s_lshl_b32 s4, s17, 16
+; SI-NEXT: v_writelane_b32 v41, s4, 31
+; SI-NEXT: s_lshl_b32 s4, s61, 16
; SI-NEXT: v_writelane_b32 v41, s4, 34
-; SI-NEXT: s_lshl_b32 s4, s35, 16
-; SI-NEXT: v_writelane_b32 v41, s4, 35
-; SI-NEXT: s_lshl_b32 s4, s37, 16
-; SI-NEXT: s_lshl_b32 s7, s17, 16
-; SI-NEXT: s_lshl_b32 s96, s61, 16
-; SI-NEXT: s_lshl_b32 s99, s72, 16
-; SI-NEXT: s_lshl_b32 s97, s74, 16
-; SI-NEXT: s_lshl_b32 s92, s75, 16
-; SI-NEXT: s_lshl_b32 s94, s76, 16
-; SI-NEXT: s_lshl_b32 s95, s93, 16
-; SI-NEXT: s_lshl_b32 s93, s16, 16
-; SI-NEXT: s_lshl_b32 s30, s73, 16
-; SI-NEXT: s_lshl_b32 s31, s90, 16
-; SI-NEXT: s_lshl_b32 s34, s34, 16
+; SI-NEXT: s_lshl_b32 s4, s19, 16
+; SI-NEXT: v_writelane_b32 v41, s4, 33
+; SI-NEXT: s_lshl_b32 s4, s20, 16
; SI-NEXT: v_writelane_b32 v41, s4, 36
-; SI-NEXT: s_lshl_b32 s35, s36, 16
-; SI-NEXT: s_lshl_b32 s86, s19, 16
-; SI-NEXT: s_lshl_b32 s36, s38, 16
-; SI-NEXT: s_lshl_b32 s22, s21, 16
-; SI-NEXT: s_lshl_b32 s37, s39, 16
-; SI-NEXT: s_lshl_b32 s24, s23, 16
-; SI-NEXT: s_lshl_b32 s38, s77, 16
-; SI-NEXT: s_lshl_b32 s28, s25, 16
-; SI-NEXT: s_lshl_b32 s39, s78, 16
-; SI-NEXT: s_lshl_b32 s61, s27, 16
-; SI-NEXT: s_lshl_b32 s48, s79, 16
-; SI-NEXT: s_lshl_b32 s89, s29, 16
-; SI-NEXT: s_lshl_b32 s49, s88, 16
-; SI-NEXT: s_lshl_b32 s60, s9, 16
-; SI-NEXT: s_lshl_b32 s50, s8, 16
-; SI-NEXT: s_lshl_b32 s90, s11, 16
-; SI-NEXT: s_lshl_b32 s91, s10, 16
-; SI-NEXT: s_lshl_b32 s70, s13, 16
-; SI-NEXT: s_lshl_b32 s51, s12, 16
-; SI-NEXT: s_lshl_b32 s71, s15, 16
-; SI-NEXT: s_lshl_b32 s52, s14, 16
-; SI-NEXT: s_lshl_b32 s20, s41, 16
-; SI-NEXT: s_lshl_b32 s53, s40, 16
-; SI-NEXT: s_lshl_b32 s81, s43, 16
-; SI-NEXT: s_lshl_b32 s54, s42, 16
-; SI-NEXT: s_lshl_b32 s63, s45, 16
-; SI-NEXT: s_lshl_b32 s55, s44, 16
-; SI-NEXT: s_lshl_b32 s72, s47, 16
-; SI-NEXT: s_lshl_b32 s64, s46, 16
-; SI-NEXT: s_lshl_b32 s82, s57, 16
-; SI-NEXT: s_lshl_b32 s65, s56, 16
-; SI-NEXT: s_lshl_b32 s74, s59, 16
-; SI-NEXT: s_lshl_b32 s66, s58, 16
-; SI-NEXT: s_lshl_b32 s75, s87, 16
-; SI-NEXT: s_mov_b32 s73, s6
-; SI-NEXT: s_lshl_b32 s67, s6, 16
-; SI-NEXT: s_lshl_b32 s76, s83, 16
-; SI-NEXT: s_mov_b32 s16, s68
-; SI-NEXT: s_lshl_b32 s68, s68, 16
-; SI-NEXT: s_lshl_b32 s85, s84, 16
-; SI-NEXT: s_mov_b32 s98, s69
-; SI-NEXT: s_lshl_b32 s69, s69, 16
-; SI-NEXT: s_lshl_b32 s17, s80, 16
-; SI-NEXT: s_mov_b32 s6, s62
-; SI-NEXT: s_lshl_b32 s26, s62, 16
+; SI-NEXT: s_lshl_b32 s4, s72, 16
+; SI-NEXT: v_writelane_b32 v41, s4, 35
+; SI-NEXT: s_lshl_b32 s4, s74, 16
+; SI-NEXT: s_lshl_b32 s16, s22, 16
+; SI-NEXT: v_writelane_b32 v41, s4, 37
+; SI-NEXT: s_lshl_b32 s6, s24, 16
+; SI-NEXT: s_lshl_b32 s73, s76, 16
+; SI-NEXT: s_lshl_b32 s98, s26, 16
+; SI-NEXT: s_lshl_b32 s63, s78, 16
+; SI-NEXT: s_lshl_b32 s96, s28, 16
+; SI-NEXT: s_lshl_b32 s62, s88, 16
+; SI-NEXT: s_lshl_b32 s97, s5, 16
+; SI-NEXT: s_lshl_b32 s99, s77, 16
+; SI-NEXT: s_lshl_b32 s85, s90, 16
+; SI-NEXT: s_lshl_b32 s86, s79, 16
+; SI-NEXT: s_lshl_b32 s81, s92, 16
+; SI-NEXT: s_lshl_b32 s82, s91, 16
+; SI-NEXT: s_lshl_b32 s70, s94, 16
+; SI-NEXT: s_lshl_b32 s71, s93, 16
+; SI-NEXT: s_lshl_b32 s68, s30, 16
+; SI-NEXT: s_lshl_b32 s69, s95, 16
+; SI-NEXT: s_lshl_b32 s66, s34, 16
+; SI-NEXT: s_lshl_b32 s67, s31, 16
+; SI-NEXT: s_lshl_b32 s64, s36, 16
+; SI-NEXT: s_lshl_b32 s65, s35, 16
+; SI-NEXT: s_lshl_b32 s54, s38, 16
+; SI-NEXT: s_lshl_b32 s55, s37, 16
+; SI-NEXT: s_lshl_b32 s52, s27, 16
+; SI-NEXT: s_lshl_b32 s53, s39, 16
+; SI-NEXT: s_lshl_b32 s50, s29, 16
+; SI-NEXT: s_lshl_b32 s51, s25, 16
+; SI-NEXT: s_lshl_b32 s48, s7, 16
+; SI-NEXT: s_lshl_b32 s49, s89, 16
+; SI-NEXT: s_lshl_b32 s38, s9, 16
+; SI-NEXT: s_lshl_b32 s39, s8, 16
+; SI-NEXT: s_lshl_b32 s37, s11, 16
+; SI-NEXT: s_lshl_b32 s35, s10, 16
+; SI-NEXT: s_lshl_b32 s31, s13, 16
+; SI-NEXT: s_lshl_b32 s36, s12, 16
+; SI-NEXT: s_lshl_b32 s95, s15, 16
+; SI-NEXT: s_lshl_b32 s34, s14, 16
+; SI-NEXT: s_lshl_b32 s93, s41, 16
+; SI-NEXT: s_lshl_b32 s30, s40, 16
+; SI-NEXT: s_lshl_b32 s91, s43, 16
+; SI-NEXT: s_lshl_b32 s94, s42, 16
+; SI-NEXT: s_lshl_b32 s92, s45, 16
+; SI-NEXT: s_lshl_b32 s90, s44, 16
+; SI-NEXT: s_lshl_b32 s88, s47, 16
+; SI-NEXT: s_lshl_b32 s28, s46, 16
+; SI-NEXT: s_lshl_b32 s78, s57, 16
+; SI-NEXT: s_lshl_b32 s26, s56, 16
+; SI-NEXT: s_lshl_b32 s76, s59, 16
+; SI-NEXT: s_lshl_b32 s24, s58, 16
+; SI-NEXT: s_lshl_b32 s74, s87, 16
+; SI-NEXT: s_mov_b32 s77, s18
+; SI-NEXT: s_lshl_b32 s22, s18, 16
+; SI-NEXT: s_lshl_b32 s72, s83, 16
+; SI-NEXT: s_mov_b32 s79, s23
+; SI-NEXT: s_lshl_b32 s20, s23, 16
+; SI-NEXT: s_lshl_b32 s61, s84, 16
+; SI-NEXT: s_mov_b32 s18, s75
+; SI-NEXT: s_lshl_b32 s19, s75, 16
+; SI-NEXT: s_lshl_b32 s60, s80, 16
+; SI-NEXT: s_lshl_b32 s17, s21, 16
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB107_3
; SI-NEXT: .LBB107_2:
-; SI-NEXT: ; implicit-def: $sgpr17
-; SI-NEXT: ; kill: killed $sgpr17
-; SI-NEXT: s_mov_b32 s16, s68
-; SI-NEXT: ; implicit-def: $sgpr17
-; SI-NEXT: ; kill: killed $sgpr17
-; SI-NEXT: s_mov_b32 s73, s6
-; SI-NEXT: ; implicit-def: $sgpr17
-; SI-NEXT: ; kill: killed $sgpr17
-; SI-NEXT: s_mov_b32 s6, s62
-; SI-NEXT: ; implicit-def: $sgpr17
-; SI-NEXT: ; kill: killed $sgpr17
-; SI-NEXT: s_mov_b32 s98, s69
-; SI-NEXT: ; implicit-def: $sgpr17
-; SI-NEXT: ; kill: killed $sgpr17
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s79, s23
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s77, s18
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s18, s75
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: ; kill: killed $sgpr6
; SI-NEXT: s_mov_b64 s[4:5], -1
-; SI-NEXT: ; implicit-def: $sgpr17
-; SI-NEXT: ; kill: killed $sgpr17
-; SI-NEXT: ; implicit-def: $sgpr7
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: ; implicit-def: $sgpr16
+; SI-NEXT: ; implicit-def: $sgpr73
+; SI-NEXT: ; implicit-def: $sgpr98
+; SI-NEXT: ; implicit-def: $sgpr63
; SI-NEXT: ; implicit-def: $sgpr96
-; SI-NEXT: ; implicit-def: $sgpr99
+; SI-NEXT: ; implicit-def: $sgpr62
; SI-NEXT: ; implicit-def: $sgpr97
-; SI-NEXT: ; implicit-def: $sgpr92
-; SI-NEXT: ; implicit-def: $sgpr94
-; SI-NEXT: ; implicit-def: $sgpr95
-; SI-NEXT: ; implicit-def: $sgpr93
-; SI-NEXT: ; implicit-def: $sgpr30
-; SI-NEXT: ; implicit-def: $sgpr31
-; SI-NEXT: ; implicit-def: $sgpr34
-; SI-NEXT: ; implicit-def: $sgpr35
+; SI-NEXT: ; implicit-def: $sgpr99
+; SI-NEXT: ; implicit-def: $sgpr85
; SI-NEXT: ; implicit-def: $sgpr86
-; SI-NEXT: ; implicit-def: $sgpr36
-; SI-NEXT: ; implicit-def: $sgpr22
-; SI-NEXT: ; implicit-def: $sgpr37
-; SI-NEXT: ; implicit-def: $sgpr24
-; SI-NEXT: ; implicit-def: $sgpr38
-; SI-NEXT: ; implicit-def: $sgpr28
-; SI-NEXT: ; implicit-def: $sgpr39
-; SI-NEXT: ; implicit-def: $sgpr61
-; SI-NEXT: ; implicit-def: $sgpr48
-; SI-NEXT: ; implicit-def: $sgpr89
-; SI-NEXT: ; implicit-def: $sgpr49
-; SI-NEXT: ; implicit-def: $sgpr60
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; implicit-def: $sgpr90
-; SI-NEXT: ; implicit-def: $sgpr91
-; SI-NEXT: ; implicit-def: $sgpr70
-; SI-NEXT: ; implicit-def: $sgpr51
-; SI-NEXT: ; implicit-def: $sgpr71
-; SI-NEXT: ; implicit-def: $sgpr52
-; SI-NEXT: ; implicit-def: $sgpr20
-; SI-NEXT: ; implicit-def: $sgpr53
; SI-NEXT: ; implicit-def: $sgpr81
-; SI-NEXT: ; implicit-def: $sgpr54
-; SI-NEXT: ; implicit-def: $sgpr63
-; SI-NEXT: ; implicit-def: $sgpr55
-; SI-NEXT: ; implicit-def: $sgpr72
-; SI-NEXT: ; implicit-def: $sgpr64
; SI-NEXT: ; implicit-def: $sgpr82
-; SI-NEXT: ; implicit-def: $sgpr65
-; SI-NEXT: ; implicit-def: $sgpr74
-; SI-NEXT: ; implicit-def: $sgpr66
-; SI-NEXT: ; implicit-def: $sgpr75
-; SI-NEXT: ; implicit-def: $sgpr67
-; SI-NEXT: ; implicit-def: $sgpr76
+; SI-NEXT: ; implicit-def: $sgpr70
+; SI-NEXT: ; implicit-def: $sgpr71
; SI-NEXT: ; implicit-def: $sgpr68
-; SI-NEXT: ; implicit-def: $sgpr85
; SI-NEXT: ; implicit-def: $sgpr69
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr54
+; SI-NEXT: ; implicit-def: $sgpr55
+; SI-NEXT: ; implicit-def: $sgpr52
+; SI-NEXT: ; implicit-def: $sgpr53
+; SI-NEXT: ; implicit-def: $sgpr50
+; SI-NEXT: ; implicit-def: $sgpr51
+; SI-NEXT: ; implicit-def: $sgpr48
+; SI-NEXT: ; implicit-def: $sgpr49
+; SI-NEXT: ; implicit-def: $sgpr38
+; SI-NEXT: ; implicit-def: $sgpr39
+; SI-NEXT: ; implicit-def: $sgpr37
+; SI-NEXT: ; implicit-def: $sgpr35
+; SI-NEXT: ; implicit-def: $sgpr31
+; SI-NEXT: ; implicit-def: $sgpr36
+; SI-NEXT: ; implicit-def: $sgpr95
+; SI-NEXT: ; implicit-def: $sgpr34
+; SI-NEXT: ; implicit-def: $sgpr93
+; SI-NEXT: ; implicit-def: $sgpr30
+; SI-NEXT: ; implicit-def: $sgpr91
+; SI-NEXT: ; implicit-def: $sgpr94
+; SI-NEXT: ; implicit-def: $sgpr92
+; SI-NEXT: ; implicit-def: $sgpr90
+; SI-NEXT: ; implicit-def: $sgpr88
+; SI-NEXT: ; implicit-def: $sgpr28
+; SI-NEXT: ; implicit-def: $sgpr78
; SI-NEXT: ; implicit-def: $sgpr26
+; SI-NEXT: ; implicit-def: $sgpr76
+; SI-NEXT: ; implicit-def: $sgpr24
+; SI-NEXT: ; implicit-def: $sgpr74
+; SI-NEXT: ; implicit-def: $sgpr22
+; SI-NEXT: ; implicit-def: $sgpr72
+; SI-NEXT: ; implicit-def: $sgpr20
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr19
+; SI-NEXT: ; implicit-def: $sgpr60
; SI-NEXT: ; implicit-def: $sgpr17
-; SI-NEXT: ; kill: killed $sgpr17
-; SI-NEXT: ; implicit-def: $sgpr17
-; SI-NEXT: ; kill: killed $sgpr17
-; SI-NEXT: ; implicit-def: $sgpr17
-; SI-NEXT: ; kill: killed $sgpr17
-; SI-NEXT: ; implicit-def: $sgpr17
-; SI-NEXT: ; kill: killed $sgpr17
-; SI-NEXT: ; implicit-def: $sgpr17
-; SI-NEXT: ; kill: killed $sgpr17
-; SI-NEXT: ; implicit-def: $sgpr17
-; SI-NEXT: ; kill: killed $sgpr17
-; SI-NEXT: ; implicit-def: $sgpr17
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: .LBB107_3: ; %Flow
; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5]
+; SI-NEXT: s_mov_b32 s4, s60
; SI-NEXT: s_mov_b32 s5, s17
-; SI-NEXT: s_mov_b32 s17, s86
-; SI-NEXT: s_mov_b32 s86, s7
+; SI-NEXT: s_mov_b32 s17, s61
+; SI-NEXT: s_mov_b32 s60, s72
+; SI-NEXT: s_mov_b32 s61, s74
+; SI-NEXT: s_mov_b32 s72, s76
+; SI-NEXT: s_mov_b32 s74, s78
+; SI-NEXT: s_mov_b32 s76, s88
+; SI-NEXT: s_mov_b32 s78, s92
+; SI-NEXT: s_mov_b32 s88, s91
+; SI-NEXT: s_mov_b32 s91, s93
+; SI-NEXT: s_mov_b32 s92, s94
+; SI-NEXT: s_mov_b32 s93, s95
+; SI-NEXT: s_mov_b32 s94, s30
+; SI-NEXT: s_mov_b32 s95, s31
+; SI-NEXT: s_mov_b32 s30, s34
+; SI-NEXT: s_mov_b32 s31, s37
+; SI-NEXT: s_mov_b32 s34, s36
+; SI-NEXT: s_mov_b32 s36, s38
+; SI-NEXT: s_mov_b32 s37, s39
+; SI-NEXT: s_mov_b32 s38, s48
+; SI-NEXT: s_mov_b32 s39, s49
+; SI-NEXT: s_mov_b32 s48, s50
+; SI-NEXT: s_mov_b32 s49, s51
+; SI-NEXT: s_mov_b32 s50, s52
+; SI-NEXT: s_mov_b32 s51, s53
+; SI-NEXT: s_mov_b32 s52, s54
+; SI-NEXT: s_mov_b32 s53, s55
+; SI-NEXT: s_mov_b32 s54, s6
+; SI-NEXT: s_mov_b32 s55, s16
; SI-NEXT: s_cbranch_vccnz .LBB107_5
; SI-NEXT: ; %bb.4: ; %cmp.true
-; SI-NEXT: s_lshl_b32 s5, s6, 16
-; SI-NEXT: v_readlane_b32 s6, v41, 24
-; SI-NEXT: s_lshl_b32 s20, s6, 16
-; SI-NEXT: v_readlane_b32 s6, v41, 23
-; SI-NEXT: s_lshl_b32 s17, s6, 16
-; SI-NEXT: v_readlane_b32 s6, v41, 22
-; SI-NEXT: s_lshl_b32 s61, s16, 16
-; SI-NEXT: s_add_i32 s16, s6, 3
-; SI-NEXT: v_readlane_b32 s6, v41, 21
-; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s6, 16
-; SI-NEXT: v_readlane_b32 s6, v41, 20
-; SI-NEXT: s_or_b32 s7, s7, s16
-; SI-NEXT: s_add_i32 s6, s6, 3
-; SI-NEXT: v_readlane_b32 s16, v41, 19
-; SI-NEXT: s_add_i32 s19, s19, 3
-; SI-NEXT: s_and_b32 s6, s6, 0xffff
-; SI-NEXT: s_lshl_b32 s16, s16, 16
-; SI-NEXT: s_and_b32 s19, s19, 0xffff
-; SI-NEXT: s_or_b32 s6, s16, s6
-; SI-NEXT: v_readlane_b32 s16, v41, 18
-; SI-NEXT: s_lshl_b32 s60, s98, 16
-; SI-NEXT: s_or_b32 s17, s17, s19
-; SI-NEXT: s_add_i32 s98, s16, 3
-; SI-NEXT: v_readlane_b32 s19, v41, 17
-; SI-NEXT: s_add_i32 s21, s21, 3
-; SI-NEXT: s_and_b32 s16, s98, 0xffff
-; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_add_i32 s11, s11, 3
-; SI-NEXT: s_add_i32 s9, s9, 3
-; SI-NEXT: s_and_b32 s21, s21, 0xffff
-; SI-NEXT: s_or_b32 s16, s19, s16
-; SI-NEXT: v_readlane_b32 s19, v41, 16
; SI-NEXT: s_add_i32 s13, s13, 3
+; SI-NEXT: s_and_b32 s13, s13, 0xffff
+; SI-NEXT: s_lshl_b32 s12, s12, 16
+; SI-NEXT: s_add_i32 s11, s11, 3
+; SI-NEXT: v_readlane_b32 s6, v41, 30
+; SI-NEXT: s_add_i32 s15, s15, 3
+; SI-NEXT: s_or_b32 s12, s12, s13
; SI-NEXT: s_and_b32 s11, s11, 0xffff
; SI-NEXT: s_lshl_b32 s10, s10, 16
+; SI-NEXT: s_lshl_b32 s13, s6, 16
+; SI-NEXT: v_readlane_b32 s6, v41, 29
+; SI-NEXT: s_and_b32 s15, s15, 0xffff
+; SI-NEXT: s_lshl_b32 s14, s14, 16
+; SI-NEXT: s_or_b32 s10, s10, s11
+; SI-NEXT: s_lshl_b32 s11, s25, 16
+; SI-NEXT: s_add_i32 s25, s6, 3
+; SI-NEXT: v_readlane_b32 s6, v41, 28
+; SI-NEXT: s_or_b32 s14, s14, s15
+; SI-NEXT: s_lshl_b32 s15, s6, 16
+; SI-NEXT: v_readlane_b32 s6, v41, 27
+; SI-NEXT: s_add_i32 s23, s6, 3
+; SI-NEXT: v_readlane_b32 s6, v41, 26
+; SI-NEXT: s_add_i32 s9, s9, 3
+; SI-NEXT: s_lshl_b32 s20, s6, 16
+; SI-NEXT: v_readlane_b32 s6, v41, 25
+; SI-NEXT: s_lshl_b32 s5, s21, 16
; SI-NEXT: s_and_b32 s9, s9, 0xffff
; SI-NEXT: s_lshl_b32 s8, s8, 16
-; SI-NEXT: s_add_i32 s29, s29, 3
-; SI-NEXT: s_or_b32 s20, s20, s21
-; SI-NEXT: s_add_i32 s96, s19, 3
-; SI-NEXT: v_readlane_b32 s21, v41, 15
-; SI-NEXT: s_add_i32 s15, s15, 3
-; SI-NEXT: s_and_b32 s13, s13, 0xffff
-; SI-NEXT: s_lshl_b32 s12, s12, 16
-; SI-NEXT: s_or_b32 s10, s10, s11
+; SI-NEXT: s_add_i32 s7, s7, 3
+; SI-NEXT: s_add_i32 s21, s6, 3
+; SI-NEXT: v_readlane_b32 s6, v41, 23
; SI-NEXT: s_or_b32 s8, s8, s9
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: s_lshl_b32 s9, s89, 16
+; SI-NEXT: s_add_i32 s29, s29, 3
+; SI-NEXT: s_lshl_b32 s19, s6, 16
+; SI-NEXT: v_readlane_b32 s6, v41, 22
+; SI-NEXT: s_or_b32 s7, s9, s7
; SI-NEXT: s_and_b32 s9, s29, 0xffff
-; SI-NEXT: s_lshl_b32 s11, s88, 16
; SI-NEXT: s_add_i32 s27, s27, 3
-; SI-NEXT: s_and_b32 s19, s96, 0xffff
-; SI-NEXT: s_lshl_b32 s21, s21, 16
-; SI-NEXT: s_and_b32 s15, s15, 0xffff
-; SI-NEXT: s_lshl_b32 s14, s14, 16
-; SI-NEXT: s_or_b32 s12, s12, s13
+; SI-NEXT: s_add_i32 s16, s6, 3
+; SI-NEXT: v_readlane_b32 s6, v41, 21
; SI-NEXT: s_or_b32 s9, s11, s9
; SI-NEXT: s_and_b32 s11, s27, 0xffff
-; SI-NEXT: s_lshl_b32 s13, s79, 16
-; SI-NEXT: s_add_i32 s25, s25, 3
-; SI-NEXT: s_or_b32 s19, s21, s19
-; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: v_readlane_b32 s21, v41, 14
-; SI-NEXT: s_or_b32 s14, s14, s15
+; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_lshl_b32 s17, s6, 16
+; SI-NEXT: v_readlane_b32 s6, v41, 20
; SI-NEXT: s_or_b32 s11, s13, s11
; SI-NEXT: s_and_b32 s13, s25, 0xffff
-; SI-NEXT: s_lshl_b32 s15, s78, 16
-; SI-NEXT: s_add_i32 s23, s23, 3
-; SI-NEXT: s_and_b32 s18, s18, 0xffff
-; SI-NEXT: s_lshl_b32 s21, s21, 16
+; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s6, s6, 3
+; SI-NEXT: v_readlane_b32 s17, v41, 19
; SI-NEXT: s_or_b32 s13, s15, s13
; SI-NEXT: s_and_b32 s15, s23, 0xffff
-; SI-NEXT: s_lshl_b32 s22, s77, 16
+; SI-NEXT: s_and_b32 s6, s6, 0xffff
+; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s60, s18, 16
+; SI-NEXT: s_or_b32 s15, s20, s15
+; SI-NEXT: s_and_b32 s20, s21, 0xffff
+; SI-NEXT: s_or_b32 s6, s17, s6
+; SI-NEXT: v_readlane_b32 s17, v41, 18
+; SI-NEXT: v_readlane_b32 s18, v41, 17
+; SI-NEXT: s_or_b32 s19, s19, s20
+; SI-NEXT: s_add_i32 s98, s17, 3
+; SI-NEXT: s_lshl_b32 s20, s18, 16
+; SI-NEXT: v_readlane_b32 s18, v41, 16
+; SI-NEXT: s_and_b32 s17, s98, 0xffff
+; SI-NEXT: s_add_i32 s96, s18, 3
+; SI-NEXT: v_readlane_b32 s18, v41, 15
+; SI-NEXT: s_or_b32 s17, s20, s17
+; SI-NEXT: s_and_b32 s20, s96, 0xffff
+; SI-NEXT: s_lshl_b32 s21, s18, 16
+; SI-NEXT: v_readlane_b32 s18, v41, 24
+; SI-NEXT: s_or_b32 s20, s21, s20
+; SI-NEXT: s_add_i32 s18, s18, 3
+; SI-NEXT: v_readlane_b32 s21, v41, 14
+; SI-NEXT: s_and_b32 s18, s18, 0xffff
+; SI-NEXT: s_lshl_b32 s21, s21, 16
; SI-NEXT: s_or_b32 s18, s21, s18
; SI-NEXT: v_readlane_b32 s21, v41, 13
-; SI-NEXT: s_or_b32 s15, s22, s15
; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: v_readlane_b32 s22, v41, 12
; SI-NEXT: s_and_b32 s21, s21, 0xffff
@@ -239293,42 +240674,20 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: s_and_b32 s27, s27, 0xffff
; SI-NEXT: s_lshl_b32 s28, s28, 16
; SI-NEXT: s_or_b32 s27, s28, s27
-; SI-NEXT: s_add_i32 s27, s27, 0x30000
-; SI-NEXT: s_add_i32 s26, s26, 0x30000
-; SI-NEXT: s_and_b32 s86, s27, 0xffff0000
-; SI-NEXT: s_lshl_b32 s27, s27, 16
-; SI-NEXT: s_add_i32 s25, s25, 0x30000
-; SI-NEXT: v_writelane_b32 v41, s27, 25
-; SI-NEXT: s_and_b32 s96, s26, 0xffff0000
-; SI-NEXT: s_lshl_b32 s26, s26, 16
-; SI-NEXT: s_add_i32 s24, s24, 0x30000
-; SI-NEXT: v_writelane_b32 v41, s26, 26
-; SI-NEXT: s_and_b32 s99, s25, 0xffff0000
-; SI-NEXT: s_lshl_b32 s25, s25, 16
-; SI-NEXT: s_add_i32 s23, s23, 0x30000
-; SI-NEXT: v_writelane_b32 v41, s25, 27
-; SI-NEXT: s_and_b32 s97, s24, 0xffff0000
-; SI-NEXT: s_lshl_b32 s24, s24, 16
; SI-NEXT: s_add_i32 s80, s80, 3
-; SI-NEXT: s_add_i32 s22, s22, 0x30000
-; SI-NEXT: v_writelane_b32 v41, s24, 28
-; SI-NEXT: s_and_b32 s92, s23, 0xffff0000
-; SI-NEXT: s_lshl_b32 s23, s23, 16
+; SI-NEXT: s_add_i32 s27, s27, 0x30000
; SI-NEXT: s_and_b32 s4, s80, 0xffff
; SI-NEXT: s_add_i32 s84, s84, 3
-; SI-NEXT: s_add_i32 s21, s21, 0x30000
-; SI-NEXT: v_writelane_b32 v41, s23, 29
-; SI-NEXT: s_and_b32 s94, s22, 0xffff0000
-; SI-NEXT: s_lshl_b32 s22, s22, 16
+; SI-NEXT: s_and_b32 s28, s27, 0xffff0000
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_and_b32 s5, s84, 0xffff
; SI-NEXT: s_add_i32 s83, s83, 3
-; SI-NEXT: s_add_i32 s18, s18, 0x30000
-; SI-NEXT: v_writelane_b32 v41, s22, 30
-; SI-NEXT: s_and_b32 s95, s21, 0xffff0000
-; SI-NEXT: s_lshl_b32 s21, s21, 16
+; SI-NEXT: s_add_i32 s26, s26, 0x30000
+; SI-NEXT: v_writelane_b32 v41, s28, 31
+; SI-NEXT: s_lshl_b32 s27, s27, 16
; SI-NEXT: s_or_b32 s5, s60, s5
; SI-NEXT: s_and_b32 s60, s83, 0xffff
+; SI-NEXT: s_lshl_b32 s61, s79, 16
; SI-NEXT: s_add_i32 s87, s87, 3
; SI-NEXT: s_add_i32 s59, s59, 3
; SI-NEXT: s_add_i32 s57, s57, 3
@@ -239336,13 +240695,11 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: s_add_i32 s45, s45, 3
; SI-NEXT: s_add_i32 s43, s43, 3
; SI-NEXT: s_add_i32 s41, s41, 3
-; SI-NEXT: s_add_i32 s19, s19, 0x30000
-; SI-NEXT: v_writelane_b32 v41, s21, 31
-; SI-NEXT: s_and_b32 s93, s18, 0xffff0000
-; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_or_b32 s76, s61, s60
+; SI-NEXT: v_writelane_b32 v41, s27, 32
+; SI-NEXT: s_and_b32 s27, s26, 0xffff0000
+; SI-NEXT: s_or_b32 vcc_lo, s61, s60
; SI-NEXT: s_and_b32 s60, s87, 0xffff
-; SI-NEXT: s_lshl_b32 s61, s73, 16
+; SI-NEXT: s_lshl_b32 s61, s77, 16
; SI-NEXT: s_and_b32 s59, s59, 0xffff
; SI-NEXT: s_lshl_b32 s58, s58, 16
; SI-NEXT: s_and_b32 s57, s57, 0xffff
@@ -239355,24 +240712,22 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: s_lshl_b32 s42, s42, 16
; SI-NEXT: s_and_b32 s41, s41, 0xffff
; SI-NEXT: s_lshl_b32 s40, s40, 16
-; SI-NEXT: s_add_i32 s16, s16, 0x30000
-; SI-NEXT: v_writelane_b32 v41, s18, 32
-; SI-NEXT: s_lshl_b32 s18, s19, 16
-; SI-NEXT: s_or_b32 s75, s61, s60
+; SI-NEXT: s_add_i32 s25, s25, 0x30000
+; SI-NEXT: v_writelane_b32 v41, s27, 33
+; SI-NEXT: s_lshl_b32 s26, s26, 16
+; SI-NEXT: s_or_b32 vcc_hi, s61, s60
; SI-NEXT: s_or_b32 s58, s58, s59
; SI-NEXT: s_or_b32 s56, s56, s57
; SI-NEXT: s_or_b32 s46, s46, s47
; SI-NEXT: s_or_b32 s44, s44, s45
; SI-NEXT: s_or_b32 s42, s42, s43
; SI-NEXT: s_or_b32 s40, s40, s41
-; SI-NEXT: s_add_i32 s6, s6, 0x30000
-; SI-NEXT: v_writelane_b32 v41, s18, 33
-; SI-NEXT: s_and_b32 s31, s16, 0xffff0000
-; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: v_writelane_b32 v41, s26, 34
+; SI-NEXT: s_and_b32 s26, s25, 0xffff0000
; SI-NEXT: s_add_i32 s4, s4, 0x30000
; SI-NEXT: s_add_i32 s5, s5, 0x30000
-; SI-NEXT: s_add_i32 s76, s76, 0x30000
-; SI-NEXT: s_add_i32 s75, s75, 0x30000
+; SI-NEXT: s_add_i32 vcc_lo, vcc_lo, 0x30000
+; SI-NEXT: s_add_i32 vcc_hi, vcc_hi, 0x30000
; SI-NEXT: s_add_i32 s58, s58, 0x30000
; SI-NEXT: s_add_i32 s56, s56, 0x30000
; SI-NEXT: s_add_i32 s46, s46, 0x30000
@@ -239383,294 +240738,311 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: s_add_i32 s12, s12, 0x30000
; SI-NEXT: s_add_i32 s10, s10, 0x30000
; SI-NEXT: s_add_i32 s8, s8, 0x30000
+; SI-NEXT: s_add_i32 s7, s7, 0x30000
; SI-NEXT: s_add_i32 s9, s9, 0x30000
; SI-NEXT: s_add_i32 s11, s11, 0x30000
; SI-NEXT: s_add_i32 s13, s13, 0x30000
; SI-NEXT: s_add_i32 s15, s15, 0x30000
-; SI-NEXT: s_add_i32 s20, s20, 0x30000
+; SI-NEXT: s_add_i32 s19, s19, 0x30000
+; SI-NEXT: s_add_i32 s16, s16, 0x30000
+; SI-NEXT: s_add_i32 s6, s6, 0x30000
; SI-NEXT: s_add_i32 s17, s17, 0x30000
-; SI-NEXT: s_add_i32 s7, s7, 0x30000
-; SI-NEXT: v_writelane_b32 v41, s16, 34
-; SI-NEXT: s_and_b32 s34, s6, 0xffff0000
-; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: s_and_b32 s30, s19, 0xffff0000
-; SI-NEXT: v_writelane_b32 v41, s6, 35
-; SI-NEXT: s_and_b32 s35, s7, 0xffff0000
-; SI-NEXT: s_lshl_b32 s6, s7, 16
-; SI-NEXT: s_and_b32 s36, s17, 0xffff0000
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_and_b32 s37, s20, 0xffff0000
-; SI-NEXT: s_lshl_b32 s22, s20, 16
-; SI-NEXT: s_and_b32 s38, s15, 0xffff0000
-; SI-NEXT: s_lshl_b32 s24, s15, 16
-; SI-NEXT: s_and_b32 s39, s13, 0xffff0000
-; SI-NEXT: s_lshl_b32 s28, s13, 16
-; SI-NEXT: s_and_b32 s48, s11, 0xffff0000
-; SI-NEXT: s_lshl_b32 s61, s11, 16
+; SI-NEXT: s_add_i32 s20, s20, 0x30000
+; SI-NEXT: s_add_i32 s18, s18, 0x30000
+; SI-NEXT: s_add_i32 s21, s21, 0x30000
+; SI-NEXT: s_add_i32 s22, s22, 0x30000
+; SI-NEXT: s_add_i32 s23, s23, 0x30000
+; SI-NEXT: s_add_i32 s24, s24, 0x30000
+; SI-NEXT: v_writelane_b32 v41, s26, 35
+; SI-NEXT: s_lshl_b32 s25, s25, 16
+; SI-NEXT: v_writelane_b32 v41, s25, 36
+; SI-NEXT: s_and_b32 s25, s24, 0xffff0000
+; SI-NEXT: s_lshl_b32 s55, s24, 16
+; SI-NEXT: s_and_b32 s73, s23, 0xffff0000
+; SI-NEXT: s_lshl_b32 s54, s23, 16
+; SI-NEXT: s_and_b32 s63, s22, 0xffff0000
+; SI-NEXT: s_lshl_b32 s98, s22, 16
+; SI-NEXT: s_and_b32 s62, s21, 0xffff0000
+; SI-NEXT: s_lshl_b32 s96, s21, 16
+; SI-NEXT: s_and_b32 s99, s18, 0xffff0000
+; SI-NEXT: s_lshl_b32 s97, s18, 16
+; SI-NEXT: s_and_b32 s86, s20, 0xffff0000
+; SI-NEXT: s_lshl_b32 s85, s20, 16
+; SI-NEXT: s_and_b32 s82, s17, 0xffff0000
+; SI-NEXT: s_lshl_b32 s81, s17, 16
+; SI-NEXT: s_and_b32 s71, s6, 0xffff0000
+; SI-NEXT: s_lshl_b32 s70, s6, 16
+; SI-NEXT: s_and_b32 s69, s16, 0xffff0000
+; SI-NEXT: s_lshl_b32 s68, s16, 16
+; SI-NEXT: s_and_b32 s67, s19, 0xffff0000
+; SI-NEXT: s_lshl_b32 s66, s19, 16
+; SI-NEXT: s_and_b32 s65, s15, 0xffff0000
+; SI-NEXT: s_lshl_b32 s64, s15, 16
+; SI-NEXT: s_and_b32 s53, s13, 0xffff0000
+; SI-NEXT: s_lshl_b32 s52, s13, 16
+; SI-NEXT: s_and_b32 s51, s11, 0xffff0000
+; SI-NEXT: s_lshl_b32 s50, s11, 16
; SI-NEXT: s_and_b32 s49, s9, 0xffff0000
-; SI-NEXT: s_lshl_b32 s89, s9, 16
-; SI-NEXT: s_and_b32 s50, s8, 0xffff0000
-; SI-NEXT: s_lshl_b32 s60, s8, 16
-; SI-NEXT: s_and_b32 s91, s10, 0xffff0000
-; SI-NEXT: s_lshl_b32 s90, s10, 16
-; SI-NEXT: s_and_b32 s51, s12, 0xffff0000
-; SI-NEXT: s_lshl_b32 s70, s12, 16
-; SI-NEXT: s_and_b32 s52, s14, 0xffff0000
-; SI-NEXT: s_lshl_b32 s71, s14, 16
-; SI-NEXT: s_and_b32 s53, s40, 0xffff0000
-; SI-NEXT: s_lshl_b32 s20, s40, 16
-; SI-NEXT: s_and_b32 s54, s42, 0xffff0000
-; SI-NEXT: s_lshl_b32 s81, s42, 16
-; SI-NEXT: s_and_b32 s55, s44, 0xffff0000
-; SI-NEXT: s_lshl_b32 s63, s44, 16
-; SI-NEXT: s_and_b32 s64, s46, 0xffff0000
-; SI-NEXT: s_lshl_b32 s72, s46, 16
-; SI-NEXT: s_and_b32 s65, s56, 0xffff0000
-; SI-NEXT: s_lshl_b32 s82, s56, 16
-; SI-NEXT: s_and_b32 s66, s58, 0xffff0000
-; SI-NEXT: s_lshl_b32 s74, s58, 16
-; SI-NEXT: s_and_b32 s67, s75, 0xffff0000
-; SI-NEXT: s_lshl_b32 s75, s75, 16
-; SI-NEXT: s_and_b32 s68, s76, 0xffff0000
-; SI-NEXT: s_lshl_b32 s76, s76, 16
-; SI-NEXT: s_and_b32 s69, s5, 0xffff0000
-; SI-NEXT: s_lshl_b32 s85, s5, 16
-; SI-NEXT: s_and_b32 s26, s4, 0xffff0000
-; SI-NEXT: s_lshl_b32 s5, s4, 16
-; SI-NEXT: v_writelane_b32 v41, s6, 36
+; SI-NEXT: s_lshl_b32 s48, s9, 16
+; SI-NEXT: s_and_b32 s39, s7, 0xffff0000
+; SI-NEXT: s_lshl_b32 s38, s7, 16
+; SI-NEXT: s_and_b32 s37, s8, 0xffff0000
+; SI-NEXT: s_lshl_b32 s36, s8, 16
+; SI-NEXT: s_and_b32 s35, s10, 0xffff0000
+; SI-NEXT: s_lshl_b32 s31, s10, 16
+; SI-NEXT: s_and_b32 s34, s12, 0xffff0000
+; SI-NEXT: s_lshl_b32 s95, s12, 16
+; SI-NEXT: s_and_b32 s30, s14, 0xffff0000
+; SI-NEXT: s_lshl_b32 s93, s14, 16
+; SI-NEXT: s_and_b32 s94, s40, 0xffff0000
+; SI-NEXT: s_lshl_b32 s91, s40, 16
+; SI-NEXT: s_and_b32 s92, s42, 0xffff0000
+; SI-NEXT: s_lshl_b32 s88, s42, 16
+; SI-NEXT: s_and_b32 s90, s44, 0xffff0000
+; SI-NEXT: s_lshl_b32 s78, s44, 16
+; SI-NEXT: s_and_b32 s28, s46, 0xffff0000
+; SI-NEXT: s_lshl_b32 s76, s46, 16
+; SI-NEXT: s_and_b32 s26, s56, 0xffff0000
+; SI-NEXT: s_lshl_b32 s74, s56, 16
+; SI-NEXT: s_and_b32 s24, s58, 0xffff0000
+; SI-NEXT: s_lshl_b32 s72, s58, 16
+; SI-NEXT: s_and_b32 s22, vcc_hi, 0xffff0000
+; SI-NEXT: s_lshl_b32 s61, vcc_hi, 16
+; SI-NEXT: s_and_b32 s20, vcc_lo, 0xffff0000
+; SI-NEXT: s_lshl_b32 s60, vcc_lo, 16
+; SI-NEXT: s_and_b32 s19, s5, 0xffff0000
+; SI-NEXT: s_lshl_b32 s17, s5, 16
+; SI-NEXT: s_and_b32 s5, s4, 0xffff0000
+; SI-NEXT: s_lshl_b32 s4, s4, 16
+; SI-NEXT: v_writelane_b32 v41, s25, 37
; SI-NEXT: .LBB107_5: ; %end
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s86
-; SI-NEXT: v_readlane_b32 s4, v41, 25
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_readlane_b32 s6, v41, 31
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6
+; SI-NEXT: v_readlane_b32 s6, v41, 32
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_readlane_b32 s6, v41, 33
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s96
-; SI-NEXT: v_readlane_b32 s4, v41, 26
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6
+; SI-NEXT: v_readlane_b32 s6, v41, 34
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
+; SI-NEXT: v_readlane_b32 s6, v41, 35
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s99
-; SI-NEXT: v_readlane_b32 s4, v41, 27
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6
+; SI-NEXT: v_readlane_b32 s6, v41, 36
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
+; SI-NEXT: v_readlane_b32 s6, v41, 37
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s97
-; SI-NEXT: v_readlane_b32 s4, v41, 28
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s55
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s92
-; SI-NEXT: v_readlane_b32 s4, v41, 29
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s73
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s54
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s94
-; SI-NEXT: v_readlane_b32 s4, v41, 30
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s63
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s98
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s95
-; SI-NEXT: v_readlane_b32 s4, v41, 31
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s62
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s96
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s93
-; SI-NEXT: v_readlane_b32 s4, v41, 32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s99
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s97
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s30
-; SI-NEXT: v_readlane_b32 s4, v41, 33
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s86
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s85
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s31
-; SI-NEXT: v_readlane_b32 s4, v41, 34
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s82
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s81
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s34
-; SI-NEXT: v_readlane_b32 s4, v41, 35
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s71
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s70
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s35
-; SI-NEXT: v_readlane_b32 s4, v41, 36
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s69
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s68
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s36
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s17
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s67
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s66
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s37
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s22
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s65
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s64
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s38
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s24
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s53
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s52
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s39
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s28
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s51
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s50
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s49
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s48
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s61
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s49
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s89
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s39
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s38
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s50
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s60
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s37
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s36
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s91
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s90
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s35
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s31
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s51
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s70
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s34
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s95
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s52
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s71
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s30
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s93
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s53
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s20
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s94
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s91
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s54
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s81
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s92
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s88
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s55
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s63
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s90
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s78
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s64
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s72
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s28
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s76
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s65
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s82
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s26
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s74
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s66
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s74
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s24
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s72
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s67
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s75
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s22
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s61
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s68
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s76
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s20
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s60
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s69
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s85
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s17
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s26
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s5
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s5
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: v_readlane_b32 s99, v40, 35
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
index c6211aae19c1b..078ba76eb1f12 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
@@ -2853,50 +2853,52 @@ define inreg <4 x i32> @bitcast_v8bf16_to_v4i32_scalar(<8 x bfloat> inreg %a, i3
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s24, 0
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v15, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v8, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v13, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v12, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s22
; SI-NEXT: s_cbranch_scc0 .LBB23_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; SI-NEXT: v_alignbit_b32 v0, v0, v11, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v9, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v7, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v5, 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v15
+; SI-NEXT: v_lshr_b64 v[0:1], v[10:11], 16
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
+; SI-NEXT: v_lshr_b64 v[1:2], v[8:9], 16
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v13
+; SI-NEXT: v_lshr_b64 v[16:17], v[4:5], 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[6:7], 16
+; SI-NEXT: v_mov_b32_e32 v3, v16
; SI-NEXT: s_cbranch_execnz .LBB23_3
; SI-NEXT: .LBB23_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v15
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v8
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v9
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v8
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v12
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_mov_b32_e32 v3, v4
; SI-NEXT: .LBB23_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB23_4:
@@ -2912,78 +2914,80 @@ define inreg <4 x i32> @bitcast_v8bf16_to_v4i32_scalar(<8 x bfloat> inreg %a, i3
; VI-NEXT: s_cbranch_execnz .LBB23_4
; VI-NEXT: .LBB23_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v7, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v0
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v4, v1, 16
-; VI-NEXT: v_add_f32_e32 v4, s4, v0
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_bfe_u32 v5, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v0
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; VI-NEXT: v_lshrrev_b64 v[5:6], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v4, 16
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v5
+; VI-NEXT: v_mov_b32_e32 v3, v4
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB23_3:
; VI-NEXT: s_branch .LBB23_2
@@ -7392,50 +7396,52 @@ define inreg <4 x float> @bitcast_v8bf16_to_v4f32_scalar(<8 x bfloat> inreg %a,
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s24, 0
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v15, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v8, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v13, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v12, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s22
; SI-NEXT: s_cbranch_scc0 .LBB47_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; SI-NEXT: v_alignbit_b32 v0, v0, v11, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v9, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v7, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v5, 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v15
+; SI-NEXT: v_lshr_b64 v[0:1], v[10:11], 16
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
+; SI-NEXT: v_lshr_b64 v[1:2], v[8:9], 16
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v13
+; SI-NEXT: v_lshr_b64 v[16:17], v[4:5], 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[6:7], 16
+; SI-NEXT: v_mov_b32_e32 v3, v16
; SI-NEXT: s_cbranch_execnz .LBB47_3
; SI-NEXT: .LBB47_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v15
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v8
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v9
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v8
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v12
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_mov_b32_e32 v3, v4
; SI-NEXT: .LBB47_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB47_4:
@@ -7451,78 +7457,80 @@ define inreg <4 x float> @bitcast_v8bf16_to_v4f32_scalar(<8 x bfloat> inreg %a,
; VI-NEXT: s_cbranch_execnz .LBB47_4
; VI-NEXT: .LBB47_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v7, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v0
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v4, v1, 16
-; VI-NEXT: v_add_f32_e32 v4, s4, v0
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_bfe_u32 v5, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v0
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; VI-NEXT: v_lshrrev_b64 v[5:6], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v4, 16
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v5
+; VI-NEXT: v_mov_b32_e32 v3, v4
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB47_3:
; VI-NEXT: s_branch .LBB47_2
@@ -11581,50 +11589,52 @@ define inreg <2 x i64> @bitcast_v8bf16_to_v2i64_scalar(<8 x bfloat> inreg %a, i3
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s24, 0
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v15, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v8, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v13, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v12, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s22
; SI-NEXT: s_cbranch_scc0 .LBB67_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; SI-NEXT: v_alignbit_b32 v0, v0, v11, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v9, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v7, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v5, 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v15
+; SI-NEXT: v_lshr_b64 v[0:1], v[10:11], 16
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
+; SI-NEXT: v_lshr_b64 v[1:2], v[8:9], 16
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v13
+; SI-NEXT: v_lshr_b64 v[16:17], v[4:5], 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[6:7], 16
+; SI-NEXT: v_mov_b32_e32 v3, v16
; SI-NEXT: s_cbranch_execnz .LBB67_3
; SI-NEXT: .LBB67_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v15
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v8
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v9
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v8
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v12
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_mov_b32_e32 v3, v4
; SI-NEXT: .LBB67_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB67_4:
@@ -11640,78 +11650,80 @@ define inreg <2 x i64> @bitcast_v8bf16_to_v2i64_scalar(<8 x bfloat> inreg %a, i3
; VI-NEXT: s_cbranch_execnz .LBB67_4
; VI-NEXT: .LBB67_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v7, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v0
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v4, v1, 16
-; VI-NEXT: v_add_f32_e32 v4, s4, v0
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_bfe_u32 v5, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v0
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; VI-NEXT: v_lshrrev_b64 v[5:6], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v4, 16
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v5
+; VI-NEXT: v_mov_b32_e32 v3, v4
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB67_3:
; VI-NEXT: s_branch .LBB67_2
@@ -15349,50 +15361,52 @@ define inreg <2 x double> @bitcast_v8bf16_to_v2f64_scalar(<8 x bfloat> inreg %a,
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s24, 0
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v15, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v8, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v13, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v12, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s22
; SI-NEXT: s_cbranch_scc0 .LBB83_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; SI-NEXT: v_alignbit_b32 v0, v0, v11, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v9, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v7, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v5, 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v15
+; SI-NEXT: v_lshr_b64 v[0:1], v[10:11], 16
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
+; SI-NEXT: v_lshr_b64 v[1:2], v[8:9], 16
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v13
+; SI-NEXT: v_lshr_b64 v[16:17], v[4:5], 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[6:7], 16
+; SI-NEXT: v_mov_b32_e32 v3, v16
; SI-NEXT: s_cbranch_execnz .LBB83_3
; SI-NEXT: .LBB83_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v15
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v8
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v9
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v8
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v12
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_mov_b32_e32 v3, v4
; SI-NEXT: .LBB83_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB83_4:
@@ -15408,78 +15422,80 @@ define inreg <2 x double> @bitcast_v8bf16_to_v2f64_scalar(<8 x bfloat> inreg %a,
; VI-NEXT: s_cbranch_execnz .LBB83_4
; VI-NEXT: .LBB83_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v7, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v0
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v4, v1, 16
-; VI-NEXT: v_add_f32_e32 v4, s4, v0
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_bfe_u32 v5, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v0
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; VI-NEXT: v_lshrrev_b64 v[5:6], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v4, 16
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v5
+; VI-NEXT: v_mov_b32_e32 v3, v4
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB83_3:
; VI-NEXT: s_branch .LBB83_2
@@ -18720,64 +18736,66 @@ define inreg <8 x i16> @bitcast_v8bf16_to_v8i16_scalar(<8 x bfloat> inreg %a, i3
; SI-NEXT: s_cmp_lg_u32 s24, 0
; SI-NEXT: v_mul_f32_e64 v15, 1.0, s16
; SI-NEXT: v_mul_f32_e64 v14, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s19
; SI-NEXT: v_mul_f32_e64 v13, 1.0, s20
; SI-NEXT: v_mul_f32_e64 v12, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v11, 1.0, s23
; SI-NEXT: s_cbranch_scc0 .LBB95_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v10
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v11
; SI-NEXT: s_cbranch_execnz .LBB95_3
; SI-NEXT: .LBB95_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v14
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v15
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v12
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v14
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v13
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v12
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; SI-NEXT: v_lshr_b64 v[4:5], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v11
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v2
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_alignbit_b32 v6, v7, v3, 16
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_lshr_b64 v[8:9], v[6:7], 16
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: v_lshr_b64 v[10:11], v[1:2], 16
-; SI-NEXT: v_lshr_b64 v[8:9], v[5:6], 16
-; SI-NEXT: v_alignbit_b32 v4, v12, v13, 16
+; SI-NEXT: v_lshr_b64 v[9:10], v[2:3], 16
+; SI-NEXT: v_mov_b32_e32 v6, v8
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v14
+; SI-NEXT: v_mov_b32_e32 v2, v9
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
; SI-NEXT: .LBB95_3: ; %end
-; SI-NEXT: v_mov_b32_e32 v1, v10
-; SI-NEXT: v_mov_b32_e32 v5, v8
+; SI-NEXT: v_mov_b32_e32 v2, v9
+; SI-NEXT: v_mov_b32_e32 v6, v8
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB95_4:
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: s_branch .LBB95_2
;
@@ -18790,78 +18808,80 @@ define inreg <8 x i16> @bitcast_v8bf16_to_v8i16_scalar(<8 x bfloat> inreg %a, i3
; VI-NEXT: s_cbranch_execnz .LBB95_4
; VI-NEXT: .LBB95_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: v_mov_b32_e32 v7, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v7
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc
+; VI-NEXT: v_add_f32_e32 v2, s4, v7
+; VI-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v7
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v0
-; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
-; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v7
+; VI-NEXT: v_bfe_u32 v6, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v3
+; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; VI-NEXT: v_or_b32_e32 v8, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; VI-NEXT: v_add_f32_e32 v3, s4, v0
-; VI-NEXT: v_bfe_u32 v8, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc
+; VI-NEXT: v_add_f32_e32 v6, s4, v7
+; VI-NEXT: v_bfe_u32 v8, v6, 16, 1
+; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v6
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc
-; VI-NEXT: v_bfe_u32 v8, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v0
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v6
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
+; VI-NEXT: v_add_f32_e32 v7, s4, v7
+; VI-NEXT: v_cndmask_b32_e32 v6, v8, v9, vcc
+; VI-NEXT: v_bfe_u32 v8, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v7
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v8, v9, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v3, v0, v3, 16
-; VI-NEXT: v_alignbit_b32 v2, v7, v2, 16
-; VI-NEXT: v_alignbit_b32 v1, v6, v1, 16
-; VI-NEXT: v_alignbit_b32 v0, v5, v4, 16
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[6:7]
+; VI-NEXT: v_lshrrev_b64 v[3:4], 16, v[4:5]
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v3
+; VI-NEXT: v_mov_b32_e32 v3, v6
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB95_3:
; VI-NEXT: s_branch .LBB95_2
@@ -21770,78 +21790,80 @@ define inreg <8 x half> @bitcast_v8bf16_to_v8f16_scalar(<8 x bfloat> inreg %a, i
; VI-NEXT: s_cbranch_execnz .LBB103_4
; VI-NEXT: .LBB103_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: v_mov_b32_e32 v7, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v7
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v7
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v7
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc
+; VI-NEXT: v_add_f32_e32 v2, s4, v7
+; VI-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v7
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v0
-; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
-; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v7
+; VI-NEXT: v_bfe_u32 v6, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v3
+; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; VI-NEXT: v_or_b32_e32 v8, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; VI-NEXT: v_add_f32_e32 v3, s4, v0
-; VI-NEXT: v_bfe_u32 v8, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc
+; VI-NEXT: v_add_f32_e32 v6, s4, v7
+; VI-NEXT: v_bfe_u32 v8, v6, 16, 1
+; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v6
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc
-; VI-NEXT: v_bfe_u32 v8, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v0
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v6
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
+; VI-NEXT: v_add_f32_e32 v7, s4, v7
+; VI-NEXT: v_cndmask_b32_e32 v6, v8, v9, vcc
+; VI-NEXT: v_bfe_u32 v8, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v7
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v8, v9, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v3, v0, v3, 16
-; VI-NEXT: v_alignbit_b32 v2, v7, v2, 16
-; VI-NEXT: v_alignbit_b32 v1, v6, v1, 16
-; VI-NEXT: v_alignbit_b32 v0, v5, v4, 16
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[6:7]
+; VI-NEXT: v_lshrrev_b64 v[3:4], 16, v[4:5]
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v3
+; VI-NEXT: v_mov_b32_e32 v3, v6
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB103_3:
; VI-NEXT: s_branch .LBB103_2
@@ -24532,94 +24554,97 @@ define inreg <16 x i8> @bitcast_v8bf16_to_v16i8_scalar(<8 x bfloat> inreg %a, i3
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s24, 0
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v16, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v0, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v25, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v26, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v23, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v24, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v28, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v23, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v27, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v5, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v30, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v25, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v29, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v13, 1.0, s22
; SI-NEXT: s_cbranch_scc0 .LBB109_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; SI-NEXT: v_alignbit_b32 v19, v1, v16, 16
-; SI-NEXT: v_alignbit_b32 v20, v6, v8, 16
-; SI-NEXT: v_lshr_b64 v[1:2], v[19:20], 8
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v23
-; SI-NEXT: v_lshr_b64 v[3:4], v[19:20], 24
-; SI-NEXT: v_alignbit_b32 v21, v2, v26, 16
-; SI-NEXT: v_alignbit_b32 v22, v14, v24, 16
-; SI-NEXT: v_lshr_b64 v[4:5], v[19:20], 16
-; SI-NEXT: v_lshr_b64 v[10:11], v[21:22], 16
-; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v0
-; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v20
-; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v23
-; SI-NEXT: v_lshrrev_b32_e32 v13, 8, v22
-; SI-NEXT: v_lshr_b64 v[17:18], v[21:22], 24
-; SI-NEXT: v_lshr_b64 v[11:12], v[21:22], 8
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v28
+; SI-NEXT: v_lshr_b64 v[19:20], v[5:6], 16
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v29
+; SI-NEXT: v_lshr_b64 v[0:1], v[23:24], 16
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v30
+; SI-NEXT: v_lshr_b64 v[21:22], v[13:14], 16
+; SI-NEXT: v_mov_b32_e32 v1, v19
+; SI-NEXT: v_lshr_b64 v[8:9], v[25:26], 16
+; SI-NEXT: v_mov_b32_e32 v9, v21
+; SI-NEXT: v_lshr_b64 v[16:17], v[0:1], 16
+; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v27
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v29
+; SI-NEXT: v_lshrrev_b32_e32 v20, 8, v19
+; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v21
+; SI-NEXT: v_lshr_b64 v[3:4], v[0:1], 24
+; SI-NEXT: v_lshr_b64 v[1:2], v[0:1], 8
+; SI-NEXT: v_lshr_b64 v[11:12], v[8:9], 24
+; SI-NEXT: v_lshr_b64 v[17:18], v[8:9], 16
+; SI-NEXT: v_lshr_b64 v[9:10], v[8:9], 8
; SI-NEXT: s_cbranch_execnz .LBB109_3
; SI-NEXT: .LBB109_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v25
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v26
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_alignbit_b32 v21, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v23
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v24
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v15
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v9
-; SI-NEXT: v_alignbit_b32 v22, v14, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v30
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v25
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; SI-NEXT: v_alignbit_b32 v19, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v27
+; SI-NEXT: v_lshr_b64 v[8:9], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v23
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; SI-NEXT: v_alignbit_b32 v20, v6, v1, 16
-; SI-NEXT: v_lshr_b64 v[3:4], v[19:20], 24
-; SI-NEXT: v_lshr_b64 v[10:11], v[21:22], 16
-; SI-NEXT: v_lshr_b64 v[4:5], v[19:20], 16
-; SI-NEXT: v_lshr_b64 v[1:2], v[19:20], 8
-; SI-NEXT: v_lshr_b64 v[17:18], v[21:22], 24
-; SI-NEXT: v_lshr_b64 v[11:12], v[21:22], 8
-; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v20
-; SI-NEXT: v_lshrrev_b32_e32 v13, 8, v22
-; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v0
-; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v10
+; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshr_b64 v[19:20], v[5:6], 16
+; SI-NEXT: v_lshr_b64 v[21:22], v[13:14], 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_mov_b32_e32 v1, v19
+; SI-NEXT: v_mov_b32_e32 v9, v21
+; SI-NEXT: v_lshr_b64 v[16:17], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[3:4], v[0:1], 24
+; SI-NEXT: v_lshr_b64 v[1:2], v[0:1], 8
+; SI-NEXT: v_lshr_b64 v[11:12], v[8:9], 24
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v10
+; SI-NEXT: v_lshr_b64 v[17:18], v[8:9], 16
+; SI-NEXT: v_lshr_b64 v[9:10], v[8:9], 8
+; SI-NEXT: v_lshrrev_b32_e32 v20, 8, v19
+; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v21
+; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v7
; SI-NEXT: .LBB109_3: ; %end
-; SI-NEXT: v_mov_b32_e32 v0, v19
-; SI-NEXT: v_mov_b32_e32 v2, v4
-; SI-NEXT: v_mov_b32_e32 v4, v20
-; SI-NEXT: v_mov_b32_e32 v8, v21
-; SI-NEXT: v_mov_b32_e32 v9, v11
-; SI-NEXT: v_mov_b32_e32 v11, v17
-; SI-NEXT: v_mov_b32_e32 v12, v22
+; SI-NEXT: v_mov_b32_e32 v2, v16
+; SI-NEXT: v_mov_b32_e32 v4, v19
+; SI-NEXT: v_mov_b32_e32 v5, v20
+; SI-NEXT: v_mov_b32_e32 v10, v17
+; SI-NEXT: v_mov_b32_e32 v12, v21
+; SI-NEXT: v_mov_b32_e32 v13, v22
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB109_4:
-; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: s_branch .LBB109_2
;
; VI-LABEL: bitcast_v8bf16_to_v16i8_scalar:
@@ -24628,142 +24653,143 @@ define inreg <16 x i8> @bitcast_v8bf16_to_v16i8_scalar(<8 x bfloat> inreg %a, i3
; VI-NEXT: s_cmp_lg_u32 s20, 0
; VI-NEXT: s_cbranch_scc0 .LBB109_3
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: s_lshr_b32 s10, s19, 24
-; VI-NEXT: s_lshr_b32 s11, s19, 16
-; VI-NEXT: s_lshr_b32 s13, s19, 8
-; VI-NEXT: s_lshr_b32 s12, s18, 16
-; VI-NEXT: s_lshr_b32 s14, s18, 8
-; VI-NEXT: s_lshr_b32 s15, s17, 24
-; VI-NEXT: s_lshr_b32 s20, s17, 16
-; VI-NEXT: s_lshr_b32 s22, s17, 8
-; VI-NEXT: s_lshr_b32 s21, s16, 16
-; VI-NEXT: s_lshr_b32 s23, s16, 8
+; VI-NEXT: s_lshr_b32 s21, s19, 24
+; VI-NEXT: s_lshr_b32 s20, s19, 16
+; VI-NEXT: s_lshr_b32 s15, s19, 8
+; VI-NEXT: s_lshr_b32 s23, s18, 16
+; VI-NEXT: s_lshr_b32 s22, s18, 8
+; VI-NEXT: s_lshr_b32 s12, s17, 24
+; VI-NEXT: s_lshr_b32 s11, s17, 16
+; VI-NEXT: s_lshr_b32 s10, s17, 8
+; VI-NEXT: s_lshr_b32 s14, s16, 16
+; VI-NEXT: s_lshr_b32 s13, s16, 8
; VI-NEXT: s_lshr_b64 s[6:7], s[18:19], 24
; VI-NEXT: s_lshr_b64 s[4:5], s[16:17], 24
; VI-NEXT: s_cbranch_execnz .LBB109_4
; VI-NEXT: .LBB109_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v6, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v6
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v6
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v19, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v6
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v6
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
+; VI-NEXT: s_lshl_b32 s4, s19, 16
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v6
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_alignbit_b32 v18, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v6
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: s_lshl_b32 s4, s18, 16
+; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[2:3]
+; VI-NEXT: v_add_f32_e32 v2, s4, v6
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v17, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v16, v0, v1, 16
-; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[16:17]
-; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[18:19]
-; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v17
-; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v17
-; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v17
-; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v16
-; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v16
-; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v19
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v19
-; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v19
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v18
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v6
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[2:3]
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v9, v12
+; VI-NEXT: v_mov_b32_e32 v1, v4
+; VI-NEXT: v_lshrrev_b64 v[16:17], 24, v[8:9]
+; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[0:1]
+; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v12
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v12
+; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v12
+; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v8
+; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v8
+; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v4
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v4
+; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; VI-NEXT: v_lshrrev_b32_e32 v11, 8, v0
; VI-NEXT: s_branch .LBB109_5
; VI-NEXT: .LBB109_3:
-; VI-NEXT: ; implicit-def: $sgpr23
-; VI-NEXT: ; implicit-def: $sgpr21
-; VI-NEXT: ; implicit-def: $sgpr4
-; VI-NEXT: ; implicit-def: $sgpr22
-; VI-NEXT: ; implicit-def: $sgpr20
-; VI-NEXT: ; implicit-def: $sgpr15
+; VI-NEXT: ; implicit-def: $sgpr13
; VI-NEXT: ; implicit-def: $sgpr14
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr10
+; VI-NEXT: ; implicit-def: $sgpr11
; VI-NEXT: ; implicit-def: $sgpr12
+; VI-NEXT: ; implicit-def: $sgpr22
+; VI-NEXT: ; implicit-def: $sgpr23
; VI-NEXT: ; implicit-def: $sgpr6
-; VI-NEXT: ; implicit-def: $sgpr13
-; VI-NEXT: ; implicit-def: $sgpr11
-; VI-NEXT: ; implicit-def: $sgpr10
+; VI-NEXT: ; implicit-def: $sgpr15
+; VI-NEXT: ; implicit-def: $sgpr20
+; VI-NEXT: ; implicit-def: $sgpr21
; VI-NEXT: s_branch .LBB109_2
; VI-NEXT: .LBB109_4:
-; VI-NEXT: v_mov_b32_e32 v18, s16
-; VI-NEXT: v_mov_b32_e32 v19, s17
-; VI-NEXT: v_mov_b32_e32 v16, s18
-; VI-NEXT: v_mov_b32_e32 v17, s19
-; VI-NEXT: v_mov_b32_e32 v1, s23
-; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_mov_b32_e32 v5, s22
-; VI-NEXT: v_mov_b32_e32 v6, s20
-; VI-NEXT: v_mov_b32_e32 v7, s15
-; VI-NEXT: v_mov_b32_e32 v9, s14
-; VI-NEXT: v_mov_b32_e32 v10, s12
-; VI-NEXT: v_mov_b32_e32 v13, s13
-; VI-NEXT: v_mov_b32_e32 v14, s11
-; VI-NEXT: v_mov_b32_e32 v15, s10
-; VI-NEXT: v_mov_b32_e32 v11, s6
-; VI-NEXT: v_mov_b32_e32 v3, s4
+; VI-NEXT: v_mov_b32_e32 v8, s18
+; VI-NEXT: v_mov_b32_e32 v12, s19
+; VI-NEXT: v_mov_b32_e32 v0, s16
+; VI-NEXT: v_mov_b32_e32 v4, s17
+; VI-NEXT: v_mov_b32_e32 v10, s23
+; VI-NEXT: v_mov_b32_e32 v9, s22
+; VI-NEXT: v_mov_b32_e32 v15, s21
+; VI-NEXT: v_mov_b32_e32 v14, s20
+; VI-NEXT: v_mov_b32_e32 v13, s15
+; VI-NEXT: v_mov_b32_e32 v2, s14
+; VI-NEXT: v_mov_b32_e32 v11, s13
+; VI-NEXT: v_mov_b32_e32 v7, s12
+; VI-NEXT: v_mov_b32_e32 v6, s11
+; VI-NEXT: v_mov_b32_e32 v5, s10
+; VI-NEXT: v_mov_b32_e32 v16, s6
+; VI-NEXT: v_mov_b32_e32 v17, s4
; VI-NEXT: .LBB109_5: ; %end
-; VI-NEXT: v_mov_b32_e32 v0, v18
-; VI-NEXT: v_mov_b32_e32 v4, v19
-; VI-NEXT: v_mov_b32_e32 v8, v16
-; VI-NEXT: v_mov_b32_e32 v12, v17
+; VI-NEXT: v_mov_b32_e32 v3, v17
+; VI-NEXT: v_mov_b32_e32 v1, v11
+; VI-NEXT: v_mov_b32_e32 v11, v16
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8bf16_to_v16i8_scalar:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
index 01e397d629ea9..ccc6e9c7e9c16 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
@@ -4052,90 +4052,92 @@ define inreg <8 x i32> @bitcast_v16bf16_to_v8i32_scalar(<16 x bfloat> inreg %a,
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e64 v22, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v23, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v20, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v21, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v18, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v19, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v16, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v17, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v14, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v15, 1.0, s24
-; SI-NEXT: v_mul_f32_e64 v12, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v13, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s28
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v0
+; SI-NEXT: v_mul_f32_e64 v31, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v22, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v30, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v20, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v29, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v18, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v28, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v27, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v26, 1.0, s27
+; SI-NEXT: v_mul_f32_e64 v25, 1.0, s29
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v0
+; SI-NEXT: v_mul_f32_e64 v12, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s28
; SI-NEXT: s_cbranch_scc0 .LBB23_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v8
-; SI-NEXT: v_alignbit_b32 v0, v0, v23, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v21, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v19, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v17, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v15, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v13, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v11, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v9, 16
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v31
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v30
+; SI-NEXT: v_lshr_b64 v[0:1], v[22:23], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[20:21], 16
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v29
+; SI-NEXT: v_lshr_b64 v[2:3], v[18:19], 16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v28
+; SI-NEXT: v_lshr_b64 v[3:4], v[16:17], 16
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v27
+; SI-NEXT: v_lshr_b64 v[4:5], v[14:15], 16
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v24
+; SI-NEXT: v_lshr_b64 v[5:6], v[12:13], 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v25
+; SI-NEXT: v_lshr_b64 v[32:33], v[8:9], 16
+; SI-NEXT: v_lshr_b64 v[6:7], v[10:11], 16
+; SI-NEXT: v_mov_b32_e32 v7, v32
; SI-NEXT: s_cbranch_execnz .LBB23_3
; SI-NEXT: .LBB23_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v23
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v20
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v18
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v19
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v29
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v18
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v28
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v16
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v14
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v15
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v27
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v14
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v12
-; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v13
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v26
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v12
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v10
-; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v24
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v25
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v9
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
+; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
+; SI-NEXT: v_mov_b32_e32 v7, v8
; SI-NEXT: .LBB23_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB23_4:
@@ -4151,150 +4153,153 @@ define inreg <8 x i32> @bitcast_v16bf16_to_v8i32_scalar(<16 x bfloat> inreg %a,
; VI-NEXT: s_cbranch_execnz .LBB23_4
; VI-NEXT: .LBB23_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s23, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v8, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v8
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v8
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
+; VI-NEXT: s_lshl_b32 s4, s22, 16
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s22, 16
-; VI-NEXT: v_alignbit_b32 v7, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: s_lshl_b32 s4, s21, 16
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[2:3]
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_alignbit_b32 v6, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_cndmask_b32_e32 v9, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_alignbit_b32 v5, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_alignbit_b32 v4, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[2:3]
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_cndmask_b32_e32 v11, v3, v5, vcc
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v8, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v8, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v2
-; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v2
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v8, v9, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3]
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v8, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v1
-; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc
-; VI-NEXT: v_add_f32_e32 v8, s4, v0
-; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
-; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_cndmask_b32_e32 v13, v5, v7, vcc
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v8, v1, 16
-; VI-NEXT: v_add_f32_e32 v8, s4, v0
-; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
-; VI-NEXT: v_bfe_u32 v9, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v0
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v8, 16
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v3
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v8
+; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v7
+; VI-NEXT: v_lshrrev_b64 v[7:8], 16, v[0:1]
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[9:10]
+; VI-NEXT: v_lshrrev_b64 v[9:10], 16, v[11:12]
+; VI-NEXT: v_cndmask_b32_e32 v1, v16, v17, vcc
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[13:14]
+; VI-NEXT: v_cndmask_b32_e64 v0, v5, v15, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v10
+; VI-NEXT: v_mov_b32_e32 v3, v9
+; VI-NEXT: v_mov_b32_e32 v5, v8
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB23_3:
; VI-NEXT: s_branch .LBB23_2
@@ -11204,90 +11209,92 @@ define inreg <8 x float> @bitcast_v16bf16_to_v8f32_scalar(<16 x bfloat> inreg %a
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e64 v22, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v23, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v20, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v21, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v18, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v19, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v16, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v17, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v14, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v15, 1.0, s24
-; SI-NEXT: v_mul_f32_e64 v12, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v13, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s28
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v0
+; SI-NEXT: v_mul_f32_e64 v31, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v22, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v30, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v20, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v29, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v18, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v28, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v27, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v26, 1.0, s27
+; SI-NEXT: v_mul_f32_e64 v25, 1.0, s29
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v0
+; SI-NEXT: v_mul_f32_e64 v12, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s28
; SI-NEXT: s_cbranch_scc0 .LBB47_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v8
-; SI-NEXT: v_alignbit_b32 v0, v0, v23, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v21, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v19, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v17, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v15, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v13, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v11, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v9, 16
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v31
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v30
+; SI-NEXT: v_lshr_b64 v[0:1], v[22:23], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[20:21], 16
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v29
+; SI-NEXT: v_lshr_b64 v[2:3], v[18:19], 16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v28
+; SI-NEXT: v_lshr_b64 v[3:4], v[16:17], 16
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v27
+; SI-NEXT: v_lshr_b64 v[4:5], v[14:15], 16
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v24
+; SI-NEXT: v_lshr_b64 v[5:6], v[12:13], 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v25
+; SI-NEXT: v_lshr_b64 v[32:33], v[8:9], 16
+; SI-NEXT: v_lshr_b64 v[6:7], v[10:11], 16
+; SI-NEXT: v_mov_b32_e32 v7, v32
; SI-NEXT: s_cbranch_execnz .LBB47_3
; SI-NEXT: .LBB47_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v23
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v20
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v18
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v19
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v29
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v18
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v28
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v16
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v14
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v15
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v27
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v14
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v12
-; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v13
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v26
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v12
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v10
-; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v24
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v25
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v9
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
+; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
+; SI-NEXT: v_mov_b32_e32 v7, v8
; SI-NEXT: .LBB47_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB47_4:
@@ -11303,150 +11310,153 @@ define inreg <8 x float> @bitcast_v16bf16_to_v8f32_scalar(<16 x bfloat> inreg %a
; VI-NEXT: s_cbranch_execnz .LBB47_4
; VI-NEXT: .LBB47_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s23, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v8, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v8
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v8
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
+; VI-NEXT: s_lshl_b32 s4, s22, 16
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s22, 16
-; VI-NEXT: v_alignbit_b32 v7, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: s_lshl_b32 s4, s21, 16
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[2:3]
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_alignbit_b32 v6, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_cndmask_b32_e32 v9, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_alignbit_b32 v5, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_alignbit_b32 v4, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[2:3]
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_cndmask_b32_e32 v11, v3, v5, vcc
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v8, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v8, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v2
-; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v2
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v8, v9, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3]
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v8, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v1
-; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc
-; VI-NEXT: v_add_f32_e32 v8, s4, v0
-; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
-; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_cndmask_b32_e32 v13, v5, v7, vcc
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v8, v1, 16
-; VI-NEXT: v_add_f32_e32 v8, s4, v0
-; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
-; VI-NEXT: v_bfe_u32 v9, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v0
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v8, 16
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v3
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v8
+; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v7
+; VI-NEXT: v_lshrrev_b64 v[7:8], 16, v[0:1]
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[9:10]
+; VI-NEXT: v_lshrrev_b64 v[9:10], 16, v[11:12]
+; VI-NEXT: v_cndmask_b32_e32 v1, v16, v17, vcc
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[13:14]
+; VI-NEXT: v_cndmask_b32_e64 v0, v5, v15, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v10
+; VI-NEXT: v_mov_b32_e32 v3, v9
+; VI-NEXT: v_mov_b32_e32 v5, v8
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB47_3:
; VI-NEXT: s_branch .LBB47_2
@@ -17924,90 +17934,92 @@ define inreg <4 x i64> @bitcast_v16bf16_to_v4i64_scalar(<16 x bfloat> inreg %a,
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e64 v22, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v23, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v20, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v21, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v18, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v19, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v16, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v17, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v14, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v15, 1.0, s24
-; SI-NEXT: v_mul_f32_e64 v12, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v13, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s28
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v0
+; SI-NEXT: v_mul_f32_e64 v31, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v22, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v30, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v20, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v29, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v18, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v28, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v27, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v26, 1.0, s27
+; SI-NEXT: v_mul_f32_e64 v25, 1.0, s29
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v0
+; SI-NEXT: v_mul_f32_e64 v12, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s28
; SI-NEXT: s_cbranch_scc0 .LBB67_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v8
-; SI-NEXT: v_alignbit_b32 v0, v0, v23, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v21, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v19, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v17, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v15, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v13, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v11, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v9, 16
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v31
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v30
+; SI-NEXT: v_lshr_b64 v[0:1], v[22:23], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[20:21], 16
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v29
+; SI-NEXT: v_lshr_b64 v[2:3], v[18:19], 16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v28
+; SI-NEXT: v_lshr_b64 v[3:4], v[16:17], 16
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v27
+; SI-NEXT: v_lshr_b64 v[4:5], v[14:15], 16
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v24
+; SI-NEXT: v_lshr_b64 v[5:6], v[12:13], 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v25
+; SI-NEXT: v_lshr_b64 v[32:33], v[8:9], 16
+; SI-NEXT: v_lshr_b64 v[6:7], v[10:11], 16
+; SI-NEXT: v_mov_b32_e32 v7, v32
; SI-NEXT: s_cbranch_execnz .LBB67_3
; SI-NEXT: .LBB67_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v23
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v20
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v18
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v19
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v29
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v18
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v28
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v16
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v14
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v15
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v27
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v14
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v12
-; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v13
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v26
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v12
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v10
-; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v24
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v25
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v9
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
+; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
+; SI-NEXT: v_mov_b32_e32 v7, v8
; SI-NEXT: .LBB67_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB67_4:
@@ -18023,150 +18035,153 @@ define inreg <4 x i64> @bitcast_v16bf16_to_v4i64_scalar(<16 x bfloat> inreg %a,
; VI-NEXT: s_cbranch_execnz .LBB67_4
; VI-NEXT: .LBB67_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s23, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v8, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v8
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v8
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
+; VI-NEXT: s_lshl_b32 s4, s22, 16
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s22, 16
-; VI-NEXT: v_alignbit_b32 v7, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: s_lshl_b32 s4, s21, 16
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[2:3]
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_alignbit_b32 v6, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_cndmask_b32_e32 v9, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_alignbit_b32 v5, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_alignbit_b32 v4, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[2:3]
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_cndmask_b32_e32 v11, v3, v5, vcc
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v8, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v8, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v2
-; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v2
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v8, v9, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3]
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v8, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v1
-; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc
-; VI-NEXT: v_add_f32_e32 v8, s4, v0
-; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
-; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_cndmask_b32_e32 v13, v5, v7, vcc
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v8, v1, 16
-; VI-NEXT: v_add_f32_e32 v8, s4, v0
-; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
-; VI-NEXT: v_bfe_u32 v9, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v0
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v8, 16
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v3
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v8
+; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v7
+; VI-NEXT: v_lshrrev_b64 v[7:8], 16, v[0:1]
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[9:10]
+; VI-NEXT: v_lshrrev_b64 v[9:10], 16, v[11:12]
+; VI-NEXT: v_cndmask_b32_e32 v1, v16, v17, vcc
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[13:14]
+; VI-NEXT: v_cndmask_b32_e64 v0, v5, v15, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v10
+; VI-NEXT: v_mov_b32_e32 v3, v9
+; VI-NEXT: v_mov_b32_e32 v5, v8
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB67_3:
; VI-NEXT: s_branch .LBB67_2
@@ -24092,90 +24107,92 @@ define inreg <4 x double> @bitcast_v16bf16_to_v4f64_scalar(<16 x bfloat> inreg %
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e64 v22, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v23, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v20, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v21, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v18, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v19, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v16, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v17, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v14, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v15, 1.0, s24
-; SI-NEXT: v_mul_f32_e64 v12, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v13, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s28
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v0
+; SI-NEXT: v_mul_f32_e64 v31, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v22, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v30, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v20, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v29, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v18, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v28, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v27, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v26, 1.0, s27
+; SI-NEXT: v_mul_f32_e64 v25, 1.0, s29
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v0
+; SI-NEXT: v_mul_f32_e64 v12, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s28
; SI-NEXT: s_cbranch_scc0 .LBB83_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v8
-; SI-NEXT: v_alignbit_b32 v0, v0, v23, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v21, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v19, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v17, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v15, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v13, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v11, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v9, 16
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v31
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v30
+; SI-NEXT: v_lshr_b64 v[0:1], v[22:23], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[20:21], 16
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v29
+; SI-NEXT: v_lshr_b64 v[2:3], v[18:19], 16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v28
+; SI-NEXT: v_lshr_b64 v[3:4], v[16:17], 16
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v27
+; SI-NEXT: v_lshr_b64 v[4:5], v[14:15], 16
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v24
+; SI-NEXT: v_lshr_b64 v[5:6], v[12:13], 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v25
+; SI-NEXT: v_lshr_b64 v[32:33], v[8:9], 16
+; SI-NEXT: v_lshr_b64 v[6:7], v[10:11], 16
+; SI-NEXT: v_mov_b32_e32 v7, v32
; SI-NEXT: s_cbranch_execnz .LBB83_3
; SI-NEXT: .LBB83_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v23
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v20
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v18
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v19
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v29
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v18
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v28
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v16
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v14
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v15
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v27
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v14
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v12
-; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v13
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v26
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v12
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v10
-; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v24
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v25
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v9
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
+; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
+; SI-NEXT: v_mov_b32_e32 v7, v8
; SI-NEXT: .LBB83_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB83_4:
@@ -24191,150 +24208,153 @@ define inreg <4 x double> @bitcast_v16bf16_to_v4f64_scalar(<16 x bfloat> inreg %
; VI-NEXT: s_cbranch_execnz .LBB83_4
; VI-NEXT: .LBB83_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s23, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v8, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v8
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v8
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
+; VI-NEXT: s_lshl_b32 s4, s22, 16
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s22, 16
-; VI-NEXT: v_alignbit_b32 v7, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: s_lshl_b32 s4, s21, 16
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[2:3]
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_alignbit_b32 v6, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_cndmask_b32_e32 v9, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_alignbit_b32 v5, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_alignbit_b32 v4, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[2:3]
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_cndmask_b32_e32 v11, v3, v5, vcc
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v8, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v8, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v2
-; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v2
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v8
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v8, v9, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3]
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v8, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v1
-; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc
-; VI-NEXT: v_add_f32_e32 v8, s4, v0
-; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
-; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_cndmask_b32_e32 v13, v5, v7, vcc
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v8, v1, 16
-; VI-NEXT: v_add_f32_e32 v8, s4, v0
-; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
-; VI-NEXT: v_bfe_u32 v9, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v0
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v8, 16
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v3
+; VI-NEXT: v_add_f32_e32 v3, s4, v8
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v8
+; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v7
+; VI-NEXT: v_lshrrev_b64 v[7:8], 16, v[0:1]
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[9:10]
+; VI-NEXT: v_lshrrev_b64 v[9:10], 16, v[11:12]
+; VI-NEXT: v_cndmask_b32_e32 v1, v16, v17, vcc
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[13:14]
+; VI-NEXT: v_cndmask_b32_e64 v0, v5, v15, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v10
+; VI-NEXT: v_mov_b32_e32 v3, v9
+; VI-NEXT: v_mov_b32_e32 v5, v8
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB83_3:
; VI-NEXT: s_branch .LBB83_2
@@ -29754,119 +29774,123 @@ define inreg <16 x i16> @bitcast_v16bf16_to_v16i16_scalar(<16 x bfloat> inreg %a
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_mul_f32_e64 v31, 1.0, s16
; SI-NEXT: v_mul_f32_e64 v30, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v20, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v16, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v18, 1.0, s19
; SI-NEXT: v_mul_f32_e64 v29, 1.0, s20
; SI-NEXT: v_mul_f32_e64 v28, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v22, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v20, 1.0, s23
; SI-NEXT: v_mul_f32_e64 v27, 1.0, s24
; SI-NEXT: v_mul_f32_e64 v26, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v23, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s27
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v22, 1.0, s27
; SI-NEXT: v_mul_f32_e64 v25, 1.0, s28
; SI-NEXT: v_mul_f32_e64 v24, 1.0, s29
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v0
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v1
; SI-NEXT: s_cbranch_scc0 .LBB95_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v31
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v30
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v18
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v20
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v22
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v23
; SI-NEXT: s_cbranch_execnz .LBB95_3
; SI-NEXT: .LBB95_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v30
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v30
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v31
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v12
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v28
-; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v26
-; SI-NEXT: v_alignbit_b32 v4, v4, v2, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v27
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6
-; SI-NEXT: v_alignbit_b32 v8, v7, v2, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v25
-; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v24
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v2
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v9
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v23
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v30
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v29
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v5
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; SI-NEXT: v_lshr_b64 v[4:5], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v25
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v24
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v27
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v5
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v26
+; SI-NEXT: v_lshr_b64 v[12:13], v[11:12], 16
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v3
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v22
+; SI-NEXT: v_lshr_b64 v[8:9], v[7:8], 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v14
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v23
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v5
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_alignbit_b32 v10, v11, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_alignbit_b32 v14, v15, v7, 16
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; SI-NEXT: v_alignbit_b32 v6, v7, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v20
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v18
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v7
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
-; SI-NEXT: v_alignbit_b32 v2, v3, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v12
-; SI-NEXT: v_lshr_b64 v[17:18], v[1:2], 16
-; SI-NEXT: v_lshr_b64 v[18:19], v[5:6], 16
-; SI-NEXT: v_lshr_b64 v[21:22], v[9:10], 16
-; SI-NEXT: v_lshr_b64 v[19:20], v[13:14], 16
-; SI-NEXT: v_alignbit_b32 v12, v24, v25, 16
+; SI-NEXT: v_lshr_b64 v[16:17], v[14:15], 16
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; SI-NEXT: v_lshr_b64 v[21:22], v[10:11], 16
+; SI-NEXT: v_lshr_b64 v[19:20], v[6:7], 16
+; SI-NEXT: v_lshr_b64 v[17:18], v[2:3], 16
+; SI-NEXT: v_mov_b32_e32 v14, v16
+; SI-NEXT: v_mov_b32_e32 v10, v21
+; SI-NEXT: v_mov_b32_e32 v6, v19
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v30
+; SI-NEXT: v_mov_b32_e32 v2, v17
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
+; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
; SI-NEXT: .LBB95_3: ; %end
-; SI-NEXT: v_mov_b32_e32 v1, v17
-; SI-NEXT: v_mov_b32_e32 v5, v18
-; SI-NEXT: v_mov_b32_e32 v9, v21
-; SI-NEXT: v_mov_b32_e32 v13, v19
+; SI-NEXT: v_mov_b32_e32 v2, v17
+; SI-NEXT: v_mov_b32_e32 v6, v19
+; SI-NEXT: v_mov_b32_e32 v10, v21
+; SI-NEXT: v_mov_b32_e32 v14, v16
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB95_4:
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_branch .LBB95_2
;
; VI-LABEL: bitcast_v16bf16_to_v16i16_scalar:
@@ -29878,150 +29902,154 @@ define inreg <16 x i16> @bitcast_v16bf16_to_v16i16_scalar(<16 x bfloat> inreg %a
; VI-NEXT: s_cbranch_execnz .LBB95_4
; VI-NEXT: .LBB95_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v0, s4, v1
-; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_mov_b32_e32 v10, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v10
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v10
+; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: s_lshl_b32 s4, s17, 16
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_add_f32_e32 v2, s4, v10
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v10
+; VI-NEXT: v_cndmask_b32_e32 v8, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_lshl_b32 s4, s17, 16
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_cndmask_b32_e32 v8, v4, v5, vcc
+; VI-NEXT: s_lshl_b32 s4, s18, 16
+; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v10
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v10
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_lshl_b32 s4, s18, 16
+; VI-NEXT: s_lshl_b32 s4, s19, 16
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v1
+; VI-NEXT: v_add_f32_e32 v4, s4, v10
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_add_f32_e32 v4, s4, v1
-; VI-NEXT: v_cndmask_b32_e32 v9, v5, v6, vcc
+; VI-NEXT: v_add_f32_e32 v4, s4, v10
+; VI-NEXT: v_cndmask_b32_e32 v11, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: s_lshl_b32 s4, s19, 16
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_add_f32_e32 v5, s4, v1
-; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
-; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
-; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
-; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: v_add_f32_e32 v5, s4, v1
-; VI-NEXT: v_cndmask_b32_e32 v10, v6, v7, vcc
+; VI-NEXT: s_lshl_b32 s4, s20, 16
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; VI-NEXT: v_add_f32_e32 v4, s4, v10
+; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; VI-NEXT: v_add_f32_e32 v5, s4, v10
; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
+; VI-NEXT: s_and_b32 s5, s21, 0xffff0000
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
-; VI-NEXT: v_add_f32_e32 v6, s4, v1
-; VI-NEXT: v_bfe_u32 v7, v6, 16, 1
-; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6
-; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_add_f32_e32 v13, s5, v10
; VI-NEXT: s_lshl_b32 s5, s22, 16
-; VI-NEXT: v_or_b32_e32 v11, 0x400000, v6
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
-; VI-NEXT: v_add_f32_e32 v6, s5, v1
-; VI-NEXT: v_cndmask_b32_e32 v11, v7, v11, vcc
+; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
+; VI-NEXT: v_add_f32_e32 v6, s5, v10
; VI-NEXT: v_bfe_u32 v7, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
-; VI-NEXT: v_or_b32_e32 v12, 0x400000, v6
+; VI-NEXT: v_or_b32_e32 v14, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: s_and_b32 s5, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v6, v7, v12, vcc
-; VI-NEXT: v_add_f32_e32 v7, s5, v1
-; VI-NEXT: v_bfe_u32 v12, v7, 16, 1
-; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v7
-; VI-NEXT: v_add_u32_e32 v12, vcc, 0x7fff, v12
-; VI-NEXT: v_or_b32_e32 v13, 0x400000, v7
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; VI-NEXT: v_cndmask_b32_e32 v7, v12, v13, vcc
-; VI-NEXT: s_lshl_b32 s5, s23, 16
-; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; VI-NEXT: v_add_f32_e32 v7, s5, v1
-; VI-NEXT: v_bfe_u32 v13, v7, 16, 1
-; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v7
-; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
-; VI-NEXT: v_or_b32_e32 v14, 0x400000, v7
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; VI-NEXT: s_and_b32 s5, s23, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v7, v13, v14, vcc
-; VI-NEXT: v_add_f32_e32 v13, s5, v1
-; VI-NEXT: v_bfe_u32 v14, v13, 16, 1
-; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13
+; VI-NEXT: v_cndmask_b32_e32 v6, v7, v14, vcc
+; VI-NEXT: v_add_f32_e32 v7, s5, v10
+; VI-NEXT: v_bfe_u32 v14, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v7
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
-; VI-NEXT: v_or_b32_e32 v15, 0x400000, v13
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; VI-NEXT: v_alignbit_b32 v6, v12, v6, 16
-; VI-NEXT: v_add_f32_e32 v12, s4, v1
-; VI-NEXT: v_alignbit_b32 v7, v13, v7, 16
-; VI-NEXT: v_bfe_u32 v13, v12, 16, 1
-; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12
-; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
-; VI-NEXT: v_or_b32_e32 v14, 0x400000, v12
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[4:5]
+; VI-NEXT: v_cndmask_b32_e32 v7, v14, v15, vcc
+; VI-NEXT: v_bfe_u32 v5, v13, 16, 1
+; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v13
; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc
-; VI-NEXT: v_add_f32_e32 v13, s4, v1
-; VI-NEXT: v_bfe_u32 v14, v13, 16, 1
-; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13
-; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v15, 0x400000, v13
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[6:7]
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
-; VI-NEXT: v_add_f32_e32 v1, s4, v1
-; VI-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc
-; VI-NEXT: v_bfe_u32 v14, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v1
-; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
-; VI-NEXT: v_or_b32_e32 v15, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v14, v15, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v2
-; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v5
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v12
+; VI-NEXT: v_add_f32_e32 v13, s4, v10
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; VI-NEXT: v_bfe_u32 v7, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v13
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v14, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v13, v7, v14, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v5
+; VI-NEXT: v_add_f32_e32 v5, s4, v10
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: s_lshl_b32 s4, s23, 16
+; VI-NEXT: v_cndmask_b32_e32 v5, v7, v15, vcc
+; VI-NEXT: v_add_f32_e32 v7, s4, v10
+; VI-NEXT: v_bfe_u32 v10, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v7
+; VI-NEXT: v_add_u32_e32 v10, vcc, 0x7fff, v10
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_cndmask_b32_e32 v15, v10, v15, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_alignbit_b32 v5, v1, v13, 16
-; VI-NEXT: v_alignbit_b32 v4, v4, v11, 16
-; VI-NEXT: v_alignbit_b32 v3, v3, v10, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v9, 16
-; VI-NEXT: v_alignbit_b32 v1, v15, v8, 16
-; VI-NEXT: v_alignbit_b32 v0, v14, v0, 16
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b64 v[15:16], 16, v[15:16]
+; VI-NEXT: v_lshrrev_b64 v[13:14], 16, v[13:14]
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[11:12]
+; VI-NEXT: v_lshrrev_b64 v[7:8], 16, v[8:9]
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3]
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v7
+; VI-NEXT: v_mov_b32_e32 v3, v10
+; VI-NEXT: v_mov_b32_e32 v5, v13
+; VI-NEXT: v_mov_b32_e32 v7, v15
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB95_3:
; VI-NEXT: s_branch .LBB95_2
@@ -35136,150 +35164,154 @@ define inreg <16 x half> @bitcast_v16bf16_to_v16f16_scalar(<16 x bfloat> inreg %
; VI-NEXT: s_cbranch_execnz .LBB103_4
; VI-NEXT: .LBB103_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v0, s4, v1
-; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_mov_b32_e32 v10, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v10
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v10
+; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: s_lshl_b32 s4, s17, 16
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_add_f32_e32 v2, s4, v10
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v10
+; VI-NEXT: v_cndmask_b32_e32 v8, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_lshl_b32 s4, s17, 16
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_cndmask_b32_e32 v8, v4, v5, vcc
+; VI-NEXT: s_lshl_b32 s4, s18, 16
+; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v10
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v10
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_lshl_b32 s4, s18, 16
+; VI-NEXT: s_lshl_b32 s4, s19, 16
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v1
+; VI-NEXT: v_add_f32_e32 v4, s4, v10
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_add_f32_e32 v4, s4, v1
-; VI-NEXT: v_cndmask_b32_e32 v9, v5, v6, vcc
+; VI-NEXT: v_add_f32_e32 v4, s4, v10
+; VI-NEXT: v_cndmask_b32_e32 v11, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: s_lshl_b32 s4, s19, 16
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_add_f32_e32 v5, s4, v1
-; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
-; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
-; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
-; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: v_add_f32_e32 v5, s4, v1
-; VI-NEXT: v_cndmask_b32_e32 v10, v6, v7, vcc
+; VI-NEXT: s_lshl_b32 s4, s20, 16
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; VI-NEXT: v_add_f32_e32 v4, s4, v10
+; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; VI-NEXT: v_add_f32_e32 v5, s4, v10
; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
+; VI-NEXT: s_and_b32 s5, s21, 0xffff0000
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
-; VI-NEXT: v_add_f32_e32 v6, s4, v1
-; VI-NEXT: v_bfe_u32 v7, v6, 16, 1
-; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6
-; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_add_f32_e32 v13, s5, v10
; VI-NEXT: s_lshl_b32 s5, s22, 16
-; VI-NEXT: v_or_b32_e32 v11, 0x400000, v6
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
-; VI-NEXT: v_add_f32_e32 v6, s5, v1
-; VI-NEXT: v_cndmask_b32_e32 v11, v7, v11, vcc
+; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
+; VI-NEXT: v_add_f32_e32 v6, s5, v10
; VI-NEXT: v_bfe_u32 v7, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
-; VI-NEXT: v_or_b32_e32 v12, 0x400000, v6
+; VI-NEXT: v_or_b32_e32 v14, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: s_and_b32 s5, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v6, v7, v12, vcc
-; VI-NEXT: v_add_f32_e32 v7, s5, v1
-; VI-NEXT: v_bfe_u32 v12, v7, 16, 1
-; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v7
-; VI-NEXT: v_add_u32_e32 v12, vcc, 0x7fff, v12
-; VI-NEXT: v_or_b32_e32 v13, 0x400000, v7
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; VI-NEXT: v_cndmask_b32_e32 v7, v12, v13, vcc
-; VI-NEXT: s_lshl_b32 s5, s23, 16
-; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; VI-NEXT: v_add_f32_e32 v7, s5, v1
-; VI-NEXT: v_bfe_u32 v13, v7, 16, 1
-; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v7
-; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
-; VI-NEXT: v_or_b32_e32 v14, 0x400000, v7
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; VI-NEXT: s_and_b32 s5, s23, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v7, v13, v14, vcc
-; VI-NEXT: v_add_f32_e32 v13, s5, v1
-; VI-NEXT: v_bfe_u32 v14, v13, 16, 1
-; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13
+; VI-NEXT: v_cndmask_b32_e32 v6, v7, v14, vcc
+; VI-NEXT: v_add_f32_e32 v7, s5, v10
+; VI-NEXT: v_bfe_u32 v14, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v7
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
-; VI-NEXT: v_or_b32_e32 v15, 0x400000, v13
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; VI-NEXT: v_alignbit_b32 v6, v12, v6, 16
-; VI-NEXT: v_add_f32_e32 v12, s4, v1
-; VI-NEXT: v_alignbit_b32 v7, v13, v7, 16
-; VI-NEXT: v_bfe_u32 v13, v12, 16, 1
-; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12
-; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
-; VI-NEXT: v_or_b32_e32 v14, 0x400000, v12
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[4:5]
+; VI-NEXT: v_cndmask_b32_e32 v7, v14, v15, vcc
+; VI-NEXT: v_bfe_u32 v5, v13, 16, 1
+; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v13
; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc
-; VI-NEXT: v_add_f32_e32 v13, s4, v1
-; VI-NEXT: v_bfe_u32 v14, v13, 16, 1
-; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13
-; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v15, 0x400000, v13
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[6:7]
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
-; VI-NEXT: v_add_f32_e32 v1, s4, v1
-; VI-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc
-; VI-NEXT: v_bfe_u32 v14, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v1
-; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
-; VI-NEXT: v_or_b32_e32 v15, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v14, v15, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v2
-; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v5
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v12
+; VI-NEXT: v_add_f32_e32 v13, s4, v10
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; VI-NEXT: v_bfe_u32 v7, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v13
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v14, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v13, v7, v14, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v5
+; VI-NEXT: v_add_f32_e32 v5, s4, v10
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: s_lshl_b32 s4, s23, 16
+; VI-NEXT: v_cndmask_b32_e32 v5, v7, v15, vcc
+; VI-NEXT: v_add_f32_e32 v7, s4, v10
+; VI-NEXT: v_bfe_u32 v10, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v7
+; VI-NEXT: v_add_u32_e32 v10, vcc, 0x7fff, v10
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_cndmask_b32_e32 v15, v10, v15, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_alignbit_b32 v5, v1, v13, 16
-; VI-NEXT: v_alignbit_b32 v4, v4, v11, 16
-; VI-NEXT: v_alignbit_b32 v3, v3, v10, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v9, 16
-; VI-NEXT: v_alignbit_b32 v1, v15, v8, 16
-; VI-NEXT: v_alignbit_b32 v0, v14, v0, 16
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b64 v[15:16], 16, v[15:16]
+; VI-NEXT: v_lshrrev_b64 v[13:14], 16, v[13:14]
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[11:12]
+; VI-NEXT: v_lshrrev_b64 v[7:8], 16, v[8:9]
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3]
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v7
+; VI-NEXT: v_mov_b32_e32 v3, v10
+; VI-NEXT: v_mov_b32_e32 v5, v13
+; VI-NEXT: v_mov_b32_e32 v7, v15
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB103_3:
; VI-NEXT: s_branch .LBB103_2
@@ -40103,186 +40135,217 @@ define inreg <32 x i8> @bitcast_v16bf16_to_v32i8_scalar(<16 x bfloat> inreg %a,
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e64 v24, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v32, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v16, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v51, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v52, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v39, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v50, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v55, 1.0, s25
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_mul_f32_e64 v40, 1.0, s24
-; SI-NEXT: v_mul_f32_e64 v53, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v54, 1.0, s26
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mul_f32_e64 v42, 1.0, s29
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: v_mul_f32_e64 v56, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v40, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v55, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v5, 1.0, s18
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: v_mul_f32_e64 v58, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v42, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v57, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v13, 1.0, s22
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: v_mul_f32_e64 v60, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v44, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v59, 1.0, s27
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e64 v43, 1.0, s28
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_mul_f32_e64 v62, 1.0, s29
+; SI-NEXT: v_mul_f32_e32 v61, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v0
+; SI-NEXT: v_mul_f32_e64 v21, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v46, 1.0, s28
; SI-NEXT: s_cbranch_scc0 .LBB109_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v8
-; SI-NEXT: v_alignbit_b32 v48, v1, v32, 16
-; SI-NEXT: v_alignbit_b32 v49, v6, v16, 16
-; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 8
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v51
-; SI-NEXT: v_alignbit_b32 v37, v2, v52, 16
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v39
-; SI-NEXT: v_alignbit_b32 v35, v2, v40, 16
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v41
-; SI-NEXT: v_alignbit_b32 v38, v14, v50, 16
-; SI-NEXT: v_alignbit_b32 v36, v22, v54, 16
-; SI-NEXT: v_alignbit_b32 v33, v2, v43, 16
-; SI-NEXT: v_alignbit_b32 v34, v30, v0, 16
-; SI-NEXT: v_lshr_b64 v[3:4], v[48:49], 24
-; SI-NEXT: v_lshr_b64 v[11:12], v[37:38], 24
-; SI-NEXT: v_lshr_b64 v[19:20], v[35:36], 24
-; SI-NEXT: v_lshr_b64 v[27:28], v[33:34], 24
-; SI-NEXT: v_lshr_b64 v[4:5], v[48:49], 16
-; SI-NEXT: v_lshr_b64 v[12:13], v[37:38], 16
-; SI-NEXT: v_lshr_b64 v[20:21], v[35:36], 16
-; SI-NEXT: v_lshr_b64 v[28:29], v[33:34], 16
-; SI-NEXT: v_lshr_b64 v[9:10], v[37:38], 8
-; SI-NEXT: v_lshr_b64 v[17:18], v[35:36], 8
-; SI-NEXT: v_lshr_b64 v[25:26], v[33:34], 8
-; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v8
-; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v49
-; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v39
-; SI-NEXT: v_lshrrev_b32_e32 v13, 8, v38
-; SI-NEXT: v_lshrrev_b32_e32 v23, 24, v53
-; SI-NEXT: v_lshrrev_b32_e32 v21, 8, v36
-; SI-NEXT: v_lshrrev_b32_e32 v31, 24, v41
-; SI-NEXT: v_lshrrev_b32_e32 v29, 8, v34
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v59
+; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v56
+; SI-NEXT: v_lshr_b64 v[35:36], v[5:6], 16
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v58
+; SI-NEXT: v_lshr_b64 v[38:39], v[13:14], 16
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v60
+; SI-NEXT: v_lshr_b64 v[51:52], v[21:22], 16
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v61
+; SI-NEXT: v_lshr_b64 v[0:1], v[40:41], 16
+; SI-NEXT: v_lshr_b64 v[8:9], v[42:43], 16
+; SI-NEXT: v_lshr_b64 v[16:17], v[44:45], 16
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v62
+; SI-NEXT: v_lshr_b64 v[53:54], v[29:30], 16
+; SI-NEXT: v_mov_b32_e32 v1, v35
+; SI-NEXT: v_mov_b32_e32 v9, v38
+; SI-NEXT: v_mov_b32_e32 v17, v51
+; SI-NEXT: v_lshr_b64 v[24:25], v[46:47], 16
+; SI-NEXT: v_lshr_b64 v[33:34], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[11:12], v[8:9], 24
+; SI-NEXT: v_lshr_b64 v[36:37], v[8:9], 16
+; SI-NEXT: v_lshr_b64 v[9:10], v[8:9], 8
+; SI-NEXT: v_mov_b32_e32 v25, v53
+; SI-NEXT: v_lshr_b64 v[48:49], v[16:17], 16
+; SI-NEXT: v_lshr_b64 v[3:4], v[0:1], 24
+; SI-NEXT: v_lshr_b64 v[1:2], v[0:1], 8
+; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v55
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v57
+; SI-NEXT: v_lshrrev_b32_e32 v10, 8, v35
+; SI-NEXT: v_lshrrev_b32_e32 v23, 24, v59
+; SI-NEXT: v_lshrrev_b32_e32 v34, 8, v38
+; SI-NEXT: v_lshrrev_b32_e32 v31, 24, v61
+; SI-NEXT: v_lshrrev_b32_e32 v32, 8, v51
+; SI-NEXT: v_lshrrev_b32_e32 v37, 8, v53
+; SI-NEXT: v_lshr_b64 v[19:20], v[16:17], 24
+; SI-NEXT: v_lshr_b64 v[17:18], v[16:17], 8
+; SI-NEXT: v_lshr_b64 v[27:28], v[24:25], 24
+; SI-NEXT: v_lshr_b64 v[49:50], v[24:25], 16
+; SI-NEXT: v_lshr_b64 v[25:26], v[24:25], 8
; SI-NEXT: s_cbranch_execnz .LBB109_3
; SI-NEXT: .LBB109_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v42
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v43
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v62
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v46
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_alignbit_b32 v33, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v41
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v55
-; SI-NEXT: v_alignbit_b32 v34, v30, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v40
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v61
+; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v2
+; SI-NEXT: v_lshr_b64 v[24:25], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v60
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v21
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v44
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v59
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v35, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v53
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v54
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v1
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v23
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v51
-; SI-NEXT: v_alignbit_b32 v36, v22, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v52
+; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v13
+; SI-NEXT: v_lshr_b64 v[16:17], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v58
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v57
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v42
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v37, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v39
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v50
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v1
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v55
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v23
+; SI-NEXT: v_lshr_b64 v[8:9], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v56
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v31
+; SI-NEXT: v_lshr_b64 v[51:52], v[21:22], 16
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v15
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v24
-; SI-NEXT: v_alignbit_b32 v38, v14, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v32
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v40
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v7
+; SI-NEXT: v_lshr_b64 v[53:54], v[29:30], 16
+; SI-NEXT: v_lshr_b64 v[38:39], v[13:14], 16
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v48, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v8
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v1
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v7
-; SI-NEXT: v_alignbit_b32 v49, v6, v0, 16
-; SI-NEXT: v_lshr_b64 v[3:4], v[48:49], 24
-; SI-NEXT: v_lshr_b64 v[11:12], v[37:38], 24
-; SI-NEXT: v_lshr_b64 v[19:20], v[35:36], 24
-; SI-NEXT: v_lshr_b64 v[27:28], v[33:34], 24
-; SI-NEXT: v_lshr_b64 v[4:5], v[48:49], 16
-; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 8
-; SI-NEXT: v_lshr_b64 v[12:13], v[37:38], 16
-; SI-NEXT: v_lshr_b64 v[9:10], v[37:38], 8
-; SI-NEXT: v_lshr_b64 v[20:21], v[35:36], 16
-; SI-NEXT: v_lshr_b64 v[17:18], v[35:36], 8
-; SI-NEXT: v_lshr_b64 v[28:29], v[33:34], 16
-; SI-NEXT: v_lshr_b64 v[25:26], v[33:34], 8
-; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v49
-; SI-NEXT: v_lshrrev_b32_e32 v13, 8, v38
-; SI-NEXT: v_lshrrev_b32_e32 v21, 8, v36
-; SI-NEXT: v_lshrrev_b32_e32 v29, 8, v34
+; SI-NEXT: v_lshr_b64 v[35:36], v[5:6], 16
+; SI-NEXT: v_mov_b32_e32 v17, v51
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_mov_b32_e32 v25, v53
+; SI-NEXT: v_mov_b32_e32 v9, v38
+; SI-NEXT: v_mov_b32_e32 v1, v35
+; SI-NEXT: v_lshr_b64 v[48:49], v[16:17], 16
+; SI-NEXT: v_lshr_b64 v[3:4], v[0:1], 24
+; SI-NEXT: v_lshr_b64 v[33:34], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[0:1], 8
+; SI-NEXT: v_lshr_b64 v[11:12], v[8:9], 24
+; SI-NEXT: v_lshr_b64 v[36:37], v[8:9], 16
+; SI-NEXT: v_lshr_b64 v[9:10], v[8:9], 8
+; SI-NEXT: v_lshr_b64 v[19:20], v[16:17], 24
+; SI-NEXT: v_lshr_b64 v[17:18], v[16:17], 8
+; SI-NEXT: v_lshr_b64 v[27:28], v[24:25], 24
+; SI-NEXT: v_lshr_b64 v[49:50], v[24:25], 16
+; SI-NEXT: v_lshr_b64 v[25:26], v[24:25], 8
+; SI-NEXT: v_lshrrev_b32_e32 v10, 8, v35
+; SI-NEXT: v_lshrrev_b32_e32 v34, 8, v38
+; SI-NEXT: v_lshrrev_b32_e32 v32, 8, v51
+; SI-NEXT: v_lshrrev_b32_e32 v37, 8, v53
; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v7
; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v15
; SI-NEXT: v_lshrrev_b32_e32 v23, 24, v23
; SI-NEXT: v_lshrrev_b32_e32 v31, 24, v31
; SI-NEXT: .LBB109_3: ; %end
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v0, v48
-; SI-NEXT: v_mov_b32_e32 v2, v4
-; SI-NEXT: v_mov_b32_e32 v4, v49
-; SI-NEXT: v_mov_b32_e32 v8, v37
-; SI-NEXT: v_mov_b32_e32 v10, v12
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v2, v33
+; SI-NEXT: v_mov_b32_e32 v4, v35
+; SI-NEXT: v_mov_b32_e32 v5, v10
+; SI-NEXT: v_mov_b32_e32 v10, v36
; SI-NEXT: v_mov_b32_e32 v12, v38
-; SI-NEXT: v_mov_b32_e32 v16, v35
-; SI-NEXT: v_mov_b32_e32 v18, v20
-; SI-NEXT: v_mov_b32_e32 v20, v36
-; SI-NEXT: v_mov_b32_e32 v24, v33
-; SI-NEXT: v_mov_b32_e32 v26, v28
-; SI-NEXT: v_mov_b32_e32 v28, v34
+; SI-NEXT: v_mov_b32_e32 v13, v34
+; SI-NEXT: v_mov_b32_e32 v18, v48
+; SI-NEXT: v_mov_b32_e32 v20, v51
+; SI-NEXT: v_mov_b32_e32 v21, v32
+; SI-NEXT: v_mov_b32_e32 v26, v49
+; SI-NEXT: v_mov_b32_e32 v28, v53
+; SI-NEXT: v_mov_b32_e32 v29, v37
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB109_4:
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: s_branch .LBB109_2
;
; VI-LABEL: bitcast_v16bf16_to_v32i8_scalar:
@@ -40291,26 +40354,26 @@ define inreg <32 x i8> @bitcast_v16bf16_to_v32i8_scalar(<16 x bfloat> inreg %a,
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB109_3
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: s_lshr_b32 s14, s23, 24
-; VI-NEXT: s_lshr_b32 s15, s23, 16
-; VI-NEXT: s_lshr_b32 s25, s23, 8
-; VI-NEXT: s_lshr_b32 s24, s22, 16
-; VI-NEXT: s_lshr_b32 s26, s22, 8
-; VI-NEXT: s_lshr_b32 s27, s21, 24
-; VI-NEXT: s_lshr_b32 s28, s21, 16
-; VI-NEXT: s_lshr_b32 s40, s21, 8
-; VI-NEXT: s_lshr_b32 s29, s20, 16
-; VI-NEXT: s_lshr_b32 s41, s20, 8
-; VI-NEXT: s_lshr_b32 s42, s19, 24
-; VI-NEXT: s_lshr_b32 s43, s19, 16
-; VI-NEXT: s_lshr_b32 s45, s19, 8
-; VI-NEXT: s_lshr_b32 s44, s18, 16
-; VI-NEXT: s_lshr_b32 s46, s18, 8
-; VI-NEXT: s_lshr_b32 s47, s17, 24
-; VI-NEXT: s_lshr_b32 s56, s17, 16
-; VI-NEXT: s_lshr_b32 s58, s17, 8
-; VI-NEXT: s_lshr_b32 s57, s16, 16
-; VI-NEXT: s_lshr_b32 s59, s16, 8
+; VI-NEXT: s_lshr_b32 s57, s23, 24
+; VI-NEXT: s_lshr_b32 s56, s23, 16
+; VI-NEXT: s_lshr_b32 s47, s23, 8
+; VI-NEXT: s_lshr_b32 s59, s22, 16
+; VI-NEXT: s_lshr_b32 s58, s22, 8
+; VI-NEXT: s_lshr_b32 s44, s21, 24
+; VI-NEXT: s_lshr_b32 s43, s21, 16
+; VI-NEXT: s_lshr_b32 s42, s21, 8
+; VI-NEXT: s_lshr_b32 s46, s20, 16
+; VI-NEXT: s_lshr_b32 s45, s20, 8
+; VI-NEXT: s_lshr_b32 s29, s19, 24
+; VI-NEXT: s_lshr_b32 s28, s19, 16
+; VI-NEXT: s_lshr_b32 s27, s19, 8
+; VI-NEXT: s_lshr_b32 s41, s18, 16
+; VI-NEXT: s_lshr_b32 s40, s18, 8
+; VI-NEXT: s_lshr_b32 s24, s17, 24
+; VI-NEXT: s_lshr_b32 s15, s17, 16
+; VI-NEXT: s_lshr_b32 s14, s17, 8
+; VI-NEXT: s_lshr_b32 s26, s16, 16
+; VI-NEXT: s_lshr_b32 s25, s16, 8
; VI-NEXT: s_lshr_b64 s[10:11], s[22:23], 24
; VI-NEXT: s_lshr_b64 s[8:9], s[20:21], 24
; VI-NEXT: s_lshr_b64 s[6:7], s[18:19], 24
@@ -40336,225 +40399,225 @@ define inreg <32 x i8> @bitcast_v16bf16_to_v32i8_scalar(<16 x bfloat> inreg %a,
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v1, v0, 16
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
; VI-NEXT: v_add_f32_e32 v0, s4, v2
-; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v2
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: s_lshl_b32 s4, s19, 16
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
; VI-NEXT: v_add_f32_e32 v3, s4, v2
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_alignbit_b32 v0, v3, v0, 16
; VI-NEXT: v_add_f32_e32 v3, s4, v2
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; VI-NEXT: v_bfe_u32 v6, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v3
+; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v2
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v9, v4, v3, 16
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; VI-NEXT: v_add_f32_e32 v3, s4, v2
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v2
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
+; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[5:6]
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_alignbit_b32 v8, v4, v3, 16
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_add_f32_e32 v3, s4, v2
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; VI-NEXT: v_bfe_u32 v6, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v3
+; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v2
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
+; VI-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc
+; VI-NEXT: s_lshl_b32 s4, s21, 16
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; VI-NEXT: v_add_f32_e32 v3, s4, v2
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[5:6]
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_alignbit_b32 v17, v4, v3, 16
+; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_add_f32_e32 v3, s4, v2
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; VI-NEXT: v_bfe_u32 v6, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v3
+; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v2
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
+; VI-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc
+; VI-NEXT: s_lshl_b32 s4, s20, 16
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; VI-NEXT: v_add_f32_e32 v3, s4, v2
+; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[5:6]
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; VI-NEXT: s_lshl_b32 s4, s23, 16
-; VI-NEXT: v_alignbit_b32 v16, v4, v3, 16
+; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_add_f32_e32 v3, s4, v2
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; VI-NEXT: v_bfe_u32 v6, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v3
+; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v2
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
+; VI-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc
+; VI-NEXT: s_lshl_b32 s4, s23, 16
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; VI-NEXT: v_add_f32_e32 v3, s4, v2
+; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[5:6]
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s4, v2
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; VI-NEXT: v_bfe_u32 v6, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v3
+; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc
; VI-NEXT: s_lshl_b32 s4, s22, 16
-; VI-NEXT: v_alignbit_b32 v25, v4, v3, 16
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; VI-NEXT: v_add_f32_e32 v3, s4, v2
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_lshrrev_b64 v[28:29], 16, v[5:6]
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_add_f32_e32 v2, s4, v2
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_bfe_u32 v4, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_alignbit_b32 v24, v2, v3, 16
-; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[24:25]
-; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[16:17]
-; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9]
-; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
-; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v25
-; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v25
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[24:25], 16, v[5:6]
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v25, v28
+; VI-NEXT: v_mov_b32_e32 v1, v4
+; VI-NEXT: v_mov_b32_e32 v9, v12
+; VI-NEXT: v_mov_b32_e32 v17, v20
+; VI-NEXT: v_lshrrev_b64 v[36:37], 24, v[24:25]
+; VI-NEXT: v_lshrrev_b64 v[37:38], 24, v[16:17]
+; VI-NEXT: v_lshrrev_b64 v[34:35], 24, v[8:9]
+; VI-NEXT: v_lshrrev_b64 v[32:33], 24, v[0:1]
+; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v28
+; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v28
+; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v28
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v24
-; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v24
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v17
-; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v17
+; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v24
+; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v20
+; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v20
+; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v16
-; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v16
-; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v9
-; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v9
-; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v9
+; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v16
+; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v12
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v12
+; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v8
-; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v8
-; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v1
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v8
+; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v4
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v4
+; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v0
+; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; VI-NEXT: s_branch .LBB109_5
; VI-NEXT: .LBB109_3:
-; VI-NEXT: ; implicit-def: $sgpr59
-; VI-NEXT: ; implicit-def: $sgpr57
+; VI-NEXT: ; implicit-def: $sgpr25
+; VI-NEXT: ; implicit-def: $sgpr26
; VI-NEXT: ; implicit-def: $sgpr4
-; VI-NEXT: ; implicit-def: $sgpr58
-; VI-NEXT: ; implicit-def: $sgpr56
-; VI-NEXT: ; implicit-def: $sgpr47
-; VI-NEXT: ; implicit-def: $sgpr46
-; VI-NEXT: ; implicit-def: $sgpr44
-; VI-NEXT: ; implicit-def: $sgpr6
-; VI-NEXT: ; implicit-def: $sgpr45
-; VI-NEXT: ; implicit-def: $sgpr43
-; VI-NEXT: ; implicit-def: $sgpr42
+; VI-NEXT: ; implicit-def: $sgpr14
+; VI-NEXT: ; implicit-def: $sgpr15
+; VI-NEXT: ; implicit-def: $sgpr24
+; VI-NEXT: ; implicit-def: $sgpr40
; VI-NEXT: ; implicit-def: $sgpr41
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr27
+; VI-NEXT: ; implicit-def: $sgpr28
; VI-NEXT: ; implicit-def: $sgpr29
+; VI-NEXT: ; implicit-def: $sgpr45
+; VI-NEXT: ; implicit-def: $sgpr46
; VI-NEXT: ; implicit-def: $sgpr8
-; VI-NEXT: ; implicit-def: $sgpr40
-; VI-NEXT: ; implicit-def: $sgpr28
-; VI-NEXT: ; implicit-def: $sgpr27
-; VI-NEXT: ; implicit-def: $sgpr26
-; VI-NEXT: ; implicit-def: $sgpr24
+; VI-NEXT: ; implicit-def: $sgpr42
+; VI-NEXT: ; implicit-def: $sgpr43
+; VI-NEXT: ; implicit-def: $sgpr44
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr59
; VI-NEXT: ; implicit-def: $sgpr10
-; VI-NEXT: ; implicit-def: $sgpr25
-; VI-NEXT: ; implicit-def: $sgpr15
-; VI-NEXT: ; implicit-def: $sgpr14
+; VI-NEXT: ; implicit-def: $sgpr47
+; VI-NEXT: ; implicit-def: $sgpr56
+; VI-NEXT: ; implicit-def: $sgpr57
; VI-NEXT: s_branch .LBB109_2
; VI-NEXT: .LBB109_4:
-; VI-NEXT: v_mov_b32_e32 v0, s16
-; VI-NEXT: v_mov_b32_e32 v1, s17
-; VI-NEXT: v_mov_b32_e32 v8, s18
-; VI-NEXT: v_mov_b32_e32 v9, s19
-; VI-NEXT: v_mov_b32_e32 v16, s20
-; VI-NEXT: v_mov_b32_e32 v17, s21
+; VI-NEXT: v_mov_b32_e32 v26, s59
+; VI-NEXT: v_mov_b32_e32 v25, s58
+; VI-NEXT: v_mov_b32_e32 v31, s57
+; VI-NEXT: v_mov_b32_e32 v30, s56
+; VI-NEXT: v_mov_b32_e32 v29, s47
+; VI-NEXT: v_mov_b32_e32 v18, s46
+; VI-NEXT: v_mov_b32_e32 v17, s45
+; VI-NEXT: v_mov_b32_e32 v23, s44
+; VI-NEXT: v_mov_b32_e32 v22, s43
+; VI-NEXT: v_mov_b32_e32 v21, s42
+; VI-NEXT: v_mov_b32_e32 v10, s41
+; VI-NEXT: v_mov_b32_e32 v9, s40
+; VI-NEXT: v_mov_b32_e32 v15, s29
+; VI-NEXT: v_mov_b32_e32 v14, s28
+; VI-NEXT: v_mov_b32_e32 v13, s27
+; VI-NEXT: v_mov_b32_e32 v2, s26
+; VI-NEXT: v_mov_b32_e32 v1, s25
+; VI-NEXT: v_mov_b32_e32 v7, s24
+; VI-NEXT: v_mov_b32_e32 v6, s15
+; VI-NEXT: v_mov_b32_e32 v5, s14
; VI-NEXT: v_mov_b32_e32 v24, s22
-; VI-NEXT: v_mov_b32_e32 v25, s23
-; VI-NEXT: v_mov_b32_e32 v35, s59
-; VI-NEXT: v_mov_b32_e32 v2, s57
-; VI-NEXT: v_mov_b32_e32 v5, s58
-; VI-NEXT: v_mov_b32_e32 v6, s56
-; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_mov_b32_e32 v34, s46
-; VI-NEXT: v_mov_b32_e32 v10, s44
-; VI-NEXT: v_mov_b32_e32 v13, s45
-; VI-NEXT: v_mov_b32_e32 v14, s43
-; VI-NEXT: v_mov_b32_e32 v15, s42
-; VI-NEXT: v_mov_b32_e32 v33, s41
-; VI-NEXT: v_mov_b32_e32 v18, s29
-; VI-NEXT: v_mov_b32_e32 v21, s40
-; VI-NEXT: v_mov_b32_e32 v22, s28
-; VI-NEXT: v_mov_b32_e32 v23, s27
-; VI-NEXT: v_mov_b32_e32 v32, s26
-; VI-NEXT: v_mov_b32_e32 v26, s24
-; VI-NEXT: v_mov_b32_e32 v29, s25
-; VI-NEXT: v_mov_b32_e32 v30, s15
-; VI-NEXT: v_mov_b32_e32 v31, s14
-; VI-NEXT: v_mov_b32_e32 v27, s10
-; VI-NEXT: v_mov_b32_e32 v19, s8
-; VI-NEXT: v_mov_b32_e32 v11, s6
-; VI-NEXT: v_mov_b32_e32 v3, s4
+; VI-NEXT: v_mov_b32_e32 v28, s23
+; VI-NEXT: v_mov_b32_e32 v16, s20
+; VI-NEXT: v_mov_b32_e32 v20, s21
+; VI-NEXT: v_mov_b32_e32 v8, s18
+; VI-NEXT: v_mov_b32_e32 v12, s19
+; VI-NEXT: v_mov_b32_e32 v0, s16
+; VI-NEXT: v_mov_b32_e32 v4, s17
+; VI-NEXT: v_mov_b32_e32 v36, s10
+; VI-NEXT: v_mov_b32_e32 v37, s8
+; VI-NEXT: v_mov_b32_e32 v34, s6
+; VI-NEXT: v_mov_b32_e32 v32, s4
; VI-NEXT: .LBB109_5: ; %end
-; VI-NEXT: v_mov_b32_e32 v4, v1
-; VI-NEXT: v_mov_b32_e32 v12, v9
-; VI-NEXT: v_mov_b32_e32 v20, v17
-; VI-NEXT: v_mov_b32_e32 v28, v25
-; VI-NEXT: v_mov_b32_e32 v1, v35
-; VI-NEXT: v_mov_b32_e32 v9, v34
-; VI-NEXT: v_mov_b32_e32 v17, v33
-; VI-NEXT: v_mov_b32_e32 v25, v32
+; VI-NEXT: v_mov_b32_e32 v3, v32
+; VI-NEXT: v_mov_b32_e32 v11, v34
+; VI-NEXT: v_mov_b32_e32 v19, v37
+; VI-NEXT: v_mov_b32_e32 v27, v36
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16bf16_to_v32i8_scalar:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
index 73b57a52201af..8055ea8be5261 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
@@ -1392,20 +1392,20 @@ define inreg i32 @bitcast_v2bf16_to_i32_scalar(<2 x bfloat> inreg %a, i32 inreg
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s18, 0
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s17
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s16
; SI-NEXT: s_cbranch_scc0 .LBB15_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4
+; SI-NEXT: v_lshr_b64 v[0:1], v[2:3], 16
; SI-NEXT: s_cbranch_execnz .LBB15_3
; SI-NEXT: .LBB15_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
; SI-NEXT: .LBB15_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB15_4:
@@ -1421,24 +1421,24 @@ define inreg i32 @bitcast_v2bf16_to_i32_scalar(<2 x bfloat> inreg %a, i32 inreg
; VI-NEXT: s_cbranch_execnz .LBB15_4
; VI-NEXT: .LBB15_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v1
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v1, s4, v1
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB15_3:
; VI-NEXT: s_branch .LBB15_2
@@ -3671,20 +3671,20 @@ define inreg float @bitcast_v2bf16_to_f32_scalar(<2 x bfloat> inreg %a, i32 inre
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s18, 0
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s17
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s16
; SI-NEXT: s_cbranch_scc0 .LBB35_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4
+; SI-NEXT: v_lshr_b64 v[0:1], v[2:3], 16
; SI-NEXT: s_cbranch_execnz .LBB35_3
; SI-NEXT: .LBB35_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
; SI-NEXT: .LBB35_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB35_4:
@@ -3700,24 +3700,24 @@ define inreg float @bitcast_v2bf16_to_f32_scalar(<2 x bfloat> inreg %a, i32 inre
; VI-NEXT: s_cbranch_execnz .LBB35_4
; VI-NEXT: .LBB35_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v1
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v1, s4, v1
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB35_3:
; VI-NEXT: s_branch .LBB35_2
@@ -5581,24 +5581,25 @@ define inreg <2 x i16> @bitcast_v2bf16_to_v2i16_scalar(<2 x bfloat> inreg %a, i3
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s18, 0
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v0, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v3, 1.0, s17
; SI-NEXT: s_cbranch_scc0 .LBB51_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
; SI-NEXT: s_cbranch_execnz .LBB51_3
; SI-NEXT: .LBB51_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[0:1], 16
; SI-NEXT: .LBB51_3: ; %end
+; SI-NEXT: v_mov_b32_e32 v0, v2
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB51_4:
-; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_branch .LBB51_2
;
@@ -5611,24 +5612,24 @@ define inreg <2 x i16> @bitcast_v2bf16_to_v2i16_scalar(<2 x bfloat> inreg %a, i3
; VI-NEXT: s_cbranch_execnz .LBB51_4
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v1
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v1, s4, v1
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB51_3:
; VI-NEXT: s_branch .LBB51_2
@@ -7278,24 +7279,24 @@ define inreg <2 x half> @bitcast_v2bf16_to_v2f16_scalar(<2 x bfloat> inreg %a, i
; VI-NEXT: s_cbranch_execnz .LBB63_4
; VI-NEXT: .LBB63_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v1
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v1, s4, v1
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB63_3:
; VI-NEXT: s_branch .LBB63_2
@@ -8720,20 +8721,20 @@ define inreg <1 x i32> @bitcast_v2bf16_to_v1i32_scalar(<2 x bfloat> inreg %a, i3
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s18, 0
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s17
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s16
; SI-NEXT: s_cbranch_scc0 .LBB73_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4
+; SI-NEXT: v_lshr_b64 v[0:1], v[2:3], 16
; SI-NEXT: s_cbranch_execnz .LBB73_3
; SI-NEXT: .LBB73_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
; SI-NEXT: .LBB73_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB73_4:
@@ -8749,24 +8750,24 @@ define inreg <1 x i32> @bitcast_v2bf16_to_v1i32_scalar(<2 x bfloat> inreg %a, i3
; VI-NEXT: s_cbranch_execnz .LBB73_4
; VI-NEXT: .LBB73_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v1
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v1, s4, v1
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB73_3:
; VI-NEXT: s_branch .LBB73_2
@@ -9336,30 +9337,31 @@ define inreg <4 x i8> @bitcast_v2bf16_to_v4i8_scalar(<2 x bfloat> inreg %a, i32
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s18, 0
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v0, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s16
; SI-NEXT: s_cbranch_scc0 .LBB77_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; SI-NEXT: v_alignbit_b32 v0, v2, v5, 16
-; SI-NEXT: v_lshrrev_b32_e32 v3, 24, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; SI-NEXT: v_lshr_b64 v[4:5], v[1:2], 16
+; SI-NEXT: v_lshrrev_b32_e32 v3, 24, v0
+; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; SI-NEXT: s_cbranch_execnz .LBB77_3
; SI-NEXT: .LBB77_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; SI-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; SI-NEXT: v_lshr_b64 v[4:5], v[1:2], 16
+; SI-NEXT: v_lshrrev_b32_e32 v3, 24, v0
+; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; SI-NEXT: .LBB77_3: ; %end
+; SI-NEXT: v_mov_b32_e32 v0, v4
+; SI-NEXT: v_mov_b32_e32 v1, v5
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB77_4:
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: s_branch .LBB77_2
;
@@ -9369,9 +9371,9 @@ define inreg <4 x i8> @bitcast_v2bf16_to_v4i8_scalar(<2 x bfloat> inreg %a, i32
; VI-NEXT: s_cmp_lg_u32 s17, 0
; VI-NEXT: s_cbranch_scc0 .LBB77_3
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: s_lshr_b32 s7, s16, 24
-; VI-NEXT: s_lshr_b32 s6, s16, 16
-; VI-NEXT: s_lshr_b32 s8, s16, 8
+; VI-NEXT: s_lshr_b32 s6, s16, 24
+; VI-NEXT: s_lshr_b32 s8, s16, 16
+; VI-NEXT: s_lshr_b32 s7, s16, 8
; VI-NEXT: s_cbranch_execnz .LBB77_4
; VI-NEXT: .LBB77_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s16, 16
@@ -9392,21 +9394,21 @@ define inreg <4 x i8> @bitcast_v2bf16_to_v4i8_scalar(<2 x bfloat> inreg %a, i32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; VI-NEXT: v_alignbit_b32 v4, v2, v1, 16
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[1:2]
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v4
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB77_3:
+; VI-NEXT: ; implicit-def: $sgpr7
; VI-NEXT: ; implicit-def: $sgpr8
; VI-NEXT: ; implicit-def: $sgpr6
-; VI-NEXT: ; implicit-def: $sgpr7
; VI-NEXT: s_branch .LBB77_2
; VI-NEXT: .LBB77_4:
-; VI-NEXT: v_mov_b32_e32 v1, s8
-; VI-NEXT: v_mov_b32_e32 v3, s7
-; VI-NEXT: v_mov_b32_e32 v2, s6
+; VI-NEXT: v_mov_b32_e32 v2, s8
; VI-NEXT: v_mov_b32_e32 v0, s16
+; VI-NEXT: v_mov_b32_e32 v3, s6
+; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v2bf16_to_v4i8_scalar:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
index d5d2d4aafaa19..08038b90687c0 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
@@ -290,34 +290,34 @@ define inreg <3 x half> @bitcast_v3bf16_to_v3f16_scalar(<3 x bfloat> inreg %a, i
; VI-NEXT: s_cbranch_execnz .LBB1_4
; VI-NEXT: .LBB1_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v1
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v1
+; VI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v1, s4, v1
; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v2, 16
-; VI-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB1_3:
; VI-NEXT: s_branch .LBB1_2
@@ -964,16 +964,16 @@ define inreg <3 x i16> @bitcast_v3bf16_to_v3i16_scalar(<3 x bfloat> inreg %a, i3
; SI-NEXT: s_cbranch_execnz .LBB5_3
; SI-NEXT: .LBB5_2: ; %cmp.true
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v1
+; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshr_b64 v[3:4], v[1:2], 16
-; SI-NEXT: v_alignbit_b32 v0, v5, v0, 16
; SI-NEXT: .LBB5_3: ; %end
; SI-NEXT: v_mov_b32_e32 v1, v3
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -992,34 +992,34 @@ define inreg <3 x i16> @bitcast_v3bf16_to_v3i16_scalar(<3 x bfloat> inreg %a, i3
; VI-NEXT: s_cbranch_execnz .LBB5_4
; VI-NEXT: .LBB5_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v1
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v1
+; VI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v1, s4, v1
; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v2, 16
-; VI-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB5_3:
; VI-NEXT: s_branch .LBB5_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index ee23420c2a662..421a7fe57c36a 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -6495,172 +6495,211 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e64 v34, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v35, 1.0, s16
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v14
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_mul_f32_e64 v60, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v59, 1.0, s19
+; SI-NEXT: v_mul_f32_e32 v56, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v47, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v46, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v45, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v44, 1.0, v9
+; SI-NEXT: v_mul_f32_e32 v43, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v42, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v41, 1.0, v15
; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e64 v63, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v62, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v61, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v58, 1.0, s27
+; SI-NEXT: v_mul_f32_e64 v57, 1.0, s29
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v0
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v14
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
-; SI-NEXT: v_mul_f32_e64 v54, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v55, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v52, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v53, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v50, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v51, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v48, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v49, 1.0, s24
-; SI-NEXT: v_mul_f32_e64 v38, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v39, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v36, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v37, 1.0, s28
+; SI-NEXT: v_mul_f32_e64 v54, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v52, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v50, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v48, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v38, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v36, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v34, 1.0, s28
; SI-NEXT: s_cbranch_scc0 .LBB23_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v17
-; SI-NEXT: v_alignbit_b32 v0, v0, v35, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v55, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v53, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v51, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v49, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v39, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v37, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v33, 16
-; SI-NEXT: v_alignbit_b32 v8, v8, v31, 16
-; SI-NEXT: v_alignbit_b32 v9, v9, v29, 16
-; SI-NEXT: v_alignbit_b32 v10, v10, v27, 16
-; SI-NEXT: v_alignbit_b32 v11, v11, v25, 16
-; SI-NEXT: v_alignbit_b32 v12, v12, v23, 16
-; SI-NEXT: v_alignbit_b32 v13, v13, v21, 16
-; SI-NEXT: v_alignbit_b32 v14, v14, v19, 16
-; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v60
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v59
+; SI-NEXT: v_lshr_b64 v[0:1], v[54:55], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[52:53], 16
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v63
+; SI-NEXT: v_lshr_b64 v[2:3], v[50:51], 16
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v62
+; SI-NEXT: v_lshr_b64 v[3:4], v[48:49], 16
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v61
+; SI-NEXT: v_lshr_b64 v[4:5], v[38:39], 16
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v58
+; SI-NEXT: v_lshr_b64 v[5:6], v[36:37], 16
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v57
+; SI-NEXT: v_lshr_b64 v[6:7], v[34:35], 16
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v56
+; SI-NEXT: v_lshr_b64 v[7:8], v[32:33], 16
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v47
+; SI-NEXT: v_lshr_b64 v[8:9], v[30:31], 16
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v46
+; SI-NEXT: v_lshr_b64 v[9:10], v[28:29], 16
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v45
+; SI-NEXT: v_lshr_b64 v[10:11], v[26:27], 16
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v44
+; SI-NEXT: v_lshr_b64 v[11:12], v[24:25], 16
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v43
+; SI-NEXT: v_lshr_b64 v[12:13], v[22:23], 16
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v42
+; SI-NEXT: v_lshr_b64 v[13:14], v[20:21], 16
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v41
+; SI-NEXT: v_lshr_b64 v[14:15], v[18:19], 16
+; SI-NEXT: v_mov_b32_e32 v15, v17
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v15
+; SI-NEXT: v_lshr_b64 v[39:40], v[16:17], 16
+; SI-NEXT: v_mov_b32_e32 v17, v15
+; SI-NEXT: v_mov_b32_e32 v15, v39
; SI-NEXT: s_cbranch_execnz .LBB23_3
; SI-NEXT: .LBB23_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v34
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v35
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v60
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v54
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v59
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v54
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v55
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v52
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v53
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v63
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v50
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v50
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v51
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v62
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v48
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v48
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v49
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v61
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v38
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v38
-; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v39
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v58
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v36
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v36
-; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v37
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v57
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v34
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v32
-; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v56
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v32
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v30
-; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
+; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v47
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v28
-; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
+; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v46
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v28
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
-; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
+; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v45
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v26
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v24
-; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
+; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v44
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v24
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
-; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
+; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v43
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v20
-; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
+; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v42
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v20
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18
-; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v41
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v18
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v17
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
+; SI-NEXT: v_lshr_b64 v[16:17], v[16:17], 16
+; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
+; SI-NEXT: v_mov_b32_e32 v15, v16
; SI-NEXT: .LBB23_3: ; %end
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB23_4:
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
@@ -6670,11 +6709,11 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v19, s30, 0
+; VI-NEXT: v_writelane_b32 v20, s30, 0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; VI-NEXT: v_writelane_b32 v19, s31, 1
+; VI-NEXT: v_writelane_b32 v20, s31, 1
; VI-NEXT: v_readfirstlane_b32 s30, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s31, v1
@@ -6682,295 +6721,303 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB23_4
; VI-NEXT: .LBB23_2: ; %cmp.true
-; VI-NEXT: s_lshl_b32 s4, s31, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s31, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_mov_b32_e32 v16, 0x40c00000
; VI-NEXT: s_lshl_b32 s4, s30, 16
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s30, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v0
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_alignbit_b32 v15, v2, v1, 16
-; VI-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: s_lshl_b32 s4, s29, 16
-; VI-NEXT: v_alignbit_b32 v14, v1, v3, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v16
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: s_lshl_b32 s4, s28, 16
-; VI-NEXT: v_alignbit_b32 v13, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v16
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: s_and_b32 s6, s28, 0xffff0000
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s27, 16
-; VI-NEXT: v_alignbit_b32 v12, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s27, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
+; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[0:1]
+; VI-NEXT: v_cndmask_b32_e64 v0, v3, v4, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; VI-NEXT: s_and_b32 s5, s26, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s26, 16
-; VI-NEXT: v_alignbit_b32 v11, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s26, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s25, 16
-; VI-NEXT: v_alignbit_b32 v10, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s25, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s24, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s24, 16
-; VI-NEXT: v_alignbit_b32 v9, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s24, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s23, 16
-; VI-NEXT: v_alignbit_b32 v8, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s22, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s22, 16
-; VI-NEXT: v_alignbit_b32 v7, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_alignbit_b32 v6, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s20, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_alignbit_b32 v5, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_alignbit_b32 v4, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v16, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s18, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v16, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v2
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v16, v17, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v16, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v1
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v16, v17, vcc
-; VI-NEXT: v_add_f32_e32 v16, s4, v0
-; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v16, v1, 16
-; VI-NEXT: v_add_f32_e32 v16, s4, v0
-; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s6, v16
+; VI-NEXT: v_bfe_u32 v5, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; VI-NEXT: s_lshl_b32 s6, s17, 16
+; VI-NEXT: v_cndmask_b32_e64 v0, v1, v3, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v1, v3, 16, 1
+; VI-NEXT: s_and_b32 s6, s17, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc
+; VI-NEXT: s_lshl_b32 s6, s19, 16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_cndmask_b32_e64 v17, v1, v5, s[4:5]
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: s_and_b32 s6, s19, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
+; VI-NEXT: s_lshl_b32 s6, s21, 16
+; VI-NEXT: v_mov_b32_e32 v1, v17
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_cndmask_b32_e64 v17, v5, v7, s[4:5]
+; VI-NEXT: v_add_f32_e32 v5, s6, v16
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: s_and_b32 s6, s21, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v3, v9, v11, vcc
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v5, v5
+; VI-NEXT: v_add_f32_e32 v5, s6, v16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
+; VI-NEXT: v_bfe_u32 v11, v5, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v5
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: s_lshl_b32 s6, s23, 16
+; VI-NEXT: v_mov_b32_e32 v3, v17
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_cndmask_b32_e64 v17, v7, v9, s[4:5]
+; VI-NEXT: v_add_f32_e32 v7, s6, v16
+; VI-NEXT: v_cndmask_b32_e32 v5, v11, v13, vcc
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: s_and_b32 s6, s23, 0xffff0000
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v5
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v7, v7
+; VI-NEXT: v_add_f32_e32 v7, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_bfe_u32 v13, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v7
+; VI-NEXT: s_lshl_b32 s6, s25, 16
+; VI-NEXT: v_mov_b32_e32 v5, v17
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_cndmask_b32_e64 v17, v9, v11, s[4:5]
+; VI-NEXT: v_add_f32_e32 v9, s6, v16
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: s_and_b32 s6, s25, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v7, v13, v15, vcc
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v9, v9
+; VI-NEXT: v_add_f32_e32 v9, s6, v16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v7
+; VI-NEXT: v_bfe_u32 v15, v9, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v9
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_mov_b32_e32 v7, v17
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_cndmask_b32_e32 v9, v15, v17, vcc
+; VI-NEXT: s_lshl_b32 s6, s27, 16
+; VI-NEXT: v_cndmask_b32_e64 v17, v11, v13, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; VI-NEXT: v_add_f32_e32 v11, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: s_and_b32 s6, s27, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v11, v11
+; VI-NEXT: v_add_f32_e32 v11, s6, v16
+; VI-NEXT: v_mov_b32_e32 v9, v17
+; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: v_bfe_u32 v17, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v0
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: s_and_b32 s7, s31, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
+; VI-NEXT: v_cndmask_b32_e64 v17, v13, v15, s[4:5]
+; VI-NEXT: v_add_f32_e32 v13, s7, v16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: s_lshl_b32 s6, s31, 16
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_mov_b32_e32 v11, v17
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_add_f32_e32 v13, s6, v16
+; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
+; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v16, 16
+; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_add_f32_e32 v13, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v15
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: s_lshl_b32 s4, s29, 16
+; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc
+; VI-NEXT: v_add_f32_e32 v15, s4, v16
+; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
+; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_cndmask_b32_e32 v15, v16, v19, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
+; VI-NEXT: v_lshrrev_b64 v[15:16], 16, v[15:16]
+; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[17:18]
+; VI-NEXT: v_mov_b32_e32 v13, v15
+; VI-NEXT: v_mov_b32_e32 v15, v16
; VI-NEXT: s_branch .LBB23_5
; VI-NEXT: .LBB23_3:
; VI-NEXT: s_branch .LBB23_2
@@ -6992,10 +7039,10 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
; VI-NEXT: .LBB23_5: ; %end
-; VI-NEXT: v_readlane_b32 s31, v19, 1
-; VI-NEXT: v_readlane_b32 s30, v19, 0
+; VI-NEXT: v_readlane_b32 s31, v20, 1
+; VI-NEXT: v_readlane_b32 s30, v20, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -21386,172 +21433,211 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e64 v34, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v35, 1.0, s16
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v14
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_mul_f32_e64 v60, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v59, 1.0, s19
+; SI-NEXT: v_mul_f32_e32 v56, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v47, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v46, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v45, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v44, 1.0, v9
+; SI-NEXT: v_mul_f32_e32 v43, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v42, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v41, 1.0, v15
; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e64 v63, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v62, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v61, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v58, 1.0, s27
+; SI-NEXT: v_mul_f32_e64 v57, 1.0, s29
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v0
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v14
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
-; SI-NEXT: v_mul_f32_e64 v54, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v55, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v52, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v53, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v50, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v51, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v48, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v49, 1.0, s24
-; SI-NEXT: v_mul_f32_e64 v38, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v39, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v36, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v37, 1.0, s28
+; SI-NEXT: v_mul_f32_e64 v54, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v52, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v50, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v48, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v38, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v36, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v34, 1.0, s28
; SI-NEXT: s_cbranch_scc0 .LBB47_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v17
-; SI-NEXT: v_alignbit_b32 v0, v0, v35, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v55, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v53, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v51, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v49, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v39, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v37, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v33, 16
-; SI-NEXT: v_alignbit_b32 v8, v8, v31, 16
-; SI-NEXT: v_alignbit_b32 v9, v9, v29, 16
-; SI-NEXT: v_alignbit_b32 v10, v10, v27, 16
-; SI-NEXT: v_alignbit_b32 v11, v11, v25, 16
-; SI-NEXT: v_alignbit_b32 v12, v12, v23, 16
-; SI-NEXT: v_alignbit_b32 v13, v13, v21, 16
-; SI-NEXT: v_alignbit_b32 v14, v14, v19, 16
-; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v60
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v59
+; SI-NEXT: v_lshr_b64 v[0:1], v[54:55], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[52:53], 16
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v63
+; SI-NEXT: v_lshr_b64 v[2:3], v[50:51], 16
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v62
+; SI-NEXT: v_lshr_b64 v[3:4], v[48:49], 16
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v61
+; SI-NEXT: v_lshr_b64 v[4:5], v[38:39], 16
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v58
+; SI-NEXT: v_lshr_b64 v[5:6], v[36:37], 16
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v57
+; SI-NEXT: v_lshr_b64 v[6:7], v[34:35], 16
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v56
+; SI-NEXT: v_lshr_b64 v[7:8], v[32:33], 16
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v47
+; SI-NEXT: v_lshr_b64 v[8:9], v[30:31], 16
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v46
+; SI-NEXT: v_lshr_b64 v[9:10], v[28:29], 16
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v45
+; SI-NEXT: v_lshr_b64 v[10:11], v[26:27], 16
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v44
+; SI-NEXT: v_lshr_b64 v[11:12], v[24:25], 16
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v43
+; SI-NEXT: v_lshr_b64 v[12:13], v[22:23], 16
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v42
+; SI-NEXT: v_lshr_b64 v[13:14], v[20:21], 16
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v41
+; SI-NEXT: v_lshr_b64 v[14:15], v[18:19], 16
+; SI-NEXT: v_mov_b32_e32 v15, v17
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v15
+; SI-NEXT: v_lshr_b64 v[39:40], v[16:17], 16
+; SI-NEXT: v_mov_b32_e32 v17, v15
+; SI-NEXT: v_mov_b32_e32 v15, v39
; SI-NEXT: s_cbranch_execnz .LBB47_3
; SI-NEXT: .LBB47_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v34
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v35
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v60
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v54
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v59
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v54
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v55
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v52
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v53
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v63
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v50
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v50
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v51
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v62
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v48
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v48
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v49
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v61
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v38
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v38
-; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v39
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v58
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v36
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v36
-; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v37
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v57
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v34
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v32
-; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v56
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v32
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v30
-; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
+; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v47
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v28
-; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
+; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v46
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v28
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
-; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
+; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v45
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v26
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v24
-; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
+; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v44
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v24
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
-; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
+; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v43
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v20
-; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
+; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v42
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v20
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18
-; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v41
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v18
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v17
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
+; SI-NEXT: v_lshr_b64 v[16:17], v[16:17], 16
+; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
+; SI-NEXT: v_mov_b32_e32 v15, v16
; SI-NEXT: .LBB47_3: ; %end
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB47_4:
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
@@ -21561,11 +21647,11 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v19, s30, 0
+; VI-NEXT: v_writelane_b32 v20, s30, 0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; VI-NEXT: v_writelane_b32 v19, s31, 1
+; VI-NEXT: v_writelane_b32 v20, s31, 1
; VI-NEXT: v_readfirstlane_b32 s30, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s31, v1
@@ -21573,295 +21659,303 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB47_4
; VI-NEXT: .LBB47_2: ; %cmp.true
-; VI-NEXT: s_lshl_b32 s4, s31, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s31, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_mov_b32_e32 v16, 0x40c00000
; VI-NEXT: s_lshl_b32 s4, s30, 16
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s30, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v0
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_alignbit_b32 v15, v2, v1, 16
-; VI-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: s_lshl_b32 s4, s29, 16
-; VI-NEXT: v_alignbit_b32 v14, v1, v3, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v16
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: s_lshl_b32 s4, s28, 16
-; VI-NEXT: v_alignbit_b32 v13, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v16
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: s_and_b32 s6, s28, 0xffff0000
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s27, 16
-; VI-NEXT: v_alignbit_b32 v12, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s27, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
+; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[0:1]
+; VI-NEXT: v_cndmask_b32_e64 v0, v3, v4, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; VI-NEXT: s_and_b32 s5, s26, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s26, 16
-; VI-NEXT: v_alignbit_b32 v11, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s26, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s25, 16
-; VI-NEXT: v_alignbit_b32 v10, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s25, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s24, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s24, 16
-; VI-NEXT: v_alignbit_b32 v9, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s24, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s23, 16
-; VI-NEXT: v_alignbit_b32 v8, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s22, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s22, 16
-; VI-NEXT: v_alignbit_b32 v7, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_alignbit_b32 v6, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s20, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_alignbit_b32 v5, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_alignbit_b32 v4, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v16, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s18, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v16, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v2
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v16, v17, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v16, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v1
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v16, v17, vcc
-; VI-NEXT: v_add_f32_e32 v16, s4, v0
-; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v16, v1, 16
-; VI-NEXT: v_add_f32_e32 v16, s4, v0
-; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s6, v16
+; VI-NEXT: v_bfe_u32 v5, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; VI-NEXT: s_lshl_b32 s6, s17, 16
+; VI-NEXT: v_cndmask_b32_e64 v0, v1, v3, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v1, v3, 16, 1
+; VI-NEXT: s_and_b32 s6, s17, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc
+; VI-NEXT: s_lshl_b32 s6, s19, 16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_cndmask_b32_e64 v17, v1, v5, s[4:5]
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: s_and_b32 s6, s19, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
+; VI-NEXT: s_lshl_b32 s6, s21, 16
+; VI-NEXT: v_mov_b32_e32 v1, v17
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_cndmask_b32_e64 v17, v5, v7, s[4:5]
+; VI-NEXT: v_add_f32_e32 v5, s6, v16
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: s_and_b32 s6, s21, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v3, v9, v11, vcc
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v5, v5
+; VI-NEXT: v_add_f32_e32 v5, s6, v16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
+; VI-NEXT: v_bfe_u32 v11, v5, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v5
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: s_lshl_b32 s6, s23, 16
+; VI-NEXT: v_mov_b32_e32 v3, v17
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_cndmask_b32_e64 v17, v7, v9, s[4:5]
+; VI-NEXT: v_add_f32_e32 v7, s6, v16
+; VI-NEXT: v_cndmask_b32_e32 v5, v11, v13, vcc
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: s_and_b32 s6, s23, 0xffff0000
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v5
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v7, v7
+; VI-NEXT: v_add_f32_e32 v7, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_bfe_u32 v13, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v7
+; VI-NEXT: s_lshl_b32 s6, s25, 16
+; VI-NEXT: v_mov_b32_e32 v5, v17
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_cndmask_b32_e64 v17, v9, v11, s[4:5]
+; VI-NEXT: v_add_f32_e32 v9, s6, v16
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: s_and_b32 s6, s25, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v7, v13, v15, vcc
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v9, v9
+; VI-NEXT: v_add_f32_e32 v9, s6, v16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v7
+; VI-NEXT: v_bfe_u32 v15, v9, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v9
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_mov_b32_e32 v7, v17
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_cndmask_b32_e32 v9, v15, v17, vcc
+; VI-NEXT: s_lshl_b32 s6, s27, 16
+; VI-NEXT: v_cndmask_b32_e64 v17, v11, v13, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; VI-NEXT: v_add_f32_e32 v11, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: s_and_b32 s6, s27, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v11, v11
+; VI-NEXT: v_add_f32_e32 v11, s6, v16
+; VI-NEXT: v_mov_b32_e32 v9, v17
+; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: v_bfe_u32 v17, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v0
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: s_and_b32 s7, s31, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
+; VI-NEXT: v_cndmask_b32_e64 v17, v13, v15, s[4:5]
+; VI-NEXT: v_add_f32_e32 v13, s7, v16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: s_lshl_b32 s6, s31, 16
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_mov_b32_e32 v11, v17
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_add_f32_e32 v13, s6, v16
+; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
+; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v16, 16
+; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_add_f32_e32 v13, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v15
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: s_lshl_b32 s4, s29, 16
+; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc
+; VI-NEXT: v_add_f32_e32 v15, s4, v16
+; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
+; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_cndmask_b32_e32 v15, v16, v19, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
+; VI-NEXT: v_lshrrev_b64 v[15:16], 16, v[15:16]
+; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[17:18]
+; VI-NEXT: v_mov_b32_e32 v13, v15
+; VI-NEXT: v_mov_b32_e32 v15, v16
; VI-NEXT: s_branch .LBB47_5
; VI-NEXT: .LBB47_3:
; VI-NEXT: s_branch .LBB47_2
@@ -21883,10 +21977,10 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
; VI-NEXT: .LBB47_5: ; %end
-; VI-NEXT: v_readlane_b32 s31, v19, 1
-; VI-NEXT: v_readlane_b32 s30, v19, 0
+; VI-NEXT: v_readlane_b32 s31, v20, 1
+; VI-NEXT: v_readlane_b32 s30, v20, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -35785,172 +35879,211 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e64 v34, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v35, 1.0, s16
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v14
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_mul_f32_e64 v60, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v59, 1.0, s19
+; SI-NEXT: v_mul_f32_e32 v56, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v47, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v46, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v45, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v44, 1.0, v9
+; SI-NEXT: v_mul_f32_e32 v43, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v42, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v41, 1.0, v15
; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e64 v63, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v62, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v61, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v58, 1.0, s27
+; SI-NEXT: v_mul_f32_e64 v57, 1.0, s29
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v0
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v14
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
-; SI-NEXT: v_mul_f32_e64 v54, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v55, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v52, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v53, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v50, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v51, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v48, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v49, 1.0, s24
-; SI-NEXT: v_mul_f32_e64 v38, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v39, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v36, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v37, 1.0, s28
+; SI-NEXT: v_mul_f32_e64 v54, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v52, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v50, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v48, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v38, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v36, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v34, 1.0, s28
; SI-NEXT: s_cbranch_scc0 .LBB67_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v17
-; SI-NEXT: v_alignbit_b32 v0, v0, v35, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v55, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v53, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v51, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v49, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v39, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v37, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v33, 16
-; SI-NEXT: v_alignbit_b32 v8, v8, v31, 16
-; SI-NEXT: v_alignbit_b32 v9, v9, v29, 16
-; SI-NEXT: v_alignbit_b32 v10, v10, v27, 16
-; SI-NEXT: v_alignbit_b32 v11, v11, v25, 16
-; SI-NEXT: v_alignbit_b32 v12, v12, v23, 16
-; SI-NEXT: v_alignbit_b32 v13, v13, v21, 16
-; SI-NEXT: v_alignbit_b32 v14, v14, v19, 16
-; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v60
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v59
+; SI-NEXT: v_lshr_b64 v[0:1], v[54:55], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[52:53], 16
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v63
+; SI-NEXT: v_lshr_b64 v[2:3], v[50:51], 16
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v62
+; SI-NEXT: v_lshr_b64 v[3:4], v[48:49], 16
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v61
+; SI-NEXT: v_lshr_b64 v[4:5], v[38:39], 16
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v58
+; SI-NEXT: v_lshr_b64 v[5:6], v[36:37], 16
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v57
+; SI-NEXT: v_lshr_b64 v[6:7], v[34:35], 16
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v56
+; SI-NEXT: v_lshr_b64 v[7:8], v[32:33], 16
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v47
+; SI-NEXT: v_lshr_b64 v[8:9], v[30:31], 16
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v46
+; SI-NEXT: v_lshr_b64 v[9:10], v[28:29], 16
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v45
+; SI-NEXT: v_lshr_b64 v[10:11], v[26:27], 16
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v44
+; SI-NEXT: v_lshr_b64 v[11:12], v[24:25], 16
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v43
+; SI-NEXT: v_lshr_b64 v[12:13], v[22:23], 16
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v42
+; SI-NEXT: v_lshr_b64 v[13:14], v[20:21], 16
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v41
+; SI-NEXT: v_lshr_b64 v[14:15], v[18:19], 16
+; SI-NEXT: v_mov_b32_e32 v15, v17
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v15
+; SI-NEXT: v_lshr_b64 v[39:40], v[16:17], 16
+; SI-NEXT: v_mov_b32_e32 v17, v15
+; SI-NEXT: v_mov_b32_e32 v15, v39
; SI-NEXT: s_cbranch_execnz .LBB67_3
; SI-NEXT: .LBB67_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v34
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v35
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v60
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v54
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v59
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v54
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v55
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v52
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v53
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v63
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v50
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v50
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v51
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v62
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v48
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v48
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v49
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v61
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v38
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v38
-; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v39
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v58
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v36
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v36
-; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v37
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v57
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v34
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v32
-; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v56
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v32
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v30
-; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
+; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v47
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v28
-; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
+; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v46
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v28
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
-; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
+; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v45
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v26
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v24
-; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
+; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v44
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v24
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
-; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
+; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v43
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v20
-; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
+; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v42
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v20
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18
-; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v41
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v18
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v17
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
+; SI-NEXT: v_lshr_b64 v[16:17], v[16:17], 16
+; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
+; SI-NEXT: v_mov_b32_e32 v15, v16
; SI-NEXT: .LBB67_3: ; %end
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB67_4:
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
@@ -35960,11 +36093,11 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v19, s30, 0
+; VI-NEXT: v_writelane_b32 v20, s30, 0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; VI-NEXT: v_writelane_b32 v19, s31, 1
+; VI-NEXT: v_writelane_b32 v20, s31, 1
; VI-NEXT: v_readfirstlane_b32 s30, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s31, v1
@@ -35972,295 +36105,303 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB67_4
; VI-NEXT: .LBB67_2: ; %cmp.true
-; VI-NEXT: s_lshl_b32 s4, s31, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s31, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_mov_b32_e32 v16, 0x40c00000
; VI-NEXT: s_lshl_b32 s4, s30, 16
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s30, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v0
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_alignbit_b32 v15, v2, v1, 16
-; VI-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: s_lshl_b32 s4, s29, 16
-; VI-NEXT: v_alignbit_b32 v14, v1, v3, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v16
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: s_lshl_b32 s4, s28, 16
-; VI-NEXT: v_alignbit_b32 v13, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v16
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: s_and_b32 s6, s28, 0xffff0000
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s27, 16
-; VI-NEXT: v_alignbit_b32 v12, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s27, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
+; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[0:1]
+; VI-NEXT: v_cndmask_b32_e64 v0, v3, v4, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; VI-NEXT: s_and_b32 s5, s26, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s26, 16
-; VI-NEXT: v_alignbit_b32 v11, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s26, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s25, 16
-; VI-NEXT: v_alignbit_b32 v10, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s25, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s24, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s24, 16
-; VI-NEXT: v_alignbit_b32 v9, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s24, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s23, 16
-; VI-NEXT: v_alignbit_b32 v8, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s22, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s22, 16
-; VI-NEXT: v_alignbit_b32 v7, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_alignbit_b32 v6, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s20, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_alignbit_b32 v5, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_alignbit_b32 v4, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v16, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s18, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v16, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v2
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v16, v17, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v16, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v1
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v16, v17, vcc
-; VI-NEXT: v_add_f32_e32 v16, s4, v0
-; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v16, v1, 16
-; VI-NEXT: v_add_f32_e32 v16, s4, v0
-; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s6, v16
+; VI-NEXT: v_bfe_u32 v5, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; VI-NEXT: s_lshl_b32 s6, s17, 16
+; VI-NEXT: v_cndmask_b32_e64 v0, v1, v3, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v1, v3, 16, 1
+; VI-NEXT: s_and_b32 s6, s17, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc
+; VI-NEXT: s_lshl_b32 s6, s19, 16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_cndmask_b32_e64 v17, v1, v5, s[4:5]
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: s_and_b32 s6, s19, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
+; VI-NEXT: s_lshl_b32 s6, s21, 16
+; VI-NEXT: v_mov_b32_e32 v1, v17
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_cndmask_b32_e64 v17, v5, v7, s[4:5]
+; VI-NEXT: v_add_f32_e32 v5, s6, v16
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: s_and_b32 s6, s21, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v3, v9, v11, vcc
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v5, v5
+; VI-NEXT: v_add_f32_e32 v5, s6, v16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
+; VI-NEXT: v_bfe_u32 v11, v5, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v5
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: s_lshl_b32 s6, s23, 16
+; VI-NEXT: v_mov_b32_e32 v3, v17
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_cndmask_b32_e64 v17, v7, v9, s[4:5]
+; VI-NEXT: v_add_f32_e32 v7, s6, v16
+; VI-NEXT: v_cndmask_b32_e32 v5, v11, v13, vcc
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: s_and_b32 s6, s23, 0xffff0000
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v5
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v7, v7
+; VI-NEXT: v_add_f32_e32 v7, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_bfe_u32 v13, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v7
+; VI-NEXT: s_lshl_b32 s6, s25, 16
+; VI-NEXT: v_mov_b32_e32 v5, v17
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_cndmask_b32_e64 v17, v9, v11, s[4:5]
+; VI-NEXT: v_add_f32_e32 v9, s6, v16
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: s_and_b32 s6, s25, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v7, v13, v15, vcc
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v9, v9
+; VI-NEXT: v_add_f32_e32 v9, s6, v16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v7
+; VI-NEXT: v_bfe_u32 v15, v9, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v9
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_mov_b32_e32 v7, v17
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_cndmask_b32_e32 v9, v15, v17, vcc
+; VI-NEXT: s_lshl_b32 s6, s27, 16
+; VI-NEXT: v_cndmask_b32_e64 v17, v11, v13, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; VI-NEXT: v_add_f32_e32 v11, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: s_and_b32 s6, s27, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v11, v11
+; VI-NEXT: v_add_f32_e32 v11, s6, v16
+; VI-NEXT: v_mov_b32_e32 v9, v17
+; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: v_bfe_u32 v17, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v0
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: s_and_b32 s7, s31, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
+; VI-NEXT: v_cndmask_b32_e64 v17, v13, v15, s[4:5]
+; VI-NEXT: v_add_f32_e32 v13, s7, v16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: s_lshl_b32 s6, s31, 16
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_mov_b32_e32 v11, v17
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_add_f32_e32 v13, s6, v16
+; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
+; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v16, 16
+; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_add_f32_e32 v13, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v15
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: s_lshl_b32 s4, s29, 16
+; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc
+; VI-NEXT: v_add_f32_e32 v15, s4, v16
+; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
+; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_cndmask_b32_e32 v15, v16, v19, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
+; VI-NEXT: v_lshrrev_b64 v[15:16], 16, v[15:16]
+; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[17:18]
+; VI-NEXT: v_mov_b32_e32 v13, v15
+; VI-NEXT: v_mov_b32_e32 v15, v16
; VI-NEXT: s_branch .LBB67_5
; VI-NEXT: .LBB67_3:
; VI-NEXT: s_branch .LBB67_2
@@ -36282,10 +36423,10 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
; VI-NEXT: .LBB67_5: ; %end
-; VI-NEXT: v_readlane_b32 s31, v19, 1
-; VI-NEXT: v_readlane_b32 s30, v19, 0
+; VI-NEXT: v_readlane_b32 s31, v20, 1
+; VI-NEXT: v_readlane_b32 s30, v20, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -49244,172 +49385,211 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e64 v34, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v35, 1.0, s16
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v14
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_mul_f32_e64 v60, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v59, 1.0, s19
+; SI-NEXT: v_mul_f32_e32 v56, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v47, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v46, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v45, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v44, 1.0, v9
+; SI-NEXT: v_mul_f32_e32 v43, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v42, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v41, 1.0, v15
; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e64 v63, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v62, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v61, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v58, 1.0, s27
+; SI-NEXT: v_mul_f32_e64 v57, 1.0, s29
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v0
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v14
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
-; SI-NEXT: v_mul_f32_e64 v54, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v55, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v52, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v53, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v50, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v51, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v48, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v49, 1.0, s24
-; SI-NEXT: v_mul_f32_e64 v38, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v39, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v36, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v37, 1.0, s28
+; SI-NEXT: v_mul_f32_e64 v54, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v52, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v50, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v48, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v38, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v36, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v34, 1.0, s28
; SI-NEXT: s_cbranch_scc0 .LBB83_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v17
-; SI-NEXT: v_alignbit_b32 v0, v0, v35, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v55, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v53, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v51, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v49, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v39, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v37, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v33, 16
-; SI-NEXT: v_alignbit_b32 v8, v8, v31, 16
-; SI-NEXT: v_alignbit_b32 v9, v9, v29, 16
-; SI-NEXT: v_alignbit_b32 v10, v10, v27, 16
-; SI-NEXT: v_alignbit_b32 v11, v11, v25, 16
-; SI-NEXT: v_alignbit_b32 v12, v12, v23, 16
-; SI-NEXT: v_alignbit_b32 v13, v13, v21, 16
-; SI-NEXT: v_alignbit_b32 v14, v14, v19, 16
-; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v60
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v59
+; SI-NEXT: v_lshr_b64 v[0:1], v[54:55], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[52:53], 16
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v63
+; SI-NEXT: v_lshr_b64 v[2:3], v[50:51], 16
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v62
+; SI-NEXT: v_lshr_b64 v[3:4], v[48:49], 16
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v61
+; SI-NEXT: v_lshr_b64 v[4:5], v[38:39], 16
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v58
+; SI-NEXT: v_lshr_b64 v[5:6], v[36:37], 16
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v57
+; SI-NEXT: v_lshr_b64 v[6:7], v[34:35], 16
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v56
+; SI-NEXT: v_lshr_b64 v[7:8], v[32:33], 16
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v47
+; SI-NEXT: v_lshr_b64 v[8:9], v[30:31], 16
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v46
+; SI-NEXT: v_lshr_b64 v[9:10], v[28:29], 16
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v45
+; SI-NEXT: v_lshr_b64 v[10:11], v[26:27], 16
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v44
+; SI-NEXT: v_lshr_b64 v[11:12], v[24:25], 16
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v43
+; SI-NEXT: v_lshr_b64 v[12:13], v[22:23], 16
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v42
+; SI-NEXT: v_lshr_b64 v[13:14], v[20:21], 16
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v41
+; SI-NEXT: v_lshr_b64 v[14:15], v[18:19], 16
+; SI-NEXT: v_mov_b32_e32 v15, v17
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v15
+; SI-NEXT: v_lshr_b64 v[39:40], v[16:17], 16
+; SI-NEXT: v_mov_b32_e32 v17, v15
+; SI-NEXT: v_mov_b32_e32 v15, v39
; SI-NEXT: s_cbranch_execnz .LBB83_3
; SI-NEXT: .LBB83_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v34
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v35
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v60
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v54
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v59
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v54
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v55
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v52
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v53
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v63
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v50
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v50
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v51
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v62
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v48
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v48
-; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v49
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v61
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v38
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v38
-; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v39
+; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v58
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v36
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v36
-; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v37
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v57
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v34
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v32
-; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v56
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v32
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v30
-; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
+; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v47
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v28
-; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
+; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v46
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v28
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
-; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
+; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v45
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v26
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v24
-; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
+; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v44
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v24
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
-; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
+; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v43
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v20
-; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
+; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v42
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v20
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18
-; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v41
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v18
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v17
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
+; SI-NEXT: v_lshr_b64 v[16:17], v[16:17], 16
+; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
+; SI-NEXT: v_mov_b32_e32 v15, v16
; SI-NEXT: .LBB83_3: ; %end
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB83_4:
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
@@ -49419,11 +49599,11 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v19, s30, 0
+; VI-NEXT: v_writelane_b32 v20, s30, 0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; VI-NEXT: v_writelane_b32 v19, s31, 1
+; VI-NEXT: v_writelane_b32 v20, s31, 1
; VI-NEXT: v_readfirstlane_b32 s30, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s31, v1
@@ -49431,295 +49611,303 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB83_4
; VI-NEXT: .LBB83_2: ; %cmp.true
-; VI-NEXT: s_lshl_b32 s4, s31, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s31, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_mov_b32_e32 v16, 0x40c00000
; VI-NEXT: s_lshl_b32 s4, s30, 16
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s30, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s4, v0
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_alignbit_b32 v15, v2, v1, 16
-; VI-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: s_lshl_b32 s4, s29, 16
-; VI-NEXT: v_alignbit_b32 v14, v1, v3, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v16
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: s_lshl_b32 s4, s28, 16
-; VI-NEXT: v_alignbit_b32 v13, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v16
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: s_and_b32 s6, s28, 0xffff0000
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s27, 16
-; VI-NEXT: v_alignbit_b32 v12, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s27, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
+; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[0:1]
+; VI-NEXT: v_cndmask_b32_e64 v0, v3, v4, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; VI-NEXT: s_and_b32 s5, s26, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s26, 16
-; VI-NEXT: v_alignbit_b32 v11, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s26, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s25, 16
-; VI-NEXT: v_alignbit_b32 v10, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s25, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s24, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s24, 16
-; VI-NEXT: v_alignbit_b32 v9, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s24, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s23, 16
-; VI-NEXT: v_alignbit_b32 v8, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s22, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s22, 16
-; VI-NEXT: v_alignbit_b32 v7, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_alignbit_b32 v6, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s20, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_alignbit_b32 v5, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_alignbit_b32 v4, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v16, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s18, 0xffff0000
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s5, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v16, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v2
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v16, v17, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v16, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v1
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v16, v17, vcc
-; VI-NEXT: v_add_f32_e32 v16, s4, v0
-; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v16, v1, 16
-; VI-NEXT: v_add_f32_e32 v16, s4, v0
-; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
+; VI-NEXT: v_add_f32_e32 v0, s6, v16
+; VI-NEXT: v_bfe_u32 v5, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; VI-NEXT: s_lshl_b32 s6, s17, 16
+; VI-NEXT: v_cndmask_b32_e64 v0, v1, v3, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v1, v3, 16, 1
+; VI-NEXT: s_and_b32 s6, s17, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc
+; VI-NEXT: s_lshl_b32 s6, s19, 16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_cndmask_b32_e64 v17, v1, v5, s[4:5]
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: s_and_b32 s6, s19, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
+; VI-NEXT: s_lshl_b32 s6, s21, 16
+; VI-NEXT: v_mov_b32_e32 v1, v17
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_cndmask_b32_e64 v17, v5, v7, s[4:5]
+; VI-NEXT: v_add_f32_e32 v5, s6, v16
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: s_and_b32 s6, s21, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v3, v9, v11, vcc
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v5, v5
+; VI-NEXT: v_add_f32_e32 v5, s6, v16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
+; VI-NEXT: v_bfe_u32 v11, v5, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v5
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: s_lshl_b32 s6, s23, 16
+; VI-NEXT: v_mov_b32_e32 v3, v17
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_cndmask_b32_e64 v17, v7, v9, s[4:5]
+; VI-NEXT: v_add_f32_e32 v7, s6, v16
+; VI-NEXT: v_cndmask_b32_e32 v5, v11, v13, vcc
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: s_and_b32 s6, s23, 0xffff0000
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v5
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v7, v7
+; VI-NEXT: v_add_f32_e32 v7, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_bfe_u32 v13, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v7
+; VI-NEXT: s_lshl_b32 s6, s25, 16
+; VI-NEXT: v_mov_b32_e32 v5, v17
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_cndmask_b32_e64 v17, v9, v11, s[4:5]
+; VI-NEXT: v_add_f32_e32 v9, s6, v16
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: s_and_b32 s6, s25, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v7, v13, v15, vcc
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v9, v9
+; VI-NEXT: v_add_f32_e32 v9, s6, v16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v7
+; VI-NEXT: v_bfe_u32 v15, v9, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v9
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_mov_b32_e32 v7, v17
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_cndmask_b32_e32 v9, v15, v17, vcc
+; VI-NEXT: s_lshl_b32 s6, s27, 16
+; VI-NEXT: v_cndmask_b32_e64 v17, v11, v13, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; VI-NEXT: v_add_f32_e32 v11, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: s_and_b32 s6, s27, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v11, v11
+; VI-NEXT: v_add_f32_e32 v11, s6, v16
+; VI-NEXT: v_mov_b32_e32 v9, v17
+; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: v_bfe_u32 v17, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v0
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: s_and_b32 s7, s31, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
+; VI-NEXT: v_cndmask_b32_e64 v17, v13, v15, s[4:5]
+; VI-NEXT: v_add_f32_e32 v13, s7, v16
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: s_lshl_b32 s6, s31, 16
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_mov_b32_e32 v11, v17
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_add_f32_e32 v13, s6, v16
+; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
+; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v16, 16
+; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_add_f32_e32 v13, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v15
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: s_lshl_b32 s4, s29, 16
+; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc
+; VI-NEXT: v_add_f32_e32 v15, s4, v16
+; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
+; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_cndmask_b32_e32 v15, v16, v19, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
+; VI-NEXT: v_lshrrev_b64 v[15:16], 16, v[15:16]
+; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[17:18]
+; VI-NEXT: v_mov_b32_e32 v13, v15
+; VI-NEXT: v_mov_b32_e32 v15, v16
; VI-NEXT: s_branch .LBB83_5
; VI-NEXT: .LBB83_3:
; VI-NEXT: s_branch .LBB83_2
@@ -49741,10 +49929,10 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
; VI-NEXT: .LBB83_5: ; %end
-; VI-NEXT: v_readlane_b32 s31, v19, 1
-; VI-NEXT: v_readlane_b32 s30, v19, 0
+; VI-NEXT: v_readlane_b32 s31, v20, 1
+; VI-NEXT: v_readlane_b32 s30, v20, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -61999,185 +62187,193 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; SI-NEXT: s_waitcnt expcnt(6)
; SI-NEXT: v_mul_f32_e64 v57, 1.0, s16
; SI-NEXT: v_mul_f32_e64 v56, 1.0, s17
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v39, 1.0, v0
+; SI-NEXT: v_mul_f32_e32 v38, 1.0, v1
; SI-NEXT: v_mul_f32_e32 v47, 1.0, v2
; SI-NEXT: v_mul_f32_e32 v46, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v49, 1.0, v5
; SI-NEXT: v_mul_f32_e32 v45, 1.0, v6
; SI-NEXT: v_mul_f32_e32 v44, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v9
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v51, 1.0, v9
; SI-NEXT: v_mul_f32_e32 v43, 1.0, v10
; SI-NEXT: v_mul_f32_e32 v42, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v53, 1.0, v13
; SI-NEXT: v_mul_f32_e32 v41, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v40, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v16
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
-; SI-NEXT: v_mul_f32_e64 v32, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19
+; SI-NEXT: v_mul_f32_e32 v55, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v17
+; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v34, 1.0, s19
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v63, 1.0, s20
; SI-NEXT: v_mul_f32_e64 v62, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v51, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v36, 1.0, s23
; SI-NEXT: v_mul_f32_e64 v61, 1.0, s24
; SI-NEXT: v_mul_f32_e64 v60, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v54, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s27
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v40, 1.0, s27
; SI-NEXT: v_mul_f32_e64 v59, 1.0, s28
; SI-NEXT: v_mul_f32_e64 v58, 1.0, s29
; SI-NEXT: s_cbranch_scc0 .LBB95_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v34
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v63
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v62
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v62
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v36
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v61
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v60
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v40
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v59
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v38
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v49
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v51
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v53
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v30
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v14
; SI-NEXT: s_cbranch_execnz .LBB95_3
; SI-NEXT: .LBB95_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v56
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v56
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v57
-; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v56, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v28
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v62
-; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v63
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v56
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v63
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v62
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; SI-NEXT: v_lshr_b64 v[4:5], v[3:4], 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v61
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v60
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v60
-; SI-NEXT: v_alignbit_b32 v4, v4, v2, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v61
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6
-; SI-NEXT: v_alignbit_b32 v8, v7, v2, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v58
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v59
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v59
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v3
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v58
+; SI-NEXT: v_lshr_b64 v[8:9], v[7:8], 16
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v5
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v45
+; SI-NEXT: v_lshr_b64 v[12:13], v[11:12], 16
+; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v44
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v41
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v47
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v9
+; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v55
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v46
+; SI-NEXT: v_lshr_b64 v[20:21], v[19:20], 16
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v7
-; SI-NEXT: v_alignbit_b32 v12, v10, v2, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v46
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v47
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10
-; SI-NEXT: v_alignbit_b32 v16, v11, v2, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v44
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v45
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v43
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v13
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v18
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v7
+; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v42
+; SI-NEXT: v_lshr_b64 v[28:29], v[27:28], 16
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v49
+; SI-NEXT: v_lshr_b64 v[16:17], v[15:16], 16
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v11
-; SI-NEXT: v_alignbit_b32 v20, v14, v2, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v42
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v43
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v26
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v11
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14
-; SI-NEXT: v_alignbit_b32 v24, v15, v2, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v41
-; SI-NEXT: v_add_f32_e32 v41, 0x40c00000, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v40
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v2
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v29
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v25
+; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v53
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v9
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v39
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; SI-NEXT: v_lshr_b64 v[24:25], v[23:24], 16
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v14
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v38
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v36
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v30
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
-; SI-NEXT: v_alignbit_b32 v26, v27, v2, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v55
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v52
-; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_alignbit_b32 v22, v23, v2, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v53
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v11
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v39
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_alignbit_b32 v18, v19, v2, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_alignbit_b32 v30, v31, v15, 16
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v10
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v9
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v14
-; SI-NEXT: v_alignbit_b32 v14, v15, v2, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v54
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v7
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; SI-NEXT: v_alignbit_b32 v10, v11, v2, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v51
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v15
+; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v51
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v7
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v40
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v34
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshr_b64 v[32:33], v[30:31], 16
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v5
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; SI-NEXT: v_alignbit_b32 v6, v7, v2, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v32
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
-; SI-NEXT: v_lshr_b64 v[33:34], v[1:2], 16
-; SI-NEXT: v_lshr_b64 v[34:35], v[5:6], 16
-; SI-NEXT: v_lshr_b64 v[35:36], v[9:10], 16
-; SI-NEXT: v_lshr_b64 v[36:37], v[13:14], 16
-; SI-NEXT: v_lshr_b64 v[37:38], v[17:18], 16
-; SI-NEXT: v_lshr_b64 v[38:39], v[21:22], 16
-; SI-NEXT: v_lshr_b64 v[50:51], v[25:26], 16
-; SI-NEXT: v_lshr_b64 v[48:49], v[29:30], 16
-; SI-NEXT: v_alignbit_b32 v28, v40, v41, 16
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshr_b64 v[54:55], v[26:27], 16
+; SI-NEXT: v_lshr_b64 v[52:53], v[22:23], 16
+; SI-NEXT: v_lshr_b64 v[50:51], v[18:19], 16
+; SI-NEXT: v_lshr_b64 v[48:49], v[14:15], 16
+; SI-NEXT: v_lshr_b64 v[37:38], v[10:11], 16
+; SI-NEXT: v_lshr_b64 v[35:36], v[6:7], 16
+; SI-NEXT: v_lshr_b64 v[33:34], v[2:3], 16
+; SI-NEXT: v_mov_b32_e32 v30, v32
+; SI-NEXT: v_mov_b32_e32 v26, v54
+; SI-NEXT: v_mov_b32_e32 v22, v52
+; SI-NEXT: v_mov_b32_e32 v18, v50
+; SI-NEXT: v_mov_b32_e32 v14, v48
+; SI-NEXT: v_mov_b32_e32 v10, v37
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
+; SI-NEXT: v_mov_b32_e32 v6, v35
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v56
+; SI-NEXT: v_mov_b32_e32 v2, v33
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
+; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
+; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
+; SI-NEXT: v_lshr_b64 v[17:18], v[17:18], 16
+; SI-NEXT: v_lshr_b64 v[21:22], v[21:22], 16
+; SI-NEXT: v_lshr_b64 v[25:26], v[25:26], 16
+; SI-NEXT: v_lshr_b64 v[29:30], v[29:30], 16
; SI-NEXT: .LBB95_3: ; %end
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -62195,49 +62391,49 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; SI-NEXT: v_mov_b32_e32 v1, v33
-; SI-NEXT: v_mov_b32_e32 v5, v34
-; SI-NEXT: v_mov_b32_e32 v9, v35
-; SI-NEXT: v_mov_b32_e32 v13, v36
-; SI-NEXT: v_mov_b32_e32 v17, v37
-; SI-NEXT: v_mov_b32_e32 v21, v38
-; SI-NEXT: v_mov_b32_e32 v25, v50
-; SI-NEXT: v_mov_b32_e32 v29, v48
+; SI-NEXT: v_mov_b32_e32 v2, v33
+; SI-NEXT: v_mov_b32_e32 v6, v35
+; SI-NEXT: v_mov_b32_e32 v10, v37
+; SI-NEXT: v_mov_b32_e32 v14, v48
+; SI-NEXT: v_mov_b32_e32 v18, v50
+; SI-NEXT: v_mov_b32_e32 v22, v52
+; SI-NEXT: v_mov_b32_e32 v26, v54
+; SI-NEXT: v_mov_b32_e32 v30, v32
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB95_4:
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: s_branch .LBB95_2
;
; VI-LABEL: bitcast_v32bf16_to_v32i16_scalar:
@@ -62256,295 +62452,302 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB95_4
; VI-NEXT: .LBB95_2: ; %cmp.true
-; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v0, s4, v1
-; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: s_lshl_b32 s5, s30, 16
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s5, v1
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s5, s30, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s5, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_lshl_b32 s5, s31, 16
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s5, v1
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: s_and_b32 s5, s31, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_add_f32_e32 v5, s5, v1
-; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
-; VI-NEXT: s_lshl_b32 s4, s29, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
-; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
-; VI-NEXT: v_alignbit_b32 v14, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
-; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_alignbit_b32 v15, v5, v4, 16
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; VI-NEXT: v_mov_b32_e32 v16, 0x40c00000
+; VI-NEXT: s_lshl_b32 s4, s26, 16
+; VI-NEXT: v_add_f32_e32 v4, s4, v16
; VI-NEXT: s_lshl_b32 s4, s28, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v13, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s27, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v12, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v16
+; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: s_lshl_b32 s4, s30, 16
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_add_f32_e32 v2, s4, v16
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s27, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: s_and_b32 s4, s30, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v16
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s26, 16
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v11, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
+; VI-NEXT: s_and_b32 s6, s26, 0xffff0000
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[2:3]
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v0, v4, 16, 1
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v1, 0x400000, v4
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s26, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s25, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v10, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
+; VI-NEXT: s_lshl_b32 s6, s24, 16
+; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
+; VI-NEXT: s_and_b32 s6, s24, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s25, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s24, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v9, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
+; VI-NEXT: s_lshl_b32 s6, s22, 16
+; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
+; VI-NEXT: s_and_b32 s6, s22, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s24, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s23, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v8, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
+; VI-NEXT: s_lshl_b32 s6, s20, 16
+; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
+; VI-NEXT: s_and_b32 s6, s20, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s22, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v7, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
+; VI-NEXT: s_lshl_b32 s6, s18, 16
+; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
+; VI-NEXT: s_and_b32 s6, s18, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; VI-NEXT: s_and_b32 s7, s16, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; VI-NEXT: v_add_f32_e32 v5, s7, v16
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v0, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v5
+; VI-NEXT: s_lshl_b32 s6, s16, 16
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
+; VI-NEXT: v_or_b32_e32 v1, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
+; VI-NEXT: v_bfe_u32 v0, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v3
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v6, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s17, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v3, s5, v16
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v1, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
+; VI-NEXT: s_lshl_b32 s4, s17, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v5, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v3
+; VI-NEXT: v_add_f32_e32 v3, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: s_and_b32 s5, s19, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v16, vcc
+; VI-NEXT: v_add_f32_e32 v3, s5, v16
+; VI-NEXT: v_cndmask_b32_e32 v17, v5, v7, vcc
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v4, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v16, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v16, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v3
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v16, v17, vcc
-; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v3, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
-; VI-NEXT: v_bfe_u32 v16, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v2
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v16, v17, vcc
-; VI-NEXT: v_add_f32_e32 v16, s4, v1
-; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_alignbit_b32 v2, v16, v2, 16
-; VI-NEXT: v_add_f32_e32 v16, s4, v1
-; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
+; VI-NEXT: v_add_f32_e32 v3, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: s_and_b32 s5, s21, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v5
+; VI-NEXT: v_add_f32_e32 v5, s5, v16
+; VI-NEXT: v_mov_b32_e32 v1, v17
+; VI-NEXT: v_cndmask_b32_e32 v17, v7, v9, vcc
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: s_lshl_b32 s4, s21, 16
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_add_f32_e32 v5, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; VI-NEXT: v_bfe_u32 v9, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v5
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: s_and_b32 s5, s23, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v7
+; VI-NEXT: v_add_f32_e32 v7, s5, v16
+; VI-NEXT: v_mov_b32_e32 v3, v17
+; VI-NEXT: v_cndmask_b32_e32 v17, v9, v11, vcc
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: s_lshl_b32 s4, s23, 16
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_add_f32_e32 v7, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; VI-NEXT: v_bfe_u32 v11, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v7
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: s_and_b32 s5, s25, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; VI-NEXT: v_add_f32_e32 v9, s5, v16
+; VI-NEXT: v_mov_b32_e32 v5, v17
+; VI-NEXT: v_cndmask_b32_e32 v17, v11, v13, vcc
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
+; VI-NEXT: s_lshl_b32 s4, s25, 16
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_add_f32_e32 v9, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
+; VI-NEXT: v_bfe_u32 v13, v9, 16, 1
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v9
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: s_and_b32 s5, s27, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
+; VI-NEXT: v_add_f32_e32 v11, s5, v16
+; VI-NEXT: v_mov_b32_e32 v7, v17
+; VI-NEXT: v_cndmask_b32_e32 v17, v13, v15, vcc
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
+; VI-NEXT: s_lshl_b32 s4, s27, 16
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: v_add_f32_e32 v11, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
+; VI-NEXT: v_bfe_u32 v15, v11, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v11
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: s_and_b32 s5, s29, 0xffff0000
+; VI-NEXT: v_mov_b32_e32 v9, v17
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v13
+; VI-NEXT: v_add_f32_e32 v13, s5, v16
+; VI-NEXT: v_cndmask_b32_e32 v17, v15, v17, vcc
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: s_lshl_b32 s4, s29, 16
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_mov_b32_e32 v11, v17
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_add_f32_e32 v13, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
+; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: v_add_f32_e32 v17, s4, v1
-; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
-; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
-; VI-NEXT: v_add_f32_e32 v1, s4, v1
-; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
-; VI-NEXT: v_bfe_u32 v18, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v1
-; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
-; VI-NEXT: v_or_b32_e32 v19, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_alignbit_b32 v1, v1, v17, 16
-; VI-NEXT: v_alignbit_b32 v0, v16, v0, 16
+; VI-NEXT: s_and_b32 s4, s31, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_add_f32_e32 v13, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v15
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: s_lshl_b32 s4, s31, 16
+; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc
+; VI-NEXT: v_add_f32_e32 v15, s4, v16
+; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
+; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_cndmask_b32_e32 v15, v16, v19, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_lshrrev_b64 v[15:16], 16, v[15:16]
+; VI-NEXT: v_mov_b32_e32 v13, v17
; VI-NEXT: s_branch .LBB95_5
; VI-NEXT: .LBB95_3:
; VI-NEXT: s_branch .LBB95_2
@@ -74902,295 +75105,302 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB103_4
; VI-NEXT: .LBB103_2: ; %cmp.true
-; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v0, s4, v1
-; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: s_lshl_b32 s5, s30, 16
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s5, v1
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s5, s30, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s5, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_lshl_b32 s5, s31, 16
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s5, v1
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: s_and_b32 s5, s31, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_add_f32_e32 v5, s5, v1
-; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
-; VI-NEXT: s_lshl_b32 s4, s29, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
-; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
-; VI-NEXT: v_alignbit_b32 v14, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
-; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_alignbit_b32 v15, v5, v4, 16
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; VI-NEXT: v_mov_b32_e32 v16, 0x40c00000
+; VI-NEXT: s_lshl_b32 s4, s26, 16
+; VI-NEXT: v_add_f32_e32 v4, s4, v16
; VI-NEXT: s_lshl_b32 s4, s28, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v13, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_add_f32_e32 v0, s4, v16
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s27, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v12, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v16
+; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: s_lshl_b32 s4, s30, 16
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; VI-NEXT: v_add_f32_e32 v2, s4, v16
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s27, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: s_and_b32 s4, s30, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; VI-NEXT: v_add_f32_e32 v3, s4, v16
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s26, 16
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v11, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
+; VI-NEXT: s_and_b32 s6, s26, 0xffff0000
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[2:3]
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v0, v4, 16, 1
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v1, 0x400000, v4
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s26, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s25, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v10, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
+; VI-NEXT: s_lshl_b32 s6, s24, 16
+; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
+; VI-NEXT: s_and_b32 s6, s24, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s25, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s24, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v9, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
+; VI-NEXT: s_lshl_b32 s6, s22, 16
+; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
+; VI-NEXT: s_and_b32 s6, s22, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s24, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s23, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v8, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
+; VI-NEXT: s_lshl_b32 s6, s20, 16
+; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
+; VI-NEXT: s_and_b32 s6, s20, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s22, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v7, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
+; VI-NEXT: s_lshl_b32 s6, s18, 16
+; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
+; VI-NEXT: s_and_b32 s6, s18, 0xffff0000
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s6, v16
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; VI-NEXT: s_and_b32 s7, s16, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; VI-NEXT: v_add_f32_e32 v5, s7, v16
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v0, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v5
+; VI-NEXT: s_lshl_b32 s6, s16, 16
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
+; VI-NEXT: v_or_b32_e32 v1, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_add_f32_e32 v3, s6, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
+; VI-NEXT: v_bfe_u32 v0, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v3
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s21, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v6, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_and_b32 s5, s17, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v3, s5, v16
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_bfe_u32 v1, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
+; VI-NEXT: s_lshl_b32 s4, s17, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: s_lshl_b32 s4, s20, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v5, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v3
+; VI-NEXT: v_add_f32_e32 v3, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: s_and_b32 s5, s19, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v16, vcc
+; VI-NEXT: v_add_f32_e32 v3, s5, v16
+; VI-NEXT: v_cndmask_b32_e32 v17, v5, v7, vcc
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; VI-NEXT: s_lshl_b32 s4, s19, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v4, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v16, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v1
-; VI-NEXT: v_bfe_u32 v16, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v3
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v16, v17, vcc
-; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_alignbit_b32 v3, v3, v2, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v1
-; VI-NEXT: v_bfe_u32 v16, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v2
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v2, v16, v17, vcc
-; VI-NEXT: v_add_f32_e32 v16, s4, v1
-; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_alignbit_b32 v2, v16, v2, 16
-; VI-NEXT: v_add_f32_e32 v16, s4, v1
-; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
+; VI-NEXT: v_add_f32_e32 v3, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: s_and_b32 s5, s21, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v5
+; VI-NEXT: v_add_f32_e32 v5, s5, v16
+; VI-NEXT: v_mov_b32_e32 v1, v17
+; VI-NEXT: v_cndmask_b32_e32 v17, v7, v9, vcc
+; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
+; VI-NEXT: s_lshl_b32 s4, s21, 16
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
+; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_add_f32_e32 v5, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; VI-NEXT: v_bfe_u32 v9, v5, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v5
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: s_and_b32 s5, s23, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v5
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v7
+; VI-NEXT: v_add_f32_e32 v7, s5, v16
+; VI-NEXT: v_mov_b32_e32 v3, v17
+; VI-NEXT: v_cndmask_b32_e32 v17, v9, v11, vcc
+; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
+; VI-NEXT: s_lshl_b32 s4, s23, 16
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
+; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_add_f32_e32 v7, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; VI-NEXT: v_bfe_u32 v11, v7, 16, 1
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v7
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: s_and_b32 s5, s25, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v7
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; VI-NEXT: v_add_f32_e32 v9, s5, v16
+; VI-NEXT: v_mov_b32_e32 v5, v17
+; VI-NEXT: v_cndmask_b32_e32 v17, v11, v13, vcc
+; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
+; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
+; VI-NEXT: s_lshl_b32 s4, s25, 16
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
+; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_add_f32_e32 v9, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
+; VI-NEXT: v_bfe_u32 v13, v9, 16, 1
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v9
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: s_and_b32 s5, s27, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v9
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
+; VI-NEXT: v_add_f32_e32 v11, s5, v16
+; VI-NEXT: v_mov_b32_e32 v7, v17
+; VI-NEXT: v_cndmask_b32_e32 v17, v13, v15, vcc
+; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
+; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
+; VI-NEXT: s_lshl_b32 s4, s27, 16
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
+; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: v_add_f32_e32 v11, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
+; VI-NEXT: v_bfe_u32 v15, v11, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v11
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: s_and_b32 s5, s29, 0xffff0000
+; VI-NEXT: v_mov_b32_e32 v9, v17
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v11
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v13
+; VI-NEXT: v_add_f32_e32 v13, s5, v16
+; VI-NEXT: v_cndmask_b32_e32 v17, v15, v17, vcc
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: s_lshl_b32 s4, s29, 16
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_mov_b32_e32 v11, v17
+; VI-NEXT: v_or_b32_e32 v17, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_add_f32_e32 v13, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
+; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: v_add_f32_e32 v17, s4, v1
-; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
-; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
-; VI-NEXT: v_add_f32_e32 v1, s4, v1
-; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
-; VI-NEXT: v_bfe_u32 v18, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v1
-; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
-; VI-NEXT: v_or_b32_e32 v19, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_alignbit_b32 v1, v1, v17, 16
-; VI-NEXT: v_alignbit_b32 v0, v16, v0, 16
+; VI-NEXT: s_and_b32 s4, s31, 0xffff0000
+; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: v_add_f32_e32 v13, s4, v16
+; VI-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v15
+; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
+; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; VI-NEXT: s_lshl_b32 s4, s31, 16
+; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc
+; VI-NEXT: v_add_f32_e32 v15, s4, v16
+; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
+; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
+; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
+; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
+; VI-NEXT: v_cndmask_b32_e32 v15, v16, v19, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
+; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
+; VI-NEXT: v_lshrrev_b64 v[15:16], 16, v[15:16]
+; VI-NEXT: v_mov_b32_e32 v13, v17
; VI-NEXT: s_branch .LBB103_5
; VI-NEXT: .LBB103_3:
; VI-NEXT: s_branch .LBB103_2
@@ -87562,1321 +87772,1481 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; SI-LABEL: bitcast_v32bf16_to_v64i8_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: s_mov_b64 exec, s[4:5]
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_writelane_b32 v40, s30, 0
+; SI-NEXT: v_writelane_b32 v40, s31, 1
+; SI-NEXT: v_writelane_b32 v40, s34, 2
+; SI-NEXT: v_writelane_b32 v40, s35, 3
+; SI-NEXT: v_writelane_b32 v40, s36, 4
+; SI-NEXT: v_writelane_b32 v40, s37, 5
+; SI-NEXT: v_writelane_b32 v40, s38, 6
+; SI-NEXT: v_writelane_b32 v40, s39, 7
+; SI-NEXT: v_writelane_b32 v40, s48, 8
+; SI-NEXT: v_writelane_b32 v40, s49, 9
+; SI-NEXT: v_writelane_b32 v40, s50, 10
+; SI-NEXT: v_writelane_b32 v40, s51, 11
+; SI-NEXT: v_writelane_b32 v40, s52, 12
+; SI-NEXT: v_writelane_b32 v40, s53, 13
+; SI-NEXT: v_writelane_b32 v40, s54, 14
+; SI-NEXT: v_writelane_b32 v40, s55, 15
+; SI-NEXT: v_writelane_b32 v40, s64, 16
+; SI-NEXT: v_writelane_b32 v40, s65, 17
+; SI-NEXT: v_writelane_b32 v40, s66, 18
+; SI-NEXT: v_writelane_b32 v40, s67, 19
+; SI-NEXT: v_writelane_b32 v40, s68, 20
+; SI-NEXT: v_writelane_b32 v40, s69, 21
+; SI-NEXT: v_writelane_b32 v40, s70, 22
+; SI-NEXT: v_writelane_b32 v40, s71, 23
+; SI-NEXT: v_writelane_b32 v40, s80, 24
+; SI-NEXT: v_writelane_b32 v40, s81, 25
+; SI-NEXT: v_writelane_b32 v40, s82, 26
+; SI-NEXT: v_writelane_b32 v40, s83, 27
+; SI-NEXT: v_writelane_b32 v40, s84, 28
+; SI-NEXT: v_writelane_b32 v40, s85, 29
+; SI-NEXT: v_writelane_b32 v40, s86, 30
+; SI-NEXT: v_writelane_b32 v40, s87, 31
+; SI-NEXT: v_writelane_b32 v40, s96, 32
+; SI-NEXT: v_writelane_b32 v40, s97, 33
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_writelane_b32 v40, s98, 34
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_mul_f32_e64 v19, 1.0, s17
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v44, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v40, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v9
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v60, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v16
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v34, 1.0, v17
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v9
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v33, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v14
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v35, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v36, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
; SI-NEXT: v_mul_f32_e64 v3, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v26, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v29, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v38, 1.0, s24
-; SI-NEXT: v_mul_f32_e64 v35, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v53, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v55, 1.0, s28
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v7, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v5, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v11, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v8, 1.0, s27
+; SI-NEXT: v_mul_f32_e64 v9, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v12, 1.0, s29
+; SI-NEXT: v_mul_f32_e64 v13, 1.0, s28
+; SI-NEXT: v_writelane_b32 v40, s99, 35
+; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB109_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v19
-; SI-NEXT: v_alignbit_b32 v23, v1, v3, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; SI-NEXT: v_alignbit_b32 v20, v1, v6, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; SI-NEXT: v_alignbit_b32 v17, v1, v38, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v53
-; SI-NEXT: v_alignbit_b32 v14, v1, v55, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v50
-; SI-NEXT: v_alignbit_b32 v11, v1, v52, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v29
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v8, v1, v46, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v61
-; SI-NEXT: v_alignbit_b32 v21, v19, v4, 16
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v35
-; SI-NEXT: v_alignbit_b32 v4, v1, v25, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v26
-; SI-NEXT: v_alignbit_b32 v18, v16, v7, 16
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v57
-; SI-NEXT: v_alignbit_b32 v3, v1, v37, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v32
-; SI-NEXT: v_alignbit_b32 v24, v22, v2, 16
-; SI-NEXT: v_alignbit_b32 v15, v13, v27, 16
-; SI-NEXT: v_alignbit_b32 v12, v10, v49, 16
-; SI-NEXT: v_alignbit_b32 v9, v7, v43, 16
-; SI-NEXT: v_alignbit_b32 v5, v6, v60, 16
-; SI-NEXT: v_alignbit_b32 v2, v1, v34, 16
-; SI-NEXT: v_readfirstlane_b32 s8, v23
-; SI-NEXT: v_readfirstlane_b32 s9, v24
-; SI-NEXT: v_readfirstlane_b32 s14, v20
-; SI-NEXT: v_readfirstlane_b32 s15, v21
-; SI-NEXT: v_readfirstlane_b32 s20, v17
-; SI-NEXT: v_readfirstlane_b32 s21, v18
-; SI-NEXT: v_readfirstlane_b32 s26, v14
-; SI-NEXT: v_readfirstlane_b32 s27, v15
-; SI-NEXT: v_readfirstlane_b32 s42, v11
-; SI-NEXT: v_readfirstlane_b32 s43, v12
-; SI-NEXT: v_readfirstlane_b32 s56, v8
-; SI-NEXT: v_readfirstlane_b32 s57, v9
-; SI-NEXT: v_readfirstlane_b32 s62, v4
-; SI-NEXT: v_readfirstlane_b32 s63, v5
-; SI-NEXT: v_readfirstlane_b32 s76, v3
-; SI-NEXT: v_readfirstlane_b32 s77, v2
-; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], 24
-; SI-NEXT: s_lshr_b64 s[6:7], s[8:9], 16
-; SI-NEXT: s_lshr_b64 s[10:11], s[8:9], 8
-; SI-NEXT: s_lshr_b64 s[8:9], s[14:15], 24
-; SI-NEXT: s_lshr_b64 s[12:13], s[14:15], 16
-; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 8
-; SI-NEXT: s_lshr_b64 s[14:15], s[20:21], 24
-; SI-NEXT: s_lshr_b64 s[18:19], s[20:21], 16
-; SI-NEXT: s_lshr_b64 s[22:23], s[20:21], 8
-; SI-NEXT: s_lshr_b64 s[20:21], s[26:27], 24
-; SI-NEXT: s_lshr_b64 s[24:25], s[26:27], 16
-; SI-NEXT: s_lshr_b64 s[28:29], s[26:27], 8
-; SI-NEXT: s_lshr_b64 s[26:27], s[42:43], 24
-; SI-NEXT: s_lshr_b64 s[40:41], s[42:43], 16
-; SI-NEXT: s_lshr_b64 s[44:45], s[42:43], 8
-; SI-NEXT: s_lshr_b64 s[42:43], s[56:57], 24
-; SI-NEXT: s_lshr_b64 s[46:47], s[56:57], 16
-; SI-NEXT: s_lshr_b64 s[58:59], s[56:57], 8
-; SI-NEXT: s_lshr_b64 s[56:57], s[62:63], 24
-; SI-NEXT: s_lshr_b64 s[60:61], s[62:63], 16
-; SI-NEXT: s_lshr_b64 s[72:73], s[62:63], 8
-; SI-NEXT: s_lshr_b64 s[62:63], s[76:77], 24
-; SI-NEXT: s_lshr_b64 s[74:75], s[76:77], 16
-; SI-NEXT: s_lshr_b64 s[76:77], s[76:77], 8
-; SI-NEXT: v_lshrrev_b32_e32 v30, 24, v26
-; SI-NEXT: v_lshrrev_b32_e32 v27, 8, v24
-; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v29
-; SI-NEXT: v_lshrrev_b32_e32 v58, 8, v21
-; SI-NEXT: v_lshrrev_b32_e32 v31, 24, v35
-; SI-NEXT: v_lshrrev_b32_e32 v28, 8, v18
-; SI-NEXT: v_lshrrev_b32_e32 v63, 24, v33
-; SI-NEXT: v_lshrrev_b32_e32 v59, 8, v15
-; SI-NEXT: v_lshrrev_b32_e32 v56, 24, v39
-; SI-NEXT: v_lshrrev_b32_e32 v47, 8, v12
-; SI-NEXT: v_lshrrev_b32_e32 v45, 24, v40
-; SI-NEXT: v_lshrrev_b32_e32 v41, 8, v9
-; SI-NEXT: v_lshrrev_b32_e32 v42, 24, v57
-; SI-NEXT: v_lshrrev_b32_e32 v54, 8, v5
-; SI-NEXT: v_lshrrev_b32_e32 v51, 24, v32
-; SI-NEXT: v_lshrrev_b32_e32 v48, 8, v2
+; SI-NEXT: v_readfirstlane_b32 s4, v19
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v3
+; SI-NEXT: s_lshr_b64 s[74:75], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v1
+; SI-NEXT: s_lshr_b32 s73, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s72, v2
+; SI-NEXT: s_lshr_b64 s[76:77], s[72:73], 16
+; SI-NEXT: s_mov_b32 s75, s76
+; SI-NEXT: s_lshr_b64 s[4:5], s[74:75], 24
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_writelane_b32 v41, s4, 0
+; SI-NEXT: v_writelane_b32 v41, s5, 1
+; SI-NEXT: v_readfirstlane_b32 s4, v6
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v7
+; SI-NEXT: s_lshr_b64 s[60:61], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v4
+; SI-NEXT: s_lshr_b32 s59, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v10
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v11
+; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v8
+; SI-NEXT: s_lshr_b32 s45, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v12
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v13
+; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v20
+; SI-NEXT: s_lshr_b32 s25, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v24
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v25
+; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v22
+; SI-NEXT: s_lshr_b32 s41, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v28
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v29
+; SI-NEXT: s_lshr_b64 s[20:21], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v26
+; SI-NEXT: s_lshr_b32 s19, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v32
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v33
+; SI-NEXT: s_lshr_b64 s[12:13], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v30
+; SI-NEXT: s_lshr_b32 s11, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v35
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v36
+; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v18
+; SI-NEXT: v_readfirstlane_b32 s58, v5
+; SI-NEXT: v_readfirstlane_b32 s44, v9
+; SI-NEXT: v_readfirstlane_b32 s24, v21
+; SI-NEXT: v_readfirstlane_b32 s40, v23
+; SI-NEXT: v_readfirstlane_b32 s18, v27
+; SI-NEXT: v_readfirstlane_b32 s10, v31
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v17
+; SI-NEXT: s_lshr_b64 s[62:63], s[58:59], 16
+; SI-NEXT: s_lshr_b64 s[56:57], s[44:45], 16
+; SI-NEXT: s_lshr_b64 s[42:43], s[24:25], 16
+; SI-NEXT: s_lshr_b64 s[22:23], s[40:41], 16
+; SI-NEXT: s_lshr_b64 s[28:29], s[18:19], 16
+; SI-NEXT: s_lshr_b64 s[14:15], s[10:11], 16
+; SI-NEXT: s_lshr_b64 s[8:9], s[4:5], 16
+; SI-NEXT: s_mov_b32 s61, s62
+; SI-NEXT: s_mov_b32 s47, s56
+; SI-NEXT: s_mov_b32 s27, s42
+; SI-NEXT: s_mov_b32 s17, s22
+; SI-NEXT: s_mov_b32 s21, s28
+; SI-NEXT: s_mov_b32 s13, s14
+; SI-NEXT: s_mov_b32 s7, s8
+; SI-NEXT: s_lshr_b64 s[88:89], s[74:75], 16
+; SI-NEXT: s_lshr_b64 s[92:93], s[74:75], 8
+; SI-NEXT: s_lshr_b64 s[90:91], s[60:61], 24
+; SI-NEXT: s_lshr_b64 s[94:95], s[60:61], 16
+; SI-NEXT: s_lshr_b64 s[30:31], s[60:61], 8
+; SI-NEXT: s_lshr_b64 s[34:35], s[46:47], 24
+; SI-NEXT: s_lshr_b64 s[36:37], s[46:47], 16
+; SI-NEXT: s_lshr_b64 s[38:39], s[46:47], 8
+; SI-NEXT: s_lshr_b64 s[48:49], s[26:27], 24
+; SI-NEXT: s_lshr_b64 s[50:51], s[26:27], 16
+; SI-NEXT: s_lshr_b64 s[52:53], s[26:27], 8
+; SI-NEXT: s_lshr_b64 s[54:55], s[16:17], 24
+; SI-NEXT: s_lshr_b64 s[64:65], s[16:17], 16
+; SI-NEXT: s_lshr_b64 s[66:67], s[16:17], 8
+; SI-NEXT: s_lshr_b64 s[68:69], s[20:21], 24
+; SI-NEXT: s_lshr_b64 s[70:71], s[20:21], 16
+; SI-NEXT: v_lshrrev_b32_e32 v48, 24, v1
+; SI-NEXT: v_lshrrev_b32_e32 v39, 24, v4
+; SI-NEXT: s_lshr_b32 s24, s76, 8
+; SI-NEXT: v_lshrrev_b32_e32 v38, 24, v8
+; SI-NEXT: s_lshr_b32 s23, s62, 8
+; SI-NEXT: v_lshrrev_b32_e32 v37, 24, v20
+; SI-NEXT: s_lshr_b32 s18, s56, 8
+; SI-NEXT: v_lshrrev_b32_e32 v34, 24, v22
+; SI-NEXT: s_lshr_b32 s17, s42, 8
+; SI-NEXT: v_lshrrev_b32_e32 v16, 24, v26
+; SI-NEXT: s_lshr_b32 s15, s22, 8
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v30
+; SI-NEXT: s_lshr_b32 s10, s28, 8
+; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v18
+; SI-NEXT: s_lshr_b32 s9, s14, 8
+; SI-NEXT: s_lshr_b32 s4, s8, 8
+; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 8
+; SI-NEXT: s_lshr_b64 s[86:87], s[12:13], 24
+; SI-NEXT: s_lshr_b64 s[96:97], s[12:13], 16
+; SI-NEXT: s_lshr_b64 s[98:99], s[12:13], 8
+; SI-NEXT: s_lshr_b64 s[80:81], s[6:7], 24
+; SI-NEXT: s_lshr_b64 s[82:83], s[6:7], 16
+; SI-NEXT: s_lshr_b64 s[84:85], s[6:7], 8
; SI-NEXT: s_cbranch_execnz .LBB109_3
; SI-NEXT: .LBB109_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v53
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v55
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v35
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v36
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_alignbit_b32 v14, v14, v13, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v38
+; SI-NEXT: v_readfirstlane_b32 s4, v15
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v17
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v18
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v14
+; SI-NEXT: s_lshr_b32 s5, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v33
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v32
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v36
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v50
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v37
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v46
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v52
+; SI-NEXT: s_lshr_b64 s[8:9], s[4:5], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v16
+; SI-NEXT: v_readfirstlane_b32 s10, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v31
+; SI-NEXT: s_lshr_b32 s11, s4, 16
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v15
+; SI-NEXT: s_lshr_b64 s[12:13], s[10:11], 16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v30
+; SI-NEXT: v_readfirstlane_b32 s10, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v29
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v28
+; SI-NEXT: v_readfirstlane_b32 s4, v15
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_readfirstlane_b32 s16, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v27
+; SI-NEXT: s_lshr_b32 s11, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v17
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v26
+; SI-NEXT: v_readfirstlane_b32 s18, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v25
+; SI-NEXT: s_lshr_b32 s17, s4, 16
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v24
+; SI-NEXT: s_lshr_b64 s[20:21], s[16:17], 16
+; SI-NEXT: v_readfirstlane_b32 s4, v16
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; SI-NEXT: v_readfirstlane_b32 s16, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v23
+; SI-NEXT: s_lshr_b32 s19, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v18
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v22
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; SI-NEXT: s_lshr_b32 s17, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v17
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: s_lshr_b32 s41, s4, 16
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_readfirstlane_b32 s4, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v21
+; SI-NEXT: v_readfirstlane_b32 s24, v13
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v20
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: s_lshr_b32 s25, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v12
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: s_lshr_b64 s[26:27], s[24:25], 16
+; SI-NEXT: s_lshr_b32 s25, s4, 16
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v61
+; SI-NEXT: v_readfirstlane_b32 s4, v10
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: s_lshr_b32 s45, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s44, v11
+; SI-NEXT: v_readfirstlane_b32 s4, v8
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: s_lshr_b64 s[46:47], s[44:45], 16
+; SI-NEXT: s_lshr_b32 s45, s4, 16
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v34
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v25
+; SI-NEXT: v_readfirstlane_b32 s4, v6
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: s_lshr_b32 s59, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s58, v7
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: v_alignbit_b32 v8, v8, v7, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v43
-; SI-NEXT: v_alignbit_b32 v11, v11, v10, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v32
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: s_lshr_b64 s[60:61], s[58:59], 16
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v57
-; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v40
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v39
-; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v1
-; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v60
-; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v6
-; SI-NEXT: v_add_f32_e32 v34, 0x40c00000, v7
-; SI-NEXT: v_add_f32_e32 v36, 0x40c00000, v10
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v32
+; SI-NEXT: v_readfirstlane_b32 s58, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v19
+; SI-NEXT: v_readfirstlane_b32 s4, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v36
-; SI-NEXT: v_alignbit_b32 v2, v1, v2, 16
-; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_alignbit_b32 v9, v7, v9, 16
-; SI-NEXT: v_alignbit_b32 v12, v10, v12, 16
-; SI-NEXT: v_readfirstlane_b32 s76, v3
-; SI-NEXT: v_readfirstlane_b32 s77, v2
-; SI-NEXT: v_readfirstlane_b32 s62, v4
-; SI-NEXT: v_readfirstlane_b32 s63, v5
-; SI-NEXT: v_readfirstlane_b32 s56, v8
-; SI-NEXT: v_readfirstlane_b32 s57, v9
-; SI-NEXT: v_readfirstlane_b32 s42, v11
-; SI-NEXT: v_readfirstlane_b32 s43, v12
-; SI-NEXT: v_readfirstlane_b32 s26, v14
-; SI-NEXT: s_lshr_b64 s[40:41], s[42:43], 16
-; SI-NEXT: s_lshr_b64 s[44:45], s[42:43], 8
-; SI-NEXT: s_lshr_b64 s[46:47], s[56:57], 16
-; SI-NEXT: s_lshr_b64 s[58:59], s[56:57], 8
-; SI-NEXT: s_lshr_b64 s[60:61], s[62:63], 16
-; SI-NEXT: s_lshr_b64 s[72:73], s[62:63], 8
-; SI-NEXT: s_lshr_b64 s[74:75], s[76:77], 16
-; SI-NEXT: v_lshrrev_b32_e32 v47, 8, v12
-; SI-NEXT: v_lshrrev_b32_e32 v41, 8, v9
-; SI-NEXT: v_lshrrev_b32_e32 v54, 8, v5
-; SI-NEXT: v_lshrrev_b32_e32 v48, 8, v2
-; SI-NEXT: v_lshrrev_b32_e32 v56, 24, v36
-; SI-NEXT: v_lshrrev_b32_e32 v45, 24, v34
-; SI-NEXT: v_lshrrev_b32_e32 v42, 24, v25
-; SI-NEXT: v_lshrrev_b32_e32 v51, 24, v32
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_alignbit_b32 v17, v17, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_readfirstlane_b32 s20, v17
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_alignbit_b32 v20, v20, v19, 16
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v23, v23, v22, 16
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v33
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v35
-; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v13
-; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v31
-; SI-NEXT: v_alignbit_b32 v15, v13, v15, 16
-; SI-NEXT: v_alignbit_b32 v18, v16, v18, 16
-; SI-NEXT: v_readfirstlane_b32 s27, v15
-; SI-NEXT: v_readfirstlane_b32 s21, v18
-; SI-NEXT: v_readfirstlane_b32 s14, v20
-; SI-NEXT: v_readfirstlane_b32 s8, v23
-; SI-NEXT: s_lshr_b64 s[18:19], s[20:21], 16
-; SI-NEXT: s_lshr_b64 s[22:23], s[20:21], 8
-; SI-NEXT: s_lshr_b64 s[24:25], s[26:27], 16
-; SI-NEXT: s_lshr_b64 s[28:29], s[26:27], 8
-; SI-NEXT: v_lshrrev_b32_e32 v28, 8, v18
-; SI-NEXT: v_lshrrev_b32_e32 v59, 8, v15
-; SI-NEXT: v_lshrrev_b32_e32 v31, 24, v31
-; SI-NEXT: v_lshrrev_b32_e32 v63, 24, v33
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v19
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v29
-; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v22
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v26
-; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v19
-; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v22
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v26
-; SI-NEXT: v_alignbit_b32 v21, v19, v21, 16
-; SI-NEXT: v_alignbit_b32 v24, v22, v24, 16
-; SI-NEXT: v_readfirstlane_b32 s15, v21
-; SI-NEXT: v_readfirstlane_b32 s9, v24
-; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], 24
-; SI-NEXT: s_lshr_b64 s[6:7], s[8:9], 16
-; SI-NEXT: s_lshr_b64 s[10:11], s[8:9], 8
-; SI-NEXT: s_lshr_b64 s[8:9], s[14:15], 24
-; SI-NEXT: s_lshr_b64 s[12:13], s[14:15], 16
-; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 8
-; SI-NEXT: s_lshr_b64 s[14:15], s[20:21], 24
-; SI-NEXT: s_lshr_b64 s[20:21], s[26:27], 24
-; SI-NEXT: s_lshr_b64 s[26:27], s[42:43], 24
-; SI-NEXT: s_lshr_b64 s[42:43], s[56:57], 24
-; SI-NEXT: s_lshr_b64 s[56:57], s[62:63], 24
-; SI-NEXT: s_lshr_b64 s[62:63], s[76:77], 24
-; SI-NEXT: s_lshr_b64 s[76:77], s[76:77], 8
-; SI-NEXT: v_lshrrev_b32_e32 v27, 8, v24
-; SI-NEXT: v_lshrrev_b32_e32 v58, 8, v21
-; SI-NEXT: v_lshrrev_b32_e32 v30, 24, v26
-; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v29
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: s_lshr_b32 s59, s4, 16
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_readfirstlane_b32 s4, v5
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: s_lshr_b32 s73, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s72, v3
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_readfirstlane_b32 s4, v1
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: s_lshr_b64 s[74:75], s[72:73], 16
+; SI-NEXT: s_lshr_b32 s73, s4, 16
+; SI-NEXT: v_readfirstlane_b32 s72, v2
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: s_lshr_b64 s[76:77], s[72:73], 16
+; SI-NEXT: v_readfirstlane_b32 s40, v18
+; SI-NEXT: v_readfirstlane_b32 s24, v13
+; SI-NEXT: v_readfirstlane_b32 s44, v9
+; SI-NEXT: s_mov_b32 s75, s76
+; SI-NEXT: s_lshr_b64 s[14:15], s[10:11], 16
+; SI-NEXT: s_lshr_b64 s[28:29], s[18:19], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[16:17], 16
+; SI-NEXT: s_lshr_b64 s[22:23], s[40:41], 16
+; SI-NEXT: s_lshr_b64 s[42:43], s[24:25], 16
+; SI-NEXT: s_lshr_b64 s[56:57], s[44:45], 16
+; SI-NEXT: s_lshr_b64 s[62:63], s[58:59], 16
+; SI-NEXT: s_lshr_b64 s[78:79], s[74:75], 24
+; SI-NEXT: s_mov_b32 s7, s8
+; SI-NEXT: s_mov_b32 s13, s14
+; SI-NEXT: s_mov_b32 s21, s28
+; SI-NEXT: s_mov_b32 s17, s22
+; SI-NEXT: s_mov_b32 s27, s42
+; SI-NEXT: s_mov_b32 s47, s56
+; SI-NEXT: s_mov_b32 s61, s62
+; SI-NEXT: v_writelane_b32 v41, s78, 0
+; SI-NEXT: v_writelane_b32 v41, s79, 1
+; SI-NEXT: s_lshr_b64 s[88:89], s[74:75], 16
+; SI-NEXT: s_lshr_b64 s[92:93], s[74:75], 8
+; SI-NEXT: s_lshr_b64 s[90:91], s[60:61], 24
+; SI-NEXT: s_lshr_b64 s[94:95], s[60:61], 16
+; SI-NEXT: s_lshr_b64 s[30:31], s[60:61], 8
+; SI-NEXT: s_lshr_b64 s[34:35], s[46:47], 24
+; SI-NEXT: s_lshr_b64 s[36:37], s[46:47], 16
+; SI-NEXT: s_lshr_b64 s[38:39], s[46:47], 8
+; SI-NEXT: s_lshr_b64 s[48:49], s[26:27], 24
+; SI-NEXT: s_lshr_b64 s[50:51], s[26:27], 16
+; SI-NEXT: s_lshr_b64 s[52:53], s[26:27], 8
+; SI-NEXT: s_lshr_b64 s[54:55], s[16:17], 24
+; SI-NEXT: s_lshr_b64 s[64:65], s[16:17], 16
+; SI-NEXT: s_lshr_b64 s[66:67], s[16:17], 8
+; SI-NEXT: s_lshr_b64 s[68:69], s[20:21], 24
+; SI-NEXT: s_lshr_b64 s[70:71], s[20:21], 16
+; SI-NEXT: s_lshr_b32 s24, s76, 8
+; SI-NEXT: s_lshr_b32 s23, s62, 8
+; SI-NEXT: s_lshr_b32 s18, s56, 8
+; SI-NEXT: s_lshr_b32 s17, s42, 8
+; SI-NEXT: s_lshr_b32 s15, s22, 8
+; SI-NEXT: s_lshr_b32 s10, s28, 8
+; SI-NEXT: s_lshr_b32 s9, s14, 8
+; SI-NEXT: s_lshr_b32 s4, s8, 8
+; SI-NEXT: v_lshrrev_b32_e32 v48, 24, v1
+; SI-NEXT: v_lshrrev_b32_e32 v39, 24, v4
+; SI-NEXT: v_lshrrev_b32_e32 v38, 24, v8
+; SI-NEXT: v_lshrrev_b32_e32 v37, 24, v12
+; SI-NEXT: v_lshrrev_b32_e32 v34, 24, v17
+; SI-NEXT: v_lshrrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v14
+; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 8
+; SI-NEXT: s_lshr_b64 s[86:87], s[12:13], 24
+; SI-NEXT: s_lshr_b64 s[96:97], s[12:13], 16
+; SI-NEXT: s_lshr_b64 s[98:99], s[12:13], 8
+; SI-NEXT: s_lshr_b64 s[80:81], s[6:7], 24
+; SI-NEXT: s_lshr_b64 s[82:83], s[6:7], 16
+; SI-NEXT: s_lshr_b64 s[84:85], s[6:7], 8
; SI-NEXT: .LBB109_3: ; %end
-; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
-; SI-NEXT: s_lshl_b32 s5, s10, 8
-; SI-NEXT: v_or_b32_e32 v23, s5, v23
-; SI-NEXT: s_and_b32 s5, s6, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_lshl_b32 s4, s4, 24
-; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
-; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_or_b32_e32 v23, s4, v23
-; SI-NEXT: buffer_store_dword v23, v0, s[0:3], 0 offen
+; SI-NEXT: s_and_b32 s7, s74, 0xff
+; SI-NEXT: s_lshl_b32 s13, s92, 8
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: s_and_b32 s13, s88, 0xff
+; SI-NEXT: v_readlane_b32 s74, v41, 0
+; SI-NEXT: s_lshl_b32 s21, s74, 24
+; SI-NEXT: s_lshl_b32 s13, s13, 16
+; SI-NEXT: s_or_b32 s13, s21, s13
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: v_mov_b32_e32 v1, s7
+; SI-NEXT: s_and_b32 s7, s76, 0xff
+; SI-NEXT: s_lshl_b32 s13, s24, 8
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: s_and_b32 s13, s73, 0xff
+; SI-NEXT: s_lshl_b32 s13, s13, 16
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v48
+; SI-NEXT: v_or_b32_e32 v2, s13, v2
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: v_or_b32_e32 v2, s7, v2
+; SI-NEXT: s_and_b32 s7, s60, 0xff
+; SI-NEXT: s_lshl_b32 s13, s30, 8
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: s_and_b32 s13, s94, 0xff
+; SI-NEXT: s_lshl_b32 s13, s13, 16
+; SI-NEXT: s_lshl_b32 s21, s90, 24
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: s_or_b32 s13, s21, s13
+; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v23, 0xff, v24
-; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v27
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
-; SI-NEXT: s_lshl_b32 s4, s16, 8
-; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v30
-; SI-NEXT: v_or_b32_e32 v20, s4, v20
-; SI-NEXT: s_and_b32 s4, s12, 0xff
-; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
-; SI-NEXT: v_or_b32_e32 v22, v24, v22
-; SI-NEXT: s_lshl_b32 s4, s4, 16
-; SI-NEXT: s_lshl_b32 s5, s8, 24
-; SI-NEXT: v_or_b32_e32 v22, v23, v22
-; SI-NEXT: v_add_i32_e32 v23, vcc, 4, v0
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: buffer_store_dword v22, v23, s[0:3], 0 offen
-; SI-NEXT: v_or_b32_e32 v20, s4, v20
+; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v22, vcc, 8, v0
-; SI-NEXT: buffer_store_dword v20, v22, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s7
+; SI-NEXT: s_and_b32 s7, s62, 0xff
+; SI-NEXT: s_lshl_b32 s13, s23, 8
+; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: s_and_b32 s13, s59, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s13, s13, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v39
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s13, v1
+; SI-NEXT: v_or_b32_e32 v1, s7, v1
+; SI-NEXT: s_and_b32 s7, s46, 0xff
+; SI-NEXT: s_lshl_b32 s13, s38, 8
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: s_and_b32 s13, s36, 0xff
+; SI-NEXT: s_lshl_b32 s13, s13, 16
+; SI-NEXT: s_lshl_b32 s21, s34, 24
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: s_or_b32 s13, s21, s13
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v58
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: s_lshl_b32 s4, s22, 8
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v62
-; SI-NEXT: v_or_b32_e32 v17, s4, v17
-; SI-NEXT: s_and_b32 s4, s18, 0xff
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v19, v21, v19
-; SI-NEXT: s_lshl_b32 s4, s4, 16
-; SI-NEXT: s_lshl_b32 s5, s14, 24
-; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: v_add_i32_e32 v20, vcc, 12, v0
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen
-; SI-NEXT: v_or_b32_e32 v17, s4, v17
+; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s7
+; SI-NEXT: s_and_b32 s7, s56, 0xff
+; SI-NEXT: s_lshl_b32 s13, s18, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 16, v0
-; SI-NEXT: buffer_store_dword v17, v19, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: s_and_b32 s13, s45, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s13, s13, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v38
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s13, v1
+; SI-NEXT: v_or_b32_e32 v1, s7, v1
+; SI-NEXT: s_and_b32 s7, s26, 0xff
+; SI-NEXT: s_lshl_b32 s13, s52, 8
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: s_and_b32 s13, s50, 0xff
+; SI-NEXT: s_lshl_b32 s13, s13, 16
+; SI-NEXT: s_lshl_b32 s18, s48, 24
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: s_or_b32 s13, s18, s13
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v28
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: s_lshl_b32 s4, s28, 8
-; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v31
-; SI-NEXT: v_or_b32_e32 v14, s4, v14
-; SI-NEXT: s_and_b32 s4, s24, 0xff
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v16, v18, v16
-; SI-NEXT: s_lshl_b32 s4, s4, 16
-; SI-NEXT: s_lshl_b32 s5, s20, 24
-; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, 20, v0
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: buffer_store_dword v16, v17, s[0:3], 0 offen
-; SI-NEXT: v_or_b32_e32 v14, s4, v14
+; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s7
+; SI-NEXT: s_and_b32 s7, s42, 0xff
+; SI-NEXT: s_lshl_b32 s13, s17, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v16, vcc, 24, v0
-; SI-NEXT: buffer_store_dword v14, v16, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: s_and_b32 s13, s25, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s13, s13, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v37
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s13, v1
+; SI-NEXT: v_or_b32_e32 v1, s7, v1
+; SI-NEXT: s_and_b32 s7, s16, 0xff
+; SI-NEXT: s_lshl_b32 s13, s66, 8
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: s_and_b32 s13, s64, 0xff
+; SI-NEXT: s_lshl_b32 s13, s13, 16
+; SI-NEXT: s_lshl_b32 s16, s54, 24
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: s_or_b32 s13, s16, s13
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v59
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: s_lshl_b32 s4, s44, 8
-; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v63
-; SI-NEXT: v_or_b32_e32 v11, s4, v11
-; SI-NEXT: s_and_b32 s4, s40, 0xff
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v13, v15, v13
-; SI-NEXT: s_lshl_b32 s4, s4, 16
-; SI-NEXT: s_lshl_b32 s5, s26, 24
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 28, v0
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen
-; SI-NEXT: v_or_b32_e32 v11, s4, v11
+; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s7
+; SI-NEXT: s_and_b32 s7, s22, 0xff
+; SI-NEXT: s_lshl_b32 s13, s15, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v13, vcc, 32, v0
-; SI-NEXT: buffer_store_dword v11, v13, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: s_and_b32 s13, s41, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s13, s13, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v34
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s13, v1
+; SI-NEXT: v_or_b32_e32 v1, s7, v1
+; SI-NEXT: s_and_b32 s7, s20, 0xff
+; SI-NEXT: s_lshl_b32 s13, s78, 8
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: s_and_b32 s13, s70, 0xff
+; SI-NEXT: s_lshl_b32 s13, s13, 16
+; SI-NEXT: s_lshl_b32 s15, s68, 24
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: s_or_b32 s13, s15, s13
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v47
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: s_lshl_b32 s4, s58, 8
-; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v56
-; SI-NEXT: v_or_b32_e32 v8, s4, v8
-; SI-NEXT: s_and_b32 s4, s46, 0xff
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v10, v12, v10
-; SI-NEXT: s_lshl_b32 s4, s4, 16
-; SI-NEXT: s_lshl_b32 s5, s42, 24
-; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 36, v0
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: buffer_store_dword v10, v11, s[0:3], 0 offen
-; SI-NEXT: v_or_b32_e32 v8, s4, v8
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v10, vcc, 40, v0
-; SI-NEXT: buffer_store_dword v8, v10, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
+; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s7
+; SI-NEXT: s_and_b32 s7, s28, 0xff
+; SI-NEXT: s_lshl_b32 s10, s10, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v41
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: s_lshl_b32 s4, s72, 8
-; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v45
-; SI-NEXT: v_or_b32_e32 v4, s4, v4
-; SI-NEXT: s_and_b32 s4, s60, 0xff
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v7, v9, v7
-; SI-NEXT: s_lshl_b32 s4, s4, 16
-; SI-NEXT: s_lshl_b32 s5, s56, 24
-; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 44, v0
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
-; SI-NEXT: v_or_b32_e32 v4, s4, v4
+; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0
+; SI-NEXT: s_or_b32 s7, s7, s10
+; SI-NEXT: s_and_b32 s10, s19, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s10, s10, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v16
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s10, v1
+; SI-NEXT: v_or_b32_e32 v1, s7, v1
+; SI-NEXT: s_and_b32 s7, s12, 0xff
+; SI-NEXT: s_lshl_b32 s10, s98, 8
+; SI-NEXT: s_or_b32 s7, s7, s10
+; SI-NEXT: s_and_b32 s10, s96, 0xff
+; SI-NEXT: s_lshl_b32 s10, s10, 16
+; SI-NEXT: s_lshl_b32 s12, s86, 24
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: s_or_b32 s10, s12, s10
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v7, vcc, 48, v0
-; SI-NEXT: buffer_store_dword v4, v7, s[0:3], 0 offen
+; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
+; SI-NEXT: s_or_b32 s7, s7, s10
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: v_mov_b32_e32 v2, s7
+; SI-NEXT: s_and_b32 s7, s14, 0xff
+; SI-NEXT: s_lshl_b32 s9, s9, 8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v54
-; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v6
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: s_lshl_b32 s4, s76, 8
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v42
-; SI-NEXT: v_or_b32_e32 v3, s4, v3
-; SI-NEXT: s_and_b32 s4, s74, 0xff
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: s_lshl_b32 s4, s4, 16
-; SI-NEXT: s_lshl_b32 s5, s62, 24
-; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, 52, v0
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
-; SI-NEXT: v_or_b32_e32 v3, s4, v3
+; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0
+; SI-NEXT: s_or_b32 s7, s7, s9
+; SI-NEXT: s_and_b32 s9, s11, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_lshl_b32 s9, s9, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v15
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s9, v1
+; SI-NEXT: v_or_b32_e32 v1, s7, v1
+; SI-NEXT: s_and_b32 s6, s6, 0xff
+; SI-NEXT: s_lshl_b32 s7, s84, 8
+; SI-NEXT: s_or_b32 s6, s6, s7
+; SI-NEXT: s_and_b32 s7, s82, 0xff
+; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_lshl_b32 s9, s80, 24
+; SI-NEXT: s_and_b32 s6, s6, 0xffff
+; SI-NEXT: s_or_b32 s7, s9, s7
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 56, v0
-; SI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
+; SI-NEXT: s_or_b32 s6, s6, s7
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v48
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v51
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0
+; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: s_and_b32 s6, s8, 0xff
+; SI-NEXT: s_lshl_b32 s4, s4, 8
+; SI-NEXT: s_and_b32 s5, s5, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_or_b32 s4, s6, s4
+; SI-NEXT: s_lshl_b32 s5, s5, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v14
+; SI-NEXT: s_and_b32 s4, s4, 0xffff
+; SI-NEXT: v_or_b32_e32 v1, s5, v1
+; SI-NEXT: v_or_b32_e32 v1, s4, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
+; SI-NEXT: v_readlane_b32 s75, v41, 1
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; SI-NEXT: v_readlane_b32 s99, v40, 35
+; SI-NEXT: v_readlane_b32 s98, v40, 34
+; SI-NEXT: v_readlane_b32 s97, v40, 33
+; SI-NEXT: v_readlane_b32 s96, v40, 32
+; SI-NEXT: v_readlane_b32 s87, v40, 31
+; SI-NEXT: v_readlane_b32 s86, v40, 30
+; SI-NEXT: v_readlane_b32 s85, v40, 29
+; SI-NEXT: v_readlane_b32 s84, v40, 28
+; SI-NEXT: v_readlane_b32 s83, v40, 27
+; SI-NEXT: v_readlane_b32 s82, v40, 26
+; SI-NEXT: v_readlane_b32 s81, v40, 25
+; SI-NEXT: v_readlane_b32 s80, v40, 24
+; SI-NEXT: v_readlane_b32 s71, v40, 23
+; SI-NEXT: v_readlane_b32 s70, v40, 22
+; SI-NEXT: v_readlane_b32 s69, v40, 21
+; SI-NEXT: v_readlane_b32 s68, v40, 20
+; SI-NEXT: v_readlane_b32 s67, v40, 19
+; SI-NEXT: v_readlane_b32 s66, v40, 18
+; SI-NEXT: v_readlane_b32 s65, v40, 17
+; SI-NEXT: v_readlane_b32 s64, v40, 16
+; SI-NEXT: v_readlane_b32 s55, v40, 15
+; SI-NEXT: v_readlane_b32 s54, v40, 14
+; SI-NEXT: v_readlane_b32 s53, v40, 13
+; SI-NEXT: v_readlane_b32 s52, v40, 12
+; SI-NEXT: v_readlane_b32 s51, v40, 11
+; SI-NEXT: v_readlane_b32 s50, v40, 10
+; SI-NEXT: v_readlane_b32 s49, v40, 9
+; SI-NEXT: v_readlane_b32 s48, v40, 8
+; SI-NEXT: v_readlane_b32 s39, v40, 7
+; SI-NEXT: v_readlane_b32 s38, v40, 6
+; SI-NEXT: v_readlane_b32 s37, v40, 5
+; SI-NEXT: v_readlane_b32 s36, v40, 4
+; SI-NEXT: v_readlane_b32 s35, v40, 3
+; SI-NEXT: v_readlane_b32 s34, v40, 2
+; SI-NEXT: v_readlane_b32 s31, v40, 1
+; SI-NEXT: v_readlane_b32 s30, v40, 0
+; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB109_4:
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $sgpr10
-; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_writelane_b32 v41, s4, 0
+; SI-NEXT: ; implicit-def: $sgpr74
+; SI-NEXT: ; implicit-def: $sgpr92
+; SI-NEXT: ; implicit-def: $sgpr88
+; SI-NEXT: v_writelane_b32 v41, s5, 1
+; SI-NEXT: ; implicit-def: $sgpr76
+; SI-NEXT: ; implicit-def: $sgpr24
+; SI-NEXT: ; implicit-def: $sgpr73
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr30
+; SI-NEXT: ; implicit-def: $sgpr94
+; SI-NEXT: ; implicit-def: $sgpr90
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr23
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: ; implicit-def: $sgpr38
+; SI-NEXT: ; implicit-def: $sgpr36
+; SI-NEXT: ; implicit-def: $sgpr34
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr18
+; SI-NEXT: ; implicit-def: $sgpr45
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $sgpr26
+; SI-NEXT: ; implicit-def: $sgpr52
+; SI-NEXT: ; implicit-def: $sgpr50
+; SI-NEXT: ; implicit-def: $sgpr48
+; SI-NEXT: ; implicit-def: $sgpr42
+; SI-NEXT: ; implicit-def: $sgpr17
+; SI-NEXT: ; implicit-def: $sgpr25
+; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $sgpr16
-; SI-NEXT: ; implicit-def: $sgpr12
-; SI-NEXT: ; implicit-def: $sgpr8
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; implicit-def: $sgpr22
-; SI-NEXT: ; implicit-def: $sgpr18
-; SI-NEXT: ; implicit-def: $sgpr14
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $sgpr15
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $sgpr10
; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $sgpr9
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $sgpr28
-; SI-NEXT: ; implicit-def: $sgpr24
+; SI-NEXT: ; implicit-def: $sgpr41
; SI-NEXT: ; implicit-def: $sgpr20
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $sgpr44
-; SI-NEXT: ; implicit-def: $sgpr40
-; SI-NEXT: ; implicit-def: $sgpr26
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $sgpr58
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr42
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $sgpr72
-; SI-NEXT: ; implicit-def: $sgpr60
-; SI-NEXT: ; implicit-def: $sgpr56
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $sgpr76
-; SI-NEXT: ; implicit-def: $sgpr74
-; SI-NEXT: ; implicit-def: $sgpr62
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $sgpr78
+; SI-NEXT: ; implicit-def: $sgpr70
+; SI-NEXT: ; implicit-def: $sgpr68
+; SI-NEXT: ; implicit-def: $sgpr28
+; SI-NEXT: ; implicit-def: $sgpr19
+; SI-NEXT: ; implicit-def: $sgpr12
+; SI-NEXT: ; implicit-def: $sgpr98
+; SI-NEXT: ; implicit-def: $sgpr96
+; SI-NEXT: ; implicit-def: $sgpr86
+; SI-NEXT: ; implicit-def: $sgpr14
+; SI-NEXT: ; implicit-def: $sgpr11
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: ; implicit-def: $sgpr82
+; SI-NEXT: ; implicit-def: $sgpr80
+; SI-NEXT: ; implicit-def: $sgpr8
+; SI-NEXT: ; implicit-def: $sgpr5
; SI-NEXT: s_branch .LBB109_2
;
; VI-LABEL: bitcast_v32bf16_to_v64i8_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v63, s30, 0
-; VI-NEXT: v_writelane_b32 v63, s31, 1
-; VI-NEXT: v_writelane_b32 v63, s34, 2
-; VI-NEXT: v_writelane_b32 v63, s35, 3
-; VI-NEXT: v_writelane_b32 v63, s36, 4
-; VI-NEXT: v_writelane_b32 v63, s37, 5
-; VI-NEXT: v_writelane_b32 v63, s38, 6
-; VI-NEXT: v_writelane_b32 v63, s39, 7
-; VI-NEXT: v_writelane_b32 v63, s48, 8
-; VI-NEXT: v_writelane_b32 v63, s49, 9
-; VI-NEXT: v_writelane_b32 v63, s50, 10
-; VI-NEXT: v_writelane_b32 v63, s51, 11
-; VI-NEXT: v_writelane_b32 v63, s52, 12
-; VI-NEXT: v_writelane_b32 v63, s53, 13
-; VI-NEXT: v_writelane_b32 v63, s54, 14
-; VI-NEXT: v_writelane_b32 v63, s55, 15
-; VI-NEXT: v_writelane_b32 v63, s64, 16
-; VI-NEXT: v_writelane_b32 v63, s65, 17
-; VI-NEXT: v_writelane_b32 v63, s66, 18
+; VI-NEXT: v_writelane_b32 v4, s30, 0
+; VI-NEXT: v_writelane_b32 v4, s31, 1
+; VI-NEXT: v_writelane_b32 v4, s34, 2
+; VI-NEXT: v_writelane_b32 v4, s35, 3
+; VI-NEXT: v_writelane_b32 v4, s36, 4
+; VI-NEXT: v_writelane_b32 v4, s37, 5
+; VI-NEXT: v_writelane_b32 v4, s38, 6
+; VI-NEXT: v_writelane_b32 v4, s39, 7
+; VI-NEXT: v_writelane_b32 v4, s48, 8
+; VI-NEXT: v_writelane_b32 v4, s49, 9
+; VI-NEXT: v_writelane_b32 v4, s50, 10
+; VI-NEXT: v_writelane_b32 v4, s51, 11
+; VI-NEXT: v_writelane_b32 v4, s52, 12
+; VI-NEXT: v_writelane_b32 v4, s53, 13
+; VI-NEXT: v_writelane_b32 v4, s54, 14
+; VI-NEXT: v_writelane_b32 v4, s55, 15
+; VI-NEXT: v_writelane_b32 v4, s64, 16
+; VI-NEXT: v_writelane_b32 v4, s65, 17
+; VI-NEXT: v_writelane_b32 v4, s66, 18
+; VI-NEXT: v_writelane_b32 v4, s67, 19
+; VI-NEXT: v_writelane_b32 v4, s68, 20
+; VI-NEXT: v_writelane_b32 v4, s69, 21
+; VI-NEXT: v_writelane_b32 v4, s70, 22
+; VI-NEXT: v_writelane_b32 v4, s71, 23
+; VI-NEXT: v_writelane_b32 v4, s80, 24
+; VI-NEXT: v_writelane_b32 v4, s81, 25
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; VI-NEXT: v_writelane_b32 v63, s67, 19
+; VI-NEXT: v_writelane_b32 v4, s82, 26
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
-; VI-NEXT: s_cbranch_scc0 .LBB109_3
+; VI-NEXT: v_writelane_b32 v4, s83, 27
+; VI-NEXT: s_cbranch_scc0 .LBB109_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: s_lshr_b32 s56, s5, 24
-; VI-NEXT: s_lshr_b32 s57, s5, 16
-; VI-NEXT: s_lshr_b32 s59, s5, 8
-; VI-NEXT: s_lshr_b32 s58, s4, 16
-; VI-NEXT: s_lshr_b32 s60, s4, 8
-; VI-NEXT: s_lshr_b32 s61, s29, 24
-; VI-NEXT: s_lshr_b32 s62, s29, 16
-; VI-NEXT: s_lshr_b32 s72, s29, 8
-; VI-NEXT: s_lshr_b32 s63, s28, 16
-; VI-NEXT: s_lshr_b32 s73, s28, 8
-; VI-NEXT: s_lshr_b32 s74, s27, 24
-; VI-NEXT: s_lshr_b32 s75, s27, 16
-; VI-NEXT: s_lshr_b32 s77, s27, 8
-; VI-NEXT: s_lshr_b32 s76, s26, 16
-; VI-NEXT: s_lshr_b32 s78, s26, 8
-; VI-NEXT: s_lshr_b32 s79, s25, 24
-; VI-NEXT: s_lshr_b32 s88, s25, 16
-; VI-NEXT: s_lshr_b32 s90, s25, 8
-; VI-NEXT: s_lshr_b32 s89, s24, 16
-; VI-NEXT: s_lshr_b32 s91, s24, 8
-; VI-NEXT: s_lshr_b32 s30, s23, 24
-; VI-NEXT: s_lshr_b32 s31, s23, 16
-; VI-NEXT: s_lshr_b32 s35, s23, 8
-; VI-NEXT: s_lshr_b32 s34, s22, 16
-; VI-NEXT: s_lshr_b32 s36, s22, 8
-; VI-NEXT: s_lshr_b32 s37, s21, 24
-; VI-NEXT: s_lshr_b32 s38, s21, 16
-; VI-NEXT: s_lshr_b32 s48, s21, 8
-; VI-NEXT: s_lshr_b32 s39, s20, 16
-; VI-NEXT: s_lshr_b32 s49, s20, 8
-; VI-NEXT: s_lshr_b32 s50, s19, 24
-; VI-NEXT: s_lshr_b32 s51, s19, 16
-; VI-NEXT: s_lshr_b32 s53, s19, 8
-; VI-NEXT: s_lshr_b32 s52, s18, 16
-; VI-NEXT: s_lshr_b32 s54, s18, 8
-; VI-NEXT: s_lshr_b32 s55, s17, 24
-; VI-NEXT: s_lshr_b32 s64, s17, 16
-; VI-NEXT: s_lshr_b32 s66, s17, 8
-; VI-NEXT: s_lshr_b32 s65, s16, 16
-; VI-NEXT: s_lshr_b32 s67, s16, 8
-; VI-NEXT: s_lshr_b64 s[44:45], s[4:5], 24
-; VI-NEXT: s_lshr_b64 s[42:43], s[28:29], 24
-; VI-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
-; VI-NEXT: s_lshr_b64 s[14:15], s[24:25], 24
-; VI-NEXT: s_lshr_b64 s[12:13], s[22:23], 24
-; VI-NEXT: s_lshr_b64 s[10:11], s[20:21], 24
-; VI-NEXT: s_lshr_b64 s[8:9], s[18:19], 24
-; VI-NEXT: s_lshr_b64 s[6:7], s[16:17], 24
-; VI-NEXT: s_cbranch_execnz .LBB109_4
+; VI-NEXT: s_lshr_b32 s7, s5, 24
+; VI-NEXT: s_lshr_b32 s9, s5, 16
+; VI-NEXT: s_lshr_b32 s11, s5, 8
+; VI-NEXT: s_lshr_b32 s13, s4, 16
+; VI-NEXT: s_lshr_b32 s15, s4, 8
+; VI-NEXT: s_lshr_b32 s41, s29, 24
+; VI-NEXT: s_lshr_b32 s47, s29, 16
+; VI-NEXT: s_lshr_b32 s57, s29, 8
+; VI-NEXT: s_lshr_b32 s88, s28, 16
+; VI-NEXT: s_lshr_b32 s89, s28, 8
+; VI-NEXT: s_lshr_b32 s90, s27, 24
+; VI-NEXT: s_lshr_b32 s91, s27, 16
+; VI-NEXT: s_lshr_b32 s30, s27, 8
+; VI-NEXT: s_lshr_b32 s31, s26, 16
+; VI-NEXT: s_lshr_b32 s34, s26, 8
+; VI-NEXT: s_lshr_b32 s35, s25, 24
+; VI-NEXT: s_lshr_b32 s36, s25, 16
+; VI-NEXT: s_lshr_b32 s37, s25, 8
+; VI-NEXT: s_lshr_b32 s38, s24, 16
+; VI-NEXT: s_lshr_b32 s39, s24, 8
+; VI-NEXT: s_lshr_b32 s48, s23, 24
+; VI-NEXT: s_lshr_b32 s49, s23, 16
+; VI-NEXT: s_lshr_b32 s50, s23, 8
+; VI-NEXT: s_lshr_b32 s51, s22, 16
+; VI-NEXT: s_lshr_b32 s52, s22, 8
+; VI-NEXT: s_lshr_b32 s53, s21, 24
+; VI-NEXT: s_lshr_b32 s54, s21, 16
+; VI-NEXT: s_lshr_b32 s55, s21, 8
+; VI-NEXT: s_lshr_b32 s64, s20, 16
+; VI-NEXT: s_lshr_b32 s65, s20, 8
+; VI-NEXT: s_lshr_b32 s66, s19, 24
+; VI-NEXT: s_lshr_b32 s67, s19, 16
+; VI-NEXT: s_lshr_b32 s68, s19, 8
+; VI-NEXT: s_lshr_b32 s69, s18, 16
+; VI-NEXT: s_lshr_b32 s70, s18, 8
+; VI-NEXT: s_lshr_b32 s71, s17, 24
+; VI-NEXT: s_lshr_b32 s80, s17, 16
+; VI-NEXT: s_lshr_b32 s81, s17, 8
+; VI-NEXT: s_lshr_b32 s82, s16, 16
+; VI-NEXT: s_lshr_b32 s83, s16, 8
+; VI-NEXT: s_lshr_b64 s[42:43], s[4:5], 24
+; VI-NEXT: s_lshr_b64 s[44:45], s[28:29], 24
+; VI-NEXT: s_lshr_b64 s[58:59], s[26:27], 24
+; VI-NEXT: s_lshr_b64 s[60:61], s[24:25], 24
+; VI-NEXT: s_lshr_b64 s[62:63], s[22:23], 24
+; VI-NEXT: s_lshr_b64 s[72:73], s[20:21], 24
+; VI-NEXT: s_lshr_b64 s[74:75], s[18:19], 24
+; VI-NEXT: s_lshr_b64 s[76:77], s[16:17], 24
+; VI-NEXT: s_mov_b32 s6, s17
+; VI-NEXT: s_mov_b32 s8, s19
+; VI-NEXT: s_mov_b32 s10, s21
+; VI-NEXT: s_mov_b32 s12, s23
+; VI-NEXT: s_mov_b32 s14, s25
+; VI-NEXT: s_mov_b32 s40, s27
+; VI-NEXT: s_mov_b32 s46, s29
+; VI-NEXT: s_mov_b32 s56, s5
+; VI-NEXT: s_cbranch_execnz .LBB109_3
; VI-NEXT: .LBB109_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s6, s17, 16
-; VI-NEXT: v_mov_b32_e32 v15, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s6, v15
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s6, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s6, v15
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v2, s6, v1
+; VI-NEXT: v_readfirstlane_b32 s6, v2
+; VI-NEXT: s_bfe_u32 s7, s6, 0x10010
+; VI-NEXT: s_add_i32 s7, s7, s6
+; VI-NEXT: s_add_i32 s8, s7, 0x7fff
+; VI-NEXT: s_or_b32 s9, s6, 0x400000
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_lshl_b32 s6, s16, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s6, v15
-; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s6, v15
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; VI-NEXT: s_lshl_b32 s6, s19, 16
-; VI-NEXT: v_alignbit_b32 v1, v3, v1, 16
-; VI-NEXT: v_add_f32_e32 v3, s6, v15
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_and_b32 s6, s19, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_add_f32_e32 v4, s6, v15
-; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; VI-NEXT: s_lshl_b32 s6, s18, 16
-; VI-NEXT: v_alignbit_b32 v4, v4, v3, 16
-; VI-NEXT: v_add_f32_e32 v3, s6, v15
-; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
-; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
-; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: s_and_b32 s6, s18, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
-; VI-NEXT: v_add_f32_e32 v5, s6, v15
-; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
-; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
-; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
-; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; VI-NEXT: s_lshl_b32 s6, s21, 16
-; VI-NEXT: v_alignbit_b32 v3, v5, v3, 16
-; VI-NEXT: v_add_f32_e32 v5, s6, v15
-; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
-; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
-; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
-; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: s_and_b32 s6, s21, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
-; VI-NEXT: v_add_f32_e32 v6, s6, v15
-; VI-NEXT: v_bfe_u32 v7, v6, 16, 1
-; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6
-; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
-; VI-NEXT: v_or_b32_e32 v8, 0x400000, v6
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
-; VI-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; VI-NEXT: s_lshl_b32 s6, s20, 16
-; VI-NEXT: v_alignbit_b32 v6, v6, v5, 16
-; VI-NEXT: v_add_f32_e32 v5, s6, v15
-; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
-; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
-; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
-; VI-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; VI-NEXT: s_and_b32 s6, s20, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc
-; VI-NEXT: v_add_f32_e32 v7, s6, v15
-; VI-NEXT: v_bfe_u32 v8, v7, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v7
-; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; VI-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; VI-NEXT: s_lshl_b32 s6, s23, 16
-; VI-NEXT: v_alignbit_b32 v5, v7, v5, 16
-; VI-NEXT: v_add_f32_e32 v7, s6, v15
-; VI-NEXT: v_bfe_u32 v8, v7, 16, 1
-; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v7
-; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
-; VI-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; VI-NEXT: s_and_b32 s6, s23, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; VI-NEXT: v_add_f32_e32 v8, s6, v15
-; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
-; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; VI-NEXT: s_lshl_b32 s6, s22, 16
-; VI-NEXT: v_alignbit_b32 v8, v8, v7, 16
-; VI-NEXT: v_add_f32_e32 v7, s6, v15
-; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
-; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
-; VI-NEXT: v_or_b32_e32 v10, 0x400000, v7
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; VI-NEXT: s_and_b32 s6, s22, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
-; VI-NEXT: v_add_f32_e32 v9, s6, v15
-; VI-NEXT: v_bfe_u32 v10, v9, 16, 1
-; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v9
-; VI-NEXT: v_add_u32_e32 v10, vcc, 0x7fff, v10
-; VI-NEXT: v_or_b32_e32 v11, 0x400000, v9
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
-; VI-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; VI-NEXT: s_lshl_b32 s6, s25, 16
-; VI-NEXT: v_alignbit_b32 v7, v9, v7, 16
-; VI-NEXT: v_add_f32_e32 v9, s6, v15
-; VI-NEXT: v_bfe_u32 v10, v9, 16, 1
-; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v9
-; VI-NEXT: v_add_u32_e32 v10, vcc, 0x7fff, v10
-; VI-NEXT: v_or_b32_e32 v11, 0x400000, v9
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
-; VI-NEXT: s_and_b32 s6, s25, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc
-; VI-NEXT: v_add_f32_e32 v10, s6, v15
-; VI-NEXT: v_bfe_u32 v11, v10, 16, 1
-; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10
-; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
-; VI-NEXT: v_or_b32_e32 v12, 0x400000, v10
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
-; VI-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; VI-NEXT: s_lshl_b32 s6, s24, 16
-; VI-NEXT: v_alignbit_b32 v10, v10, v9, 16
-; VI-NEXT: v_add_f32_e32 v9, s6, v15
-; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
-; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
-; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
-; VI-NEXT: v_or_b32_e32 v12, 0x400000, v9
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
-; VI-NEXT: s_and_b32 s6, s24, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc
-; VI-NEXT: v_add_f32_e32 v11, s6, v15
-; VI-NEXT: v_bfe_u32 v12, v11, 16, 1
-; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v11
-; VI-NEXT: v_add_u32_e32 v12, vcc, 0x7fff, v12
-; VI-NEXT: v_or_b32_e32 v13, 0x400000, v11
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
-; VI-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; VI-NEXT: s_lshl_b32 s6, s27, 16
-; VI-NEXT: v_alignbit_b32 v9, v11, v9, 16
-; VI-NEXT: v_add_f32_e32 v11, s6, v15
-; VI-NEXT: v_bfe_u32 v12, v11, 16, 1
-; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v11
-; VI-NEXT: v_add_u32_e32 v12, vcc, 0x7fff, v12
-; VI-NEXT: v_or_b32_e32 v13, 0x400000, v11
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
-; VI-NEXT: s_and_b32 s6, s27, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc
-; VI-NEXT: v_add_f32_e32 v12, s6, v15
-; VI-NEXT: v_bfe_u32 v13, v12, 16, 1
-; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12
-; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
-; VI-NEXT: v_or_b32_e32 v14, 0x400000, v12
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
-; VI-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; VI-NEXT: s_lshl_b32 s6, s26, 16
-; VI-NEXT: v_alignbit_b32 v12, v12, v11, 16
-; VI-NEXT: v_add_f32_e32 v11, s6, v15
-; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
-; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
-; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
-; VI-NEXT: v_or_b32_e32 v14, 0x400000, v11
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
-; VI-NEXT: s_and_b32 s6, s26, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
-; VI-NEXT: v_add_f32_e32 v13, s6, v15
-; VI-NEXT: v_bfe_u32 v14, v13, 16, 1
-; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13
-; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v13
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
-; VI-NEXT: v_cndmask_b32_e32 v13, v14, v16, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; VI-NEXT: s_lshl_b32 s6, s29, 16
-; VI-NEXT: v_alignbit_b32 v11, v13, v11, 16
-; VI-NEXT: v_add_f32_e32 v13, s6, v15
-; VI-NEXT: v_bfe_u32 v14, v13, 16, 1
-; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13
-; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
-; VI-NEXT: v_or_b32_e32 v16, 0x400000, v13
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
-; VI-NEXT: s_and_b32 s6, s29, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v13, v14, v16, vcc
-; VI-NEXT: v_add_f32_e32 v14, s6, v15
-; VI-NEXT: v_bfe_u32 v16, v14, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v14
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v14
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
-; VI-NEXT: v_cndmask_b32_e32 v14, v16, v17, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; VI-NEXT: s_lshl_b32 s6, s28, 16
-; VI-NEXT: v_alignbit_b32 v14, v14, v13, 16
-; VI-NEXT: v_add_f32_e32 v13, s6, v15
-; VI-NEXT: v_bfe_u32 v16, v13, 16, 1
-; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v13
-; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
-; VI-NEXT: v_or_b32_e32 v17, 0x400000, v13
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
-; VI-NEXT: s_and_b32 s6, s28, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v13, v16, v17, vcc
-; VI-NEXT: v_add_f32_e32 v16, s6, v15
-; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
-; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; VI-NEXT: s_lshl_b32 s6, s5, 16
-; VI-NEXT: v_alignbit_b32 v13, v16, v13, 16
-; VI-NEXT: v_add_f32_e32 v16, s6, v15
-; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
-; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
-; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
+; VI-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-NEXT: s_cselect_b32 s6, s9, s8
+; VI-NEXT: s_and_b32 s7, s17, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s8, s7, 0x10010
+; VI-NEXT: s_add_i32 s8, s8, s7
+; VI-NEXT: s_add_i32 s10, s8, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[8:9], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s10
+; VI-NEXT: s_lshr_b32 s7, s7, 16
+; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
+; VI-NEXT: s_lshl_b32 s7, s16, 16
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s8, s7, 0x10010
+; VI-NEXT: s_add_i32 s8, s8, s7
+; VI-NEXT: s_add_i32 s10, s8, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[8:9], vcc, exec
+; VI-NEXT: s_cselect_b32 s8, s7, s10
+; VI-NEXT: s_and_b32 s7, s16, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[10:11], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s9, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s19, 16
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_lshr_b64 s[16:17], s[8:9], 16
+; VI-NEXT: s_bfe_u32 s8, s7, 0x10010
+; VI-NEXT: s_add_i32 s8, s8, s7
+; VI-NEXT: s_add_i32 s10, s8, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[8:9], vcc, exec
+; VI-NEXT: s_cselect_b32 s8, s7, s10
+; VI-NEXT: s_and_b32 s7, s19, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[10:11], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s9, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s18, 16
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[10:11], vcc, exec
+; VI-NEXT: s_cselect_b32 s10, s7, s9
+; VI-NEXT: s_and_b32 s7, s18, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[12:13], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s11, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s21, 16
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[18:19], s[10:11], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[10:11], vcc, exec
+; VI-NEXT: s_cselect_b32 s10, s7, s9
+; VI-NEXT: s_and_b32 s7, s21, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[12:13], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s11, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s20, 16
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[10:11], s[10:11], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[12:13], vcc, exec
+; VI-NEXT: s_cselect_b32 s12, s7, s9
+; VI-NEXT: s_and_b32 s7, s20, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s13, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s23, 16
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[20:21], s[12:13], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[12:13], vcc, exec
+; VI-NEXT: s_cselect_b32 s12, s7, s9
+; VI-NEXT: s_and_b32 s7, s23, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s13, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s22, 16
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[12:13], s[12:13], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: s_cselect_b32 s14, s7, s9
+; VI-NEXT: s_and_b32 s7, s22, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[22:23], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s15, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s25, 16
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[22:23], s[14:15], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[14:15], vcc, exec
+; VI-NEXT: s_cselect_b32 s14, s7, s9
+; VI-NEXT: s_and_b32 s7, s25, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[40:41], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s15, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s24, 16
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[14:15], s[14:15], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[40:41], vcc, exec
+; VI-NEXT: s_cselect_b32 s40, s7, s9
+; VI-NEXT: s_and_b32 s7, s24, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[24:25], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s41, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s27, 16
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[24:25], s[40:41], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[40:41], vcc, exec
+; VI-NEXT: s_cselect_b32 s40, s7, s9
+; VI-NEXT: s_and_b32 s7, s27, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[42:43], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s41, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s26, 16
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[40:41], s[40:41], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[42:43], vcc, exec
+; VI-NEXT: s_cselect_b32 s42, s7, s9
+; VI-NEXT: s_and_b32 s7, s26, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[26:27], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s43, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s29, 16
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[26:27], s[42:43], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[42:43], vcc, exec
+; VI-NEXT: s_cselect_b32 s42, s7, s9
+; VI-NEXT: s_and_b32 s7, s29, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[44:45], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s43, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s28, 16
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[46:47], s[42:43], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[42:43], vcc, exec
+; VI-NEXT: s_cselect_b32 s42, s7, s9
+; VI-NEXT: s_and_b32 s7, s28, 0xffff0000
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[28:29], vcc, exec
+; VI-NEXT: s_cselect_b32 s7, s7, s9
+; VI-NEXT: s_lshr_b32 s43, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s5, 16
+; VI-NEXT: v_add_f32_e32 v2, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: s_bfe_u32 s9, s7, 0x10010
+; VI-NEXT: s_add_i32 s9, s9, s7
+; VI-NEXT: s_lshr_b64 s[28:29], s[42:43], 16
+; VI-NEXT: s_addk_i32 s9, 0x7fff
+; VI-NEXT: s_bitset1_b32 s7, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[42:43], vcc, exec
+; VI-NEXT: s_cselect_b32 s42, s7, s9
; VI-NEXT: s_and_b32 s5, s5, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
-; VI-NEXT: v_add_f32_e32 v17, s5, v15
-; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
-; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
-; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
-; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; VI-NEXT: v_add_f32_e32 v2, s5, v1
+; VI-NEXT: v_readfirstlane_b32 s5, v2
+; VI-NEXT: s_bfe_u32 s7, s5, 0x10010
+; VI-NEXT: s_add_i32 s7, s7, s5
+; VI-NEXT: s_addk_i32 s7, 0x7fff
+; VI-NEXT: s_bitset1_b32 s5, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[44:45], vcc, exec
+; VI-NEXT: s_cselect_b32 s5, s5, s7
+; VI-NEXT: s_lshr_b32 s43, s5, 16
; VI-NEXT: s_lshl_b32 s5, s4, 16
-; VI-NEXT: v_alignbit_b32 v16, v17, v16, 16
-; VI-NEXT: v_add_f32_e32 v17, s5, v15
-; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
-; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
+; VI-NEXT: v_add_f32_e32 v2, s5, v1
+; VI-NEXT: v_readfirstlane_b32 s5, v2
+; VI-NEXT: s_bfe_u32 s7, s5, 0x10010
+; VI-NEXT: s_add_i32 s7, s7, s5
+; VI-NEXT: s_lshr_b64 s[56:57], s[42:43], 16
+; VI-NEXT: s_addk_i32 s7, 0x7fff
+; VI-NEXT: s_bitset1_b32 s5, 22
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: s_and_b64 s[42:43], vcc, exec
+; VI-NEXT: s_cselect_b32 s42, s5, s7
; VI-NEXT: s_and_b32 s4, s4, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
-; VI-NEXT: v_add_f32_e32 v15, s4, v15
-; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
-; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
-; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
-; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
-; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
-; VI-NEXT: v_cndmask_b32_e32 v15, v18, v19, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_alignbit_b32 v15, v15, v17, 16
-; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
-; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
-; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
-; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[13:14]
-; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
-; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
-; VI-NEXT: v_lshrrev_b32_e32 v26, 24, v16
-; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v16
-; VI-NEXT: v_lshrrev_b32_e32 v27, 8, v16
-; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v15
-; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v14
-; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v14
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v13
-; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v13
-; VI-NEXT: v_lshrrev_b32_e32 v36, 24, v12
-; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v12
-; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v11
-; VI-NEXT: v_lshrrev_b32_e32 v39, 8, v11
-; VI-NEXT: v_lshrrev_b32_e32 v49, 24, v10
-; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v10
-; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v10
-; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; VI-NEXT: v_lshrrev_b32_e32 v52, 8, v9
-; VI-NEXT: v_lshrrev_b32_e32 v54, 24, v8
-; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v8
-; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v8
-; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v7
-; VI-NEXT: v_lshrrev_b32_e32 v41, 8, v7
-; VI-NEXT: v_lshrrev_b32_e32 v43, 24, v6
-; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v6
-; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v6
-; VI-NEXT: v_lshrrev_b32_e32 v45, 16, v5
-; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v5
-; VI-NEXT: v_lshrrev_b32_e32 v56, 24, v4
-; VI-NEXT: v_lshrrev_b32_e32 v47, 16, v4
-; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v4
-; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v3
-; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v3
-; VI-NEXT: v_lshrrev_b32_e32 v61, 24, v2
-; VI-NEXT: v_lshrrev_b32_e32 v60, 16, v2
-; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v2
-; VI-NEXT: v_lshrrev_b32_e32 v62, 16, v1
-; VI-NEXT: v_lshrrev_b32_e32 v18, 8, v1
-; VI-NEXT: s_branch .LBB109_5
-; VI-NEXT: .LBB109_3:
-; VI-NEXT: ; implicit-def: $sgpr67
-; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: v_add_f32_e32 v1, s4, v1
+; VI-NEXT: v_readfirstlane_b32 s4, v1
+; VI-NEXT: s_bfe_u32 s5, s4, 0x10010
+; VI-NEXT: s_add_i32 s5, s5, s4
+; VI-NEXT: s_add_i32 s7, s5, 0x7fff
+; VI-NEXT: s_or_b32 s9, s4, 0x400000
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cselect_b32 s4, s9, s7
+; VI-NEXT: s_lshr_b32 s43, s4, 16
+; VI-NEXT: s_lshr_b64 s[4:5], s[42:43], 16
+; VI-NEXT: s_mov_b32 s17, s6
+; VI-NEXT: s_mov_b32 s19, s8
+; VI-NEXT: s_mov_b32 s21, s10
+; VI-NEXT: s_mov_b32 s23, s12
+; VI-NEXT: s_mov_b32 s25, s14
+; VI-NEXT: s_mov_b32 s27, s40
+; VI-NEXT: s_mov_b32 s29, s46
+; VI-NEXT: s_mov_b32 s5, s56
+; VI-NEXT: s_lshr_b64 s[42:43], s[4:5], 24
+; VI-NEXT: s_lshr_b64 s[44:45], s[28:29], 24
+; VI-NEXT: s_lshr_b32 s7, s56, 24
+; VI-NEXT: s_lshr_b32 s9, s56, 16
+; VI-NEXT: s_lshr_b32 s11, s56, 8
+; VI-NEXT: s_lshr_b32 s13, s4, 16
+; VI-NEXT: s_lshr_b32 s15, s4, 8
+; VI-NEXT: s_lshr_b32 s41, s46, 24
+; VI-NEXT: s_lshr_b32 s47, s46, 16
+; VI-NEXT: s_lshr_b32 s57, s46, 8
+; VI-NEXT: s_lshr_b32 s88, s28, 16
+; VI-NEXT: s_lshr_b32 s89, s28, 8
+; VI-NEXT: s_lshr_b32 s90, s40, 24
+; VI-NEXT: s_lshr_b32 s91, s40, 16
+; VI-NEXT: s_lshr_b32 s30, s40, 8
+; VI-NEXT: s_lshr_b32 s31, s26, 16
+; VI-NEXT: s_lshr_b32 s34, s26, 8
+; VI-NEXT: s_lshr_b32 s35, s14, 24
+; VI-NEXT: s_lshr_b32 s36, s14, 16
+; VI-NEXT: s_lshr_b32 s37, s14, 8
+; VI-NEXT: s_lshr_b32 s38, s24, 16
+; VI-NEXT: s_lshr_b32 s39, s24, 8
+; VI-NEXT: s_lshr_b32 s48, s12, 24
+; VI-NEXT: s_lshr_b32 s49, s12, 16
+; VI-NEXT: s_lshr_b32 s50, s12, 8
+; VI-NEXT: s_lshr_b32 s51, s22, 16
+; VI-NEXT: s_lshr_b32 s52, s22, 8
+; VI-NEXT: s_lshr_b32 s53, s10, 24
+; VI-NEXT: s_lshr_b32 s54, s10, 16
+; VI-NEXT: s_lshr_b32 s55, s10, 8
+; VI-NEXT: s_lshr_b32 s64, s20, 16
+; VI-NEXT: s_lshr_b32 s65, s20, 8
+; VI-NEXT: s_lshr_b32 s66, s8, 24
+; VI-NEXT: s_lshr_b32 s67, s8, 16
+; VI-NEXT: s_lshr_b32 s68, s8, 8
+; VI-NEXT: s_lshr_b32 s69, s18, 16
+; VI-NEXT: s_lshr_b32 s70, s18, 8
+; VI-NEXT: s_lshr_b32 s71, s6, 24
+; VI-NEXT: s_lshr_b32 s80, s6, 16
+; VI-NEXT: s_lshr_b32 s81, s6, 8
+; VI-NEXT: s_lshr_b32 s82, s16, 16
+; VI-NEXT: s_lshr_b32 s83, s16, 8
+; VI-NEXT: s_lshr_b64 s[58:59], s[26:27], 24
+; VI-NEXT: s_lshr_b64 s[60:61], s[24:25], 24
+; VI-NEXT: s_lshr_b64 s[62:63], s[22:23], 24
+; VI-NEXT: s_lshr_b64 s[72:73], s[20:21], 24
+; VI-NEXT: s_lshr_b64 s[74:75], s[18:19], 24
+; VI-NEXT: s_lshr_b64 s[76:77], s[16:17], 24
+; VI-NEXT: .LBB109_3: ; %end
+; VI-NEXT: s_and_b32 s5, s16, 0xff
+; VI-NEXT: s_lshl_b32 s16, s83, 8
+; VI-NEXT: s_or_b32 s5, s5, s16
+; VI-NEXT: s_lshl_b32 s16, s76, 8
+; VI-NEXT: s_and_b32 s17, s82, 0xff
+; VI-NEXT: s_or_b32 s16, s17, s16
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s16, s16, 16
+; VI-NEXT: s_or_b32 s5, s5, s16
+; VI-NEXT: v_mov_b32_e32 v1, s5
+; VI-NEXT: s_and_b32 s5, s6, 0xff
+; VI-NEXT: s_lshl_b32 s6, s81, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s80, 0xff
+; VI-NEXT: s_lshl_b32 s16, s71, 8
+; VI-NEXT: s_or_b32 s6, s6, s16
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: s_and_b32 s5, s18, 0xff
+; VI-NEXT: s_lshl_b32 s6, s70, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s69, 0xff
+; VI-NEXT: s_lshl_b32 s16, s74, 8
+; VI-NEXT: s_or_b32 s6, s6, s16
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
+; VI-NEXT: v_add_u32_e32 v1, vcc, 4, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: s_and_b32 s5, s8, 0xff
+; VI-NEXT: s_lshl_b32 s6, s68, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s67, 0xff
+; VI-NEXT: s_lshl_b32 s8, s66, 8
+; VI-NEXT: s_or_b32 s6, s6, s8
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 8, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: s_and_b32 s5, s20, 0xff
+; VI-NEXT: s_lshl_b32 s6, s65, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s64, 0xff
+; VI-NEXT: s_lshl_b32 s8, s72, 8
+; VI-NEXT: s_or_b32 s6, s6, s8
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 12, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: s_and_b32 s5, s10, 0xff
+; VI-NEXT: s_lshl_b32 s6, s55, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s54, 0xff
+; VI-NEXT: s_lshl_b32 s8, s53, 8
+; VI-NEXT: s_or_b32 s6, s6, s8
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 16, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: s_and_b32 s5, s22, 0xff
+; VI-NEXT: s_lshl_b32 s6, s52, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s51, 0xff
+; VI-NEXT: s_lshl_b32 s8, s62, 8
+; VI-NEXT: s_or_b32 s6, s6, s8
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 20, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: s_and_b32 s5, s12, 0xff
+; VI-NEXT: s_lshl_b32 s6, s50, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s49, 0xff
+; VI-NEXT: s_lshl_b32 s8, s48, 8
+; VI-NEXT: s_or_b32 s6, s6, s8
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 24, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: s_and_b32 s5, s24, 0xff
+; VI-NEXT: s_lshl_b32 s6, s39, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s38, 0xff
+; VI-NEXT: s_lshl_b32 s8, s60, 8
+; VI-NEXT: s_or_b32 s6, s6, s8
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 28, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: s_and_b32 s5, s14, 0xff
+; VI-NEXT: s_lshl_b32 s6, s37, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s36, 0xff
+; VI-NEXT: s_lshl_b32 s8, s35, 8
+; VI-NEXT: s_or_b32 s6, s6, s8
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 32, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: s_and_b32 s5, s26, 0xff
+; VI-NEXT: s_lshl_b32 s6, s34, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s31, 0xff
+; VI-NEXT: s_lshl_b32 s8, s58, 8
+; VI-NEXT: s_or_b32 s6, s6, s8
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 36, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: s_and_b32 s5, s40, 0xff
+; VI-NEXT: s_lshl_b32 s6, s30, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s91, 0xff
+; VI-NEXT: s_lshl_b32 s8, s90, 8
+; VI-NEXT: s_or_b32 s6, s6, s8
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 40, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: s_and_b32 s5, s28, 0xff
+; VI-NEXT: s_lshl_b32 s6, s89, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s88, 0xff
+; VI-NEXT: s_lshl_b32 s8, s44, 8
+; VI-NEXT: s_or_b32 s6, s6, s8
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 44, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: s_and_b32 s5, s46, 0xff
+; VI-NEXT: s_lshl_b32 s6, s57, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s6, s47, 0xff
+; VI-NEXT: s_lshl_b32 s8, s41, 8
+; VI-NEXT: s_or_b32 s6, s6, s8
+; VI-NEXT: s_and_b32 s5, s5, 0xffff
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 48, v0
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: s_and_b32 s4, s4, 0xff
+; VI-NEXT: s_lshl_b32 s5, s15, 8
+; VI-NEXT: s_or_b32 s4, s4, s5
+; VI-NEXT: s_and_b32 s5, s13, 0xff
+; VI-NEXT: s_lshl_b32 s6, s42, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s4, s4, 0xffff
+; VI-NEXT: s_lshl_b32 s5, s5, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 52, v0
+; VI-NEXT: s_or_b32 s4, s4, s5
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v2, s4
+; VI-NEXT: s_and_b32 s4, s56, 0xff
+; VI-NEXT: s_lshl_b32 s5, s11, 8
+; VI-NEXT: s_or_b32 s4, s4, s5
+; VI-NEXT: s_and_b32 s5, s9, 0xff
+; VI-NEXT: s_lshl_b32 s6, s7, 8
+; VI-NEXT: s_or_b32 s5, s5, s6
+; VI-NEXT: s_and_b32 s4, s4, 0xffff
+; VI-NEXT: s_lshl_b32 s5, s5, 16
+; VI-NEXT: v_add_u32_e32 v1, vcc, 56, v0
+; VI-NEXT: s_or_b32 s4, s4, s5
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
+; VI-NEXT: v_mov_b32_e32 v1, s4
+; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
+; VI-NEXT: v_readlane_b32 s83, v4, 27
+; VI-NEXT: v_readlane_b32 s82, v4, 26
+; VI-NEXT: v_readlane_b32 s81, v4, 25
+; VI-NEXT: v_readlane_b32 s80, v4, 24
+; VI-NEXT: v_readlane_b32 s71, v4, 23
+; VI-NEXT: v_readlane_b32 s70, v4, 22
+; VI-NEXT: v_readlane_b32 s69, v4, 21
+; VI-NEXT: v_readlane_b32 s68, v4, 20
+; VI-NEXT: v_readlane_b32 s67, v4, 19
+; VI-NEXT: v_readlane_b32 s66, v4, 18
+; VI-NEXT: v_readlane_b32 s65, v4, 17
+; VI-NEXT: v_readlane_b32 s64, v4, 16
+; VI-NEXT: v_readlane_b32 s55, v4, 15
+; VI-NEXT: v_readlane_b32 s54, v4, 14
+; VI-NEXT: v_readlane_b32 s53, v4, 13
+; VI-NEXT: v_readlane_b32 s52, v4, 12
+; VI-NEXT: v_readlane_b32 s51, v4, 11
+; VI-NEXT: v_readlane_b32 s50, v4, 10
+; VI-NEXT: v_readlane_b32 s49, v4, 9
+; VI-NEXT: v_readlane_b32 s48, v4, 8
+; VI-NEXT: v_readlane_b32 s39, v4, 7
+; VI-NEXT: v_readlane_b32 s38, v4, 6
+; VI-NEXT: v_readlane_b32 s37, v4, 5
+; VI-NEXT: v_readlane_b32 s36, v4, 4
+; VI-NEXT: v_readlane_b32 s35, v4, 3
+; VI-NEXT: v_readlane_b32 s34, v4, 2
+; VI-NEXT: v_readlane_b32 s31, v4, 1
+; VI-NEXT: v_readlane_b32 s30, v4, 0
+; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
+; VI-NEXT: s_mov_b64 exec, s[4:5]
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB109_4:
+; VI-NEXT: ; implicit-def: $sgpr83
+; VI-NEXT: ; implicit-def: $sgpr82
+; VI-NEXT: ; implicit-def: $sgpr76
; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: ; implicit-def: $sgpr81
+; VI-NEXT: ; implicit-def: $sgpr80
+; VI-NEXT: ; implicit-def: $sgpr71
+; VI-NEXT: ; implicit-def: $sgpr70
+; VI-NEXT: ; implicit-def: $sgpr69
+; VI-NEXT: ; implicit-def: $sgpr74
+; VI-NEXT: ; implicit-def: $sgpr8
+; VI-NEXT: ; implicit-def: $sgpr68
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr65
; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr72
+; VI-NEXT: ; implicit-def: $sgpr10
; VI-NEXT: ; implicit-def: $sgpr55
; VI-NEXT: ; implicit-def: $sgpr54
-; VI-NEXT: ; implicit-def: $sgpr52
-; VI-NEXT: ; implicit-def: $sgpr8
; VI-NEXT: ; implicit-def: $sgpr53
+; VI-NEXT: ; implicit-def: $sgpr52
; VI-NEXT: ; implicit-def: $sgpr51
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr12
; VI-NEXT: ; implicit-def: $sgpr50
; VI-NEXT: ; implicit-def: $sgpr49
-; VI-NEXT: ; implicit-def: $sgpr39
-; VI-NEXT: ; implicit-def: $sgpr10
; VI-NEXT: ; implicit-def: $sgpr48
+; VI-NEXT: ; implicit-def: $sgpr39
; VI-NEXT: ; implicit-def: $sgpr38
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr14
; VI-NEXT: ; implicit-def: $sgpr37
; VI-NEXT: ; implicit-def: $sgpr36
-; VI-NEXT: ; implicit-def: $sgpr34
-; VI-NEXT: ; implicit-def: $sgpr12
; VI-NEXT: ; implicit-def: $sgpr35
+; VI-NEXT: ; implicit-def: $sgpr34
; VI-NEXT: ; implicit-def: $sgpr31
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr40
; VI-NEXT: ; implicit-def: $sgpr30
; VI-NEXT: ; implicit-def: $sgpr91
-; VI-NEXT: ; implicit-def: $sgpr89
-; VI-NEXT: ; implicit-def: $sgpr14
; VI-NEXT: ; implicit-def: $sgpr90
+; VI-NEXT: ; implicit-def: $sgpr89
; VI-NEXT: ; implicit-def: $sgpr88
-; VI-NEXT: ; implicit-def: $sgpr79
-; VI-NEXT: ; implicit-def: $sgpr78
-; VI-NEXT: ; implicit-def: $sgpr76
-; VI-NEXT: ; implicit-def: $sgpr40
-; VI-NEXT: ; implicit-def: $sgpr77
-; VI-NEXT: ; implicit-def: $sgpr75
-; VI-NEXT: ; implicit-def: $sgpr74
-; VI-NEXT: ; implicit-def: $sgpr73
-; VI-NEXT: ; implicit-def: $sgpr63
-; VI-NEXT: ; implicit-def: $sgpr42
-; VI-NEXT: ; implicit-def: $sgpr72
-; VI-NEXT: ; implicit-def: $sgpr62
-; VI-NEXT: ; implicit-def: $sgpr61
-; VI-NEXT: ; implicit-def: $sgpr60
-; VI-NEXT: ; implicit-def: $sgpr58
; VI-NEXT: ; implicit-def: $sgpr44
-; VI-NEXT: ; implicit-def: $sgpr59
+; VI-NEXT: ; implicit-def: $sgpr46
; VI-NEXT: ; implicit-def: $sgpr57
+; VI-NEXT: ; implicit-def: $sgpr47
+; VI-NEXT: ; implicit-def: $sgpr41
+; VI-NEXT: ; implicit-def: $sgpr15
+; VI-NEXT: ; implicit-def: $sgpr13
+; VI-NEXT: ; implicit-def: $sgpr42
; VI-NEXT: ; implicit-def: $sgpr56
+; VI-NEXT: ; implicit-def: $sgpr11
+; VI-NEXT: ; implicit-def: $sgpr9
+; VI-NEXT: ; implicit-def: $sgpr7
; VI-NEXT: s_branch .LBB109_2
-; VI-NEXT: .LBB109_4:
-; VI-NEXT: v_mov_b32_e32 v19, s44
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v19, s42
-; VI-NEXT: v_mov_b32_e32 v1, s16
-; VI-NEXT: v_mov_b32_e32 v2, s17
-; VI-NEXT: v_mov_b32_e32 v3, s18
-; VI-NEXT: v_mov_b32_e32 v4, s19
-; VI-NEXT: v_mov_b32_e32 v5, s20
-; VI-NEXT: v_mov_b32_e32 v6, s21
-; VI-NEXT: v_mov_b32_e32 v7, s22
-; VI-NEXT: v_mov_b32_e32 v8, s23
-; VI-NEXT: v_mov_b32_e32 v9, s24
-; VI-NEXT: v_mov_b32_e32 v10, s25
-; VI-NEXT: v_mov_b32_e32 v11, s26
-; VI-NEXT: v_mov_b32_e32 v12, s27
-; VI-NEXT: v_mov_b32_e32 v13, s28
-; VI-NEXT: v_mov_b32_e32 v14, s29
-; VI-NEXT: v_mov_b32_e32 v15, s4
-; VI-NEXT: v_mov_b32_e32 v16, s5
-; VI-NEXT: v_mov_b32_e32 v18, s67
-; VI-NEXT: v_mov_b32_e32 v62, s65
-; VI-NEXT: v_mov_b32_e32 v17, s66
-; VI-NEXT: v_mov_b32_e32 v60, s64
-; VI-NEXT: v_mov_b32_e32 v61, s55
-; VI-NEXT: v_mov_b32_e32 v58, s54
-; VI-NEXT: v_mov_b32_e32 v59, s52
-; VI-NEXT: v_mov_b32_e32 v57, s53
-; VI-NEXT: v_mov_b32_e32 v47, s51
-; VI-NEXT: v_mov_b32_e32 v56, s50
-; VI-NEXT: v_mov_b32_e32 v46, s49
-; VI-NEXT: v_mov_b32_e32 v45, s39
-; VI-NEXT: v_mov_b32_e32 v44, s48
-; VI-NEXT: v_mov_b32_e32 v42, s38
-; VI-NEXT: v_mov_b32_e32 v43, s37
-; VI-NEXT: v_mov_b32_e32 v41, s36
-; VI-NEXT: v_mov_b32_e32 v40, s34
-; VI-NEXT: v_mov_b32_e32 v55, s35
-; VI-NEXT: v_mov_b32_e32 v53, s31
-; VI-NEXT: v_mov_b32_e32 v54, s30
-; VI-NEXT: v_mov_b32_e32 v52, s91
-; VI-NEXT: v_mov_b32_e32 v51, s89
-; VI-NEXT: v_mov_b32_e32 v50, s90
-; VI-NEXT: v_mov_b32_e32 v48, s88
-; VI-NEXT: v_mov_b32_e32 v49, s79
-; VI-NEXT: v_mov_b32_e32 v39, s78
-; VI-NEXT: v_mov_b32_e32 v38, s76
-; VI-NEXT: v_mov_b32_e32 v37, s77
-; VI-NEXT: v_mov_b32_e32 v35, s75
-; VI-NEXT: v_mov_b32_e32 v36, s74
-; VI-NEXT: v_mov_b32_e32 v34, s73
-; VI-NEXT: v_mov_b32_e32 v33, s63
-; VI-NEXT: v_mov_b32_e32 v32, s72
-; VI-NEXT: v_mov_b32_e32 v30, s62
-; VI-NEXT: v_mov_b32_e32 v31, s61
-; VI-NEXT: v_mov_b32_e32 v29, s60
-; VI-NEXT: v_mov_b32_e32 v28, s58
-; VI-NEXT: v_mov_b32_e32 v27, s59
-; VI-NEXT: v_mov_b32_e32 v25, s57
-; VI-NEXT: v_mov_b32_e32 v26, s56
-; VI-NEXT: v_mov_b32_e32 v21, s12
-; VI-NEXT: v_mov_b32_e32 v22, s10
-; VI-NEXT: v_mov_b32_e32 v23, s8
-; VI-NEXT: v_mov_b32_e32 v24, s6
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v19, s40
-; VI-NEXT: v_mov_b32_e32 v20, s14
-; VI-NEXT: .LBB109_5: ; %end
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; VI-NEXT: v_or_b32_sdwa v2, v2, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v24
-; VI-NEXT: v_or_b32_sdwa v1, v1, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v17, v62, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v61
-; VI-NEXT: v_or_b32_sdwa v1, v60, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v23
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v58
-; VI-NEXT: v_or_b32_sdwa v1, v59, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v57
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v56
-; VI-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v47, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v46
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v22
-; VI-NEXT: v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v45, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v44
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v43
-; VI-NEXT: v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v42, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v41
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v21
-; VI-NEXT: v_or_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v40, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v55
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v54
-; VI-NEXT: v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v53, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v52
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v20
-; VI-NEXT: v_or_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v51, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v50
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v49
-; VI-NEXT: v_or_b32_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v48, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v39
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v19
-; VI-NEXT: v_or_b32_sdwa v1, v11, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v38, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v37
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v36
-; VI-NEXT: v_or_b32_sdwa v1, v12, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v35, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v34
-; VI-NEXT: v_or_b32_sdwa v1, v13, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_readlane_b32 s67, v63, 19
-; VI-NEXT: v_readlane_b32 s66, v63, 18
-; VI-NEXT: v_readlane_b32 s65, v63, 17
-; VI-NEXT: v_readlane_b32 s64, v63, 16
-; VI-NEXT: v_readlane_b32 s55, v63, 15
-; VI-NEXT: v_readlane_b32 s54, v63, 14
-; VI-NEXT: v_readlane_b32 s53, v63, 13
-; VI-NEXT: v_readlane_b32 s52, v63, 12
-; VI-NEXT: v_readlane_b32 s51, v63, 11
-; VI-NEXT: v_readlane_b32 s50, v63, 10
-; VI-NEXT: v_readlane_b32 s49, v63, 9
-; VI-NEXT: v_readlane_b32 s48, v63, 8
-; VI-NEXT: v_readlane_b32 s39, v63, 7
-; VI-NEXT: v_readlane_b32 s38, v63, 6
-; VI-NEXT: v_readlane_b32 s37, v63, 5
-; VI-NEXT: v_readlane_b32 s36, v63, 4
-; VI-NEXT: v_readlane_b32 s35, v63, 3
-; VI-NEXT: v_readlane_b32 s34, v63, 2
-; VI-NEXT: v_readlane_b32 s31, v63, 1
-; VI-NEXT: v_readlane_b32 s30, v63, 0
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; VI-NEXT: v_or_b32_sdwa v2, v33, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v32
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v31
-; VI-NEXT: v_or_b32_sdwa v1, v14, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v30, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v29
-; VI-NEXT: v_or_b32_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; VI-NEXT: v_or_b32_sdwa v2, v28, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
-; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v27
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v26
-; VI-NEXT: v_or_b32_sdwa v1, v16, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v25, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
-; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v32bf16_to_v64i8_scalar:
; GFX9: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
index 14e17ce49cca0..1dcc010349123 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
@@ -2272,30 +2272,32 @@ define inreg i64 @bitcast_v4bf16_to_i64_scalar(<4 x bfloat> inreg %a, i32 inreg
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s20, 0
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v7, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
; SI-NEXT: s_cbranch_scc0 .LBB23_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_alignbit_b32 v0, v0, v5, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v3, 16
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v7
+; SI-NEXT: v_lshr_b64 v[8:9], v[2:3], 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[4:5], 16
+; SI-NEXT: v_mov_b32_e32 v1, v8
; SI-NEXT: s_cbranch_execnz .LBB23_3
; SI-NEXT: .LBB23_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_mov_b32_e32 v1, v2
; SI-NEXT: .LBB23_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB23_4:
@@ -2311,42 +2313,43 @@ define inreg i64 @bitcast_v4bf16_to_i64_scalar(<4 x bfloat> inreg %a, i32 inreg
; VI-NEXT: s_cbranch_execnz .LBB23_4
; VI-NEXT: .LBB23_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v4, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v4
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v4
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v4
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v4
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v2
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB23_3:
; VI-NEXT: s_branch .LBB23_2
@@ -5460,30 +5463,32 @@ define inreg double @bitcast_v4bf16_to_f64_scalar(<4 x bfloat> inreg %a, i32 inr
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s20, 0
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v7, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
; SI-NEXT: s_cbranch_scc0 .LBB47_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_alignbit_b32 v0, v0, v5, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v3, 16
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v7
+; SI-NEXT: v_lshr_b64 v[8:9], v[2:3], 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[4:5], 16
+; SI-NEXT: v_mov_b32_e32 v1, v8
; SI-NEXT: s_cbranch_execnz .LBB47_3
; SI-NEXT: .LBB47_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_mov_b32_e32 v1, v2
; SI-NEXT: .LBB47_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB47_4:
@@ -5499,42 +5504,43 @@ define inreg double @bitcast_v4bf16_to_f64_scalar(<4 x bfloat> inreg %a, i32 inr
; VI-NEXT: s_cbranch_execnz .LBB47_4
; VI-NEXT: .LBB47_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v4, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v4
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v4
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v4
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v4
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v2
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB47_3:
; VI-NEXT: s_branch .LBB47_2
@@ -8361,30 +8367,32 @@ define inreg <2 x i32> @bitcast_v4bf16_to_v2i32_scalar(<4 x bfloat> inreg %a, i3
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s20, 0
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v7, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
; SI-NEXT: s_cbranch_scc0 .LBB67_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_alignbit_b32 v0, v0, v5, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v3, 16
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v7
+; SI-NEXT: v_lshr_b64 v[8:9], v[2:3], 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[4:5], 16
+; SI-NEXT: v_mov_b32_e32 v1, v8
; SI-NEXT: s_cbranch_execnz .LBB67_3
; SI-NEXT: .LBB67_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_mov_b32_e32 v1, v2
; SI-NEXT: .LBB67_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB67_4:
@@ -8400,42 +8408,43 @@ define inreg <2 x i32> @bitcast_v4bf16_to_v2i32_scalar(<4 x bfloat> inreg %a, i3
; VI-NEXT: s_cbranch_execnz .LBB67_4
; VI-NEXT: .LBB67_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v4, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v4
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v4
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v4
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v4
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v2
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB67_3:
; VI-NEXT: s_branch .LBB67_2
@@ -10937,30 +10946,32 @@ define inreg <2 x float> @bitcast_v4bf16_to_v2f32_scalar(<4 x bfloat> inreg %a,
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s20, 0
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v7, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
; SI-NEXT: s_cbranch_scc0 .LBB83_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_alignbit_b32 v0, v0, v5, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v3, 16
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v7
+; SI-NEXT: v_lshr_b64 v[8:9], v[2:3], 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[4:5], 16
+; SI-NEXT: v_mov_b32_e32 v1, v8
; SI-NEXT: s_cbranch_execnz .LBB83_3
; SI-NEXT: .LBB83_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_mov_b32_e32 v1, v2
; SI-NEXT: .LBB83_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB83_4:
@@ -10976,42 +10987,43 @@ define inreg <2 x float> @bitcast_v4bf16_to_v2f32_scalar(<4 x bfloat> inreg %a,
; VI-NEXT: s_cbranch_execnz .LBB83_4
; VI-NEXT: .LBB83_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v4, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v4
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v4
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v4
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v4
+; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v2
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB83_3:
; VI-NEXT: s_branch .LBB83_2
@@ -13151,37 +13163,38 @@ define inreg <4 x i16> @bitcast_v4bf16_to_v4i16_scalar(<4 x bfloat> inreg %a, i3
; SI-NEXT: s_cmp_lg_u32 s20, 0
; SI-NEXT: v_mul_f32_e64 v7, 1.0, s16
; SI-NEXT: v_mul_f32_e64 v6, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v5, 1.0, s19
; SI-NEXT: s_cbranch_scc0 .LBB95_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v5
; SI-NEXT: s_cbranch_execnz .LBB95_3
; SI-NEXT: .LBB95_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v6
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v7
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; SI-NEXT: v_lshr_b64 v[4:5], v[1:2], 16
-; SI-NEXT: v_alignbit_b32 v0, v6, v0, 16
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v6
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; SI-NEXT: v_lshr_b64 v[4:5], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
+; SI-NEXT: v_mov_b32_e32 v2, v4
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: .LBB95_3: ; %end
-; SI-NEXT: v_mov_b32_e32 v1, v4
+; SI-NEXT: v_mov_b32_e32 v2, v4
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB95_4:
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: s_branch .LBB95_2
;
@@ -13194,42 +13207,43 @@ define inreg <4 x i16> @bitcast_v4bf16_to_v4i16_scalar(<4 x bfloat> inreg %a, i3
; VI-NEXT: s_cbranch_execnz .LBB95_4
; VI-NEXT: .LBB95_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v3, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v3
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v3
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
+; VI-NEXT: v_add_f32_e32 v2, s4, v3
+; VI-NEXT: v_bfe_u32 v4, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
-; VI-NEXT: v_bfe_u32 v4, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v0
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_add_f32_e32 v3, s4, v3
+; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
+; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v1, v0, v1, 16
-; VI-NEXT: v_alignbit_b32 v0, v3, v2, 16
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3]
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v2
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB95_3:
; VI-NEXT: s_branch .LBB95_2
@@ -15062,42 +15076,43 @@ define inreg <4 x half> @bitcast_v4bf16_to_v4f16_scalar(<4 x bfloat> inreg %a, i
; VI-NEXT: s_cbranch_execnz .LBB103_4
; VI-NEXT: .LBB103_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v3, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v3
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v3
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
+; VI-NEXT: v_add_f32_e32 v2, s4, v3
+; VI-NEXT: v_bfe_u32 v4, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
-; VI-NEXT: v_bfe_u32 v4, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v0
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_add_f32_e32 v3, s4, v3
+; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
+; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v1, v0, v1, 16
-; VI-NEXT: v_alignbit_b32 v0, v3, v2, 16
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3]
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v2
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB103_3:
; VI-NEXT: s_branch .LBB103_2
@@ -16737,52 +16752,54 @@ define inreg <8 x i8> @bitcast_v4bf16_to_v8i8_scalar(<4 x bfloat> inreg %a, i32
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s20, 0
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v15, 1.0, s17
; SI-NEXT: v_mul_f32_e64 v12, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v0, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v5, 1.0, s18
; SI-NEXT: s_cbranch_scc0 .LBB109_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; SI-NEXT: v_alignbit_b32 v9, v1, v12, 16
-; SI-NEXT: v_alignbit_b32 v10, v6, v8, 16
-; SI-NEXT: v_lshr_b64 v[3:4], v[9:10], 24
-; SI-NEXT: v_lshr_b64 v[4:5], v[9:10], 16
-; SI-NEXT: v_lshr_b64 v[1:2], v[9:10], 8
-; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v0
-; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v10
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v15
+; SI-NEXT: v_lshr_b64 v[10:11], v[5:6], 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[12:13], 16
+; SI-NEXT: v_mov_b32_e32 v1, v10
+; SI-NEXT: v_lshr_b64 v[8:9], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[3:4], v[0:1], 24
+; SI-NEXT: v_lshr_b64 v[1:2], v[0:1], 8
+; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v14
+; SI-NEXT: v_lshrrev_b32_e32 v9, 8, v10
; SI-NEXT: s_cbranch_execnz .LBB109_3
; SI-NEXT: .LBB109_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v11
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v12
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v12
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; SI-NEXT: v_alignbit_b32 v9, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v7
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; SI-NEXT: v_alignbit_b32 v10, v6, v1, 16
-; SI-NEXT: v_lshr_b64 v[3:4], v[9:10], 24
-; SI-NEXT: v_lshr_b64 v[4:5], v[9:10], 16
-; SI-NEXT: v_lshr_b64 v[1:2], v[9:10], 8
-; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v10
-; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshr_b64 v[10:11], v[5:6], 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_mov_b32_e32 v1, v10
+; SI-NEXT: v_lshr_b64 v[3:4], v[0:1], 24
+; SI-NEXT: v_lshr_b64 v[8:9], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[0:1], 8
+; SI-NEXT: v_lshrrev_b32_e32 v9, 8, v10
+; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v7
; SI-NEXT: .LBB109_3: ; %end
-; SI-NEXT: v_mov_b32_e32 v0, v9
-; SI-NEXT: v_mov_b32_e32 v2, v4
+; SI-NEXT: v_mov_b32_e32 v2, v8
; SI-NEXT: v_mov_b32_e32 v4, v10
+; SI-NEXT: v_mov_b32_e32 v5, v9
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB109_4:
-; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: s_branch .LBB109_2
;
@@ -16793,11 +16810,11 @@ define inreg <8 x i8> @bitcast_v4bf16_to_v8i8_scalar(<4 x bfloat> inreg %a, i32
; VI-NEXT: s_cbranch_scc0 .LBB109_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b64 s[4:5], s[16:17], 24
-; VI-NEXT: s_lshr_b32 s8, s17, 24
-; VI-NEXT: s_lshr_b32 s5, s17, 16
-; VI-NEXT: s_lshr_b32 s10, s17, 8
-; VI-NEXT: s_lshr_b32 s9, s16, 16
-; VI-NEXT: s_lshr_b32 s11, s16, 8
+; VI-NEXT: s_lshr_b32 s5, s17, 24
+; VI-NEXT: s_lshr_b32 s11, s17, 16
+; VI-NEXT: s_lshr_b32 s8, s17, 8
+; VI-NEXT: s_lshr_b32 s10, s16, 16
+; VI-NEXT: s_lshr_b32 s9, s16, 8
; VI-NEXT: s_cbranch_execnz .LBB109_4
; VI-NEXT: .LBB109_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s17, 16
@@ -16810,58 +16827,59 @@ define inreg <8 x i8> @bitcast_v4bf16_to_v8i8_scalar(<4 x bfloat> inreg %a, i32
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v3, v2, v3, vcc
+; VI-NEXT: v_cndmask_b32_e32 v5, v2, v3, vcc
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
-; VI-NEXT: s_lshl_b32 s4, s16, 16
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1
+; VI-NEXT: v_lshrrev_b64 v[1:2], 16, v[5:6]
+; VI-NEXT: s_lshl_b32 s4, s16, 16
+; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
-; VI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
-; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v2, v6, v3, 16
-; VI-NEXT: v_alignbit_b32 v1, v0, v4, 16
-; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[1:2]
-; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v2
-; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v2
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; VI-NEXT: v_lshrrev_b64 v[9:10], 16, v[2:3]
+; VI-NEXT: v_mov_b32_e32 v10, v1
+; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v5
+; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[9:10]
+; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v9
+; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v9
; VI-NEXT: v_mov_b32_e32 v4, v8
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB109_3:
-; VI-NEXT: ; implicit-def: $sgpr11
; VI-NEXT: ; implicit-def: $sgpr9
-; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: ; implicit-def: $sgpr10
-; VI-NEXT: ; implicit-def: $sgpr5
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: ; implicit-def: $sgpr8
+; VI-NEXT: ; implicit-def: $sgpr11
+; VI-NEXT: ; implicit-def: $sgpr5
; VI-NEXT: s_branch .LBB109_2
; VI-NEXT: .LBB109_4:
-; VI-NEXT: v_mov_b32_e32 v1, s11
-; VI-NEXT: v_mov_b32_e32 v2, s9
-; VI-NEXT: v_mov_b32_e32 v5, s10
-; VI-NEXT: v_mov_b32_e32 v7, s8
-; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_mov_b32_e32 v0, s16
-; VI-NEXT: v_mov_b32_e32 v6, s5
+; VI-NEXT: v_mov_b32_e32 v6, s11
+; VI-NEXT: v_mov_b32_e32 v2, s10
+; VI-NEXT: v_mov_b32_e32 v1, s9
+; VI-NEXT: v_mov_b32_e32 v7, s5
+; VI-NEXT: v_mov_b32_e32 v5, s8
+; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_mov_b32_e32 v4, s17
; VI-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
index 6ada0cb8c46f1..4abb70e0ec5c9 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
@@ -2214,40 +2214,42 @@ define inreg <3 x i32> @bitcast_v6bf16_to_v3i32_scalar(<6 x bfloat> inreg %a, i3
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s22, 0
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v11, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v7, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v5, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v9, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v3, 1.0, s20
; SI-NEXT: s_cbranch_scc0 .LBB11_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; SI-NEXT: v_alignbit_b32 v0, v0, v8, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v6, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v4, 16
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v9
+; SI-NEXT: v_lshr_b64 v[0:1], v[7:8], 16
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
+; SI-NEXT: v_lshr_b64 v[12:13], v[3:4], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[5:6], 16
+; SI-NEXT: v_mov_b32_e32 v2, v12
; SI-NEXT: s_cbranch_execnz .LBB11_3
; SI-NEXT: .LBB11_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v7
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v8
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v5
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v9
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v10
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_mov_b32_e32 v2, v3
; SI-NEXT: .LBB11_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB11_4:
@@ -2263,60 +2265,61 @@ define inreg <3 x i32> @bitcast_v6bf16_to_v3i32_scalar(<6 x bfloat> inreg %a, i3
; VI-NEXT: s_cbranch_execnz .LBB11_4
; VI-NEXT: .LBB11_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v5, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v5
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v5
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v5
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v5
; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v3, v1, 16
-; VI-NEXT: v_add_f32_e32 v3, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_lshrrev_b64 v[3:4], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v5
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_bfe_u32 v4, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v5
+; VI-NEXT: v_bfe_u32 v4, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v3, 16
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v3
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB11_3:
; VI-NEXT: s_branch .LBB11_2
@@ -5430,40 +5433,42 @@ define inreg <3 x float> @bitcast_v6bf16_to_v3f32_scalar(<6 x bfloat> inreg %a,
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s22, 0
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v11, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v7, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v5, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v9, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v3, 1.0, s20
; SI-NEXT: s_cbranch_scc0 .LBB27_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; SI-NEXT: v_alignbit_b32 v0, v0, v8, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v6, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v4, 16
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v9
+; SI-NEXT: v_lshr_b64 v[0:1], v[7:8], 16
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
+; SI-NEXT: v_lshr_b64 v[12:13], v[3:4], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[5:6], 16
+; SI-NEXT: v_mov_b32_e32 v2, v12
; SI-NEXT: s_cbranch_execnz .LBB27_3
; SI-NEXT: .LBB27_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v7
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v8
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v5
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v9
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v10
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
+; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; SI-NEXT: v_mov_b32_e32 v2, v3
; SI-NEXT: .LBB27_3: ; %end
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB27_4:
@@ -5479,60 +5484,61 @@ define inreg <3 x float> @bitcast_v6bf16_to_v3f32_scalar(<6 x bfloat> inreg %a,
; VI-NEXT: s_cbranch_execnz .LBB27_4
; VI-NEXT: .LBB27_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v5, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v5
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v5
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v5
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v5
; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; VI-NEXT: v_add_f32_e32 v3, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v1, v3, v1, 16
-; VI-NEXT: v_add_f32_e32 v3, s4, v0
-; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
+; VI-NEXT: v_lshrrev_b64 v[3:4], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v5
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; VI-NEXT: v_bfe_u32 v4, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v5
+; VI-NEXT: v_bfe_u32 v4, v1, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v0, v3, 16
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v3
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB27_3:
; VI-NEXT: s_branch .LBB27_2
@@ -8098,70 +8104,73 @@ define inreg <12 x i8> @bitcast_v6bf16_to_v12i8_scalar(<6 x bfloat> inreg %a, i3
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s22, 0
-; SI-NEXT: v_mul_f32_e64 v17, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v18, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v15, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v16, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v0, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v14, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v21, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v17, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v20, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v5, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v19, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v9, 1.0, s20
; SI-NEXT: s_cbranch_scc0 .LBB39_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v15
-; SI-NEXT: v_alignbit_b32 v12, v1, v18, 16
-; SI-NEXT: v_alignbit_b32 v13, v6, v16, 16
-; SI-NEXT: v_lshr_b64 v[3:4], v[12:13], 24
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; SI-NEXT: v_lshr_b64 v[4:5], v[12:13], 16
-; SI-NEXT: v_alignbit_b32 v8, v10, v14, 16
-; SI-NEXT: v_lshr_b64 v[1:2], v[12:13], 8
-; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v15
-; SI-NEXT: v_lshrrev_b32_e32 v11, 24, v0
-; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v13
-; SI-NEXT: v_lshrrev_b32_e32 v9, 8, v8
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v21
+; SI-NEXT: v_lshr_b64 v[14:15], v[5:6], 16
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v19
+; SI-NEXT: v_lshr_b64 v[0:1], v[17:18], 16
+; SI-NEXT: v_lshr_b64 v[15:16], v[9:10], 16
+; SI-NEXT: v_mov_b32_e32 v1, v14
+; SI-NEXT: v_lshr_b64 v[3:4], v[0:1], 24
+; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v20
+; SI-NEXT: v_lshrrev_b32_e32 v11, 24, v19
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v14
+; SI-NEXT: v_lshrrev_b32_e32 v16, 8, v15
+; SI-NEXT: v_lshr_b64 v[12:13], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[0:1], 8
; SI-NEXT: s_cbranch_execnz .LBB39_3
; SI-NEXT: .LBB39_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v17
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_alignbit_b32 v12, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v15
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v20
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v9
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v17
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v7
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; SI-NEXT: v_alignbit_b32 v13, v6, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v14
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v19
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; SI-NEXT: v_lshr_b64 v[3:4], v[12:13], 24
-; SI-NEXT: v_alignbit_b32 v8, v10, v1, 16
-; SI-NEXT: v_lshr_b64 v[4:5], v[12:13], 16
-; SI-NEXT: v_lshr_b64 v[1:2], v[12:13], 8
-; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v13
-; SI-NEXT: v_lshrrev_b32_e32 v9, 8, v8
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshr_b64 v[14:15], v[5:6], 16
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v2
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; SI-NEXT: v_mov_b32_e32 v1, v14
+; SI-NEXT: v_lshr_b64 v[15:16], v[9:10], 16
+; SI-NEXT: v_lshr_b64 v[3:4], v[0:1], 24
+; SI-NEXT: v_lshr_b64 v[12:13], v[0:1], 16
+; SI-NEXT: v_lshr_b64 v[1:2], v[0:1], 8
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v14
+; SI-NEXT: v_lshrrev_b32_e32 v16, 8, v15
; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; SI-NEXT: v_lshrrev_b32_e32 v11, 24, v0
+; SI-NEXT: v_lshrrev_b32_e32 v11, 24, v5
; SI-NEXT: .LBB39_3: ; %end
-; SI-NEXT: v_mov_b32_e32 v0, v12
-; SI-NEXT: v_mov_b32_e32 v2, v4
-; SI-NEXT: v_mov_b32_e32 v4, v13
+; SI-NEXT: v_mov_b32_e32 v2, v12
+; SI-NEXT: v_mov_b32_e32 v4, v14
+; SI-NEXT: v_mov_b32_e32 v5, v8
+; SI-NEXT: v_mov_b32_e32 v8, v15
+; SI-NEXT: v_mov_b32_e32 v9, v16
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB39_4:
-; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: s_branch .LBB39_2
;
@@ -8171,110 +8180,110 @@ define inreg <12 x i8> @bitcast_v6bf16_to_v12i8_scalar(<6 x bfloat> inreg %a, i3
; VI-NEXT: s_cmp_lg_u32 s19, 0
; VI-NEXT: s_cbranch_scc0 .LBB39_3
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: s_lshr_b32 s19, s16, 8
-; VI-NEXT: s_lshr_b32 s10, s18, 16
-; VI-NEXT: s_lshr_b32 s11, s18, 8
+; VI-NEXT: s_lshr_b32 s19, s18, 16
+; VI-NEXT: s_lshr_b32 s15, s18, 8
; VI-NEXT: s_lshr_b32 s12, s17, 24
-; VI-NEXT: s_lshr_b32 s13, s17, 16
-; VI-NEXT: s_lshr_b32 s15, s17, 8
+; VI-NEXT: s_lshr_b32 s11, s17, 16
+; VI-NEXT: s_lshr_b32 s10, s17, 8
; VI-NEXT: s_lshr_b32 s14, s16, 16
+; VI-NEXT: s_lshr_b32 s13, s16, 8
; VI-NEXT: s_lshr_b64 s[6:7], s[18:19], 24
; VI-NEXT: s_lshr_b64 s[4:5], s[16:17], 24
; VI-NEXT: s_cbranch_execnz .LBB39_4
; VI-NEXT: .LBB39_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_mov_b32_e32 v3, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v3
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v3
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_alignbit_b32 v15, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
+; VI-NEXT: v_add_f32_e32 v0, s4, v3
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v3
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
-; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: s_lshl_b32 s4, s18, 16
-; VI-NEXT: v_alignbit_b32 v14, v2, v1, 16
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
+; VI-NEXT: v_add_f32_e32 v2, s4, v3
+; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v8, v0, v1, 16
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_add_f32_e32 v3, s4, v3
+; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[2:3]
+; VI-NEXT: v_mov_b32_e32 v1, v4
; VI-NEXT: v_mov_b32_e32 v9, 0x7fc07fc0
-; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[14:15]
+; VI-NEXT: v_lshrrev_b64 v[14:15], 24, v[0:1]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9]
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v8
-; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v15
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v15
-; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v15
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v14
-; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v14
+; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v4
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v4
+; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; VI-NEXT: s_branch .LBB39_5
; VI-NEXT: .LBB39_3:
-; VI-NEXT: ; implicit-def: $sgpr19
+; VI-NEXT: ; implicit-def: $sgpr13
; VI-NEXT: ; implicit-def: $sgpr14
; VI-NEXT: ; implicit-def: $sgpr4
-; VI-NEXT: ; implicit-def: $sgpr15
-; VI-NEXT: ; implicit-def: $sgpr13
-; VI-NEXT: ; implicit-def: $sgpr12
-; VI-NEXT: ; implicit-def: $sgpr11
; VI-NEXT: ; implicit-def: $sgpr10
+; VI-NEXT: ; implicit-def: $sgpr11
+; VI-NEXT: ; implicit-def: $sgpr12
+; VI-NEXT: ; implicit-def: $sgpr15
+; VI-NEXT: ; implicit-def: $sgpr19
; VI-NEXT: ; implicit-def: $sgpr6
; VI-NEXT: s_branch .LBB39_2
; VI-NEXT: .LBB39_4:
-; VI-NEXT: v_mov_b32_e32 v14, s16
-; VI-NEXT: v_mov_b32_e32 v15, s17
; VI-NEXT: v_mov_b32_e32 v8, s18
-; VI-NEXT: v_mov_b32_e32 v1, s19
+; VI-NEXT: v_mov_b32_e32 v0, s16
+; VI-NEXT: v_mov_b32_e32 v4, s17
+; VI-NEXT: v_mov_b32_e32 v10, s19
+; VI-NEXT: v_mov_b32_e32 v13, s15
; VI-NEXT: v_mov_b32_e32 v2, s14
-; VI-NEXT: v_mov_b32_e32 v5, s15
-; VI-NEXT: v_mov_b32_e32 v6, s13
+; VI-NEXT: v_mov_b32_e32 v1, s13
; VI-NEXT: v_mov_b32_e32 v7, s12
-; VI-NEXT: v_mov_b32_e32 v13, s11
-; VI-NEXT: v_mov_b32_e32 v10, s10
+; VI-NEXT: v_mov_b32_e32 v6, s11
+; VI-NEXT: v_mov_b32_e32 v5, s10
; VI-NEXT: v_mov_b32_e32 v11, s6
-; VI-NEXT: v_mov_b32_e32 v3, s4
+; VI-NEXT: v_mov_b32_e32 v14, s4
; VI-NEXT: .LBB39_5: ; %end
-; VI-NEXT: v_mov_b32_e32 v0, v14
-; VI-NEXT: v_mov_b32_e32 v4, v15
+; VI-NEXT: v_mov_b32_e32 v3, v14
; VI-NEXT: v_mov_b32_e32 v9, v13
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -11854,33 +11863,32 @@ define inreg <6 x half> @bitcast_v6bf16_to_v6f16_scalar(<6 x bfloat> inreg %a, i
; VI-NEXT: s_cbranch_execnz .LBB49_4
; VI-NEXT: .LBB49_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: v_mov_b32_e32 v3, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v3
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v3, v2, v3, vcc
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v3
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
+; VI-NEXT: v_add_f32_e32 v2, s4, v3
+; VI-NEXT: v_bfe_u32 v4, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v3
+; VI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
@@ -11889,25 +11897,27 @@ define inreg <6 x half> @bitcast_v6bf16_to_v6f16_scalar(<6 x bfloat> inreg %a, i
; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
; VI-NEXT: s_lshl_b32 s4, s18, 16
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v3
; VI-NEXT: v_bfe_u32 v6, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v2
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
+; VI-NEXT: v_add_f32_e32 v3, s4, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc
-; VI-NEXT: v_bfe_u32 v6, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v0
+; VI-NEXT: v_bfe_u32 v6, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v3
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
-; VI-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v2, v0, v2, 16
-; VI-NEXT: v_alignbit_b32 v1, v5, v1, 16
-; VI-NEXT: v_alignbit_b32 v0, v4, v3, 16
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[3:4], 16, v[4:5]
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v3
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB49_3:
; VI-NEXT: s_branch .LBB49_2
@@ -12814,49 +12824,51 @@ define inreg <6 x i16> @bitcast_v6bf16_to_v6i16_scalar(<6 x bfloat> inreg %a, i3
; SI-NEXT: s_cmp_lg_u32 s22, 0
; SI-NEXT: v_mul_f32_e64 v11, 1.0, s16
; SI-NEXT: v_mul_f32_e64 v10, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v8, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v9, 1.0, s21
; SI-NEXT: s_cbranch_scc0 .LBB53_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v9
; SI-NEXT: s_cbranch_execnz .LBB53_3
; SI-NEXT: .LBB53_2: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v10
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v2
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v9
-; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v8
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v10
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v9
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_lshr_b64 v[6:7], v[4:5], 16
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: v_lshr_b64 v[6:7], v[1:2], 16
-; SI-NEXT: v_alignbit_b32 v4, v5, v9, 16
+; SI-NEXT: v_lshr_b64 v[7:8], v[2:3], 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
+; SI-NEXT: v_mov_b32_e32 v2, v7
+; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; SI-NEXT: .LBB53_3: ; %end
-; SI-NEXT: v_mov_b32_e32 v1, v6
+; SI-NEXT: v_mov_b32_e32 v2, v7
+; SI-NEXT: v_mov_b32_e32 v4, v6
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB53_4:
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_branch .LBB53_2
;
@@ -12869,33 +12881,32 @@ define inreg <6 x i16> @bitcast_v6bf16_to_v6i16_scalar(<6 x bfloat> inreg %a, i3
; VI-NEXT: s_cbranch_execnz .LBB53_4
; VI-NEXT: .LBB53_2: ; %cmp.true
; VI-NEXT: s_lshl_b32 s4, s16, 16
-; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
+; VI-NEXT: v_mov_b32_e32 v3, 0x40c00000
+; VI-NEXT: v_add_f32_e32 v0, s4, v3
+; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
-; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v3, v2, v3, vcc
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v1, s4, v3
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
; VI-NEXT: s_lshl_b32 s4, s17, 16
-; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; VI-NEXT: v_add_f32_e32 v1, s4, v0
-; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
+; VI-NEXT: v_add_f32_e32 v2, s4, v3
+; VI-NEXT: v_bfe_u32 v4, v2, 16, 1
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; VI-NEXT: v_add_f32_e32 v2, s4, v3
+; VI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
@@ -12904,25 +12915,27 @@ define inreg <6 x i16> @bitcast_v6bf16_to_v6i16_scalar(<6 x bfloat> inreg %a, i3
; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
; VI-NEXT: s_lshl_b32 s4, s18, 16
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; VI-NEXT: v_add_f32_e32 v2, s4, v0
+; VI-NEXT: v_add_f32_e32 v2, s4, v3
; VI-NEXT: v_bfe_u32 v6, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v2
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; VI-NEXT: v_add_f32_e32 v0, s4, v0
+; VI-NEXT: v_add_f32_e32 v3, s4, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc
-; VI-NEXT: v_bfe_u32 v6, v0, 16, 1
-; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v0
+; VI-NEXT: v_bfe_u32 v6, v3, 16, 1
+; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v3
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
-; VI-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_alignbit_b32 v2, v0, v2, 16
-; VI-NEXT: v_alignbit_b32 v1, v5, v1, 16
-; VI-NEXT: v_alignbit_b32 v0, v4, v3, 16
+; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; VI-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshrrev_b64 v[3:4], 16, v[4:5]
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, v3
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB53_3:
; VI-NEXT: s_branch .LBB53_2
diff --git a/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll b/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
index 18cf120a1d299..61645200690f5 100644
--- a/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
@@ -27,24 +27,26 @@ define amdgpu_kernel void @any_extend_vector_inreg_v16i8_to_v4i32(ptr addrspace(
; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:1
; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0
; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:3
-; GFX6-NEXT: s_lshr_b32 s8, s9, 16
-; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NEXT: s_lshr_b32 s7, s9, 16
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_lshl_b64 s[6:7], s[4:5], 8
-; GFX6-NEXT: v_mov_b32_e32 v1, s11
-; GFX6-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:9
+; GFX6-NEXT: s_lshl_b64 s[8:9], s[4:5], 8
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s11
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:9
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s5
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:2
+; GFX6-NEXT: s_lshr_b64 s[4:5], s[6:7], 16
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v1, s5
-; GFX6-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:2
-; GFX6-NEXT: v_alignbit_b32 v0, s8, v0, 16
+; GFX6-NEXT: v_mov_b32_e32 v0, s9
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:12
+; GFX6-NEXT: s_lshr_b32 s5, s4, 8
+; GFX6-NEXT: s_lshr_b32 s4, s4, 24
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v1, s7
-; GFX6-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:12
+; GFX6-NEXT: v_mov_b32_e32 v0, s5
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:5
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 24, v0
-; GFX6-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:5
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:7
; GFX6-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index 30ad46d959b7e..12704fcf6312e 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -46065,18 +46065,18 @@ define <32 x bfloat> @v_select_v32bf16(i1 %cond, <32 x bfloat> %a, <32 x bfloat>
define amdgpu_ps <2 x i32> @s_select_v3bf16(<3 x bfloat> inreg %a, <3 x bfloat> inreg %b, i32 %c) {
; GCN-LABEL: s_select_v3bf16:
; GCN: ; %bb.0:
-; GCN-NEXT: v_mul_f32_e64 v1, 1.0, s1
-; GCN-NEXT: v_mul_f32_e64 v2, 1.0, s0
-; GCN-NEXT: v_mul_f32_e64 v3, 1.0, s4
-; GCN-NEXT: v_mul_f32_e64 v4, 1.0, s3
+; GCN-NEXT: v_mul_f32_e64 v2, 1.0, s1
+; GCN-NEXT: v_mul_f32_e64 v1, 1.0, s0
+; GCN-NEXT: v_mul_f32_e64 v4, 1.0, s4
+; GCN-NEXT: v_mul_f32_e64 v3, 1.0, s3
; GCN-NEXT: v_mul_f32_e64 v5, 1.0, s2
; GCN-NEXT: v_mul_f32_e64 v6, 1.0, s5
-; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GCN-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; GCN-NEXT: v_alignbit_b32 v2, v3, v4, 16
+; GCN-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; GCN-NEXT: v_lshr_b64 v[2:3], v[3:4], 16
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v5, vcc
; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
@@ -46087,13 +46087,13 @@ define amdgpu_ps <2 x i32> @s_select_v3bf16(<3 x bfloat> inreg %a, <3 x bfloat>
; GFX7-LABEL: s_select_v3bf16:
; GFX7: ; %bb.0:
; GFX7-NEXT: v_mul_f32_e64 v1, 1.0, s1
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_mul_f32_e64 v2, 1.0, s0
-; GFX7-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX7-NEXT: v_mul_f32_e64 v1, 1.0, s0
+; GFX7-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; GFX7-NEXT: v_mul_f32_e64 v2, 1.0, s4
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX7-NEXT: v_mul_f32_e64 v3, 1.0, s3
-; GFX7-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v2
+; GFX7-NEXT: v_mul_f32_e64 v2, 1.0, s3
+; GFX7-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
; GFX7-NEXT: v_mul_f32_e64 v3, 1.0, s2
; GFX7-NEXT: v_mul_f32_e64 v4, 1.0, s5
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -46203,22 +46203,22 @@ define amdgpu_ps <2 x i32> @s_select_v3bf16(<3 x bfloat> inreg %a, <3 x bfloat>
define amdgpu_ps <2 x i32> @s_select_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat> inreg %b, i32 %c) {
; GCN-LABEL: s_select_v4bf16:
; GCN: ; %bb.0:
-; GCN-NEXT: v_mul_f32_e64 v1, 1.0, s1
-; GCN-NEXT: v_mul_f32_e64 v2, 1.0, s0
-; GCN-NEXT: v_mul_f32_e64 v3, 1.0, s5
-; GCN-NEXT: v_mul_f32_e64 v4, 1.0, s4
-; GCN-NEXT: v_mul_f32_e64 v5, 1.0, s3
-; GCN-NEXT: v_mul_f32_e64 v6, 1.0, s2
-; GCN-NEXT: v_mul_f32_e64 v7, 1.0, s7
-; GCN-NEXT: v_mul_f32_e64 v8, 1.0, s6
-; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GCN-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; GCN-NEXT: v_alignbit_b32 v2, v3, v4, 16
-; GCN-NEXT: v_alignbit_b32 v3, v5, v6, 16
-; GCN-NEXT: v_alignbit_b32 v4, v7, v8, 16
+; GCN-NEXT: v_mul_f32_e64 v2, 1.0, s1
+; GCN-NEXT: v_mul_f32_e64 v1, 1.0, s0
+; GCN-NEXT: v_mul_f32_e64 v4, 1.0, s5
+; GCN-NEXT: v_mul_f32_e64 v3, 1.0, s4
+; GCN-NEXT: v_mul_f32_e64 v6, 1.0, s3
+; GCN-NEXT: v_mul_f32_e64 v5, 1.0, s2
+; GCN-NEXT: v_mul_f32_e64 v8, 1.0, s7
+; GCN-NEXT: v_mul_f32_e64 v7, 1.0, s6
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GCN-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
+; GCN-NEXT: v_lshr_b64 v[2:3], v[3:4], 16
+; GCN-NEXT: v_lshr_b64 v[3:4], v[5:6], 16
+; GCN-NEXT: v_lshr_b64 v[4:5], v[7:8], 16
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc
; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
@@ -46229,21 +46229,21 @@ define amdgpu_ps <2 x i32> @s_select_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat>
; GFX7-LABEL: s_select_v4bf16:
; GFX7: ; %bb.0:
; GFX7-NEXT: v_mul_f32_e64 v1, 1.0, s1
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_mul_f32_e64 v2, 1.0, s0
-; GFX7-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX7-NEXT: v_mul_f32_e64 v1, 1.0, s0
+; GFX7-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
; GFX7-NEXT: v_mul_f32_e64 v2, 1.0, s5
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX7-NEXT: v_mul_f32_e64 v3, 1.0, s4
-; GFX7-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v2
+; GFX7-NEXT: v_mul_f32_e64 v2, 1.0, s4
+; GFX7-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
; GFX7-NEXT: v_mul_f32_e64 v3, 1.0, s3
-; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX7-NEXT: v_mul_f32_e64 v4, 1.0, s2
-; GFX7-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v3
+; GFX7-NEXT: v_mul_f32_e64 v3, 1.0, s2
+; GFX7-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
; GFX7-NEXT: v_mul_f32_e64 v4, 1.0, s7
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX7-NEXT: v_mul_f32_e64 v5, 1.0, s6
-; GFX7-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; GFX7-NEXT: v_mul_f32_e64 v4, 1.0, s6
+; GFX7-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/build_vector.ll b/llvm/test/CodeGen/AMDGPU/build_vector.ll
index 763f436997c21..74a79e1bb71a0 100644
--- a/llvm/test/CodeGen/AMDGPU/build_vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/build_vector.ll
@@ -186,10 +186,12 @@ define amdgpu_kernel void @build_vector_v2i16_trunc (ptr addrspace(1) %out, i32
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 5
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_alignbit_b32 v0, 5, s6, 16
+; GFX6-NEXT: s_lshr_b64 s[4:5], s[6:7], 16
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
index ab96dcf1f6069..a2a8d2192232e 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
@@ -488,13 +488,13 @@ define amdgpu_kernel void @uniform_vec_i16_HH(ptr addrspace(1) %out, i32 %a, i32
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_lshr_b32 s3, s3, 16
+; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], 16
+; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s1
-; GCN-NEXT: s_lshr_b32 s0, s3, 16
; GCN-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NEXT: v_alignbit_b32 v0, s0, v0, 16
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
index 30bcdf97e26fd..4ff8bf23638f1 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
@@ -5023,20 +5023,20 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f32_sign_v2bf16(<2 x float> in
; GFX8-NEXT: s_add_i32 s6, s4, 0x7fff
; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], s0, s0
; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], exec
-; GFX8-NEXT: s_cselect_b32 s3, s3, s6
-; GFX8-NEXT: s_bfe_u32 s0, s1, 0x10010
-; GFX8-NEXT: s_add_i32 s0, s0, s1
-; GFX8-NEXT: s_or_b32 s4, s1, 0x400000
-; GFX8-NEXT: s_add_i32 s5, s0, 0x7fff
-; GFX8-NEXT: v_cmp_u_f32_e64 s[0:1], s1, s1
-; GFX8-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; GFX8-NEXT: s_cselect_b32 s0, s4, s5
-; GFX8-NEXT: s_lshr_b32 s0, s0, 16
-; GFX8-NEXT: v_mov_b32_e32 v0, s3
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, 16
-; GFX8-NEXT: s_mov_b32 s0, 0x7fff7fff
+; GFX8-NEXT: s_cselect_b32 s0, s3, s6
+; GFX8-NEXT: s_bfe_u32 s4, s1, 0x10010
+; GFX8-NEXT: s_add_i32 s4, s4, s1
+; GFX8-NEXT: s_or_b32 s3, s1, 0x400000
+; GFX8-NEXT: s_add_i32 s6, s4, 0x7fff
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], s1, s1
+; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX8-NEXT: s_cselect_b32 s1, s3, s6
+; GFX8-NEXT: s_lshr_b32 s1, s1, 16
+; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], 16
+; GFX8-NEXT: s_mov_b32 s1, 0x7fff7fff
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s2
-; GFX8-NEXT: v_bfi_b32 v0, s0, v0, v1
+; GFX8-NEXT: v_bfi_b32 v0, s1, v0, v1
; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
@@ -5185,29 +5185,29 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> i
; GFX8-NEXT: s_addk_i32 s8, 0x7fff
; GFX8-NEXT: s_bitset1_b32 s5, 22
; GFX8-NEXT: s_and_b64 s[6:7], s[6:7], exec
-; GFX8-NEXT: s_cselect_b32 s5, s5, s8
-; GFX8-NEXT: v_readfirstlane_b32 s8, v3
-; GFX8-NEXT: s_bitcmp1_b32 s8, 0
-; GFX8-NEXT: s_cselect_b64 s[6:7], -1, 0
-; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[6:7]
-; GFX8-NEXT: s_and_b64 s[6:7], s[12:13], exec
+; GFX8-NEXT: s_cselect_b32 s6, s5, s8
+; GFX8-NEXT: v_readfirstlane_b32 s5, v3
+; GFX8-NEXT: s_bitcmp1_b32 s5, 0
+; GFX8-NEXT: s_cselect_b64 s[8:9], -1, 0
+; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
+; GFX8-NEXT: s_and_b64 s[8:9], s[12:13], exec
; GFX8-NEXT: v_cmp_u_f64_e64 s[2:3], s[2:3], s[2:3]
-; GFX8-NEXT: s_cselect_b32 s6, 1, -1
-; GFX8-NEXT: s_add_i32 s6, s8, s6
+; GFX8-NEXT: s_cselect_b32 s7, 1, -1
+; GFX8-NEXT: s_add_i32 s7, s5, s7
; GFX8-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; GFX8-NEXT: s_cselect_b32 s0, s8, s6
+; GFX8-NEXT: s_cselect_b32 s0, s5, s7
; GFX8-NEXT: s_bfe_u32 s1, s0, 0x10010
; GFX8-NEXT: s_add_i32 s1, s1, s0
-; GFX8-NEXT: s_add_i32 s6, s1, 0x7fff
+; GFX8-NEXT: s_add_i32 s5, s1, 0x7fff
; GFX8-NEXT: s_or_b32 s7, s0, 0x400000
; GFX8-NEXT: s_and_b64 s[0:1], s[2:3], exec
-; GFX8-NEXT: s_cselect_b32 s0, s7, s6
-; GFX8-NEXT: s_lshr_b32 s0, s0, 16
-; GFX8-NEXT: v_mov_b32_e32 v0, s5
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, 16
-; GFX8-NEXT: s_mov_b32 s0, 0x7fff7fff
+; GFX8-NEXT: s_cselect_b32 s0, s7, s5
+; GFX8-NEXT: s_lshr_b32 s7, s0, 16
+; GFX8-NEXT: s_lshr_b64 s[0:1], s[6:7], 16
+; GFX8-NEXT: s_mov_b32 s1, 0x7fff7fff
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s4
-; GFX8-NEXT: v_bfi_b32 v0, s0, v0, v1
+; GFX8-NEXT: v_bfi_b32 v0, s1, v0, v1
; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
@@ -5421,19 +5421,19 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2bf16_sign_v2f32(<2 x bfloat> i
; GFX8-NEXT: s_addk_i32 s3, 0x7fff
; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], s1, s1
; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], exec
-; GFX8-NEXT: s_cselect_b32 s1, s1, s3
-; GFX8-NEXT: s_bfe_u32 s3, s2, 0x10010
-; GFX8-NEXT: s_add_i32 s3, s3, s2
-; GFX8-NEXT: s_addk_i32 s3, 0x7fff
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], s2, s2
-; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], exec
-; GFX8-NEXT: s_cselect_b32 s2, s2, s3
-; GFX8-NEXT: s_lshr_b32 s2, s2, 16
-; GFX8-NEXT: v_mov_b32_e32 v0, s1
-; GFX8-NEXT: v_alignbit_b32 v0, s2, v0, 16
+; GFX8-NEXT: s_cselect_b32 s4, s1, s3
+; GFX8-NEXT: s_bfe_u32 s1, s2, 0x10010
+; GFX8-NEXT: s_add_i32 s1, s1, s2
+; GFX8-NEXT: s_addk_i32 s1, 0x7fff
+; GFX8-NEXT: v_cmp_u_f32_e64 s[6:7], s2, s2
+; GFX8-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; GFX8-NEXT: s_cselect_b32 s1, s2, s1
+; GFX8-NEXT: s_lshr_b32 s5, s1, 16
+; GFX8-NEXT: s_lshr_b64 s[2:3], s[4:5], 16
; GFX8-NEXT: s_mov_b32 s1, 0x7fff7fff
-; GFX8-NEXT: v_mov_b32_e32 v1, s0
-; GFX8-NEXT: v_bfi_b32 v0, s1, v1, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s2
+; GFX8-NEXT: v_bfi_b32 v0, s1, v0, v1
; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
index 10c60dfc9b34c..5424ebfcffcd1 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
@@ -409,7 +409,7 @@ define amdgpu_kernel void @s_fneg_fabs_v2bf16_non_bc_src(ptr addrspace(1) %out,
; CI-NEXT: v_add_f32_e64 v1, s2, 2.0
; CI-NEXT: v_add_f32_e64 v0, s3, 1.0
; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; CI-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; CI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
; CI-NEXT: v_or_b32_e32 v2, 0x80008000, v0
; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
@@ -441,7 +441,7 @@ define amdgpu_kernel void @s_fneg_fabs_v2bf16_non_bc_src(ptr addrspace(1) %out,
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
; VI-NEXT: v_or_b32_e32 v2, 0x80008000, v0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
@@ -709,16 +709,16 @@ define amdgpu_kernel void @fold_user_fneg_fabs_v2bf16(ptr addrspace(1) %out, <2
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: s_and_b32 s3, s2, 0x7fff0000
-; CI-NEXT: s_and_b32 s2, s2, 0x7fff
-; CI-NEXT: s_lshl_b32 s2, s2, 16
-; CI-NEXT: v_mul_f32_e64 v0, s3, -4.0
-; CI-NEXT: v_mul_f32_e64 v1, s2, -4.0
-; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; CI-NEXT: v_alignbit_b32 v2, v0, v1, 16
-; CI-NEXT: v_mov_b32_e32 v0, s0
-; CI-NEXT: v_mov_b32_e32 v1, s1
-; CI-NEXT: flat_store_dword v[0:1], v2
+; CI-NEXT: s_and_b32 s3, s2, 0x7fff
+; CI-NEXT: s_and_b32 s2, s2, 0x7fff0000
+; CI-NEXT: v_mul_f32_e64 v0, s2, -4.0
+; CI-NEXT: s_lshl_b32 s2, s3, 16
+; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; CI-NEXT: v_mul_f32_e64 v0, s2, -4.0
+; CI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; CI-NEXT: v_mov_b32_e32 v2, s1
+; CI-NEXT: v_mov_b32_e32 v1, s0
+; CI-NEXT: flat_store_dword v[1:2], v0
; CI-NEXT: s_endpgm
;
; VI-LABEL: fold_user_fneg_fabs_v2bf16:
@@ -749,10 +749,10 @@ define amdgpu_kernel void @fold_user_fneg_fabs_v2bf16(ptr addrspace(1) %out, <2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_alignbit_b32 v2, v1, v0, 16
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v2, s1
+; VI-NEXT: v_mov_b32_e32 v1, s0
+; VI-NEXT: flat_store_dword v[1:2], v0
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: fold_user_fneg_fabs_v2bf16:
@@ -956,17 +956,17 @@ define amdgpu_kernel void @s_fneg_multi_use_fabs_foldable_neg_v2bf16(ptr addrspa
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v1, s1
+; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: s_and_b32 s1, s4, 0x7fff
+; CI-NEXT: s_and_b32 s2, s4, 0x7fff0000
+; CI-NEXT: v_mul_f32_e64 v4, s2, -4.0
; CI-NEXT: s_lshl_b32 s1, s1, 16
+; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
; CI-NEXT: v_mul_f32_e64 v4, s1, -4.0
-; CI-NEXT: s_and_b32 s1, s4, 0x7fff0000
-; CI-NEXT: v_mul_f32_e64 v5, s1, -4.0
; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_and_b32 s0, s4, 0x7fff7fff
-; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; CI-NEXT: v_alignbit_b32 v4, v5, v4, 16
+; CI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
; CI-NEXT: v_mov_b32_e32 v5, s0
-; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: flat_store_dword v[0:1], v5
; CI-NEXT: flat_store_dword v[2:3], v4
@@ -1000,10 +1000,10 @@ define amdgpu_kernel void @s_fneg_multi_use_fabs_foldable_neg_v2bf16(ptr addrspa
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_and_b32 s0, s4, 0x7fff7fff
-; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_alignbit_b32 v4, v5, v4, 16
+; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[4:5]
; VI-NEXT: v_mov_b32_e32 v5, s0
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
diff --git a/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll b/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
index 84b904ff67151..63aadaacbeb3a 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
@@ -627,18 +627,18 @@ define amdgpu_kernel void @v_fneg_fold_v2bf16(ptr addrspace(1) %out, ptr addrspa
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: v_mov_b32_e32 v1, s3
-; CI-NEXT: flat_load_dword v2, v[0:1]
+; CI-NEXT: flat_load_dword v1, v[0:1]
; CI-NEXT: v_mov_b32_e32 v0, s0
-; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_xor_b32_e32 v3, 0x8000, v2
-; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; CI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; CI-NEXT: v_mul_f32_e64 v2, -v2, v2
-; CI-NEXT: v_mul_f32_e32 v3, v3, v4
-; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; CI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; CI-NEXT: v_xor_b32_e32 v2, 0x8000, v1
+; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; CI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; CI-NEXT: v_mul_f32_e64 v4, -v1, v1
+; CI-NEXT: v_mul_f32_e32 v1, v2, v3
+; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
+; CI-NEXT: v_lshr_b64 v[2:3], v[1:2], 16
+; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm
;
@@ -648,34 +648,34 @@ define amdgpu_kernel void @v_fneg_fold_v2bf16(ptr addrspace(1) %out, ptr addrspa
; GFX8-NEXT: s_add_i32 s12, s12, s17
; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x8000
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x8000
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: flat_load_dword v2, v[0:1]
+; GFX8-NEXT: flat_load_dword v1, v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX8-NEXT: v_xor_b32_sdwa v5, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX8-NEXT: v_xor_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_mul_f32_e32 v3, v5, v4
-; GFX8-NEXT: v_mul_f32_e32 v2, v2, v6
-; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX8-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v2
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
-; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
-; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; GFX8-NEXT: v_xor_b32_sdwa v4, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
+; GFX8-NEXT: v_xor_b32_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_mul_f32_e32 v2, v4, v3
+; GFX8-NEXT: v_mul_f32_e32 v3, v1, v5
+; GFX8-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX8-NEXT: v_bfe_u32 v5, v3, 16, 1
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v2
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
+; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v2
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc
+; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; GFX8-NEXT: v_lshrrev_b64 v[2:3], 16, v[1:2]
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fshl.ll b/llvm/test/CodeGen/AMDGPU/fshl.ll
index 792f2aa711455..ae86d0a6f6153 100644
--- a/llvm/test/CodeGen/AMDGPU/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshl.ll
@@ -18,12 +18,15 @@ define amdgpu_kernel void @fshl_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s1
-; SI-NEXT: s_lshr_b32 s1, s0, 1
-; SI-NEXT: v_alignbit_b32 v0, s0, v0, 1
-; SI-NEXT: s_not_b32 s0, s2
-; SI-NEXT: v_mov_b32_e32 v1, s0
-; SI-NEXT: v_alignbit_b32 v0, s1, v0, v1
+; SI-NEXT: s_mov_b32 s8, s1
+; SI-NEXT: s_mov_b32 s9, s0
+; SI-NEXT: s_lshr_b32 s3, s0, 1
+; SI-NEXT: s_lshr_b64 s[0:1], s[8:9], 1
+; SI-NEXT: s_not_b32 s2, s2
+; SI-NEXT: s_mov_b32 s1, s3
+; SI-NEXT: s_and_b32 s2, s2, 31
+; SI-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
@@ -32,14 +35,17 @@ define amdgpu_kernel void @fshl_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s1
+; VI-NEXT: s_mov_b32 s6, s1
+; VI-NEXT: s_mov_b32 s7, s0
+; VI-NEXT: s_lshr_b32 s3, s0, 1
; VI-NEXT: s_not_b32 s2, s2
-; VI-NEXT: s_lshr_b32 s1, s0, 1
-; VI-NEXT: v_alignbit_b32 v0, s0, v0, 1
-; VI-NEXT: v_mov_b32_e32 v1, s2
-; VI-NEXT: v_alignbit_b32 v2, s1, v0, v1
+; VI-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_and_b32 s2, s2, 31
+; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
@@ -125,10 +131,12 @@ define amdgpu_kernel void @fshl_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s3
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
-; SI-NEXT: v_alignbit_b32 v0, s2, v0, 25
+; SI-NEXT: s_mov_b32 s0, s3
+; SI-NEXT: s_mov_b32 s1, s2
+; SI-NEXT: s_lshr_b64 s[0:1], s[0:1], 25
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
@@ -136,10 +144,12 @@ define amdgpu_kernel void @fshl_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s3
-; VI-NEXT: v_alignbit_b32 v2, s2, v0, 25
+; VI-NEXT: s_mov_b32 s4, s3
+; VI-NEXT: s_mov_b32 s5, s2
+; VI-NEXT: s_lshr_b64 s[2:3], s[4:5], 25
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
@@ -205,41 +215,51 @@ define amdgpu_kernel void @fshl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s3
-; SI-NEXT: v_alignbit_b32 v0, s1, v0, 1
-; SI-NEXT: s_not_b32 s3, s5
-; SI-NEXT: s_lshr_b32 s1, s1, 1
-; SI-NEXT: v_mov_b32_e32 v1, s3
-; SI-NEXT: v_alignbit_b32 v1, s1, v0, v1
-; SI-NEXT: v_mov_b32_e32 v0, s2
-; SI-NEXT: s_not_b32 s1, s4
-; SI-NEXT: v_alignbit_b32 v0, s0, v0, 1
-; SI-NEXT: s_lshr_b32 s0, s0, 1
-; SI-NEXT: v_mov_b32_e32 v2, s1
-; SI-NEXT: v_alignbit_b32 v0, s0, v0, v2
+; SI-NEXT: s_mov_b32 s6, s3
+; SI-NEXT: s_mov_b32 s7, s1
+; SI-NEXT: s_lshr_b32 s12, s1, 1
+; SI-NEXT: s_lshr_b64 s[6:7], s[6:7], 1
+; SI-NEXT: s_not_b32 s1, s5
+; SI-NEXT: s_mov_b32 s7, s12
+; SI-NEXT: s_and_b32 s1, s1, 31
+; SI-NEXT: s_mov_b32 s3, s0
+; SI-NEXT: s_lshr_b64 s[6:7], s[6:7], s1
+; SI-NEXT: s_lshr_b32 s5, s0, 1
+; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], 1
+; SI-NEXT: s_not_b32 s2, s4
+; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_and_b32 s2, s2, 31
+; SI-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s6
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fshl_v2i32:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
-; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x3c
-; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x3c
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s3
-; VI-NEXT: s_not_b32 s7, s7
-; VI-NEXT: s_lshr_b32 s3, s1, 1
-; VI-NEXT: v_alignbit_b32 v0, s1, v0, 1
-; VI-NEXT: v_mov_b32_e32 v1, s7
-; VI-NEXT: v_alignbit_b32 v1, s3, v0, v1
-; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: s_not_b32 s1, s6
-; VI-NEXT: v_alignbit_b32 v0, s0, v0, 1
-; VI-NEXT: s_lshr_b32 s0, s0, 1
-; VI-NEXT: v_mov_b32_e32 v2, s1
-; VI-NEXT: v_alignbit_b32 v0, s0, v0, v2
-; VI-NEXT: v_mov_b32_e32 v2, s4
-; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: s_mov_b32 s8, s3
+; VI-NEXT: s_mov_b32 s9, s1
+; VI-NEXT: s_lshr_b32 s10, s1, 1
+; VI-NEXT: s_lshr_b64 s[8:9], s[8:9], 1
+; VI-NEXT: s_not_b32 s1, s5
+; VI-NEXT: s_mov_b32 s9, s10
+; VI-NEXT: s_and_b32 s1, s1, 31
+; VI-NEXT: s_mov_b32 s3, s0
+; VI-NEXT: s_lshr_b64 s[8:9], s[8:9], s1
+; VI-NEXT: s_lshr_b32 s5, s0, 1
+; VI-NEXT: s_lshr_b64 s[0:1], s[2:3], 1
+; VI-NEXT: s_not_b32 s2, s4
+; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_and_b32 s2, s2, 31
+; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; VI-NEXT: v_mov_b32_e32 v2, s6
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s8
+; VI-NEXT: v_mov_b32_e32 v3, s7
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
;
@@ -357,10 +377,13 @@ define amdgpu_kernel void @fshl_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s3
-; SI-NEXT: v_mov_b32_e32 v2, s2
-; SI-NEXT: v_alignbit_b32 v1, s1, v0, 23
-; SI-NEXT: v_alignbit_b32 v0, s0, v2, 25
+; SI-NEXT: s_mov_b32 s8, s3
+; SI-NEXT: s_mov_b32 s9, s1
+; SI-NEXT: s_mov_b32 s3, s0
+; SI-NEXT: s_lshr_b64 s[8:9], s[8:9], 23
+; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], 25
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s8
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
@@ -369,11 +392,14 @@ define amdgpu_kernel void @fshl_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s3
-; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_alignbit_b32 v1, s1, v0, 23
-; VI-NEXT: v_alignbit_b32 v0, s0, v2, 25
+; VI-NEXT: s_mov_b32 s6, s3
+; VI-NEXT: s_mov_b32 s7, s1
+; VI-NEXT: s_mov_b32 s3, s0
+; VI-NEXT: s_lshr_b64 s[0:1], s[6:7], 23
+; VI-NEXT: s_lshr_b64 s[2:3], s[2:3], 25
; VI-NEXT: v_mov_b32_e32 v2, s4
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s0
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -451,70 +477,90 @@ define amdgpu_kernel void @fshl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; SI-LABEL: fshl_v4i32:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
-; SI-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x15
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x15
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_not_b32 s5, s19
-; SI-NEXT: v_mov_b32_e32 v0, s15
-; SI-NEXT: v_alignbit_b32 v0, s11, v0, 1
-; SI-NEXT: s_lshr_b32 s4, s11, 1
-; SI-NEXT: v_mov_b32_e32 v1, s5
-; SI-NEXT: v_alignbit_b32 v3, s4, v0, v1
-; SI-NEXT: v_mov_b32_e32 v0, s14
-; SI-NEXT: s_not_b32 s5, s18
-; SI-NEXT: v_alignbit_b32 v0, s10, v0, 1
-; SI-NEXT: s_lshr_b32 s4, s10, 1
-; SI-NEXT: v_mov_b32_e32 v1, s5
-; SI-NEXT: v_alignbit_b32 v2, s4, v0, v1
-; SI-NEXT: v_mov_b32_e32 v0, s13
-; SI-NEXT: s_not_b32 s5, s17
-; SI-NEXT: v_alignbit_b32 v0, s9, v0, 1
-; SI-NEXT: s_lshr_b32 s4, s9, 1
-; SI-NEXT: v_mov_b32_e32 v1, s5
-; SI-NEXT: v_alignbit_b32 v1, s4, v0, v1
-; SI-NEXT: v_mov_b32_e32 v0, s12
-; SI-NEXT: s_not_b32 s5, s16
-; SI-NEXT: v_alignbit_b32 v0, s8, v0, 1
-; SI-NEXT: s_lshr_b32 s4, s8, 1
-; SI-NEXT: v_mov_b32_e32 v4, s5
-; SI-NEXT: v_alignbit_b32 v0, s4, v0, v4
+; SI-NEXT: s_mov_b32 s16, s15
+; SI-NEXT: s_mov_b32 s17, s11
+; SI-NEXT: s_lshr_b32 s18, s11, 1
+; SI-NEXT: s_lshr_b64 s[16:17], s[16:17], 1
+; SI-NEXT: s_not_b32 s7, s7
+; SI-NEXT: s_mov_b32 s17, s18
+; SI-NEXT: s_and_b32 s7, s7, 31
+; SI-NEXT: s_mov_b32 s15, s10
+; SI-NEXT: s_lshr_b64 s[16:17], s[16:17], s7
+; SI-NEXT: s_lshr_b32 s7, s10, 1
+; SI-NEXT: s_lshr_b64 s[10:11], s[14:15], 1
+; SI-NEXT: s_not_b32 s6, s6
+; SI-NEXT: s_mov_b32 s11, s7
+; SI-NEXT: s_and_b32 s6, s6, 31
+; SI-NEXT: s_lshr_b64 s[6:7], s[10:11], s6
+; SI-NEXT: s_mov_b32 s10, s13
+; SI-NEXT: s_mov_b32 s11, s9
+; SI-NEXT: s_lshr_b32 s7, s9, 1
+; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], 1
+; SI-NEXT: s_not_b32 s5, s5
+; SI-NEXT: s_mov_b32 s11, s7
+; SI-NEXT: s_and_b32 s5, s5, 31
+; SI-NEXT: s_mov_b32 s13, s8
+; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], s5
+; SI-NEXT: s_lshr_b32 s5, s8, 1
+; SI-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
+; SI-NEXT: s_not_b32 s4, s4
+; SI-NEXT: s_mov_b32 s9, s5
+; SI-NEXT: s_and_b32 s4, s4, 31
+; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], s4
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: v_mov_b32_e32 v1, s10
+; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v3, s16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fshl_v4i32:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
+; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x54
-; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s15
+; VI-NEXT: s_mov_b32 s4, s15
+; VI-NEXT: s_mov_b32 s5, s11
+; VI-NEXT: s_lshr_b32 s16, s11, 1
+; VI-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
; VI-NEXT: s_not_b32 s3, s3
-; VI-NEXT: s_lshr_b32 s6, s11, 1
-; VI-NEXT: v_alignbit_b32 v0, s11, v0, 1
-; VI-NEXT: v_mov_b32_e32 v1, s3
-; VI-NEXT: v_alignbit_b32 v3, s6, v0, v1
-; VI-NEXT: v_mov_b32_e32 v0, s14
-; VI-NEXT: s_not_b32 s2, s2
-; VI-NEXT: v_alignbit_b32 v0, s10, v0, 1
+; VI-NEXT: s_mov_b32 s5, s16
+; VI-NEXT: s_and_b32 s3, s3, 31
+; VI-NEXT: s_mov_b32 s15, s10
+; VI-NEXT: s_lshr_b64 s[4:5], s[4:5], s3
; VI-NEXT: s_lshr_b32 s3, s10, 1
-; VI-NEXT: v_mov_b32_e32 v1, s2
-; VI-NEXT: v_alignbit_b32 v2, s3, v0, v1
-; VI-NEXT: v_mov_b32_e32 v0, s13
+; VI-NEXT: s_lshr_b64 s[10:11], s[14:15], 1
+; VI-NEXT: s_not_b32 s2, s2
+; VI-NEXT: s_mov_b32 s11, s3
+; VI-NEXT: s_and_b32 s2, s2, 31
+; VI-NEXT: s_lshr_b64 s[2:3], s[10:11], s2
+; VI-NEXT: s_mov_b32 s10, s13
+; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_lshr_b32 s3, s9, 1
+; VI-NEXT: s_lshr_b64 s[10:11], s[10:11], 1
; VI-NEXT: s_not_b32 s1, s1
-; VI-NEXT: v_alignbit_b32 v0, s9, v0, 1
-; VI-NEXT: s_lshr_b32 s2, s9, 1
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_alignbit_b32 v1, s2, v0, v1
-; VI-NEXT: v_mov_b32_e32 v0, s12
-; VI-NEXT: s_not_b32 s0, s0
-; VI-NEXT: v_alignbit_b32 v0, s8, v0, 1
+; VI-NEXT: s_mov_b32 s11, s3
+; VI-NEXT: s_and_b32 s1, s1, 31
+; VI-NEXT: s_mov_b32 s13, s8
+; VI-NEXT: s_lshr_b64 s[10:11], s[10:11], s1
; VI-NEXT: s_lshr_b32 s1, s8, 1
-; VI-NEXT: v_mov_b32_e32 v4, s0
-; VI-NEXT: v_alignbit_b32 v0, s1, v0, v4
-; VI-NEXT: v_mov_b32_e32 v4, s4
-; VI-NEXT: v_mov_b32_e32 v5, s5
+; VI-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
+; VI-NEXT: s_not_b32 s0, s0
+; VI-NEXT: s_mov_b32 s9, s1
+; VI-NEXT: s_and_b32 s0, s0, 31
+; VI-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
+; VI-NEXT: v_mov_b32_e32 v4, s6
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s10
+; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v3, s4
+; VI-NEXT: v_mov_b32_e32 v5, s7
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
;
@@ -690,14 +736,20 @@ define amdgpu_kernel void @fshl_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s15
-; SI-NEXT: v_mov_b32_e32 v1, s14
-; SI-NEXT: v_alignbit_b32 v3, s11, v0, 31
-; SI-NEXT: v_mov_b32_e32 v0, s13
-; SI-NEXT: v_alignbit_b32 v2, s10, v1, 23
-; SI-NEXT: v_alignbit_b32 v1, s9, v0, 25
-; SI-NEXT: v_mov_b32_e32 v0, s12
-; SI-NEXT: v_alignbit_b32 v0, s8, v0, 31
+; SI-NEXT: s_mov_b32 s4, s15
+; SI-NEXT: s_mov_b32 s5, s11
+; SI-NEXT: s_mov_b32 s15, s10
+; SI-NEXT: s_mov_b32 s10, s13
+; SI-NEXT: s_mov_b32 s11, s9
+; SI-NEXT: s_mov_b32 s13, s8
+; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 31
+; SI-NEXT: s_lshr_b64 s[6:7], s[14:15], 23
+; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], 25
+; SI-NEXT: s_lshr_b64 s[8:9], s[12:13], 31
+; SI-NEXT: v_mov_b32_e32 v0, s8
+; SI-NEXT: v_mov_b32_e32 v1, s10
+; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v3, s4
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
@@ -706,15 +758,21 @@ define amdgpu_kernel void @fshl_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s15
-; VI-NEXT: v_mov_b32_e32 v1, s14
-; VI-NEXT: v_mov_b32_e32 v4, s13
-; VI-NEXT: v_alignbit_b32 v3, s11, v0, 31
-; VI-NEXT: v_alignbit_b32 v2, s10, v1, 23
-; VI-NEXT: v_alignbit_b32 v1, s9, v4, 25
-; VI-NEXT: v_mov_b32_e32 v0, s12
+; VI-NEXT: s_mov_b32 s2, s15
+; VI-NEXT: s_mov_b32 s3, s11
+; VI-NEXT: s_mov_b32 s15, s10
+; VI-NEXT: s_mov_b32 s6, s13
+; VI-NEXT: s_mov_b32 s7, s9
+; VI-NEXT: s_mov_b32 s13, s8
+; VI-NEXT: s_lshr_b64 s[2:3], s[2:3], 31
+; VI-NEXT: s_lshr_b64 s[4:5], s[14:15], 23
+; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], 25
+; VI-NEXT: s_lshr_b64 s[8:9], s[12:13], 31
; VI-NEXT: v_mov_b32_e32 v5, s1
-; VI-NEXT: v_alignbit_b32 v0, s8, v0, 31
+; VI-NEXT: v_mov_b32_e32 v0, s8
+; VI-NEXT: v_mov_b32_e32 v1, s6
+; VI-NEXT: v_mov_b32_e32 v2, s4
+; VI-NEXT: v_mov_b32_e32 v3, s2
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fshr.ll b/llvm/test/CodeGen/AMDGPU/fshr.ll
index a32d4d8dcda88..7afb2cf317869 100644
--- a/llvm/test/CodeGen/AMDGPU/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshr.ll
@@ -30,9 +30,11 @@ define amdgpu_kernel void @fshr_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s1
-; SI-NEXT: v_mov_b32_e32 v1, s2
-; SI-NEXT: v_alignbit_b32 v0, s0, v0, v1
+; SI-NEXT: s_mov_b32 s8, s1
+; SI-NEXT: s_mov_b32 s9, s0
+; SI-NEXT: s_and_b32 s0, s2, 31
+; SI-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
@@ -41,11 +43,13 @@ define amdgpu_kernel void @fshr_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s1
-; VI-NEXT: v_mov_b32_e32 v1, s2
-; VI-NEXT: v_alignbit_b32 v2, s0, v0, v1
+; VI-NEXT: s_mov_b32 s6, s1
+; VI-NEXT: s_mov_b32 s7, s0
+; VI-NEXT: s_and_b32 s0, s2, 31
+; VI-NEXT: s_lshr_b64 s[0:1], s[6:7], s0
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
@@ -131,10 +135,12 @@ define amdgpu_kernel void @fshr_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s3
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
-; SI-NEXT: v_alignbit_b32 v0, s2, v0, 7
+; SI-NEXT: s_mov_b32 s0, s3
+; SI-NEXT: s_mov_b32 s1, s2
+; SI-NEXT: s_lshr_b64 s[0:1], s[0:1], 7
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
@@ -142,10 +148,12 @@ define amdgpu_kernel void @fshr_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s3
-; VI-NEXT: v_alignbit_b32 v2, s2, v0, 7
+; VI-NEXT: s_mov_b32 s4, s3
+; VI-NEXT: s_mov_b32 s5, s2
+; VI-NEXT: s_lshr_b64 s[2:3], s[4:5], 7
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
@@ -218,24 +226,30 @@ define amdgpu_kernel void @fshr_i32_imm_src0(ptr addrspace(1) %in, i32 %x, i32 %
; SI-LABEL: fshr_i32_imm_src0:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s9, 7
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s8, s3
+; SI-NEXT: s_and_b32 s0, s2, 31
; SI-NEXT: s_mov_b32 s5, s1
-; SI-NEXT: v_alignbit_b32 v0, 7, s3, v0
+; SI-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fshr_i32_imm_src0:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_mov_b32 s5, 7
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_alignbit_b32 v2, 7, s3, v0
+; VI-NEXT: s_mov_b32 s4, s3
+; VI-NEXT: s_and_b32 s2, s2, 31
+; VI-NEXT: s_lshr_b64 s[2:3], s[4:5], s2
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
@@ -312,18 +326,21 @@ define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; SI-LABEL: fshr_v2i32:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xf
-; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xf
+; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s3
-; SI-NEXT: v_mov_b32_e32 v1, s9
-; SI-NEXT: v_alignbit_b32 v1, s1, v0, v1
-; SI-NEXT: v_mov_b32_e32 v0, s2
-; SI-NEXT: v_mov_b32_e32 v2, s8
-; SI-NEXT: v_alignbit_b32 v0, s0, v0, v2
-; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT: s_mov_b32 s6, s3
+; SI-NEXT: s_mov_b32 s7, s1
+; SI-NEXT: s_and_b32 s1, s5, 31
+; SI-NEXT: s_mov_b32 s3, s0
+; SI-NEXT: s_and_b32 s0, s4, 31
+; SI-NEXT: s_lshr_b64 s[6:7], s[6:7], s1
+; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s0
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s6
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fshr_v2i32:
@@ -332,13 +349,16 @@ define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x3c
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s3
-; VI-NEXT: v_mov_b32_e32 v1, s7
-; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_alignbit_b32 v1, s1, v0, v1
-; VI-NEXT: v_mov_b32_e32 v0, s6
-; VI-NEXT: v_alignbit_b32 v0, s0, v2, v0
+; VI-NEXT: s_mov_b32 s8, s3
+; VI-NEXT: s_mov_b32 s9, s1
+; VI-NEXT: s_and_b32 s1, s7, 31
+; VI-NEXT: s_mov_b32 s3, s0
+; VI-NEXT: s_and_b32 s0, s6, 31
+; VI-NEXT: s_lshr_b64 s[8:9], s[8:9], s1
+; VI-NEXT: s_lshr_b64 s[0:1], s[2:3], s0
; VI-NEXT: v_mov_b32_e32 v2, s4
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s8
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -449,10 +469,13 @@ define amdgpu_kernel void @fshr_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s3
-; SI-NEXT: v_mov_b32_e32 v2, s2
-; SI-NEXT: v_alignbit_b32 v1, s1, v0, 9
-; SI-NEXT: v_alignbit_b32 v0, s0, v2, 7
+; SI-NEXT: s_mov_b32 s8, s3
+; SI-NEXT: s_mov_b32 s9, s1
+; SI-NEXT: s_mov_b32 s3, s0
+; SI-NEXT: s_lshr_b64 s[8:9], s[8:9], 9
+; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], 7
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s8
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
@@ -461,11 +484,14 @@ define amdgpu_kernel void @fshr_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s3
-; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_alignbit_b32 v1, s1, v0, 9
-; VI-NEXT: v_alignbit_b32 v0, s0, v2, 7
+; VI-NEXT: s_mov_b32 s6, s3
+; VI-NEXT: s_mov_b32 s7, s1
+; VI-NEXT: s_mov_b32 s3, s0
+; VI-NEXT: s_lshr_b64 s[0:1], s[6:7], 9
+; VI-NEXT: s_lshr_b64 s[2:3], s[2:3], 7
; VI-NEXT: v_mov_b32_e32 v2, s4
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s0
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -561,13 +587,19 @@ define amdgpu_kernel void @fshr_v2i32_imm_src1(ptr addrspace(1) %in, <2 x i32> %
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s8, 9
+; SI-NEXT: s_mov_b32 s10, 7
; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s3
-; SI-NEXT: v_mov_b32_e32 v2, s2
-; SI-NEXT: v_alignbit_b32 v1, s1, 9, v0
-; SI-NEXT: v_alignbit_b32 v0, s0, 7, v2
+; SI-NEXT: s_mov_b32 s9, s1
+; SI-NEXT: s_and_b32 s1, s3, 31
+; SI-NEXT: s_mov_b32 s11, s0
+; SI-NEXT: s_and_b32 s0, s2, 31
+; SI-NEXT: s_lshr_b64 s[8:9], s[8:9], s1
+; SI-NEXT: s_lshr_b64 s[0:1], s[10:11], s0
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s8
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
@@ -575,12 +607,18 @@ define amdgpu_kernel void @fshr_v2i32_imm_src1(ptr addrspace(1) %in, <2 x i32> %
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-NEXT: s_mov_b32 s6, 9
+; VI-NEXT: s_mov_b32 s8, 7
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s3
-; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_alignbit_b32 v1, s1, 9, v0
-; VI-NEXT: v_alignbit_b32 v0, s0, 7, v2
+; VI-NEXT: s_mov_b32 s7, s1
+; VI-NEXT: s_and_b32 s1, s3, 31
+; VI-NEXT: s_mov_b32 s9, s0
+; VI-NEXT: s_and_b32 s0, s2, 31
+; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], s1
+; VI-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
; VI-NEXT: v_mov_b32_e32 v2, s4
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s6
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -687,24 +725,30 @@ define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; SI-LABEL: fshr_v4i32:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x15
-; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x15
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s15
-; SI-NEXT: v_mov_b32_e32 v1, s3
-; SI-NEXT: v_alignbit_b32 v3, s11, v0, v1
-; SI-NEXT: v_mov_b32_e32 v0, s14
-; SI-NEXT: v_mov_b32_e32 v1, s2
-; SI-NEXT: v_alignbit_b32 v2, s10, v0, v1
-; SI-NEXT: v_mov_b32_e32 v0, s13
-; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_alignbit_b32 v1, s9, v0, v1
-; SI-NEXT: v_mov_b32_e32 v0, s12
-; SI-NEXT: v_mov_b32_e32 v4, s0
-; SI-NEXT: v_alignbit_b32 v0, s8, v0, v4
-; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; SI-NEXT: s_mov_b32 s4, s15
+; SI-NEXT: s_mov_b32 s5, s11
+; SI-NEXT: s_and_b32 s6, s19, 31
+; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], s6
+; SI-NEXT: s_mov_b32 s15, s10
+; SI-NEXT: s_and_b32 s5, s18, 31
+; SI-NEXT: s_lshr_b64 s[6:7], s[14:15], s5
+; SI-NEXT: s_mov_b32 s10, s13
+; SI-NEXT: s_mov_b32 s11, s9
+; SI-NEXT: s_and_b32 s5, s17, 31
+; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], s5
+; SI-NEXT: s_mov_b32 s13, s8
+; SI-NEXT: s_and_b32 s5, s16, 31
+; SI-NEXT: s_lshr_b64 s[8:9], s[12:13], s5
+; SI-NEXT: v_mov_b32_e32 v0, s8
+; SI-NEXT: v_mov_b32_e32 v1, s10
+; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v3, s4
+; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fshr_v4i32:
@@ -713,19 +757,25 @@ define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x54
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s15
-; VI-NEXT: v_mov_b32_e32 v1, s3
-; VI-NEXT: v_mov_b32_e32 v2, s14
-; VI-NEXT: v_alignbit_b32 v3, s11, v0, v1
-; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_alignbit_b32 v2, s10, v2, v0
-; VI-NEXT: v_mov_b32_e32 v0, s13
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_alignbit_b32 v1, s9, v0, v1
-; VI-NEXT: v_mov_b32_e32 v0, s12
-; VI-NEXT: v_mov_b32_e32 v4, s0
-; VI-NEXT: v_alignbit_b32 v0, s8, v0, v4
+; VI-NEXT: s_mov_b32 s6, s15
+; VI-NEXT: s_mov_b32 s7, s11
+; VI-NEXT: s_and_b32 s3, s3, 31
+; VI-NEXT: s_mov_b32 s15, s10
+; VI-NEXT: s_and_b32 s2, s2, 31
+; VI-NEXT: s_mov_b32 s10, s13
+; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_and_b32 s1, s1, 31
+; VI-NEXT: s_mov_b32 s13, s8
+; VI-NEXT: s_and_b32 s0, s0, 31
+; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], s3
+; VI-NEXT: s_lshr_b64 s[2:3], s[14:15], s2
+; VI-NEXT: s_lshr_b64 s[10:11], s[10:11], s1
+; VI-NEXT: s_lshr_b64 s[0:1], s[12:13], s0
; VI-NEXT: v_mov_b32_e32 v4, s4
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s10
+; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
@@ -874,14 +924,20 @@ define amdgpu_kernel void @fshr_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s15
-; SI-NEXT: v_mov_b32_e32 v1, s14
-; SI-NEXT: v_alignbit_b32 v3, s11, v0, 1
-; SI-NEXT: v_mov_b32_e32 v0, s13
-; SI-NEXT: v_alignbit_b32 v2, s10, v1, 9
-; SI-NEXT: v_alignbit_b32 v1, s9, v0, 7
-; SI-NEXT: v_mov_b32_e32 v0, s12
-; SI-NEXT: v_alignbit_b32 v0, s8, v0, 1
+; SI-NEXT: s_mov_b32 s4, s15
+; SI-NEXT: s_mov_b32 s5, s11
+; SI-NEXT: s_mov_b32 s15, s10
+; SI-NEXT: s_mov_b32 s10, s13
+; SI-NEXT: s_mov_b32 s11, s9
+; SI-NEXT: s_mov_b32 s13, s8
+; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
+; SI-NEXT: s_lshr_b64 s[6:7], s[14:15], 9
+; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], 7
+; SI-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
+; SI-NEXT: v_mov_b32_e32 v0, s8
+; SI-NEXT: v_mov_b32_e32 v1, s10
+; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v3, s4
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
@@ -890,15 +946,21 @@ define amdgpu_kernel void @fshr_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s15
-; VI-NEXT: v_mov_b32_e32 v1, s14
-; VI-NEXT: v_mov_b32_e32 v4, s13
-; VI-NEXT: v_alignbit_b32 v3, s11, v0, 1
-; VI-NEXT: v_alignbit_b32 v2, s10, v1, 9
-; VI-NEXT: v_alignbit_b32 v1, s9, v4, 7
-; VI-NEXT: v_mov_b32_e32 v0, s12
+; VI-NEXT: s_mov_b32 s2, s15
+; VI-NEXT: s_mov_b32 s3, s11
+; VI-NEXT: s_mov_b32 s15, s10
+; VI-NEXT: s_mov_b32 s6, s13
+; VI-NEXT: s_mov_b32 s7, s9
+; VI-NEXT: s_mov_b32 s13, s8
+; VI-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; VI-NEXT: s_lshr_b64 s[4:5], s[14:15], 9
+; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], 7
+; VI-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
; VI-NEXT: v_mov_b32_e32 v5, s1
-; VI-NEXT: v_alignbit_b32 v0, s8, v0, 1
+; VI-NEXT: v_mov_b32_e32 v0, s8
+; VI-NEXT: v_mov_b32_e32 v1, s6
+; VI-NEXT: v_mov_b32_e32 v2, s4
+; VI-NEXT: v_mov_b32_e32 v3, s2
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
@@ -1021,36 +1083,56 @@ define amdgpu_kernel void @fshr_v4i32_imm_src0(ptr addrspace(1) %in, <4 x i32> %
; SI-LABEL: fshr_v4i32_imm_src0:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
+; SI-NEXT: s_mov_b32 s7, 33
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s15
-; SI-NEXT: v_mov_b32_e32 v1, s14
-; SI-NEXT: v_alignbit_b32 v3, 33, s11, v0
-; SI-NEXT: v_mov_b32_e32 v0, s13
-; SI-NEXT: v_alignbit_b32 v2, 9, s10, v1
-; SI-NEXT: v_alignbit_b32 v1, 7, s9, v0
-; SI-NEXT: v_mov_b32_e32 v0, s12
-; SI-NEXT: v_alignbit_b32 v0, 1, s8, v0
+; SI-NEXT: s_mov_b32 s6, s11
+; SI-NEXT: s_and_b32 s4, s15, 31
+; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], s4
+; SI-NEXT: s_mov_b32 s11, 9
+; SI-NEXT: s_and_b32 s5, s14, 31
+; SI-NEXT: s_lshr_b64 s[6:7], s[10:11], s5
+; SI-NEXT: s_mov_b32 s11, 7
+; SI-NEXT: s_mov_b32 s10, s9
+; SI-NEXT: s_and_b32 s5, s13, 31
+; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], s5
+; SI-NEXT: s_mov_b32 s9, 1
+; SI-NEXT: s_and_b32 s5, s12, 31
+; SI-NEXT: s_lshr_b64 s[8:9], s[8:9], s5
+; SI-NEXT: v_mov_b32_e32 v0, s8
+; SI-NEXT: v_mov_b32_e32 v1, s10
+; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v3, s4
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fshr_v4i32_imm_src0:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_mov_b32 s1, 33
+; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; VI-NEXT: s_mov_b32 s7, 7
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s15
-; VI-NEXT: v_mov_b32_e32 v1, s14
-; VI-NEXT: v_mov_b32_e32 v4, s13
-; VI-NEXT: v_alignbit_b32 v3, 33, s11, v0
-; VI-NEXT: v_alignbit_b32 v2, 9, s10, v1
-; VI-NEXT: v_alignbit_b32 v1, 7, s9, v4
-; VI-NEXT: v_mov_b32_e32 v0, s12
-; VI-NEXT: v_mov_b32_e32 v5, s1
-; VI-NEXT: v_alignbit_b32 v0, 1, s8, v0
-; VI-NEXT: v_mov_b32_e32 v4, s0
+; VI-NEXT: s_mov_b32 s0, s11
+; VI-NEXT: s_and_b32 s4, s15, 31
+; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], s4
+; VI-NEXT: s_mov_b32 s11, 9
+; VI-NEXT: s_and_b32 s1, s14, 31
+; VI-NEXT: s_lshr_b64 s[4:5], s[10:11], s1
+; VI-NEXT: s_mov_b32 s6, s9
+; VI-NEXT: s_and_b32 s1, s13, 31
+; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], s1
+; VI-NEXT: s_mov_b32 s9, 1
+; VI-NEXT: s_and_b32 s1, s12, 31
+; VI-NEXT: s_lshr_b64 s[8:9], s[8:9], s1
+; VI-NEXT: v_mov_b32_e32 v5, s3
+; VI-NEXT: v_mov_b32_e32 v0, s8
+; VI-NEXT: v_mov_b32_e32 v1, s6
+; VI-NEXT: v_mov_b32_e32 v2, s4
+; VI-NEXT: v_mov_b32_e32 v3, s0
+; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
index 76016e46426bd..92ea83fdfb982 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
@@ -238,11 +238,11 @@ define amdgpu_kernel void @s_insertelement_v2i16_0_reghi(ptr addrspace(1) %out,
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dword s2, s[2:3], 0x0
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_lshr_b32 s0, s2, 16
-; VI-NEXT: v_alignbit_b32 v2, s0, v2, 16
+; VI-NEXT: s_lshr_b32 s5, s2, 16
+; VI-NEXT: s_lshr_b64 s[0:1], s[4:5], 16
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
@@ -256,11 +256,11 @@ define amdgpu_kernel void @s_insertelement_v2i16_0_reghi(ptr addrspace(1) %out,
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_load_dword s2, s[2:3], 0x0
; CI-NEXT: v_mov_b32_e32 v0, s0
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: s_lshr_b32 s0, s2, 16
-; CI-NEXT: v_alignbit_b32 v2, s0, v2, 16
+; CI-NEXT: s_lshr_b32 s5, s2, 16
+; CI-NEXT: s_lshr_b64 s[0:1], s[4:5], 16
+; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm
;
@@ -312,16 +312,16 @@ define amdgpu_kernel void @s_insertelement_v2i16_0_reghi_multi_use_1(ptr addrspa
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dword s2, s[2:3], 0x0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: s_lshr_b32 s0, s4, 16
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_lshr_b32 s3, s4, 16
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_lshr_b32 s1, s2, 16
-; VI-NEXT: v_alignbit_b32 v2, s1, v2, 16
+; VI-NEXT: s_lshr_b32 s5, s2, 16
+; VI-NEXT: s_lshr_b64 s[0:1], s[4:5], 16
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: ;;#ASMSTART
-; VI-NEXT: ; use s0
+; VI-NEXT: ; use s3
; VI-NEXT: ;;#ASMEND
; VI-NEXT: s_endpgm
;
@@ -334,16 +334,16 @@ define amdgpu_kernel void @s_insertelement_v2i16_0_reghi_multi_use_1(ptr addrspa
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_load_dword s2, s[2:3], 0x0
-; CI-NEXT: v_mov_b32_e32 v1, s1
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v0, s0
-; CI-NEXT: s_lshr_b32 s0, s4, 16
+; CI-NEXT: v_mov_b32_e32 v1, s1
+; CI-NEXT: s_lshr_b32 s3, s4, 16
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: s_lshr_b32 s1, s2, 16
-; CI-NEXT: v_alignbit_b32 v2, s1, v2, 16
+; CI-NEXT: s_lshr_b32 s5, s2, 16
+; CI-NEXT: s_lshr_b64 s[0:1], s[4:5], 16
+; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: ;;#ASMSTART
-; CI-NEXT: ; use s0
+; CI-NEXT: ; use s3
; CI-NEXT: ;;#ASMEND
; CI-NEXT: s_endpgm
;
@@ -405,19 +405,19 @@ define amdgpu_kernel void @s_insertelement_v2i16_0_reghi_both_multi_use_1(ptr ad
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dword s2, s[2:3], 0x0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: s_lshr_b32 s0, s4, 16
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_lshr_b32 s3, s4, 16
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_lshr_b32 s1, s2, 16
-; VI-NEXT: v_alignbit_b32 v2, s1, v2, 16
+; VI-NEXT: s_lshr_b32 s5, s2, 16
+; VI-NEXT: s_lshr_b64 s[0:1], s[4:5], 16
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: ;;#ASMSTART
-; VI-NEXT: ; use s0
+; VI-NEXT: ; use s3
; VI-NEXT: ;;#ASMEND
; VI-NEXT: ;;#ASMSTART
-; VI-NEXT: ; use s1
+; VI-NEXT: ; use s5
; VI-NEXT: ;;#ASMEND
; VI-NEXT: s_endpgm
;
@@ -430,19 +430,19 @@ define amdgpu_kernel void @s_insertelement_v2i16_0_reghi_both_multi_use_1(ptr ad
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_load_dword s2, s[2:3], 0x0
-; CI-NEXT: v_mov_b32_e32 v1, s1
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v0, s0
-; CI-NEXT: s_lshr_b32 s0, s4, 16
+; CI-NEXT: v_mov_b32_e32 v1, s1
+; CI-NEXT: s_lshr_b32 s3, s4, 16
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: s_lshr_b32 s1, s2, 16
-; CI-NEXT: v_alignbit_b32 v2, s1, v2, 16
+; CI-NEXT: s_lshr_b32 s5, s2, 16
+; CI-NEXT: s_lshr_b64 s[0:1], s[4:5], 16
+; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: ;;#ASMSTART
-; CI-NEXT: ; use s0
+; CI-NEXT: ; use s3
; CI-NEXT: ;;#ASMEND
; CI-NEXT: ;;#ASMSTART
-; CI-NEXT: ; use s1
+; CI-NEXT: ; use s5
; CI-NEXT: ;;#ASMEND
; CI-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
index 6f63384be90fd..2d60c5729ed52 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
@@ -9775,17 +9775,17 @@ define amdgpu_kernel void @constant_zextload_v4i8_to_v4i16(ptr addrspace(1) %out
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NOHSA-NEXT: s_load_dword s4, s[2:3], 0x0
; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
-; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NOHSA-NEXT: s_and_b32 s5, s4, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s6, s4, 24
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
-; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xff
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v0, s6, v0, 16
-; GFX6-NOHSA-NEXT: s_lshl_b32 s5, s5, 8
-; GFX6-NOHSA-NEXT: s_or_b32 s4, s4, s5
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v0
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: s_lshr_b32 s5, s4, 24
+; GFX6-NOHSA-NEXT: s_and_b32 s2, s4, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s6, s4, 0xff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s2, s2, 8
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; GFX6-NOHSA-NEXT: s_or_b32 s5, s6, s2
+; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xff00ff
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NOHSA-NEXT: s_endpgm
;
@@ -9800,15 +9800,15 @@ define amdgpu_kernel void @constant_zextload_v4i8_to_v4i16(ptr addrspace(1) %out
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_lshr_b32 s3, s2, 24
; GFX7-HSA-NEXT: s_and_b32 s0, s2, 0xff00
-; GFX7-HSA-NEXT: s_lshr_b32 s1, s2, 24
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
-; GFX7-HSA-NEXT: s_and_b32 s2, s2, 0xff
-; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 8
-; GFX7-HSA-NEXT: v_alignbit_b32 v2, s1, v2, 16
-; GFX7-HSA-NEXT: s_or_b32 s0, s2, s0
-; GFX7-HSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v2
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-HSA-NEXT: s_and_b32 s4, s2, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s5, s0, 8
+; GFX7-HSA-NEXT: s_lshr_b64 s[0:1], s[2:3], 16
+; GFX7-HSA-NEXT: s_or_b32 s1, s4, s5
+; GFX7-HSA-NEXT: s_and_b32 s0, s0, 0xff00ff
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s0
; GFX7-HSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX7-HSA-NEXT: s_endpgm
;
@@ -9820,15 +9820,15 @@ define amdgpu_kernel void @constant_zextload_v4i8_to_v4i16(ptr addrspace(1) %out
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NOHSA-NEXT: s_lshr_b32 s0, s2, 24
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NOHSA-NEXT: s_and_b32 s1, s2, 0xff
-; GFX8-NOHSA-NEXT: s_lshl_b32 s2, s2, 8
-; GFX8-NOHSA-NEXT: v_alignbit_b32 v2, s0, v2, 16
-; GFX8-NOHSA-NEXT: s_and_b32 s0, s2, 0xff0000
-; GFX8-NOHSA-NEXT: s_or_b32 s0, s1, s0
-; GFX8-NOHSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v2
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NOHSA-NEXT: s_lshr_b32 s3, s2, 24
+; GFX8-NOHSA-NEXT: s_lshl_b32 s0, s2, 8
+; GFX8-NOHSA-NEXT: s_and_b32 s4, s2, 0xff
+; GFX8-NOHSA-NEXT: s_and_b32 s5, s0, 0xff0000
+; GFX8-NOHSA-NEXT: s_lshr_b64 s[0:1], s[2:3], 16
+; GFX8-NOHSA-NEXT: s_or_b32 s1, s4, s5
+; GFX8-NOHSA-NEXT: s_and_b32 s0, s0, 0xff00ff
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s0
; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-NOHSA-NEXT: s_endpgm
;
@@ -10062,26 +10062,28 @@ define amdgpu_kernel void @constant_zextload_v8i8_to_v8i16(ptr addrspace(1) %out
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NOHSA-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
-; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NOHSA-NEXT: s_and_b32 s6, s4, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s7, s4, 24
-; GFX6-NOHSA-NEXT: s_and_b32 s8, s5, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s9, s5, 24
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s5
-; GFX6-NOHSA-NEXT: s_and_b32 s5, s5, 0xff
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s4
-; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xff
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v0, s9, v0, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s2, s4, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s7, s5, 24
+; GFX6-NOHSA-NEXT: s_and_b32 s8, s4, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s9, s5, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s10, s5, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s11, s4, 0xff
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, s5
+; GFX6-NOHSA-NEXT: s_lshl_b32 s9, s9, 8
; GFX6-NOHSA-NEXT: s_lshl_b32 s8, s8, 8
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v1, s7, v1, 16
-; GFX6-NOHSA-NEXT: s_lshl_b32 s6, s6, 8
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v0
-; GFX6-NOHSA-NEXT: s_or_b32 s5, s5, s8
-; GFX6-NOHSA-NEXT: s_or_b32 s4, s4, s6
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v1
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s2
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; GFX6-NOHSA-NEXT: s_or_b32 s5, s10, s9
+; GFX6-NOHSA-NEXT: s_or_b32 s7, s11, s8
+; GFX6-NOHSA-NEXT: s_and_b32 s6, s6, 0xff00ff
+; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xff00ff
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s6
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX6-NOHSA-NEXT: s_endpgm
;
@@ -10096,24 +10098,26 @@ define amdgpu_kernel void @constant_zextload_v8i8_to_v8i16(ptr addrspace(1) %out
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-HSA-NEXT: s_lshr_b32 s5, s3, 24
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s3
-; GFX7-HSA-NEXT: v_alignbit_b32 v0, s5, v0, 16
; GFX7-HSA-NEXT: s_and_b32 s0, s2, 0xff00
-; GFX7-HSA-NEXT: s_lshr_b32 s1, s2, 24
-; GFX7-HSA-NEXT: s_and_b32 s4, s3, 0xff00
-; GFX7-HSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
-; GFX7-HSA-NEXT: s_and_b32 s3, s3, 0xff
-; GFX7-HSA-NEXT: s_lshl_b32 s4, s4, 8
-; GFX7-HSA-NEXT: v_alignbit_b32 v0, s1, v0, 16
-; GFX7-HSA-NEXT: s_and_b32 s1, s2, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s5, s3, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s6, s3, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s7, s2, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s5, s5, 8
; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 8
-; GFX7-HSA-NEXT: s_or_b32 s3, s3, s4
-; GFX7-HSA-NEXT: s_or_b32 s0, s1, s0
-; GFX7-HSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: s_lshr_b32 s4, s2, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s1, s3, 24
+; GFX7-HSA-NEXT: s_or_b32 s5, s6, s5
+; GFX7-HSA-NEXT: s_or_b32 s6, s7, s0
+; GFX7-HSA-NEXT: s_mov_b32 s0, s3
+; GFX7-HSA-NEXT: s_lshr_b64 s[0:1], s[0:1], 16
+; GFX7-HSA-NEXT: s_mov_b32 s3, s4
+; GFX7-HSA-NEXT: s_and_b32 s7, s0, 0xff00ff
+; GFX7-HSA-NEXT: s_lshr_b64 s[0:1], s[2:3], 16
+; GFX7-HSA-NEXT: s_and_b32 s0, s0, 0xff00ff
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_endpgm
;
@@ -10122,28 +10126,29 @@ define amdgpu_kernel void @constant_zextload_v8i8_to_v8i16(ptr addrspace(1) %out
; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NOHSA-NEXT: s_lshr_b32 s0, s2, 24
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NOHSA-NEXT: s_lshr_b32 s1, s3, 24
; GFX8-NOHSA-NEXT: s_bfe_u32 s4, s3, 0x80010
; GFX8-NOHSA-NEXT: s_and_b32 s5, s3, 0xff
; GFX8-NOHSA-NEXT: s_lshl_b32 s3, s3, 8
-; GFX8-NOHSA-NEXT: v_alignbit_b32 v0, s0, v0, 16
-; GFX8-NOHSA-NEXT: s_and_b32 s0, s2, 0xff
-; GFX8-NOHSA-NEXT: s_lshl_b32 s2, s2, 8
+; GFX8-NOHSA-NEXT: s_and_b32 s3, s3, 0xff0000
; GFX8-NOHSA-NEXT: s_lshl_b32 s1, s1, 16
+; GFX8-NOHSA-NEXT: s_or_b32 s5, s5, s3
+; GFX8-NOHSA-NEXT: s_lshl_b32 s3, s2, 8
+; GFX8-NOHSA-NEXT: s_lshr_b32 s0, s2, 24
+; GFX8-NOHSA-NEXT: s_or_b32 s4, s4, s1
+; GFX8-NOHSA-NEXT: s_and_b32 s1, s2, 0xff
; GFX8-NOHSA-NEXT: s_and_b32 s3, s3, 0xff0000
-; GFX8-NOHSA-NEXT: s_and_b32 s2, s2, 0xff0000
-; GFX8-NOHSA-NEXT: s_or_b32 s1, s4, s1
-; GFX8-NOHSA-NEXT: s_or_b32 s3, s5, s3
-; GFX8-NOHSA-NEXT: s_or_b32 s0, s0, s2
-; GFX8-NOHSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NOHSA-NEXT: s_or_b32 s6, s1, s3
+; GFX8-NOHSA-NEXT: s_mov_b32 s3, s0
+; GFX8-NOHSA-NEXT: s_lshr_b64 s[0:1], s[2:3], 16
+; GFX8-NOHSA-NEXT: s_and_b32 s0, s0, 0xff00ff
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s4
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_endpgm
;
@@ -10500,43 +10505,48 @@ define amdgpu_kernel void @constant_zextload_v16i8_to_v16i16(ptr addrspace(1) %o
; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NOHSA-NEXT: s_and_b32 s8, s6, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s9, s6, 24
-; GFX6-NOHSA-NEXT: s_and_b32 s10, s7, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s11, s7, 24
-; GFX6-NOHSA-NEXT: s_and_b32 s12, s4, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s13, s4, 24
-; GFX6-NOHSA-NEXT: s_and_b32 s14, s5, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s15, s5, 24
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s5
-; GFX6-NOHSA-NEXT: s_and_b32 s5, s5, 0xff
+; GFX6-NOHSA-NEXT: s_lshr_b32 s12, s6, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s9, s7, 24
+; GFX6-NOHSA-NEXT: s_and_b32 s13, s6, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s14, s7, 0xff00
+; GFX6-NOHSA-NEXT: s_lshr_b32 s15, s4, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s11, s5, 24
+; GFX6-NOHSA-NEXT: s_and_b32 s16, s4, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s17, s5, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s18, s5, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s19, s4, 0xff
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s5
+; GFX6-NOHSA-NEXT: s_and_b32 s20, s7, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s21, s6, 0xff
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s7
+; GFX6-NOHSA-NEXT: s_lshl_b32 s17, s17, 8
+; GFX6-NOHSA-NEXT: s_lshl_b32 s16, s16, 8
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[10:11], s[10:11], 16
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s15
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; GFX6-NOHSA-NEXT: s_lshl_b32 s5, s14, 8
+; GFX6-NOHSA-NEXT: s_lshl_b32 s11, s13, 8
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, s12
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
+; GFX6-NOHSA-NEXT: s_or_b32 s7, s18, s17
+; GFX6-NOHSA-NEXT: s_or_b32 s9, s19, s16
+; GFX6-NOHSA-NEXT: s_and_b32 s10, s10, 0xff00ff
+; GFX6-NOHSA-NEXT: s_or_b32 s5, s20, s5
+; GFX6-NOHSA-NEXT: s_or_b32 s11, s21, s11
+; GFX6-NOHSA-NEXT: s_and_b32 s8, s8, 0xff00ff
+; GFX6-NOHSA-NEXT: s_and_b32 s6, s6, 0xff00ff
+; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xff00ff
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s8
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s9
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s4
-; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xff
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
-; GFX6-NOHSA-NEXT: s_and_b32 s7, s7, 0xff
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s6
-; GFX6-NOHSA-NEXT: s_and_b32 s6, s6, 0xff
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v0, s15, v0, 16
-; GFX6-NOHSA-NEXT: s_lshl_b32 s14, s14, 8
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v1, s13, v1, 16
-; GFX6-NOHSA-NEXT: s_lshl_b32 s12, s12, 8
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v2, s11, v2, 16
-; GFX6-NOHSA-NEXT: s_lshl_b32 s10, s10, 8
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v4, s9, v3, 16
-; GFX6-NOHSA-NEXT: s_lshl_b32 s8, s8, 8
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v0
-; GFX6-NOHSA-NEXT: s_or_b32 s5, s5, s14
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v1
-; GFX6-NOHSA-NEXT: s_or_b32 s4, s4, s12
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v7, 0xff00ff, v2
-; GFX6-NOHSA-NEXT: s_or_b32 s7, s7, s10
-; GFX6-NOHSA-NEXT: s_or_b32 s6, s6, s8
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v5, 0xff00ff, v4
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s7
-; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s10
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX6-NOHSA-NEXT: s_endpgm
;
@@ -10549,48 +10559,52 @@ define amdgpu_kernel void @constant_zextload_v16i8_to_v16i16(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-HSA-NEXT: s_lshr_b32 s13, s5, 24
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s5
-; GFX7-HSA-NEXT: v_alignbit_b32 v0, s13, v0, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s11, s4, 24
-; GFX7-HSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
-; GFX7-HSA-NEXT: v_alignbit_b32 v0, s11, v0, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s9, s7, 24
-; GFX7-HSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s7
-; GFX7-HSA-NEXT: v_alignbit_b32 v0, s9, v0, 16
-; GFX7-HSA-NEXT: s_and_b32 s2, s6, 0xff00
-; GFX7-HSA-NEXT: s_lshr_b32 s3, s6, 24
-; GFX7-HSA-NEXT: s_and_b32 s8, s7, 0xff00
-; GFX7-HSA-NEXT: s_and_b32 s10, s4, 0xff00
-; GFX7-HSA-NEXT: s_and_b32 s12, s5, 0xff00
-; GFX7-HSA-NEXT: v_and_b32_e32 v7, 0xff00ff, v0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
-; GFX7-HSA-NEXT: s_and_b32 s5, s5, 0xff
-; GFX7-HSA-NEXT: s_lshl_b32 s12, s12, 8
-; GFX7-HSA-NEXT: s_and_b32 s4, s4, 0xff
-; GFX7-HSA-NEXT: s_lshl_b32 s10, s10, 8
-; GFX7-HSA-NEXT: s_and_b32 s7, s7, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s13, s5, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s8, s4, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s14, s5, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s13, s13, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s12, s4, 24
+; GFX7-HSA-NEXT: s_or_b32 s13, s14, s13
+; GFX7-HSA-NEXT: s_and_b32 s14, s4, 0xff
; GFX7-HSA-NEXT: s_lshl_b32 s8, s8, 8
-; GFX7-HSA-NEXT: v_alignbit_b32 v0, s3, v0, 16
-; GFX7-HSA-NEXT: s_and_b32 s3, s6, 0xff
+; GFX7-HSA-NEXT: s_lshr_b32 s9, s5, 24
+; GFX7-HSA-NEXT: s_or_b32 s14, s14, s8
+; GFX7-HSA-NEXT: s_mov_b32 s8, s5
+; GFX7-HSA-NEXT: s_mov_b32 s5, s12
+; GFX7-HSA-NEXT: s_and_b32 s11, s7, 0xff00
+; GFX7-HSA-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
+; GFX7-HSA-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; GFX7-HSA-NEXT: s_and_b32 s2, s6, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s5, s7, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s9, s11, 8
+; GFX7-HSA-NEXT: s_or_b32 s5, s5, s9
+; GFX7-HSA-NEXT: s_and_b32 s9, s6, 0xff
; GFX7-HSA-NEXT: s_lshl_b32 s2, s2, 8
-; GFX7-HSA-NEXT: s_or_b32 s5, s5, s12
-; GFX7-HSA-NEXT: s_or_b32 s4, s4, s10
-; GFX7-HSA-NEXT: s_or_b32 s7, s7, s8
-; GFX7-HSA-NEXT: s_or_b32 s2, s3, s2
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_lshr_b32 s10, s6, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s3, s7, 24
+; GFX7-HSA-NEXT: s_or_b32 s9, s9, s2
+; GFX7-HSA-NEXT: s_mov_b32 s2, s7
+; GFX7-HSA-NEXT: s_lshr_b64 s[2:3], s[2:3], 16
+; GFX7-HSA-NEXT: s_mov_b32 s7, s10
+; GFX7-HSA-NEXT: s_and_b32 s11, s2, 0xff00ff
+; GFX7-HSA-NEXT: s_lshr_b64 s[2:3], s[6:7], 16
+; GFX7-HSA-NEXT: s_and_b32 s8, s8, 0xff00ff
+; GFX7-HSA-NEXT: s_and_b32 s4, s4, 0xff00ff
+; GFX7-HSA-NEXT: s_and_b32 s2, s2, 0xff00ff
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s2
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s3
-; GFX7-HSA-NEXT: v_and_b32_e32 v5, 0xff00ff, v0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s7
-; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s2
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s9
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s8
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_endpgm
@@ -10601,50 +10615,52 @@ define amdgpu_kernel void @constant_zextload_v16i8_to_v16i16(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NOHSA-NEXT: s_lshr_b32 s3, s4, 24
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
-; GFX8-NOHSA-NEXT: v_alignbit_b32 v0, s3, v0, 16
-; GFX8-NOHSA-NEXT: s_and_b32 s3, s4, 0xff
-; GFX8-NOHSA-NEXT: s_lshl_b32 s4, s4, 8
-; GFX8-NOHSA-NEXT: s_lshr_b32 s8, s5, 24
-; GFX8-NOHSA-NEXT: s_and_b32 s4, s4, 0xff0000
+; GFX8-NOHSA-NEXT: s_lshr_b32 s3, s5, 24
; GFX8-NOHSA-NEXT: s_bfe_u32 s9, s5, 0x80010
-; GFX8-NOHSA-NEXT: s_lshl_b32 s8, s8, 16
-; GFX8-NOHSA-NEXT: s_or_b32 s4, s3, s4
-; GFX8-NOHSA-NEXT: s_lshr_b32 s3, s7, 24
-; GFX8-NOHSA-NEXT: s_lshr_b32 s2, s6, 24
-; GFX8-NOHSA-NEXT: s_or_b32 s8, s9, s8
-; GFX8-NOHSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v0
-; GFX8-NOHSA-NEXT: s_lshl_b32 s3, s3, 16
-; GFX8-NOHSA-NEXT: s_bfe_u32 s9, s7, 0x80010
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NOHSA-NEXT: s_and_b32 s10, s5, 0xff
; GFX8-NOHSA-NEXT: s_lshl_b32 s5, s5, 8
-; GFX8-NOHSA-NEXT: s_or_b32 s3, s9, s3
-; GFX8-NOHSA-NEXT: s_and_b32 s9, s7, 0xff
-; GFX8-NOHSA-NEXT: s_lshl_b32 s7, s7, 8
-; GFX8-NOHSA-NEXT: v_alignbit_b32 v0, s2, v0, 16
-; GFX8-NOHSA-NEXT: s_and_b32 s2, s6, 0xff
-; GFX8-NOHSA-NEXT: s_lshl_b32 s6, s6, 8
+; GFX8-NOHSA-NEXT: s_lshl_b32 s3, s3, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s2, s4, 24
; GFX8-NOHSA-NEXT: s_and_b32 s5, s5, 0xff0000
-; GFX8-NOHSA-NEXT: s_and_b32 s7, s7, 0xff0000
-; GFX8-NOHSA-NEXT: s_and_b32 s6, s6, 0xff0000
-; GFX8-NOHSA-NEXT: s_or_b32 s5, s10, s5
-; GFX8-NOHSA-NEXT: s_or_b32 s7, s9, s7
-; GFX8-NOHSA-NEXT: s_or_b32 s2, s2, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: s_or_b32 s9, s9, s3
+; GFX8-NOHSA-NEXT: s_lshl_b32 s3, s4, 8
+; GFX8-NOHSA-NEXT: s_and_b32 s11, s4, 0xff
+; GFX8-NOHSA-NEXT: s_or_b32 s10, s10, s5
+; GFX8-NOHSA-NEXT: s_and_b32 s3, s3, 0xff0000
+; GFX8-NOHSA-NEXT: s_mov_b32 s5, s2
+; GFX8-NOHSA-NEXT: s_or_b32 s11, s11, s3
+; GFX8-NOHSA-NEXT: s_lshr_b64 s[2:3], s[4:5], 16
+; GFX8-NOHSA-NEXT: s_and_b32 s4, s2, 0xff00ff
+; GFX8-NOHSA-NEXT: s_lshr_b32 s2, s7, 24
+; GFX8-NOHSA-NEXT: s_lshl_b32 s2, s2, 16
+; GFX8-NOHSA-NEXT: s_bfe_u32 s3, s7, 0x80010
+; GFX8-NOHSA-NEXT: s_or_b32 s5, s3, s2
+; GFX8-NOHSA-NEXT: s_lshl_b32 s3, s7, 8
+; GFX8-NOHSA-NEXT: s_and_b32 s2, s7, 0xff
+; GFX8-NOHSA-NEXT: s_and_b32 s3, s3, 0xff0000
+; GFX8-NOHSA-NEXT: s_lshr_b32 s8, s6, 24
+; GFX8-NOHSA-NEXT: s_or_b32 s12, s2, s3
+; GFX8-NOHSA-NEXT: s_lshl_b32 s3, s6, 8
+; GFX8-NOHSA-NEXT: s_and_b32 s2, s6, 0xff
+; GFX8-NOHSA-NEXT: s_and_b32 s3, s3, 0xff0000
+; GFX8-NOHSA-NEXT: s_mov_b32 s7, s8
+; GFX8-NOHSA-NEXT: s_or_b32 s13, s2, s3
+; GFX8-NOHSA-NEXT: s_lshr_b64 s[2:3], s[6:7], 16
+; GFX8-NOHSA-NEXT: s_and_b32 s2, s2, 0xff00ff
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s2
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s3
-; GFX8-NOHSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s7
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s2
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[2:5]
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s9
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_endpgm
@@ -11272,81 +11288,92 @@ define amdgpu_kernel void @constant_zextload_v32i8_to_v32i16(ptr addrspace(1) %o
; GFX6-NOHSA-NEXT: s_mov_b32 s11, 0xf000
; GFX6-NOHSA-NEXT: s_mov_b32 s10, -1
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NOHSA-NEXT: s_and_b32 s12, s6, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s13, s6, 24
-; GFX6-NOHSA-NEXT: s_and_b32 s14, s7, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s15, s7, 24
-; GFX6-NOHSA-NEXT: s_and_b32 s16, s4, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s17, s4, 24
-; GFX6-NOHSA-NEXT: s_and_b32 s18, s5, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s19, s5, 24
-; GFX6-NOHSA-NEXT: s_and_b32 s20, s2, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s21, s2, 24
-; GFX6-NOHSA-NEXT: s_and_b32 s22, s3, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s23, s3, 24
-; GFX6-NOHSA-NEXT: s_and_b32 s24, s0, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s25, s0, 24
-; GFX6-NOHSA-NEXT: s_and_b32 s26, s1, 0xff00
-; GFX6-NOHSA-NEXT: s_lshr_b32 s27, s1, 24
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s1
-; GFX6-NOHSA-NEXT: s_and_b32 s1, s1, 0xff
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s0
-; GFX6-NOHSA-NEXT: s_and_b32 s0, s0, 0xff
+; GFX6-NOHSA-NEXT: s_lshr_b32 s20, s6, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s13, s7, 24
+; GFX6-NOHSA-NEXT: s_and_b32 s21, s6, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s22, s7, 0xff00
+; GFX6-NOHSA-NEXT: s_lshr_b32 s23, s4, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s15, s5, 24
+; GFX6-NOHSA-NEXT: s_and_b32 s24, s4, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s25, s5, 0xff00
+; GFX6-NOHSA-NEXT: s_lshr_b32 s26, s2, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s17, s3, 24
+; GFX6-NOHSA-NEXT: s_and_b32 s27, s2, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s28, s3, 0xff00
+; GFX6-NOHSA-NEXT: s_lshr_b32 s29, s0, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s19, s1, 24
+; GFX6-NOHSA-NEXT: s_and_b32 s30, s0, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s31, s1, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s33, s1, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s34, s0, 0xff
+; GFX6-NOHSA-NEXT: s_mov_b32 s18, s1
+; GFX6-NOHSA-NEXT: s_and_b32 s35, s3, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s36, s2, 0xff
+; GFX6-NOHSA-NEXT: s_mov_b32 s16, s3
+; GFX6-NOHSA-NEXT: s_and_b32 s37, s5, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s38, s4, 0xff
+; GFX6-NOHSA-NEXT: s_mov_b32 s14, s5
+; GFX6-NOHSA-NEXT: s_and_b32 s39, s7, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s40, s6, 0xff
+; GFX6-NOHSA-NEXT: s_mov_b32 s12, s7
+; GFX6-NOHSA-NEXT: s_lshl_b32 s31, s31, 8
+; GFX6-NOHSA-NEXT: s_lshl_b32 s30, s30, 8
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[18:19], s[18:19], 16
+; GFX6-NOHSA-NEXT: s_mov_b32 s1, s29
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[0:1], s[0:1], 16
+; GFX6-NOHSA-NEXT: s_lshl_b32 s1, s28, 8
+; GFX6-NOHSA-NEXT: s_lshl_b32 s19, s27, 8
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[16:17], s[16:17], 16
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, s26
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[2:3], s[2:3], 16
+; GFX6-NOHSA-NEXT: s_lshl_b32 s3, s25, 8
+; GFX6-NOHSA-NEXT: s_lshl_b32 s17, s24, 8
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[14:15], s[14:15], 16
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s23
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; GFX6-NOHSA-NEXT: s_lshl_b32 s5, s22, 8
+; GFX6-NOHSA-NEXT: s_lshl_b32 s15, s21, 8
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[12:13], s[12:13], 16
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, s20
+; GFX6-NOHSA-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
+; GFX6-NOHSA-NEXT: s_or_b32 s7, s33, s31
+; GFX6-NOHSA-NEXT: s_or_b32 s13, s34, s30
+; GFX6-NOHSA-NEXT: s_and_b32 s18, s18, 0xff00ff
+; GFX6-NOHSA-NEXT: s_and_b32 s0, s0, 0xff00ff
+; GFX6-NOHSA-NEXT: s_or_b32 s1, s35, s1
+; GFX6-NOHSA-NEXT: s_or_b32 s19, s36, s19
+; GFX6-NOHSA-NEXT: s_and_b32 s16, s16, 0xff00ff
+; GFX6-NOHSA-NEXT: s_and_b32 s2, s2, 0xff00ff
+; GFX6-NOHSA-NEXT: s_or_b32 s3, s37, s3
+; GFX6-NOHSA-NEXT: s_or_b32 s17, s38, s17
+; GFX6-NOHSA-NEXT: s_and_b32 s14, s14, 0xff00ff
+; GFX6-NOHSA-NEXT: s_or_b32 s5, s39, s5
+; GFX6-NOHSA-NEXT: s_or_b32 s15, s40, s15
+; GFX6-NOHSA-NEXT: s_and_b32 s12, s12, 0xff00ff
+; GFX6-NOHSA-NEXT: s_and_b32 s6, s6, 0xff00ff
+; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xff00ff
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s15
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s12
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s17
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s3
-; GFX6-NOHSA-NEXT: s_and_b32 s3, s3, 0xff
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s2
-; GFX6-NOHSA-NEXT: s_and_b32 s2, s2, 0xff
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s5
-; GFX6-NOHSA-NEXT: s_and_b32 s5, s5, 0xff
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s4
-; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xff
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s7
-; GFX6-NOHSA-NEXT: s_and_b32 s7, s7, 0xff
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s6
-; GFX6-NOHSA-NEXT: s_and_b32 s6, s6, 0xff
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v0, s27, v0, 16
-; GFX6-NOHSA-NEXT: s_lshl_b32 s26, s26, 8
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v1, s25, v1, 16
-; GFX6-NOHSA-NEXT: s_lshl_b32 s24, s24, 8
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v2, s23, v2, 16
-; GFX6-NOHSA-NEXT: s_lshl_b32 s22, s22, 8
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v8, s21, v3, 16
-; GFX6-NOHSA-NEXT: s_lshl_b32 s20, s20, 8
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v4, s19, v4, 16
-; GFX6-NOHSA-NEXT: s_lshl_b32 s18, s18, 8
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v9, s17, v5, 16
-; GFX6-NOHSA-NEXT: s_lshl_b32 s16, s16, 8
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v6, s15, v6, 16
-; GFX6-NOHSA-NEXT: s_lshl_b32 s14, s14, 8
-; GFX6-NOHSA-NEXT: v_alignbit_b32 v10, s13, v7, 16
-; GFX6-NOHSA-NEXT: s_lshl_b32 s12, s12, 8
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v0
-; GFX6-NOHSA-NEXT: s_or_b32 s1, s1, s26
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v1
-; GFX6-NOHSA-NEXT: s_or_b32 s0, s0, s24
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v7, 0xff00ff, v2
-; GFX6-NOHSA-NEXT: s_or_b32 s3, s3, s22
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v5, 0xff00ff, v8
-; GFX6-NOHSA-NEXT: s_or_b32 s2, s2, s20
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v11, 0xff00ff, v4
-; GFX6-NOHSA-NEXT: s_or_b32 s5, s5, s18
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v9, 0xff00ff, v9
-; GFX6-NOHSA-NEXT: s_or_b32 s4, s4, s16
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v15, 0xff00ff, v6
-; GFX6-NOHSA-NEXT: s_or_b32 s7, s7, s14
-; GFX6-NOHSA-NEXT: s_or_b32 s6, s6, s12
-; GFX6-NOHSA-NEXT: v_and_b32_e32 v13, 0xff00ff, v10
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v12, s6
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v14, s7
-; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[8:11], 0 offset:48
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v8, s4
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s5
-; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[8:11], 0 offset:32
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s2
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s3
-; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s19
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s16
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s18
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GFX6-NOHSA-NEXT: s_endpgm
;
@@ -11354,99 +11381,106 @@ define amdgpu_kernel void @constant_zextload_v32i8_to_v32i16(ptr addrspace(1) %o
; GFX7-HSA: ; %bb.0:
; GFX7-HSA-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0
; GFX7-HSA-NEXT: s_add_i32 s12, s12, s17
-; GFX7-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX7-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX7-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-HSA-NEXT: s_lshr_b32 s25, s1, 24
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s1
-; GFX7-HSA-NEXT: v_alignbit_b32 v0, s25, v0, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s23, s0, 24
-; GFX7-HSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
-; GFX7-HSA-NEXT: v_alignbit_b32 v0, s23, v0, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s21, s3, 24
-; GFX7-HSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s3
-; GFX7-HSA-NEXT: v_alignbit_b32 v0, s21, v0, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s19, s2, 24
-; GFX7-HSA-NEXT: s_and_b32 s24, s1, 0xff00
-; GFX7-HSA-NEXT: v_and_b32_e32 v7, 0xff00ff, v0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
-; GFX7-HSA-NEXT: s_and_b32 s22, s0, 0xff00
-; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xff
-; GFX7-HSA-NEXT: s_lshl_b32 s24, s24, 8
-; GFX7-HSA-NEXT: v_alignbit_b32 v0, s19, v0, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s17, s5, 24
+; GFX7-HSA-NEXT: s_and_b32 s22, s1, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s12, s0, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s23, s1, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s22, s22, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s21, s0, 24
+; GFX7-HSA-NEXT: s_or_b32 s22, s23, s22
+; GFX7-HSA-NEXT: s_and_b32 s23, s0, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s12, s12, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s13, s1, 24
+; GFX7-HSA-NEXT: s_or_b32 s23, s23, s12
+; GFX7-HSA-NEXT: s_mov_b32 s12, s1
+; GFX7-HSA-NEXT: s_mov_b32 s1, s21
; GFX7-HSA-NEXT: s_and_b32 s20, s3, 0xff00
-; GFX7-HSA-NEXT: s_or_b32 s24, s1, s24
-; GFX7-HSA-NEXT: s_and_b32 s0, s0, 0xff
-; GFX7-HSA-NEXT: s_lshl_b32 s1, s22, 8
-; GFX7-HSA-NEXT: v_and_b32_e32 v5, 0xff00ff, v0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s5
-; GFX7-HSA-NEXT: s_and_b32 s18, s2, 0xff00
-; GFX7-HSA-NEXT: s_or_b32 s22, s0, s1
+; GFX7-HSA-NEXT: s_lshr_b64 s[12:13], s[12:13], 16
+; GFX7-HSA-NEXT: s_lshr_b64 s[0:1], s[0:1], 16
+; GFX7-HSA-NEXT: s_and_b32 s19, s2, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s13, s0, 0xff00ff
; GFX7-HSA-NEXT: s_and_b32 s0, s3, 0xff
; GFX7-HSA-NEXT: s_lshl_b32 s1, s20, 8
-; GFX7-HSA-NEXT: v_alignbit_b32 v0, s17, v0, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s15, s4, 24
-; GFX7-HSA-NEXT: s_and_b32 s16, s5, 0xff00
-; GFX7-HSA-NEXT: s_or_b32 s3, s0, s1
+; GFX7-HSA-NEXT: s_or_b32 s20, s0, s1
; GFX7-HSA-NEXT: s_and_b32 s0, s2, 0xff
-; GFX7-HSA-NEXT: s_lshl_b32 s1, s18, 8
-; GFX7-HSA-NEXT: v_and_b32_e32 v11, 0xff00ff, v0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
-; GFX7-HSA-NEXT: s_and_b32 s14, s4, 0xff00
-; GFX7-HSA-NEXT: s_or_b32 s2, s0, s1
+; GFX7-HSA-NEXT: s_lshl_b32 s1, s19, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s18, s2, 24
+; GFX7-HSA-NEXT: s_or_b32 s19, s0, s1
+; GFX7-HSA-NEXT: s_lshr_b32 s1, s3, 24
+; GFX7-HSA-NEXT: s_mov_b32 s0, s3
+; GFX7-HSA-NEXT: s_lshr_b64 s[0:1], s[0:1], 16
+; GFX7-HSA-NEXT: s_mov_b32 s3, s18
+; GFX7-HSA-NEXT: s_and_b32 s17, s5, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s21, s0, 0xff00ff
+; GFX7-HSA-NEXT: s_lshr_b64 s[0:1], s[2:3], 16
+; GFX7-HSA-NEXT: s_and_b32 s10, s4, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s2, s0, 0xff00ff
; GFX7-HSA-NEXT: s_and_b32 s0, s5, 0xff
-; GFX7-HSA-NEXT: s_lshl_b32 s1, s16, 8
-; GFX7-HSA-NEXT: v_alignbit_b32 v0, s15, v0, 16
-; GFX7-HSA-NEXT: s_and_b32 s12, s7, 0xff00
-; GFX7-HSA-NEXT: s_lshr_b32 s13, s7, 24
-; GFX7-HSA-NEXT: s_or_b32 s5, s0, s1
-; GFX7-HSA-NEXT: v_and_b32_e32 v9, 0xff00ff, v0
+; GFX7-HSA-NEXT: s_lshl_b32 s1, s17, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s16, s4, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s11, s5, 24
+; GFX7-HSA-NEXT: s_or_b32 s3, s0, s1
; GFX7-HSA-NEXT: s_and_b32 s0, s4, 0xff
-; GFX7-HSA-NEXT: s_lshl_b32 s1, s14, 8
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s7
-; GFX7-HSA-NEXT: s_and_b32 s10, s6, 0xff00
-; GFX7-HSA-NEXT: s_or_b32 s4, s0, s1
-; GFX7-HSA-NEXT: v_alignbit_b32 v0, s13, v0, 16
+; GFX7-HSA-NEXT: s_lshl_b32 s1, s10, 8
+; GFX7-HSA-NEXT: s_mov_b32 s10, s5
+; GFX7-HSA-NEXT: s_or_b32 s17, s0, s1
+; GFX7-HSA-NEXT: s_lshr_b64 s[0:1], s[10:11], 16
+; GFX7-HSA-NEXT: s_mov_b32 s5, s16
+; GFX7-HSA-NEXT: s_and_b32 s15, s7, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s10, s0, 0xff00ff
+; GFX7-HSA-NEXT: s_lshr_b64 s[0:1], s[4:5], 16
+; GFX7-HSA-NEXT: s_and_b32 s14, s6, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s4, s0, 0xff00ff
; GFX7-HSA-NEXT: s_and_b32 s0, s7, 0xff
-; GFX7-HSA-NEXT: s_lshl_b32 s1, s12, 8
-; GFX7-HSA-NEXT: s_lshr_b32 s11, s6, 24
-; GFX7-HSA-NEXT: v_and_b32_e32 v15, 0xff00ff, v0
-; GFX7-HSA-NEXT: s_or_b32 s0, s0, s1
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
-; GFX7-HSA-NEXT: s_and_b32 s1, s6, 0xff
-; GFX7-HSA-NEXT: s_lshl_b32 s6, s10, 8
-; GFX7-HSA-NEXT: s_or_b32 s1, s1, s6
-; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s0
+; GFX7-HSA-NEXT: s_lshl_b32 s1, s15, 8
+; GFX7-HSA-NEXT: s_or_b32 s5, s0, s1
+; GFX7-HSA-NEXT: s_and_b32 s0, s6, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s1, s14, 8
+; GFX7-HSA-NEXT: s_or_b32 s11, s0, s1
+; GFX7-HSA-NEXT: s_lshr_b32 s1, s7, 24
+; GFX7-HSA-NEXT: s_mov_b32 s0, s7
+; GFX7-HSA-NEXT: s_lshr_b64 s[0:1], s[0:1], 16
+; GFX7-HSA-NEXT: s_lshr_b32 s7, s6, 24
+; GFX7-HSA-NEXT: s_and_b32 s14, s0, 0xff00ff
+; GFX7-HSA-NEXT: s_lshr_b64 s[0:1], s[6:7], 16
+; GFX7-HSA-NEXT: s_and_b32 s12, s12, 0xff00ff
+; GFX7-HSA-NEXT: s_and_b32 s0, s0, 0xff00ff
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s0
; GFX7-HSA-NEXT: s_add_u32 s0, s8, 48
-; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s1
; GFX7-HSA-NEXT: s_addc_u32 s1, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s1
-; GFX7-HSA-NEXT: v_alignbit_b32 v0, s11, v0, 16
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
; GFX7-HSA-NEXT: s_add_u32 s0, s8, 32
-; GFX7-HSA-NEXT: v_and_b32_e32 v13, 0xff00ff, v0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s14
; GFX7-HSA-NEXT: s_addc_u32 s1, s9, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s4
-; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s1
-; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
; GFX7-HSA-NEXT: s_add_u32 s0, s8, 16
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s10
; GFX7-HSA-NEXT: s_addc_u32 s1, s9, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s1
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s3
-; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s22
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s21
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_endpgm
@@ -11463,90 +11497,94 @@ define amdgpu_kernel void @constant_zextload_v32i8_to_v32i16(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: s_lshl_b32 s1, s1, 8
; GFX8-NOHSA-NEXT: s_lshl_b32 s14, s14, 16
; GFX8-NOHSA-NEXT: s_and_b32 s1, s1, 0xff0000
-; GFX8-NOHSA-NEXT: s_lshr_b32 s13, s0, 24
; GFX8-NOHSA-NEXT: s_or_b32 s14, s15, s14
; GFX8-NOHSA-NEXT: s_or_b32 s15, s16, s1
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: s_lshl_b32 s16, s0, 8
+; GFX8-NOHSA-NEXT: s_lshr_b32 s13, s0, 24
; GFX8-NOHSA-NEXT: s_and_b32 s1, s0, 0xff
-; GFX8-NOHSA-NEXT: s_lshl_b32 s0, s0, 8
-; GFX8-NOHSA-NEXT: s_and_b32 s0, s0, 0xff0000
-; GFX8-NOHSA-NEXT: v_alignbit_b32 v0, s13, v0, 16
-; GFX8-NOHSA-NEXT: s_or_b32 s13, s1, s0
+; GFX8-NOHSA-NEXT: s_and_b32 s16, s16, 0xff0000
+; GFX8-NOHSA-NEXT: s_or_b32 s16, s1, s16
+; GFX8-NOHSA-NEXT: s_mov_b32 s1, s13
+; GFX8-NOHSA-NEXT: s_lshr_b64 s[0:1], s[0:1], 16
+; GFX8-NOHSA-NEXT: s_and_b32 s13, s0, 0xff00ff
; GFX8-NOHSA-NEXT: s_lshr_b32 s0, s3, 24
; GFX8-NOHSA-NEXT: s_lshl_b32 s0, s0, 16
; GFX8-NOHSA-NEXT: s_bfe_u32 s1, s3, 0x80010
-; GFX8-NOHSA-NEXT: s_or_b32 s16, s1, s0
+; GFX8-NOHSA-NEXT: s_or_b32 s17, s1, s0
; GFX8-NOHSA-NEXT: s_lshl_b32 s1, s3, 8
; GFX8-NOHSA-NEXT: s_and_b32 s0, s3, 0xff
; GFX8-NOHSA-NEXT: s_and_b32 s1, s1, 0xff0000
-; GFX8-NOHSA-NEXT: s_or_b32 s3, s0, s1
+; GFX8-NOHSA-NEXT: s_lshr_b32 s12, s2, 24
+; GFX8-NOHSA-NEXT: s_or_b32 s18, s0, s1
; GFX8-NOHSA-NEXT: s_lshl_b32 s1, s2, 8
; GFX8-NOHSA-NEXT: s_and_b32 s0, s2, 0xff
; GFX8-NOHSA-NEXT: s_and_b32 s1, s1, 0xff0000
-; GFX8-NOHSA-NEXT: s_lshr_b32 s12, s2, 24
-; GFX8-NOHSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
-; GFX8-NOHSA-NEXT: s_or_b32 s2, s0, s1
+; GFX8-NOHSA-NEXT: s_mov_b32 s3, s12
+; GFX8-NOHSA-NEXT: s_or_b32 s19, s0, s1
+; GFX8-NOHSA-NEXT: s_lshr_b64 s[0:1], s[2:3], 16
+; GFX8-NOHSA-NEXT: s_and_b32 s2, s0, 0xff00ff
; GFX8-NOHSA-NEXT: s_lshr_b32 s0, s5, 24
; GFX8-NOHSA-NEXT: s_lshl_b32 s0, s0, 16
; GFX8-NOHSA-NEXT: s_bfe_u32 s1, s5, 0x80010
-; GFX8-NOHSA-NEXT: v_alignbit_b32 v0, s12, v0, 16
-; GFX8-NOHSA-NEXT: s_or_b32 s12, s1, s0
+; GFX8-NOHSA-NEXT: s_or_b32 s3, s1, s0
; GFX8-NOHSA-NEXT: s_lshl_b32 s1, s5, 8
; GFX8-NOHSA-NEXT: s_and_b32 s0, s5, 0xff
; GFX8-NOHSA-NEXT: s_and_b32 s1, s1, 0xff0000
-; GFX8-NOHSA-NEXT: s_or_b32 s5, s0, s1
+; GFX8-NOHSA-NEXT: s_lshr_b32 s11, s4, 24
+; GFX8-NOHSA-NEXT: s_or_b32 s12, s0, s1
; GFX8-NOHSA-NEXT: s_lshl_b32 s1, s4, 8
; GFX8-NOHSA-NEXT: s_and_b32 s0, s4, 0xff
; GFX8-NOHSA-NEXT: s_and_b32 s1, s1, 0xff0000
-; GFX8-NOHSA-NEXT: s_lshr_b32 s11, s4, 24
-; GFX8-NOHSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
-; GFX8-NOHSA-NEXT: s_or_b32 s4, s0, s1
+; GFX8-NOHSA-NEXT: s_mov_b32 s5, s11
+; GFX8-NOHSA-NEXT: s_or_b32 s20, s0, s1
+; GFX8-NOHSA-NEXT: s_lshr_b64 s[0:1], s[4:5], 16
+; GFX8-NOHSA-NEXT: s_and_b32 s4, s0, 0xff00ff
; GFX8-NOHSA-NEXT: s_lshr_b32 s0, s7, 24
; GFX8-NOHSA-NEXT: s_lshl_b32 s0, s0, 16
; GFX8-NOHSA-NEXT: s_bfe_u32 s1, s7, 0x80010
-; GFX8-NOHSA-NEXT: s_or_b32 s0, s1, s0
-; GFX8-NOHSA-NEXT: s_and_b32 s1, s7, 0xff
-; GFX8-NOHSA-NEXT: s_lshl_b32 s7, s7, 8
-; GFX8-NOHSA-NEXT: v_alignbit_b32 v0, s11, v0, 16
-; GFX8-NOHSA-NEXT: s_and_b32 s7, s7, 0xff0000
+; GFX8-NOHSA-NEXT: s_or_b32 s5, s1, s0
+; GFX8-NOHSA-NEXT: s_lshl_b32 s1, s7, 8
+; GFX8-NOHSA-NEXT: s_and_b32 s0, s7, 0xff
+; GFX8-NOHSA-NEXT: s_and_b32 s1, s1, 0xff0000
; GFX8-NOHSA-NEXT: s_lshr_b32 s10, s6, 24
-; GFX8-NOHSA-NEXT: v_and_b32_e32 v5, 0xff00ff, v0
-; GFX8-NOHSA-NEXT: s_or_b32 s1, s1, s7
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NOHSA-NEXT: s_and_b32 s7, s6, 0xff
-; GFX8-NOHSA-NEXT: s_lshl_b32 s6, s6, 8
-; GFX8-NOHSA-NEXT: s_and_b32 s6, s6, 0xff0000
-; GFX8-NOHSA-NEXT: s_or_b32 s6, s7, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s0
+; GFX8-NOHSA-NEXT: s_or_b32 s11, s0, s1
+; GFX8-NOHSA-NEXT: s_lshl_b32 s1, s6, 8
+; GFX8-NOHSA-NEXT: s_and_b32 s0, s6, 0xff
+; GFX8-NOHSA-NEXT: s_and_b32 s1, s1, 0xff0000
+; GFX8-NOHSA-NEXT: s_mov_b32 s7, s10
+; GFX8-NOHSA-NEXT: s_or_b32 s21, s0, s1
+; GFX8-NOHSA-NEXT: s_lshr_b64 s[0:1], s[6:7], 16
+; GFX8-NOHSA-NEXT: s_and_b32 s0, s0, 0xff00ff
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 48
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s1
; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s1
-; GFX8-NOHSA-NEXT: v_alignbit_b32 v0, s10, v0, 16
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 32
-; GFX8-NOHSA-NEXT: v_and_b32_e32 v7, 0xff00ff, v0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s21
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[6:9]
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s1
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 16
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s5
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s1
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s3
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s16
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[2:5]
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s13
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s19
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s17
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s15
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s14
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
index f879dc660203f..e6133535f78e0 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
@@ -9829,14 +9829,14 @@ define amdgpu_kernel void @global_zextload_v4i8_to_v4i16(ptr addrspace(1) %out,
; GCN-NOHSA-SI-NEXT: s_mov_b32 s4, s0
; GCN-NOHSA-SI-NEXT: s_mov_b32 s5, s1
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v1, 0xff00, v0
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v2, 24, v0
+; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v1, 24, v0
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, 0xff00, v0
; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v3, 0xff, v0
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v2, 8, v1
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v1, 0xff00ff, v0
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v0, v3, v2
-; GCN-NOHSA-SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GCN-NOHSA-SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v1, v3, v2
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, 0xff00ff, v0
+; GCN-NOHSA-SI-NEXT: buffer_store_dwordx2 v[1:2], off, s[4:7], 0
; GCN-NOHSA-SI-NEXT: s_endpgm
;
; GCN-HSA-LABEL: global_zextload_v4i8_to_v4i16:
@@ -9848,18 +9848,18 @@ define amdgpu_kernel void @global_zextload_v4i8_to_v4i16(ptr addrspace(1) %out,
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: flat_load_dword v2, v[0:1]
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GCN-HSA-NEXT: flat_load_dword v0, v[0:1]
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s1
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
-; GCN-HSA-NEXT: v_and_b32_e32 v3, 0xff00, v2
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v4, 24, v2
-; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xff, v2
-; GCN-HSA-NEXT: v_alignbit_b32 v2, v4, v2, 16
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v4, 8, v3
-; GCN-HSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v2
-; GCN-HSA-NEXT: v_or_b32_e32 v2, v5, v4
-; GCN-HSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 24, v0
+; GCN-HSA-NEXT: v_and_b32_e32 v4, 0xff00, v0
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xff, v0
+; GCN-HSA-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; GCN-HSA-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GCN-HSA-NEXT: v_or_b32_e32 v4, v5, v4
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xff00ff, v0
+; GCN-HSA-NEXT: flat_store_dwordx2 v[2:3], v[4:5]
; GCN-HSA-NEXT: s_endpgm
;
; GCN-NOHSA-VI-LABEL: global_zextload_v4i8_to_v4i16:
@@ -9878,10 +9878,10 @@ define amdgpu_kernel void @global_zextload_v4i8_to_v4i16(ptr addrspace(1) %out,
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 24, v0
; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v2, 8, v0
-; GCN-NOHSA-VI-NEXT: v_alignbit_b32 v1, v1, v0, 16
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v2, 0xff0000, v2
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v3, 0xff0000, v2
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b64 v[1:2], 16, v[0:1]
+; GCN-NOHSA-VI-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v1, 0xff00ff, v1
-; GCN-NOHSA-VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NOHSA-VI-NEXT: s_endpgm
;
@@ -10180,33 +10180,39 @@ define amdgpu_kernel void @global_sextload_v4i8_to_v4i16(ptr addrspace(1) %out,
define amdgpu_kernel void @global_zextload_v8i8_to_v8i16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
; GCN-NOHSA-SI-LABEL: global_zextload_v8i8_to_v8i16:
; GCN-NOHSA-SI: ; %bb.0:
-; GCN-NOHSA-SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s6, -1
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s10, s6
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s11, s7
+; GCN-NOHSA-SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s3, 0xf000
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s2, -1
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s10, s2
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s11, s3
; GCN-NOHSA-SI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s2
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s3
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s6
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s7
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s4, s0
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s5, s1
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, 0xff00, v0
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, 0xff00, v1
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v5, 24, v1
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v6, 0xff, v1
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v7, 0xff, v0
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v1, v5, v1, 16
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v0, v3, v0, 16
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v5, 8, v2
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v3, 0xff00ff, v1
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v2, v6, v4
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v1, 0xff00ff, v0
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v0, v7, v5
-; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s6, v1
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s1, s0, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s7, s6, 24
+; GCN-NOHSA-SI-NEXT: s_and_b32 s8, s0, 0xff00
+; GCN-NOHSA-SI-NEXT: s_and_b32 s9, s6, 0xff00
+; GCN-NOHSA-SI-NEXT: s_and_b32 s10, s6, 0xff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s11, s0, 0xff
+; GCN-NOHSA-SI-NEXT: s_lshl_b32 s9, s9, 8
+; GCN-NOHSA-SI-NEXT: s_lshl_b32 s8, s8, 8
+; GCN-NOHSA-SI-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b64 s[0:1], s[0:1], 16
+; GCN-NOHSA-SI-NEXT: s_or_b32 s7, s10, s9
+; GCN-NOHSA-SI-NEXT: s_or_b32 s8, s11, s8
+; GCN-NOHSA-SI-NEXT: s_and_b32 s6, s6, 0xff00ff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s9, s0, 0xff00ff
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s8
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s9
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s7
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s6
+; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NOHSA-SI-NEXT: s_endpgm
;
; GCN-HSA-LABEL: global_zextload_v8i8_to_v8i16:
@@ -10222,20 +10228,26 @@ define amdgpu_kernel void @global_zextload_v8i8_to_v8i16(ptr addrspace(1) %out,
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
-; GCN-HSA-NEXT: v_and_b32_e32 v2, 0xff00, v0
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GCN-HSA-NEXT: v_and_b32_e32 v6, 0xff00, v1
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 24, v1
-; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xff, v1
-; GCN-HSA-NEXT: v_and_b32_e32 v9, 0xff, v0
-; GCN-HSA-NEXT: v_alignbit_b32 v1, v7, v1, 16
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; GCN-HSA-NEXT: v_alignbit_b32 v0, v3, v0, 16
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v7, 8, v2
-; GCN-HSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v1
-; GCN-HSA-NEXT: v_or_b32_e32 v2, v8, v6
-; GCN-HSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v0
-; GCN-HSA-NEXT: v_or_b32_e32 v0, v9, v7
+; GCN-HSA-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-HSA-NEXT: v_readfirstlane_b32 s2, v1
+; GCN-HSA-NEXT: s_lshr_b32 s1, s0, 24
+; GCN-HSA-NEXT: s_lshr_b32 s3, s2, 24
+; GCN-HSA-NEXT: s_and_b32 s4, s0, 0xff00
+; GCN-HSA-NEXT: s_and_b32 s5, s2, 0xff00
+; GCN-HSA-NEXT: s_and_b32 s6, s2, 0xff
+; GCN-HSA-NEXT: s_and_b32 s7, s0, 0xff
+; GCN-HSA-NEXT: s_lshl_b32 s5, s5, 8
+; GCN-HSA-NEXT: s_lshl_b32 s4, s4, 8
+; GCN-HSA-NEXT: s_lshr_b64 s[2:3], s[2:3], 16
+; GCN-HSA-NEXT: s_lshr_b64 s[0:1], s[0:1], 16
+; GCN-HSA-NEXT: s_or_b32 s1, s6, s5
+; GCN-HSA-NEXT: s_or_b32 s3, s7, s4
+; GCN-HSA-NEXT: s_and_b32 s2, s2, 0xff00ff
+; GCN-HSA-NEXT: s_and_b32 s0, s0, 0xff00ff
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s2
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_endpgm
;
@@ -10253,22 +10265,26 @@ define amdgpu_kernel void @global_zextload_v8i8_to_v8i16(ptr addrspace(1) %out,
; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s4, v1
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s4, v0
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s6, v1
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s5, s4, 24
-; GCN-NOHSA-VI-NEXT: s_bfe_u32 s6, s4, 0x80010
-; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s4, 0xff
-; GCN-NOHSA-VI-NEXT: s_lshl_b32 s4, s4, 8
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v2, 24, v0
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v1, 8, v0
-; GCN-NOHSA-VI-NEXT: s_lshl_b32 s5, s5, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xff0000
-; GCN-NOHSA-VI-NEXT: v_alignbit_b32 v2, v2, v0, 16
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v3, 0xff0000, v1
-; GCN-NOHSA-VI-NEXT: s_or_b32 s5, s6, s5
-; GCN-NOHSA-VI-NEXT: s_or_b32 s4, s7, s4
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v1, 0xff00ff, v2
-; GCN-NOHSA-VI-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s4
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s7, s6, 24
+; GCN-NOHSA-VI-NEXT: s_bfe_u32 s8, s6, 0x80010
+; GCN-NOHSA-VI-NEXT: s_and_b32 s9, s6, 0xff
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s6, s6, 8
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s11, s4, 8
+; GCN-NOHSA-VI-NEXT: s_and_b32 s10, s4, 0xff
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s7, s7, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xff0000
+; GCN-NOHSA-VI-NEXT: s_and_b32 s11, s11, 0xff0000
+; GCN-NOHSA-VI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; GCN-NOHSA-VI-NEXT: s_or_b32 s5, s8, s7
+; GCN-NOHSA-VI-NEXT: s_or_b32 s6, s9, s6
+; GCN-NOHSA-VI-NEXT: s_or_b32 s7, s10, s11
+; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xff00ff
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s5
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NOHSA-VI-NEXT: s_endpgm
@@ -10764,35 +10780,48 @@ define amdgpu_kernel void @global_zextload_v16i8_to_v16i16(ptr addrspace(1) %out
; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, 0xff00, v2
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v5, 24, v2
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v6, 0xff00, v3
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v7, 24, v3
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, 0xff00, v0
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v9, 24, v0
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v10, 0xff00, v1
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v11, 24, v1
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v12, 0xff, v1
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v13, 0xff, v0
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v14, 0xff, v3
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v15, 0xff, v2
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v1, v11, v1, 16
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v10, 8, v10
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v0, v9, v0, 16
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v7, v7, v3, 16
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v5, v5, v2, 16
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v3, 0xff00ff, v1
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v2, v12, v10
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v1, 0xff00ff, v0
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v0, v13, v8
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v7, 0xff00ff, v7
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v6, v14, v6
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v5, 0xff00ff, v5
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v4, v15, v4
-; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s4, v2
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s6, v3
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s8, v0
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s10, v1
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s5, s4, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s7, s6, 24
+; GCN-NOHSA-SI-NEXT: s_and_b32 s12, s4, 0xff00
+; GCN-NOHSA-SI-NEXT: s_and_b32 s13, s6, 0xff00
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s9, s8, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s11, s10, 24
+; GCN-NOHSA-SI-NEXT: s_and_b32 s14, s8, 0xff00
+; GCN-NOHSA-SI-NEXT: s_and_b32 s15, s10, 0xff00
+; GCN-NOHSA-SI-NEXT: s_and_b32 s16, s10, 0xff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s17, s8, 0xff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s18, s6, 0xff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s19, s4, 0xff
+; GCN-NOHSA-SI-NEXT: s_lshl_b32 s15, s15, 8
+; GCN-NOHSA-SI-NEXT: s_lshl_b32 s14, s14, 8
+; GCN-NOHSA-SI-NEXT: s_lshr_b64 s[10:11], s[10:11], 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
+; GCN-NOHSA-SI-NEXT: s_lshl_b32 s9, s13, 8
+; GCN-NOHSA-SI-NEXT: s_lshl_b32 s11, s12, 8
+; GCN-NOHSA-SI-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; GCN-NOHSA-SI-NEXT: s_or_b32 s5, s16, s15
+; GCN-NOHSA-SI-NEXT: s_or_b32 s7, s17, s14
+; GCN-NOHSA-SI-NEXT: s_and_b32 s10, s10, 0xff00ff
+; GCN-NOHSA-SI-NEXT: s_or_b32 s9, s18, s9
+; GCN-NOHSA-SI-NEXT: s_or_b32 s11, s19, s11
+; GCN-NOHSA-SI-NEXT: s_and_b32 s6, s6, 0xff00ff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s4, s4, 0xff00ff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s8, s8, 0xff00ff
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s11
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s4
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s9
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s6
+; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s7
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s8
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s5
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s10
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NOHSA-SI-NEXT: s_endpgm
;
@@ -10806,43 +10835,55 @@ define amdgpu_kernel void @global_zextload_v16i8_to_v16i16(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
-; GCN-HSA-NEXT: v_and_b32_e32 v4, 0xff00, v2
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 24, v2
-; GCN-HSA-NEXT: v_and_b32_e32 v6, 0xff00, v3
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 24, v3
-; GCN-HSA-NEXT: v_and_b32_e32 v12, 0xff00, v0
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v13, 24, v0
-; GCN-HSA-NEXT: v_and_b32_e32 v14, 0xff00, v1
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v15, 24, v1
-; GCN-HSA-NEXT: v_and_b32_e32 v18, 0xff, v3
-; GCN-HSA-NEXT: v_and_b32_e32 v19, 0xff, v2
-; GCN-HSA-NEXT: v_alignbit_b32 v7, v7, v3, 16
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; GCN-HSA-NEXT: v_alignbit_b32 v5, v5, v2, 16
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GCN-HSA-NEXT: v_and_b32_e32 v16, 0xff, v1
-; GCN-HSA-NEXT: v_and_b32_e32 v17, 0xff, v0
-; GCN-HSA-NEXT: v_alignbit_b32 v1, v15, v1, 16
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v14, 8, v14
-; GCN-HSA-NEXT: v_alignbit_b32 v0, v13, v0, 16
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v12, 8, v12
-; GCN-HSA-NEXT: v_and_b32_e32 v7, 0xff00ff, v7
-; GCN-HSA-NEXT: v_or_b32_e32 v6, v18, v6
-; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xff00ff, v5
-; GCN-HSA-NEXT: v_or_b32_e32 v4, v19, v4
-; GCN-HSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v1
-; GCN-HSA-NEXT: v_or_b32_e32 v2, v16, v14
-; GCN-HSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v0
-; GCN-HSA-NEXT: v_or_b32_e32 v0, v17, v12
-; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
+; GCN-HSA-NEXT: v_readfirstlane_b32 s6, v0
+; GCN-HSA-NEXT: v_readfirstlane_b32 s8, v1
+; GCN-HSA-NEXT: v_readfirstlane_b32 s2, v2
+; GCN-HSA-NEXT: v_readfirstlane_b32 s4, v3
+; GCN-HSA-NEXT: s_lshr_b32 s7, s6, 24
+; GCN-HSA-NEXT: s_lshr_b32 s9, s8, 24
+; GCN-HSA-NEXT: s_lshr_b32 s3, s2, 24
+; GCN-HSA-NEXT: s_lshr_b32 s5, s4, 24
+; GCN-HSA-NEXT: s_and_b32 s10, s2, 0xff00
+; GCN-HSA-NEXT: s_and_b32 s11, s4, 0xff00
+; GCN-HSA-NEXT: s_and_b32 s12, s6, 0xff00
+; GCN-HSA-NEXT: s_and_b32 s13, s8, 0xff00
+; GCN-HSA-NEXT: s_and_b32 s14, s8, 0xff
+; GCN-HSA-NEXT: s_and_b32 s15, s6, 0xff
+; GCN-HSA-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
+; GCN-HSA-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
+; GCN-HSA-NEXT: s_and_b32 s16, s4, 0xff
+; GCN-HSA-NEXT: s_and_b32 s17, s2, 0xff
+; GCN-HSA-NEXT: s_lshl_b32 s13, s13, 8
+; GCN-HSA-NEXT: s_lshl_b32 s12, s12, 8
+; GCN-HSA-NEXT: s_lshl_b32 s7, s11, 8
+; GCN-HSA-NEXT: s_lshl_b32 s9, s10, 8
+; GCN-HSA-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; GCN-HSA-NEXT: s_lshr_b64 s[2:3], s[2:3], 16
+; GCN-HSA-NEXT: s_or_b32 s3, s14, s13
+; GCN-HSA-NEXT: s_or_b32 s5, s15, s12
+; GCN-HSA-NEXT: s_and_b32 s8, s8, 0xff00ff
+; GCN-HSA-NEXT: s_and_b32 s6, s6, 0xff00ff
+; GCN-HSA-NEXT: s_or_b32 s7, s16, s7
+; GCN-HSA-NEXT: s_or_b32 s9, s17, s9
+; GCN-HSA-NEXT: s_and_b32 s4, s4, 0xff00ff
+; GCN-HSA-NEXT: s_and_b32 s2, s2, 0xff00ff
+; GCN-HSA-NEXT: s_add_u32 s0, s0, 16
+; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s8
+; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
; GCN-HSA-NEXT: s_endpgm
;
; GCN-NOHSA-VI-LABEL: global_zextload_v16i8_to_v16i16:
@@ -10859,42 +10900,50 @@ define amdgpu_kernel void @global_zextload_v16i8_to_v16i16(ptr addrspace(1) %out
; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s4, v3
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s5, v1
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s5, 24
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s9, s4, 24
-; GCN-NOHSA-VI-NEXT: s_bfe_u32 s10, s4, 0x80010
-; GCN-NOHSA-VI-NEXT: s_and_b32 s11, s4, 0xff
-; GCN-NOHSA-VI-NEXT: s_lshl_b32 s4, s4, 8
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v4, 24, v2
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v1, 8, v0
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v5, 8, v2
-; GCN-NOHSA-VI-NEXT: s_bfe_u32 s7, s5, 0x80010
-; GCN-NOHSA-VI-NEXT: s_and_b32 s8, s5, 0xff
-; GCN-NOHSA-VI-NEXT: s_lshl_b32 s5, s5, 8
-; GCN-NOHSA-VI-NEXT: s_lshl_b32 s6, s6, 16
-; GCN-NOHSA-VI-NEXT: s_lshl_b32 s9, s9, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xff0000
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v6, 0xff0000, v1
-; GCN-NOHSA-VI-NEXT: v_alignbit_b32 v4, v4, v2, 16
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v7, 0xff0000, v5
-; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xff0000
-; GCN-NOHSA-VI-NEXT: s_or_b32 s6, s7, s6
-; GCN-NOHSA-VI-NEXT: s_or_b32 s7, s10, s9
-; GCN-NOHSA-VI-NEXT: s_or_b32 s4, s11, s4
-; GCN-NOHSA-VI-NEXT: v_alignbit_b32 v3, v3, v0, 16
-; GCN-NOHSA-VI-NEXT: v_or_b32_sdwa v0, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v5, 0xff00ff, v4
-; GCN-NOHSA-VI-NEXT: v_or_b32_sdwa v4, v2, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GCN-NOHSA-VI-NEXT: s_or_b32 s5, s8, s5
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s7
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v1, 0xff00ff, v3
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s6
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s6, v0
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s4, v2
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s8, v3
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s9, v1
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s7, s6, 24
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s5, s4, 24
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s10, s9, 24
+; GCN-NOHSA-VI-NEXT: s_and_b32 s13, s6, 0xff
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s14, s6, 8
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s15, s8, 24
+; GCN-NOHSA-VI-NEXT: s_bfe_u32 s16, s8, 0x80010
+; GCN-NOHSA-VI-NEXT: s_and_b32 s17, s8, 0xff
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s8, s8, 8
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s19, s4, 8
+; GCN-NOHSA-VI-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
+; GCN-NOHSA-VI-NEXT: s_bfe_u32 s11, s9, 0x80010
+; GCN-NOHSA-VI-NEXT: s_and_b32 s12, s9, 0xff
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s9, s9, 8
+; GCN-NOHSA-VI-NEXT: s_and_b32 s18, s4, 0xff
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s10, s10, 16
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s7, s15, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s8, s8, 0xff0000
+; GCN-NOHSA-VI-NEXT: s_and_b32 s15, s19, 0xff0000
+; GCN-NOHSA-VI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s9, s9, 0xff0000
+; GCN-NOHSA-VI-NEXT: s_and_b32 s14, s14, 0xff0000
+; GCN-NOHSA-VI-NEXT: s_or_b32 s5, s11, s10
+; GCN-NOHSA-VI-NEXT: s_or_b32 s7, s16, s7
+; GCN-NOHSA-VI-NEXT: s_or_b32 s8, s17, s8
+; GCN-NOHSA-VI-NEXT: s_or_b32 s11, s18, s15
+; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xff00ff
+; GCN-NOHSA-VI-NEXT: s_or_b32 s9, s12, s9
+; GCN-NOHSA-VI-NEXT: s_or_b32 s10, s13, s14
+; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xff00ff
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s11
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s10
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s9
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s5
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: global_zextload_v16i8_to_v16i16:
@@ -11767,71 +11816,97 @@ define amdgpu_kernel void @global_zextload_v32i8_to_v32i16(ptr addrspace(1) %out
; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s6
; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s7
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:16
-; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, 0xff00, v2
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v5, 0xff00, v3
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v6, 0xff, v3
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v7, 0xff, v2
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v6, v6, v5
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v4, v7, v4
-; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0
+; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0
; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v5, 24, v3
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v3, v5, v3, 16
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v7, 0xff00ff, v3
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v3, 24, v2
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v5, 0xff00ff, v2
+; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(1)
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s4, v2
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s6, v3
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s8, v0
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s10, v1
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v3, 0xff00, v10
-; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:48
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v2, 24, v10
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s12, v6
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s14, v7
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s16, v4
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s18, v5
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s5, s4, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s7, s6, 24
+; GCN-NOHSA-SI-NEXT: s_and_b32 s20, s4, 0xff00
+; GCN-NOHSA-SI-NEXT: s_and_b32 s21, s6, 0xff00
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s9, s8, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s11, s10, 24
+; GCN-NOHSA-SI-NEXT: s_and_b32 s22, s8, 0xff00
+; GCN-NOHSA-SI-NEXT: s_and_b32 s23, s10, 0xff00
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s13, s12, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s15, s14, 24
+; GCN-NOHSA-SI-NEXT: s_and_b32 s24, s12, 0xff00
+; GCN-NOHSA-SI-NEXT: s_and_b32 s25, s14, 0xff00
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s17, s16, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s19, s18, 24
+; GCN-NOHSA-SI-NEXT: s_and_b32 s26, s16, 0xff00
+; GCN-NOHSA-SI-NEXT: s_and_b32 s27, s18, 0xff00
+; GCN-NOHSA-SI-NEXT: s_and_b32 s28, s18, 0xff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s29, s16, 0xff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s30, s14, 0xff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s31, s12, 0xff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s33, s10, 0xff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s34, s8, 0xff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s35, s6, 0xff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s36, s4, 0xff
+; GCN-NOHSA-SI-NEXT: s_lshl_b32 s27, s27, 8
+; GCN-NOHSA-SI-NEXT: s_lshl_b32 s26, s26, 8
+; GCN-NOHSA-SI-NEXT: s_lshr_b64 s[18:19], s[18:19], 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b64 s[16:17], s[16:17], 16
+; GCN-NOHSA-SI-NEXT: s_lshl_b32 s17, s25, 8
+; GCN-NOHSA-SI-NEXT: s_lshl_b32 s19, s24, 8
+; GCN-NOHSA-SI-NEXT: s_lshr_b64 s[14:15], s[14:15], 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b64 s[12:13], s[12:13], 16
+; GCN-NOHSA-SI-NEXT: s_lshl_b32 s13, s23, 8
+; GCN-NOHSA-SI-NEXT: s_lshl_b32 s15, s22, 8
+; GCN-NOHSA-SI-NEXT: s_lshr_b64 s[10:11], s[10:11], 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
+; GCN-NOHSA-SI-NEXT: s_lshl_b32 s9, s21, 8
+; GCN-NOHSA-SI-NEXT: s_lshl_b32 s11, s20, 8
+; GCN-NOHSA-SI-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; GCN-NOHSA-SI-NEXT: s_or_b32 s5, s28, s27
+; GCN-NOHSA-SI-NEXT: s_or_b32 s7, s29, s26
+; GCN-NOHSA-SI-NEXT: s_and_b32 s18, s18, 0xff00ff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s16, s16, 0xff00ff
+; GCN-NOHSA-SI-NEXT: s_or_b32 s17, s30, s17
+; GCN-NOHSA-SI-NEXT: s_or_b32 s19, s31, s19
+; GCN-NOHSA-SI-NEXT: s_and_b32 s14, s14, 0xff00ff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s12, s12, 0xff00ff
+; GCN-NOHSA-SI-NEXT: s_or_b32 s13, s33, s13
+; GCN-NOHSA-SI-NEXT: s_or_b32 s15, s34, s15
+; GCN-NOHSA-SI-NEXT: s_and_b32 s10, s10, 0xff00ff
+; GCN-NOHSA-SI-NEXT: s_or_b32 s9, s35, s9
+; GCN-NOHSA-SI-NEXT: s_or_b32 s11, s36, s11
+; GCN-NOHSA-SI-NEXT: s_and_b32 s6, s6, 0xff00ff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s4, s4, 0xff00ff
+; GCN-NOHSA-SI-NEXT: s_and_b32 s8, s8, 0xff00ff
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s11
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s4
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s9
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s6
+; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v4, 24, v11
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v5, 24, v8
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v6, 24, v9
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v7, v6, v9, 16
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v5, v5, v8, 16
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v12, v4, v11, 16
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v13, v2, v10, 16
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, 0xff00, v11
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, 0xff00, v8
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v6, 0xff00, v9
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v14, 24, v1
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v14, v14, v1, 16
-; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v15, 24, v0
-; GCN-NOHSA-SI-NEXT: v_alignbit_b32 v15, v15, v0, 16
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v16, 0xff00, v0
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v17, 0xff00, v1
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v18, 0xff, v0
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v0, 8, v6
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v6, 8, v2
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v2, v9, v0
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v0, v8, v6
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v6, v11, v4
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v4, v10, v3
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v3, 8, v17
-; GCN-NOHSA-SI-NEXT: v_lshlrev_b32_e32 v8, 8, v16
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v10, v1, v3
-; GCN-NOHSA-SI-NEXT: v_or_b32_e32 v8, v18, v8
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v3, 0xff00ff, v7
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v1, 0xff00ff, v5
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v7, 0xff00ff, v12
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v5, 0xff00ff, v13
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v11, 0xff00ff, v14
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v9, 0xff00ff, v15
-; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
-; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s15
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s8
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s13
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s10
+; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s19
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s12
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s17
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s14
+; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s7
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s16
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s5
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s18
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NOHSA-SI-NEXT: s_endpgm
;
@@ -11844,88 +11919,112 @@ define amdgpu_kernel void @global_zextload_v32i8_to_v32i16(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
+; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s0
+; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
+; GCN-HSA-NEXT: v_readfirstlane_b32 s4, v2
+; GCN-HSA-NEXT: v_readfirstlane_b32 s6, v3
+; GCN-HSA-NEXT: v_readfirstlane_b32 s8, v0
+; GCN-HSA-NEXT: v_readfirstlane_b32 s10, v1
+; GCN-HSA-NEXT: s_lshr_b32 s5, s4, 24
+; GCN-HSA-NEXT: s_lshr_b32 s7, s6, 24
+; GCN-HSA-NEXT: s_and_b32 s12, s4, 0xff00
+; GCN-HSA-NEXT: s_and_b32 s13, s6, 0xff00
+; GCN-HSA-NEXT: s_lshr_b32 s9, s8, 24
+; GCN-HSA-NEXT: s_lshr_b32 s11, s10, 24
+; GCN-HSA-NEXT: s_and_b32 s14, s8, 0xff00
+; GCN-HSA-NEXT: s_and_b32 s15, s10, 0xff00
; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCN-HSA-NEXT: s_lshr_b64 s[2:3], s[10:11], 16
+; GCN-HSA-NEXT: s_and_b32 s17, s8, 0xff
+; GCN-HSA-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
+; GCN-HSA-NEXT: s_and_b32 s3, s6, 0xff
+; GCN-HSA-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
+; GCN-HSA-NEXT: s_and_b32 s16, s10, 0xff
+; GCN-HSA-NEXT: s_lshl_b32 s14, s14, 8
+; GCN-HSA-NEXT: s_lshl_b32 s9, s13, 8
+; GCN-HSA-NEXT: s_and_b32 s10, s4, 0xff
+; GCN-HSA-NEXT: s_lshl_b32 s11, s12, 8
+; GCN-HSA-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; GCN-HSA-NEXT: s_and_b32 s8, s8, 0xff00ff
+; GCN-HSA-NEXT: s_and_b32 s6, s6, 0xff00ff
+; GCN-HSA-NEXT: s_lshl_b32 s15, s15, 8
+; GCN-HSA-NEXT: s_or_b32 s7, s17, s14
+; GCN-HSA-NEXT: s_and_b32 s2, s2, 0xff00ff
+; GCN-HSA-NEXT: s_or_b32 s3, s3, s9
+; GCN-HSA-NEXT: s_or_b32 s9, s10, s11
+; GCN-HSA-NEXT: s_and_b32 s4, s4, 0xff00ff
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s8
+; GCN-HSA-NEXT: s_or_b32 s5, s16, s15
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s7
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s5
+; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
+; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
+; GCN-HSA-NEXT: v_readfirstlane_b32 s6, v0
+; GCN-HSA-NEXT: v_readfirstlane_b32 s8, v1
+; GCN-HSA-NEXT: v_readfirstlane_b32 s2, v2
+; GCN-HSA-NEXT: v_readfirstlane_b32 s4, v3
+; GCN-HSA-NEXT: s_lshr_b32 s7, s6, 24
+; GCN-HSA-NEXT: s_lshr_b32 s9, s8, 24
+; GCN-HSA-NEXT: s_lshr_b32 s3, s2, 24
+; GCN-HSA-NEXT: s_lshr_b32 s5, s4, 24
+; GCN-HSA-NEXT: s_and_b32 s10, s2, 0xff00
+; GCN-HSA-NEXT: s_and_b32 s11, s4, 0xff00
+; GCN-HSA-NEXT: s_and_b32 s12, s6, 0xff00
+; GCN-HSA-NEXT: s_and_b32 s13, s8, 0xff00
+; GCN-HSA-NEXT: s_and_b32 s14, s8, 0xff
+; GCN-HSA-NEXT: s_and_b32 s15, s6, 0xff
+; GCN-HSA-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
+; GCN-HSA-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
+; GCN-HSA-NEXT: s_and_b32 s16, s4, 0xff
+; GCN-HSA-NEXT: s_and_b32 s17, s2, 0xff
+; GCN-HSA-NEXT: s_lshl_b32 s13, s13, 8
+; GCN-HSA-NEXT: s_lshl_b32 s12, s12, 8
+; GCN-HSA-NEXT: s_lshl_b32 s7, s11, 8
+; GCN-HSA-NEXT: s_lshl_b32 s9, s10, 8
+; GCN-HSA-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; GCN-HSA-NEXT: s_lshr_b64 s[2:3], s[2:3], 16
+; GCN-HSA-NEXT: s_or_b32 s3, s14, s13
+; GCN-HSA-NEXT: s_or_b32 s5, s15, s12
+; GCN-HSA-NEXT: s_and_b32 s8, s8, 0xff00ff
+; GCN-HSA-NEXT: s_and_b32 s6, s6, 0xff00ff
+; GCN-HSA-NEXT: s_or_b32 s7, s16, s7
+; GCN-HSA-NEXT: s_or_b32 s9, s17, s9
+; GCN-HSA-NEXT: s_and_b32 s4, s4, 0xff00ff
+; GCN-HSA-NEXT: s_and_b32 s10, s2, 0xff00ff
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s3
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
; GCN-HSA-NEXT: s_add_u32 s2, s0, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s0
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[4:7]
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s3
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s2
-; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v9, 24, v7
-; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xff00, v7
-; GCN-HSA-NEXT: v_and_b32_e32 v17, 0xff, v7
-; GCN-HSA-NEXT: v_alignbit_b32 v7, v9, v7, 16
-; GCN-HSA-NEXT: v_and_b32_e32 v16, 0xff00, v6
-; GCN-HSA-NEXT: v_and_b32_e32 v9, 0xff00ff, v7
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 24, v6
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v8, 8, v8
-; GCN-HSA-NEXT: v_alignbit_b32 v7, v7, v6, 16
-; GCN-HSA-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v16, 8, v16
-; GCN-HSA-NEXT: v_or_b32_e32 v8, v17, v8
-; GCN-HSA-NEXT: v_and_b32_e32 v7, 0xff00ff, v7
-; GCN-HSA-NEXT: v_or_b32_e32 v6, v6, v16
-; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[6:9]
-; GCN-HSA-NEXT: v_and_b32_e32 v12, 0xff, v5
-; GCN-HSA-NEXT: v_and_b32_e32 v6, 0xff00, v4
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xff00, v5
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v9, 24, v5
-; GCN-HSA-NEXT: v_and_b32_e32 v13, 0xff, v4
-; GCN-HSA-NEXT: v_alignbit_b32 v5, v9, v5, 16
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v8, 8, v8
-; GCN-HSA-NEXT: v_alignbit_b32 v9, v7, v4, 16
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v4, 8, v6
-; GCN-HSA-NEXT: v_or_b32_e32 v6, v12, v8
-; GCN-HSA-NEXT: v_or_b32_e32 v4, v13, v4
-; GCN-HSA-NEXT: v_and_b32_e32 v7, 0xff00ff, v5
-; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xff00ff, v9
-; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
-; GCN-HSA-NEXT: v_and_b32_e32 v18, 0xff00, v2
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v19, 24, v2
-; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xff00, v3
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v12, 24, v3
-; GCN-HSA-NEXT: v_and_b32_e32 v13, 0xff00, v0
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v9, 24, v0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
-; GCN-HSA-NEXT: v_and_b32_e32 v10, 0xff, v3
-; GCN-HSA-NEXT: v_and_b32_e32 v4, 0xff00, v1
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 24, v1
-; GCN-HSA-NEXT: v_and_b32_e32 v6, 0xff, v1
-; GCN-HSA-NEXT: v_and_b32_e32 v7, 0xff, v0
-; GCN-HSA-NEXT: v_and_b32_e32 v11, 0xff, v2
-; GCN-HSA-NEXT: v_alignbit_b32 v1, v5, v1, 16
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GCN-HSA-NEXT: v_alignbit_b32 v0, v9, v0, 16
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v5, 8, v13
-; GCN-HSA-NEXT: v_alignbit_b32 v9, v12, v3, 16
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v8, 8, v8
-; GCN-HSA-NEXT: v_alignbit_b32 v12, v19, v2, 16
-; GCN-HSA-NEXT: v_lshlrev_b32_e32 v13, 8, v18
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
-; GCN-HSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v1
-; GCN-HSA-NEXT: v_or_b32_e32 v2, v6, v4
-; GCN-HSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v0
-; GCN-HSA-NEXT: v_or_b32_e32 v0, v7, v5
-; GCN-HSA-NEXT: v_and_b32_e32 v7, 0xff00ff, v9
-; GCN-HSA-NEXT: v_or_b32_e32 v6, v10, v8
-; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xff00ff, v12
-; GCN-HSA-NEXT: v_or_b32_e32 v4, v11, v13
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[14:15], v[4:7]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; GCN-HSA-NEXT: s_endpgm
;
; GCN-NOHSA-VI-LABEL: global_zextload_v32i8_to_v32i16:
@@ -11943,79 +12042,95 @@ define amdgpu_kernel void @global_zextload_v32i8_to_v32i16(ptr addrspace(1) %out
; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(1)
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s4, v3
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s6, v0
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s6, v7
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s7, v5
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s5, v1
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s8, s7, 24
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s11, s6, 24
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s17, s4, 24
-; GCN-NOHSA-VI-NEXT: s_bfe_u32 s18, s4, 0x80010
-; GCN-NOHSA-VI-NEXT: s_and_b32 s19, s4, 0xff
-; GCN-NOHSA-VI-NEXT: s_lshl_b32 s4, s4, 8
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v8, 24, v2
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v5, 8, v4
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v11, 8, v2
-; GCN-NOHSA-VI-NEXT: s_bfe_u32 s9, s7, 0x80010
-; GCN-NOHSA-VI-NEXT: s_and_b32 s10, s7, 0xff
-; GCN-NOHSA-VI-NEXT: s_lshl_b32 s7, s7, 8
-; GCN-NOHSA-VI-NEXT: s_bfe_u32 s12, s6, 0x80010
-; GCN-NOHSA-VI-NEXT: s_and_b32 s13, s6, 0xff
-; GCN-NOHSA-VI-NEXT: s_lshl_b32 s6, s6, 8
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s14, s5, 24
-; GCN-NOHSA-VI-NEXT: s_bfe_u32 s15, s5, 0x80010
-; GCN-NOHSA-VI-NEXT: s_and_b32 s16, s5, 0xff
-; GCN-NOHSA-VI-NEXT: s_lshl_b32 s5, s5, 8
-; GCN-NOHSA-VI-NEXT: s_lshl_b32 s8, s8, 16
-; GCN-NOHSA-VI-NEXT: s_lshl_b32 s11, s11, 16
-; GCN-NOHSA-VI-NEXT: s_lshl_b32 s17, s17, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xff0000
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 24, v6
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v9, 8, v6
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v10, 8, v0
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, 0xff0000, v5
-; GCN-NOHSA-VI-NEXT: v_alignbit_b32 v13, v8, v2, 16
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v11, 0xff0000, v11
-; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xff0000
-; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xff0000
-; GCN-NOHSA-VI-NEXT: s_lshl_b32 s14, s14, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xff0000
-; GCN-NOHSA-VI-NEXT: s_or_b32 s8, s9, s8
-; GCN-NOHSA-VI-NEXT: s_or_b32 s9, s12, s11
-; GCN-NOHSA-VI-NEXT: s_or_b32 s11, s18, s17
-; GCN-NOHSA-VI-NEXT: s_or_b32 s4, s19, s4
-; GCN-NOHSA-VI-NEXT: v_alignbit_b32 v7, v7, v4, 16
-; GCN-NOHSA-VI-NEXT: v_alignbit_b32 v1, v1, v6, 16
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v9, 0xff0000, v9
-; GCN-NOHSA-VI-NEXT: v_alignbit_b32 v3, v3, v0, 16
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v10, 0xff0000, v10
-; GCN-NOHSA-VI-NEXT: v_or_b32_sdwa v4, v4, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GCN-NOHSA-VI-NEXT: v_or_b32_sdwa v12, v2, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v13, 0xff00ff, v13
-; GCN-NOHSA-VI-NEXT: s_or_b32 s7, s10, s7
-; GCN-NOHSA-VI-NEXT: s_or_b32 s6, s13, s6
-; GCN-NOHSA-VI-NEXT: s_or_b32 s10, s15, s14
-; GCN-NOHSA-VI-NEXT: s_or_b32 s5, s16, s5
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v14, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v15, s11
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v5, 0xff00ff, v7
-; GCN-NOHSA-VI-NEXT: v_or_b32_sdwa v8, v6, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v9, 0xff00ff, v1
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v1, 0xff00ff, v3
-; GCN-NOHSA-VI-NEXT: v_or_b32_sdwa v0, v0, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s10
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v10, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v11, s9
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s7
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s8
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s8, v6
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s4, v2
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s12, v3
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s13, v1
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s10, v4
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s15, v5
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s7, s6, 24
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s9, s8, 24
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s14, v7
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s5, s4, 24
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s11, s10, 24
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s16, s15, 24
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s20, s10, 8
+; GCN-NOHSA-VI-NEXT: s_and_b32 s24, s8, 0xff
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s25, s8, 8
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s26, s13, 24
+; GCN-NOHSA-VI-NEXT: s_and_b32 s29, s6, 0xff
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s30, s6, 8
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s31, s12, 24
+; GCN-NOHSA-VI-NEXT: s_bfe_u32 s33, s12, 0x80010
+; GCN-NOHSA-VI-NEXT: s_and_b32 s34, s12, 0xff
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s12, s12, 8
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s36, s4, 8
+; GCN-NOHSA-VI-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
+; GCN-NOHSA-VI-NEXT: s_bfe_u32 s17, s15, 0x80010
+; GCN-NOHSA-VI-NEXT: s_and_b32 s18, s15, 0xff
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s15, s15, 8
+; GCN-NOHSA-VI-NEXT: s_and_b32 s19, s10, 0xff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s21, s14, 24
+; GCN-NOHSA-VI-NEXT: s_bfe_u32 s22, s14, 0x80010
+; GCN-NOHSA-VI-NEXT: s_and_b32 s23, s14, 0xff
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s14, s14, 8
+; GCN-NOHSA-VI-NEXT: s_bfe_u32 s27, s13, 0x80010
+; GCN-NOHSA-VI-NEXT: s_and_b32 s28, s13, 0xff
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s13, s13, 8
+; GCN-NOHSA-VI-NEXT: s_and_b32 s35, s4, 0xff
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s16, s16, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s20, s20, 0xff0000
+; GCN-NOHSA-VI-NEXT: s_lshr_b64 s[10:11], s[10:11], 16
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s9, s26, 16
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s7, s31, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s12, s12, 0xff0000
+; GCN-NOHSA-VI-NEXT: s_and_b32 s26, s36, 0xff0000
+; GCN-NOHSA-VI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s15, s15, 0xff0000
+; GCN-NOHSA-VI-NEXT: s_lshl_b32 s11, s21, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s14, s14, 0xff0000
+; GCN-NOHSA-VI-NEXT: s_and_b32 s21, s25, 0xff0000
+; GCN-NOHSA-VI-NEXT: s_and_b32 s13, s13, 0xff0000
+; GCN-NOHSA-VI-NEXT: s_and_b32 s25, s30, 0xff0000
+; GCN-NOHSA-VI-NEXT: s_or_b32 s5, s17, s16
+; GCN-NOHSA-VI-NEXT: s_or_b32 s16, s19, s20
+; GCN-NOHSA-VI-NEXT: s_or_b32 s7, s33, s7
+; GCN-NOHSA-VI-NEXT: s_or_b32 s12, s34, s12
+; GCN-NOHSA-VI-NEXT: s_or_b32 s19, s35, s26
+; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xff00ff
+; GCN-NOHSA-VI-NEXT: s_or_b32 s15, s18, s15
+; GCN-NOHSA-VI-NEXT: s_and_b32 s10, s10, 0xff00ff
+; GCN-NOHSA-VI-NEXT: s_or_b32 s11, s22, s11
+; GCN-NOHSA-VI-NEXT: s_or_b32 s14, s23, s14
+; GCN-NOHSA-VI-NEXT: s_or_b32 s17, s24, s21
+; GCN-NOHSA-VI-NEXT: s_and_b32 s8, s8, 0xff00ff
+; GCN-NOHSA-VI-NEXT: s_or_b32 s9, s27, s9
+; GCN-NOHSA-VI-NEXT: s_or_b32 s13, s28, s13
+; GCN-NOHSA-VI-NEXT: s_or_b32 s18, s29, s25
+; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xff00ff
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s19
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s12
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s18
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s13
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s9
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v8, s17
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v9, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v10, s14
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:32
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v11, s11
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s10
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s15
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s5
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:16
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: global_zextload_v32i8_to_v32i16:
diff --git a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
index 52ef811875f88..a6c019bf374d7 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
@@ -18,7 +18,7 @@ define amdgpu_kernel void @scalar_to_vector_v2i32(ptr addrspace(1) %out, ptr add
; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: v_mov_b32_e32 v1, v0
@@ -40,7 +40,7 @@ define amdgpu_kernel void @scalar_to_vector_v2i32(ptr addrspace(1) %out, ptr add
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
; VI-NEXT: v_mov_b32_e32 v1, v0
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: s_endpgm
@@ -86,7 +86,7 @@ define amdgpu_kernel void @scalar_to_vector_v2f32(ptr addrspace(1) %out, ptr add
; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: v_mov_b32_e32 v1, v0
@@ -108,7 +108,7 @@ define amdgpu_kernel void @scalar_to_vector_v2f32(ptr addrspace(1) %out, ptr add
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; VI-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
; VI-NEXT: v_mov_b32_e32 v1, v0
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: s_endpgm
>From b9371bd8776e51aeb862fbfd552fd34446619390 Mon Sep 17 00:00:00 2001
From: Akash Dutta <137309513+akadutta at users.noreply.github.com>
Date: Fri, 7 Nov 2025 15:23:30 -0600
Subject: [PATCH 7/8] Delete extra space
---
llvm/lib/Target/AMDGPU/SOPInstructions.td | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 337722d44f80d..0a49527d14f94 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -206,7 +206,6 @@ class DivergentBinFrag<SDPatternOperator Op> : PatFrag <
// trivially true predicate to eliminate the check.
let GISelPredicateCode = [{return true;}];
}
-
let isMoveImm = 1 in {
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
def S_MOV_B32 : SOP1_32 <"s_mov_b32">;
>From 985d315c9213540991bfe65c971b6e67ccbe7b52 Mon Sep 17 00:00:00 2001
From: Akash Dutta <137309513+akadutta at users.noreply.github.com>
Date: Fri, 7 Nov 2025 15:27:39 -0600
Subject: [PATCH 8/8] Revert incorrect space removal
---
llvm/lib/Target/AMDGPU/SOPInstructions.td | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 0a49527d14f94..84287b621fe78 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -206,6 +206,8 @@ class DivergentBinFrag<SDPatternOperator Op> : PatFrag <
// trivially true predicate to eliminate the check.
let GISelPredicateCode = [{return true;}];
}
+
+
let isMoveImm = 1 in {
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
def S_MOV_B32 : SOP1_32 <"s_mov_b32">;
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