[llvm] [RISCV] Adopt SpacemitX60's scheduling model for `-mtune=generic` (PR #167008)
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 7 11:51:38 PST 2025
https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/167008
Per our discussions in RISC-V roundtable during LLVM Dev Meeting 2025, there has been a consensus to create a base / generic scheduling model for the most common performance tuning usages. As the first step, we agree to use SpacemitX60's scheduling model for that purpose for the time being, with an expectation to create a standalone generic model that could evolve independently in the future.
This patch sets `-mtune=generic` to use SpacemitX60's scheduling model, and documents the rationale behind it, including the roadmap ahead as we discussed.
-------
Note that I didn't make the same change on `-mcpu=generic-rv32/64`, because it would invalidate most of, if not all of the codegen tests (we set TuneCPU to generic-rv32/64 when `-mtune` is empty). I would like to solicit opinions on whether we should do it or not.
For reference:
- X86: `-mtune=generic` is equal to `-mtune=sandy-bridge`. But in the absent of `-mtune`, the `-mtune` is set of i586, which uses `NoSchedModel`. The rationale behind it is similar to what I mentioned above: setting to i586 can make sure it won't break any the codegen tests
- AArch64: `-mtune=generic` is equal to `-mtune=cortex-a510` -- same for the case where `-mtune` is empty. I guess they bit the bullet and updated all the test cases when they made that decision (i.e. to use cotext-a510 rather than NoSchedModel for codegen tests)
So I guess the question here is: should we update all affected codegen tests? On one hand it makes the tests less stable whenever we update SpacemitX60's scheduling model -- which is still relatively active. On the other hand, it's more straightforward if we maintain the consistency between `generic` and `generic-rv32/64` -- both of them use the same scheduling model.
>From 13d78ef202885d1f1e6d375503e86c49b9b33d3f Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Fri, 7 Nov 2025 11:06:53 -0800
Subject: [PATCH 1/3] [RISCV] Adopt SpacemitX60's scheduling model for
`-mtune=generic`
---
llvm/docs/RISCVUsage.rst | 13 +++++++++++++
llvm/docs/ReleaseNotes.md | 1 +
llvm/lib/Target/RISCV/RISCVProcessors.td | 16 +++++++++++-----
3 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index d03f383a92b3b..64b486d71c1ae 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -601,3 +601,16 @@ Clang's ``-msmall-data-limit=`` option controls what the threshold size is (in b
The small data limit threshold is also used to separate small constants into sections with names starting with ``.srodata``. LLD does not place these with the ``.sdata`` and ``.sbss`` sections as ``.srodata`` sections are read only and the other two are writable. Instead the ``.srodata`` sections are placed adjacent to ``.rodata``.
Data suggests that these options can produce significant improvements across a range of benchmarks.
+
+Scheduling Model and Tuning
+===========================
+
+RISC-V is highly configurable, meaning its scheduling models could be highly diversified as well. Yet we still believe it is helpful to provide a "generic" tuning processor / scheduling model that represents the "lowest common denominator" RISC-V implementation at the time. The idea is that it could serve as a "good-enough" baseline model for performance tuning purposes on some of the most common use cases.
+
+Though details of this generic scheduling model might evolve over time, we always have some _expectations_ on the kind of processors it is used for.
+
+For example, the ``generic`` tuning processor is expected to target in-order application processors designed for general-purpose computing. It is usually (but not required to be) RVA22U64- or RVA23U64-capable. The ``generic-ooo`` has a similar set of expectations, except it is targeting out-of-order application processors.
+
+Right now, we simply assign a scheduling model that is widely used by the community to ``generic``. But in the future, we can create a standalone scheduling model for ``generic``, or even create a generic model for each of the individual sectors. For example, a ``generic-embedded`` for embedded processors and a ``generic-server`` for server workloads.
+
+These future generic models could even serve as the "base" model for other scheduling models to derive from: it's not uncommon for multiple processors to share a similar set of instruction scheduling info except a few key instructions, and this is especially true for RISC-V given its highly configurable nature. If we could design the base model in a way that it can be _parameterized_ by subtarget tuning features, we can substitue the traditional way of creating individual scheduling models with a combination of base scheduling model + different subtarget features.
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 23bba99ec874f..d330120214705 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -138,6 +138,7 @@ Changes to the RISC-V Backend
* Adds experimental support for the 'Zibi` (Branch with Immediate) extension.
* Add support for Zvfofp8min (OFP8 conversion extension)
* Adds assembler support for the Andes `XAndesvsinth` (Andes Vector Small Int Handling Extension).
+* `-mtune=generic` now uses the scheduling model from SpacemitX60 instead of an empty scheduling model.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index e86431f78f1ba..136e89687fa55 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -88,6 +88,17 @@ class RISCVTuneProcessorModel<string n,
defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore];
+// Support generic for compatibility with other targets. The triple will be used
+// to change to the appropriate rv32/rv64 version.
+// `generic` is expected to target in-order application processors designed for
+// general-purpose computing.
+def GENERIC : RISCVTuneProcessorModel<"generic", SpacemitX60Model>,
+ GenericTuneInfo;
+// `generic-ooo` is expected to target out-of-order application processors designed
+// for general-purpose computing.
+def GENERIC_OOO : RISCVTuneProcessorModel<"generic-ooo", GenericOOOModel>,
+ GenericTuneInfo;
+
def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
NoSchedModel,
[Feature32Bit,
@@ -100,11 +111,6 @@ def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
FeatureStdExtI],
GenericTuneFeatures>,
GenericTuneInfo;
-// Support generic for compatibility with other targets. The triple will be used
-// to change to the appropriate rv32/rv64 version.
-def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo;
-def GENERIC_OOO : RISCVTuneProcessorModel<"generic-ooo", GenericOOOModel>,
- GenericTuneInfo;
def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
MIPSP8700Model,
>From f004f865520037270ad6c1d4385f4cf0ed4f1494 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Fri, 7 Nov 2025 11:28:54 -0800
Subject: [PATCH 2/3] fixup! Add the description on superscalar and Linux
---
llvm/docs/RISCVUsage.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 64b486d71c1ae..e213db332cf38 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -609,7 +609,7 @@ RISC-V is highly configurable, meaning its scheduling models could be highly div
Though details of this generic scheduling model might evolve over time, we always have some _expectations_ on the kind of processors it is used for.
-For example, the ``generic`` tuning processor is expected to target in-order application processors designed for general-purpose computing. It is usually (but not required to be) RVA22U64- or RVA23U64-capable. The ``generic-ooo`` has a similar set of expectations, except it is targeting out-of-order application processors.
+For example, the ``generic`` tuning processor is expected to target in-order, superscalar application processors designed for general-purpose computing. It is usually RVA22U64- or RVA23U64-capable intended to run Linux. The ``generic-ooo`` has a similar set of expectations, except it is targeting out-of-order application processors.
Right now, we simply assign a scheduling model that is widely used by the community to ``generic``. But in the future, we can create a standalone scheduling model for ``generic``, or even create a generic model for each of the individual sectors. For example, a ``generic-embedded`` for embedded processors and a ``generic-server`` for server workloads.
>From 0fc7c742a85976cbb7e44a9e13c165e9fadb027c Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Fri, 7 Nov 2025 11:50:44 -0800
Subject: [PATCH 3/3] fixup! Formatting
---
llvm/lib/Target/RISCV/RISCVProcessors.td | 21 ++++++++++-----------
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 136e89687fa55..9e31d08ae2243 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -88,17 +88,6 @@ class RISCVTuneProcessorModel<string n,
defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore];
-// Support generic for compatibility with other targets. The triple will be used
-// to change to the appropriate rv32/rv64 version.
-// `generic` is expected to target in-order application processors designed for
-// general-purpose computing.
-def GENERIC : RISCVTuneProcessorModel<"generic", SpacemitX60Model>,
- GenericTuneInfo;
-// `generic-ooo` is expected to target out-of-order application processors designed
-// for general-purpose computing.
-def GENERIC_OOO : RISCVTuneProcessorModel<"generic-ooo", GenericOOOModel>,
- GenericTuneInfo;
-
def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
NoSchedModel,
[Feature32Bit,
@@ -111,6 +100,16 @@ def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
FeatureStdExtI],
GenericTuneFeatures>,
GenericTuneInfo;
+// Support generic for compatibility with other targets. The triple will be used
+// to change to the appropriate rv32/rv64 version.
+// `generic` is expected to target in-order application processors designed for
+// general-purpose computing.
+def GENERIC : RISCVTuneProcessorModel<"generic", SpacemitX60Model>,
+ GenericTuneInfo;
+// `generic-ooo` is expected to target out-of-order application processors designed
+// for general-purpose computing.
+def GENERIC_OOO : RISCVTuneProcessorModel<"generic-ooo", GenericOOOModel>,
+ GenericTuneInfo;
def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
MIPSP8700Model,
More information about the llvm-commits
mailing list