[llvm] [llvm][RISCV] Do not assume V extension on seeing vector type. (PR #166994)

[Chenguang Wang via llvm-commits]

https://github.com/wecing updated https://github.com/llvm/llvm-project/pull/166994

>From a46983a068adc40f247a8689ff26705c2b665319 Mon Sep 17 00:00:00 2001
From: Chenguang Wang <w3cing at gmail.com>
Date: Fri, 7 Nov 2025 10:44:12 -0800
Subject: [PATCH 1/2] [llvm][RISCV] Do not assume V extension on seeing vector
 type.

We have a private extension which also uses the vector type in the
frontend. Our platform does not have the V extension, so it triggered
assertion failures from within getLMULCost().

I am not sure what is the best way to handle this, or if there are more
such assertions within the codebase. But it feels reasonable to check
for V extension before assuming LMUL exists.
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 7bc0b5b394828..ababe42604ba5 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2140,8 +2140,9 @@ InstructionCost RISCVTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
   // Assume memory ops cost scale with the number of vector registers
   // possible accessed by the instruction.  Note that BasicTTI already
   // handles the LT.first term for us.
-  if (LT.second.isVector() && CostKind != TTI::TCK_CodeSize)
-    BaseCost *= TLI->getLMULCost(LT.second);
+  if (TLI->getSubtarget().hasVInstructions())
+    if (LT.second.isVector() && CostKind != TTI::TCK_CodeSize)
+      BaseCost *= TLI->getLMULCost(LT.second);
   return Cost + BaseCost;
 }
 

>From b7abc70280eabf4509b92d1503b5b7696d6030ef Mon Sep 17 00:00:00 2001
From: Chenguang Wang <w3cing at gmail.com>
Date: Fri, 7 Nov 2025 11:15:38 -0800
Subject: [PATCH 2/2] use ST->hasVInstructions() and reduce if-nesting

---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index ababe42604ba5..332433b4e530b 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2140,9 +2140,9 @@ InstructionCost RISCVTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
   // Assume memory ops cost scale with the number of vector registers
   // possible accessed by the instruction.  Note that BasicTTI already
   // handles the LT.first term for us.
-  if (TLI->getSubtarget().hasVInstructions())
-    if (LT.second.isVector() && CostKind != TTI::TCK_CodeSize)
-      BaseCost *= TLI->getLMULCost(LT.second);
+  if (ST->hasVInstructions() && LT.second.isVector() &&
+      CostKind != TTI::TCK_CodeSize)
+    BaseCost *= TLI->getLMULCost(LT.second);
   return Cost + BaseCost;
 }