[llvm] AArch64: align pair-wise spills on WoS to 16-byte (PR #166902)

[Eli Friedman via llvm-commits]

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@@ -1568,8 +1569,14 @@ static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2,
     return true;
   if (!NeedsWinCFI)
     return false;
+  // ARM64EC introduced `save_any_regp` which expects 16-byte alignment.
+  // Accomodate that by ensuring that we re-align to 16-bytes when doing paired
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efriedma-quic wrote:

I don't really want to regress general arm64 codegen to handle edge cases.  If it was rare, maybe it wouldn't matter, but the test changes seem to indicate it isn't that rare.

In some cases, we actually could make the stores 16-byte aligned by just rearranging where we insert padding.  Like, in stack-hazard-windows.ll, we have 8 bytes of padding at sp+40; if we move that to sp+8, we can shuffle the paired stores up 8 bytes, so they're aligned.

https://github.com/llvm/llvm-project/pull/166902