[llvm] [AMDGPU] Stop optimising readfirstlane in pass AMDGPUUniformIntrinsicCombine (PR #166955)

[Jay Foad via llvm-commits]

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@@ -57,10 +57,8 @@ static bool optimizeUniformIntrinsic(IntrinsicInst &II,
                                      const UniformityInfo &UI,
                                      ValueMap<const Value *, bool> &Tracker) {
   llvm::Intrinsic::ID IID = II.getIntrinsicID();
-
   switch (IID) {
   case Intrinsic::amdgcn_permlane64:
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jayfoad wrote:

Suggest adding a comment here saying that we deliberately do not simplify readfirstlane with a uniform argument, so that frontends can use it to force a copy to SGPR and thereby prevent the backend from generating unwanted waterfall loops.

https://github.com/llvm/llvm-project/pull/166955