[llvm] AArch64: align pair-wise spills on WoS to 16-byte (PR #166902)

[Benjamin Maxwell via llvm-commits]

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@@ -1752,15 +1760,15 @@ void computeCalleeSaveRegisterPairs(const AArch64FrameLowering &AFL,
       switch (RPI.Type) {
       case RegPairInfo::GPR:
         if (AArch64::GPR64RegClass.contains(NextReg) &&
-            !invalidateRegisterPairing(RPI.Reg1, NextReg, IsWindows,
-                                       NeedsWinCFI, NeedsFrameRecord, IsFirst,
-                                       TRI))
+            !invalidateRegisterPairing(i - FirstReg, RPI.Reg1, NextReg,
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MacDue wrote:

I find this "Spilled" variable somewhat confusing. On Windows, this is going to wrap to 0, -1, -2, ... on an `unsigned` type.  

Could you keep the numbers sensible by handling both cases explicitly:  `unsigned SpillIndex = NeedsWinCFI ? FirstReg - i : i;`

Also, please rename `Spilled` -> `SpillIndex` ('Spilled' sounds like a boolean).


https://github.com/llvm/llvm-project/pull/166902