[llvm] [AArch64][SVE] Avoid redundant extend of unsigned i8/i16 extracts. (PR #165863)

[Ricardo Jesus via llvm-commits]

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@@ -3592,6 +3592,19 @@ let Predicates = [HasSVE_or_SME] in {
 
   def : Pat<(sext (i32 (vector_extract nxv4i32:$vec, VectorIndexS:$index))),
             (SMOVvi32to64 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>;
+
+  // Extracts of ``unsigned'' i8 or i16 elements lead to the zero-extend being
+  // transformed to an AND mask. The mask is redundant since UMOV already zeroes
+  // the high bits of the destination register.
+  // We do something similar in the Neon versions of these patterns.
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rj-jesus wrote:

I believe I had intended it to help with reviewing, but I've now removed it.

https://github.com/llvm/llvm-project/pull/165863