[llvm] [AArch64] Fold scalar-to-vector shuffles into DUP/FMOV (PR #166962)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 6f0909717..27b9f4f76 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -15682,9 +15682,11 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
       bool IsLoSplatHiZero = true;
       for (unsigned i = 0; i < NumElts; ++i) {
         SDValue Vi = Op.getOperand(i);
-        bool violates = (i < HalfElts) ? (Vi != FirstVal)
-                                      : !IsZero(Vi);
-        if (violates) { IsLoSplatHiZero = false; break; }
+        bool violates = (i < HalfElts) ? (Vi != FirstVal) : !IsZero(Vi);
+        if (violates) {
+          IsLoSplatHiZero = false;
+          break;
+        }
       }
 
       if (IsLoSplatHiZero) {
@@ -15693,21 +15695,21 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
 
         auto buildSubregToReg = [&](SDValue LoHalf) -> SDValue {
           SDValue ZeroImm = DAG.getTargetConstant(0, DL, MVT::i32);
-          SDValue SubIdx  = DAG.getTargetConstant(AArch64::dsub, DL, MVT::i32);
+          SDValue SubIdx = DAG.getTargetConstant(AArch64::dsub, DL, MVT::i32);
           SDNode *N = DAG.getMachineNode(TargetOpcode::SUBREG_TO_REG, DL, VT,
-                                        {ZeroImm, LoHalf, SubIdx});
+                                         {ZeroImm, LoHalf, SubIdx});
           return SDValue(N, 0);
         };
 
         if (LaneBits == 64) {
           // v2i64
           SDValue First64 = DAG.getZExtOrTrunc(FirstVal, DL, MVT::i64);
-          SDValue Lo      = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, HalfVT, First64);
+          SDValue Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, HalfVT, First64);
           return buildSubregToReg(Lo);
         } else {
           // v4i32/v8i16/v16i8
           SDValue FirstW = DAG.getZExtOrTrunc(FirstVal, DL, MVT::i32);
-          SDValue DupLo  = DAG.getNode(AArch64ISD::DUP, DL, HalfVT, FirstW);
+          SDValue DupLo = DAG.getNode(AArch64ISD::DUP, DL, HalfVT, FirstW);
           return buildSubregToReg(DupLo);
         }
       }

``````````

</details>


https://github.com/llvm/llvm-project/pull/166962