[llvm] [SPIRV] Fix failing assertion in SPIRVAsmPrinter (PR #166909)
Juan Manuel Martinez Caamaño via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 7 01:12:24 PST 2025
https://github.com/jmmartinez created https://github.com/llvm/llvm-project/pull/166909
With `+SPV_KHR_float_controls2` and when there is a non-int `OpConstantNull` we
would call `MI.getOperand(1).getImm()` when `MI` was not an `OpTypeInt` (the
associated test has an `OpTypeArray` zeroinitialized).
Under this conditions an assertion is triggered.
This patch adds the missing condition.
>From a43f7dd8b97e3e6aa998bceb2f95b578fd337a88 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Juan=20Manuel=20Martinez=20Caama=C3=B1o?=
<jmartinezcaamao at gmail.com>
Date: Fri, 7 Nov 2025 09:29:21 +0100
Subject: [PATCH 1/3] Pre-commit test
---
llvm/test/CodeGen/SPIRV/non_int_constant_null.ll | 10 ++++++++++
1 file changed, 10 insertions(+)
create mode 100644 llvm/test/CodeGen/SPIRV/non_int_constant_null.ll
diff --git a/llvm/test/CodeGen/SPIRV/non_int_constant_null.ll b/llvm/test/CodeGen/SPIRV/non_int_constant_null.ll
new file mode 100644
index 0000000000000..948fecc92380a
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/non_int_constant_null.ll
@@ -0,0 +1,10 @@
+; RUN: not llc -mtriple spirv64-unknown-unknown %s --spirv-ext=+SPV_KHR_float_controls2 -o -
+; Assertion `isImm() && "Wrong MachineOperand accessor"' failed
+; On TypeMI->getOperand(1).getImm() then TypeMI is OpTypeArray %8, %17
+
+ at A = addrspace(1) constant [1 x i8] zeroinitializer
+
+define spir_kernel void @foo() {
+entry:
+ ret void
+}
>From 54631ebca46a680937464b9ed352d650170dd64e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Juan=20Manuel=20Martinez=20Caama=C3=B1o?=
<jmartinezcaamao at gmail.com>
Date: Fri, 7 Nov 2025 10:00:19 +0100
Subject: [PATCH 2/3] [SPIRV] Fix failing assertion in SPIRVAsmPrinter
When +SPV_KHR_float_controls2 and there was a non-int OpConstantZero we
would call MI.getOperand(1).getImm() when MI was not an OpTypeInt (the
associated test has an OpTypeArray zeroinitialized).
This patch adds the missing condition.
---
llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp | 5 ++++-
.../CodeGen/SPIRV/non_int_constant_null.ll | 21 ++++++++++++++++---
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
index 0175f2fb3698b..75e5d81a804f1 100644
--- a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
@@ -633,7 +633,10 @@ void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
// Check if the constant is int32, if not skip it.
const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
MachineInstr *TypeMI = MRI.getVRegDef(MI->getOperand(1).getReg());
- if (!TypeMI || TypeMI->getOperand(1).getImm() != 32)
+ bool IsInt32Ty = TypeMI &&
+ TypeMI->getOpcode() == SPIRV::OpTypeInt &&
+ TypeMI->getOperand(1).getImm() == 32;
+ if (!IsInt32Ty)
continue;
ConstZero = MI;
diff --git a/llvm/test/CodeGen/SPIRV/non_int_constant_null.ll b/llvm/test/CodeGen/SPIRV/non_int_constant_null.ll
index 948fecc92380a..0ba016aaa30aa 100644
--- a/llvm/test/CodeGen/SPIRV/non_int_constant_null.ll
+++ b/llvm/test/CodeGen/SPIRV/non_int_constant_null.ll
@@ -1,9 +1,24 @@
-; RUN: not llc -mtriple spirv64-unknown-unknown %s --spirv-ext=+SPV_KHR_float_controls2 -o -
-; Assertion `isImm() && "Wrong MachineOperand accessor"' failed
-; On TypeMI->getOperand(1).getImm() then TypeMI is OpTypeArray %8, %17
+; RUN: llc -mtriple spirv64-unknown-unknown %s --spirv-ext=+SPV_KHR_float_controls2 -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -mtriple spirv64-unknown-unknown %s --spirv-ext=+SPV_KHR_float_controls2 -o - -filetype=obj | spirv-val %}
@A = addrspace(1) constant [1 x i8] zeroinitializer
+; CHECK: OpName %[[#FOO:]] "foo"
+; CHECK: OpName %[[#A:]] "A"
+; CHECK: OpDecorate %[[#A]] Constant
+; CHECK: OpDecorate %[[#A]] LinkageAttributes "A" Export
+; CHECK: %[[#INT8:]] = OpTypeInt 8 0
+; CHECK: %[[#INT32:]] = OpTypeInt 32 0
+; CHECK: %[[#ONE:]] = OpConstant %[[#INT32]] 1
+; CHECK: %[[#ARR_INT8:]] = OpTypeArray %[[#INT8]] %7
+; CHECK: %[[#ARR_INT8_PTR:]] = OpTypePointer CrossWorkgroup %[[#ARR_INT8]]
+; CHECK: %[[#ARR_INT8_ZERO:]] = OpConstantNull %[[#ARR_INT8]]
+; CHECK: %13 = OpVariable %[[#ARR_INT8_PTR]] CrossWorkgroup %[[#ARR_INT8_ZERO]]
+; CHECK: %[[#FOO]] = OpFunction
+; CHECK: = OpLabel
+; CHECK: OpReturn
+; CHECK: OpFunctionEnd
+
define spir_kernel void @foo() {
entry:
ret void
>From db3552b1474775f5ad76d54b12aeb6a44eff68d0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Juan=20Manuel=20Martinez=20Caama=C3=B1o?=
<jmartinezcaamao at gmail.com>
Date: Fri, 7 Nov 2025 10:02:43 +0100
Subject: [PATCH 3/3] [Refactor] redundant conditions and rename variables
---
llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp | 21 ++++++++++-----------
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
index 75e5d81a804f1..b10846aeee6a4 100644
--- a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
@@ -612,13 +612,10 @@ void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
// Collect the SPIRVTypes for fp16, fp32, and fp64 and the constant of
// type int32 with 0 value to represent the FP Fast Math Mode.
std::vector<const MachineInstr *> SPIRVFloatTypes;
- const MachineInstr *ConstZero = nullptr;
+ const MachineInstr *ConstZeroInt32 = nullptr;
for (const MachineInstr *MI :
MAI->getMSInstrs(SPIRV::MB_TypeConstVars)) {
- // Skip if the instruction is not OpTypeFloat or OpConstant.
unsigned OpCode = MI->getOpcode();
- if (OpCode != SPIRV::OpTypeFloat && OpCode != SPIRV::OpConstantNull)
- continue;
// Collect the SPIRV type if it's a float.
if (OpCode == SPIRV::OpTypeFloat) {
@@ -629,17 +626,19 @@ void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
continue;
}
SPIRVFloatTypes.push_back(MI);
- } else {
+ continue;
+ }
+
+ if (OpCode == SPIRV::OpConstantNull) {
// Check if the constant is int32, if not skip it.
const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
MachineInstr *TypeMI = MRI.getVRegDef(MI->getOperand(1).getReg());
bool IsInt32Ty = TypeMI &&
TypeMI->getOpcode() == SPIRV::OpTypeInt &&
TypeMI->getOperand(1).getImm() == 32;
- if (!IsInt32Ty)
- continue;
-
- ConstZero = MI;
+ if (IsInt32Ty)
+ ConstZeroInt32 = MI;
+ continue;
}
}
@@ -660,9 +659,9 @@ void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
MCRegister TypeReg =
MAI->getRegisterAlias(MF, MI->getOperand(0).getReg());
Inst.addOperand(MCOperand::createReg(TypeReg));
- assert(ConstZero && "There should be a constant zero.");
+ assert(ConstZeroInt32 && "There should be a constant zero.");
MCRegister ConstReg = MAI->getRegisterAlias(
- ConstZero->getMF(), ConstZero->getOperand(0).getReg());
+ ConstZeroInt32->getMF(), ConstZeroInt32->getOperand(0).getReg());
Inst.addOperand(MCOperand::createReg(ConstReg));
outputMCInst(Inst);
}
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