[llvm] [AMDGPU] Add pattern to select scalar ops for fshr with uniform operands (PR #165295)

[Jay Foad via llvm-commits]

jayfoad wrote:

I really don't think it's worth worrying about the slight regressions pre-GFX9.

Firstly it only seems to affect SI (GFX6) and not VI (GFX8).

Secondly the only large regressions I noticed were for bitcasting 256-bit or larger vector types, which is not super common.

Thirdly it only seems to affect cases that are uniform but where the inputs are in VGPRs, so SIFixSGPRCopies converts all the S_LSHR_B64 to V_LSHRREV_B64, thereby defeating the point of this patch. This is a generic problem with all patterns that want to choose different expansions for SALU vs VALU, and not something you need to try to solve in this patch. (If you _did_ want to improve this case, then maybe we should select to a new S_ALIGNBIT_B32_pseudo instruction that gets expanded after SIFixSGPRCopies to either S_LSHR_B64 or V_ALIGNBIT_B32.)

https://github.com/llvm/llvm-project/pull/165295