[llvm] [AMDGPU] Allow folding of non-subregs through REG_SEQUENCE (PR #151033)

[Matt Arsenault via llvm-commits]

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@@ -1465,6 +1477,33 @@ void SIFoldOperandsImpl::foldOperand(
       return;
   }
 
+  if (!FoldingImmLike && OpToFold.isReg() && ST->needsAlignedVGPRs()) {
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arsenm wrote:

For the GWS cases, the high 32-bits are just discarded. The requirement is just the register used is even aligned, which currently we can only encode by using the 64-bit aligned register classes.

This case is far removed from something this pass should have to worry about. If the instruction were properly defined, you wouldn't have to worry about it. Ideally instructions accurately express their constraints and don't require special casing anywhere else 

https://github.com/llvm/llvm-project/pull/151033