[clang] [llvm] [SelectionDAG] Fix assertion failure on inline asm register type mismatch (PR #166615)

[Phoebe Wang via llvm-commits]

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@@ -1,13 +1,13 @@
 // RUN: %clang_cc1 -verify -triple x86_64-unknown-unknown -emit-llvm-only %s
+// RUN: %clang_cc1 -verify -triple x86_64-unknown-unknown -emit-llvm-only -fopenmp %s
 typedef int vec256 __attribute__((ext_vector_type(8)));
 
 vec256 foo(vec256 in) {
   vec256 out;
 
-  asm("something %0" : : "y"(in)); // expected-error {{invalid input size for constraint 'y'}}
-  asm("something %0" : "=y"(out)); // expected-error {{invalid output size for constraint '=y'}}
-  asm("something %0, %0" : "+y"(out)); // expected-error {{invalid output size for constraint '+y'}}
+  asm("something %0" : : "y"(in)); // expected-error {{invalid type 'vec256' (vector of 8 'int' values) in asm input for constraint 'y'}}
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phoebewang wrote:

Or use `{{.*}}` to ignore the difference.

https://github.com/llvm/llvm-project/pull/166615