[llvm] [mlir] [SPIRV]Added support for extension SPV_ALTERA_arbitrary_precision_fixed_point (PR #136085)
Aadesh Premkumar via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 6 05:11:38 PST 2025
https://github.com/aadeshps-mcw updated https://github.com/llvm/llvm-project/pull/136085
>From ae8f7f897671bc7cd50c5ba33ef731bb89238e29 Mon Sep 17 00:00:00 2001
From: Aadesh PremKumar <aadesh.premkumar at multicorewareinc.com>
Date: Tue, 13 May 2025 11:59:12 +0530
Subject: [PATCH 1/6] --Updated the test file
---
llvm/docs/SPIRVUsage.rst | 3 +
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 73 +++++
llvm/lib/Target/SPIRV/SPIRVBuiltins.td | 14 +
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 6 +-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 29 +-
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 21 ++
.../lib/Target/SPIRV/SPIRVSymbolicOperands.td | 3 +
...arbitrary-precision-fixed-point-numbers.ll | 255 ++++++++++++++++++
8 files changed, 398 insertions(+), 6 deletions(-)
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index 9ecd39025e781..4221b512cbcee 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -243,6 +243,9 @@ Below is a list of supported SPIR-V extensions, sorted alphabetically by their e
- Adds execution mode and capability to enable maximal reconvergence.
* - ``SPV_ALTERA_blocking_pipes``
- Adds new pipe read and write functions that have blocking semantics instead of the non-blocking semantics of the existing pipe read/write functions.
+ * - ``SPV_INTEL_arbitrary_precision_fixed_point``
+ - Add instructions for fixed point arithmetic. The extension works without SPV_INTEL_arbitrary_precision_integers, but together they allow greater flexibility in representing arbitrary precision data types.
+
SPIR-V representation in LLVM IR
================================
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index b2cbdb2ad7375..86a41ff83e3b9 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -2399,6 +2399,77 @@ static bool generateBlockingPipesInst(const SPIRV::IncomingCall *Call,
return buildOpFromWrapper(MIRBuilder, Opcode, Call, Register(0));
}
+static bool buildAPFixedPointInst(const SPIRV::IncomingCall *Call,
+ unsigned Opcode, MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ MachineRegisterInfo *MRI = MIRBuilder.getMRI();
+ SmallVector<uint32_t, 1> ImmArgs;
+ Register InputReg = Call->Arguments[0];
+ const Type *RetTy = GR->getTypeForSPIRVType(Call->ReturnType);
+ bool IsSRet = RetTy->isVoidTy();
+
+ if (IsSRet) {
+ const LLT ValTy = MRI->getType(InputReg);
+ Register ActualRetValReg = MRI->createGenericVirtualRegister(ValTy);
+ SPIRVType *InstructionType =
+ GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
+ InputReg = Call->Arguments[1];
+ auto InputType = GR->getTypeForSPIRVType(GR->getSPIRVTypeForVReg(InputReg));
+ Register PtrInputReg;
+ if (InputType->getTypeID() == llvm::Type::TypeID::TypedPointerTyID) {
+ LLT InputLLT = MRI->getType(InputReg);
+ PtrInputReg = MRI->createGenericVirtualRegister(InputLLT);
+ SPIRVType *PtrType =
+ GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
+ MachineMemOperand *MMO1 = MIRBuilder.getMF().getMachineMemOperand(
+ MachinePointerInfo(), MachineMemOperand::MOLoad,
+ InputLLT.getSizeInBytes(), Align(4));
+ MIRBuilder.buildLoad(PtrInputReg, InputReg, *MMO1);
+ MRI->setRegClass(PtrInputReg, &SPIRV::iIDRegClass);
+ GR->assignSPIRVTypeToVReg(PtrType, PtrInputReg, MIRBuilder.getMF());
+ }
+
+ for (unsigned index = 2; index < 7; index++) {
+ ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
+ }
+
+ // Emit the instruction
+ auto MIB = MIRBuilder.buildInstr(Opcode)
+ .addDef(ActualRetValReg)
+ .addUse(GR->getSPIRVTypeID(InstructionType));
+ if (PtrInputReg)
+ MIB.addUse(PtrInputReg);
+ else
+ MIB.addUse(InputReg);
+
+ for (uint32_t Imm : ImmArgs)
+ MIB.addImm(Imm);
+ unsigned Size = ValTy.getSizeInBytes();
+ // Store result to the pointer passed in Arg[0]
+ MachineMemOperand *MMO = MIRBuilder.getMF().getMachineMemOperand(
+ MachinePointerInfo(), MachineMemOperand::MOStore, Size, Align(4));
+ MRI->setRegClass(ActualRetValReg, &SPIRV::pIDRegClass);
+ MIRBuilder.buildStore(ActualRetValReg, Call->Arguments[0], *MMO);
+ return true;
+ } else {
+ for (unsigned index = 1; index < 6; index++)
+ ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
+
+ return buildOpFromWrapper(MIRBuilder, Opcode, Call,
+ GR->getSPIRVTypeID(Call->ReturnType), ImmArgs);
+ }
+}
+
+static bool generateAPFixedPointInst(const SPIRV::IncomingCall *Call,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
+ unsigned Opcode =
+ SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
+
+ return buildAPFixedPointInst(Call, Opcode, MIRBuilder, GR);
+}
+
static bool
generateTernaryBitwiseFunctionINTELInst(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
@@ -3051,6 +3122,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
return generateExtendedBitOpsInst(Call.get(), MIRBuilder, GR);
case SPIRV::BindlessINTEL:
return generateBindlessImageINTELInst(Call.get(), MIRBuilder, GR);
+ case SPIRV::ArbitraryPrecisionFixedPoint:
+ return generateAPFixedPointInst(Call.get(), MIRBuilder, GR);
case SPIRV::TernaryBitwiseINTEL:
return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
case SPIRV::Block2DLoadStore:
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
index 492a98e1995fe..bf657503a386a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
@@ -71,6 +71,7 @@ def TernaryBitwiseINTEL : BuiltinGroup;
def Block2DLoadStore : BuiltinGroup;
def Pipe : BuiltinGroup;
def PredicatedLoadStore : BuiltinGroup;
+def ArbitraryPrecisionFixedPoint : BuiltinGroup;
def BlockingPipes : BuiltinGroup;
//===----------------------------------------------------------------------===//
@@ -1181,6 +1182,19 @@ defm : DemangledNativeBuiltin<"__spirv_WritePipeBlockingINTEL", OpenCL_std, Bloc
defm : DemangledNativeBuiltin<"__spirv_ReadPipeBlockingINTEL", OpenCL_std, BlockingPipes, 0, 0, OpReadPipeBlockingALTERA>;
defm : DemangledNativeBuiltin<"__spirv_ReadClockKHR", OpenCL_std, KernelClock, 1, 1, OpReadClockKHR>;
+//SPV_INTEL_arbitrary_precision_fixed_point
+defm : DemangledNativeBuiltin<"__spirv_FixedSqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSqrtINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedRecipINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRecipINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedRsqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRsqrtINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedLogINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedLogINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedExpINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedExpINTEL>;
+
//===----------------------------------------------------------------------===//
// Class defining an atomic instruction on floating-point numbers.
//
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index f681b0d9fb433..7a9f43b767966 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -161,7 +161,11 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
{"SPV_INTEL_kernel_attributes",
SPIRV::Extension::Extension::SPV_INTEL_kernel_attributes},
{"SPV_ALTERA_blocking_pipes",
- SPIRV::Extension::Extension::SPV_ALTERA_blocking_pipes}};
+ SPIRV::Extension::Extension::SPV_ALTERA_blocking_pipes},
+ {"SPV_INTEL_int4", SPIRV::Extension::Extension::SPV_INTEL_int4},
+ {"SPV_ALTERA_arbitrary_precision_fixed_point",
+ SPIRV::Extension::Extension::
+ SPV_ALTERA_arbitrary_precision_fixed_point}};
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
StringRef ArgValue,
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 03bd61bdf2cf6..9a5181964c68c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -994,8 +994,27 @@ def OpPredicatedLoadINTEL: Op<6528, (outs ID:$res), (ins TYPE:$resType, ID:$ptr,
def OpPredicatedStoreINTEL: Op<6529, (outs), (ins ID:$ptr, ID:$object, ID:$predicate, variable_ops),
"OpPredicatedStoreINTEL $ptr $object $predicate">;
-//SPV_ALTERA_blocking_pipes
-def OpReadPipeBlockingALTERA :Op<5946, (outs), (ins ID:$pipe, ID:$pointer, ID:$packetSize, ID:$packetAlignment),
- "OpReadPipeBlockingALTERA $pipe $pointer $packetSize $packetAlignment">;
-def OpWritePipeBlockingALTERA :Op<5946, (outs), (ins ID:$pipe, ID:$pointer, ID:$packetSize, ID:$packetAlignment),
- "OpWritePipeBlockingALTERA $pipe $pointer $packetSize $packetAlignment">;
+//SPV_INTEL_arbitrary_precision_fixed_point
+def OpFixedSqrtINTEL: Op<5923, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSqrtINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedRecipINTEL: Op<5924, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedRecipINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedRsqrtINTEL: Op<5925, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedRsqrtINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinINTEL: Op<5926, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedCosINTEL: Op<5927, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedCosINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinCosINTEL: Op<5928, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinCosINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinPiINTEL: Op<5929, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinPiINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedCosPiINTEL: Op<5930, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedCosPiINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinCosPiINTEL: Op<5931, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinCosPiINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedLogINTEL: Op<5932, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedLogINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedExpINTEL: Op<5933, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedExpINTEL $result_type $input $sign $l $rl $q $o">;
+
\ No newline at end of file
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index af76016861761..f9f62066c1628 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1670,6 +1670,27 @@ void addInstrRequirements(const MachineInstr &MI,
Reqs.addCapability(SPIRV::Capability::GroupNonUniformRotateKHR);
Reqs.addCapability(SPIRV::Capability::GroupNonUniform);
break;
+ case SPIRV::OpFixedCosINTEL:
+ case SPIRV::OpFixedSinINTEL:
+ case SPIRV::OpFixedCosPiINTEL:
+ case SPIRV::OpFixedSinPiINTEL:
+ case SPIRV::OpFixedExpINTEL:
+ case SPIRV::OpFixedLogINTEL:
+ case SPIRV::OpFixedRecipINTEL:
+ case SPIRV::OpFixedSqrtINTEL:
+ case SPIRV::OpFixedSinCosINTEL:
+ case SPIRV::OpFixedSinCosPiINTEL:
+ case SPIRV::OpFixedRsqrtINTEL:
+ if (!ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point))
+ report_fatal_error("This instruction requires the "
+ "following SPIR-V extension: "
+ "SPV_INTEL_arbitrary_precision_fixed_point",
+ false);
+ Reqs.addExtension(
+ SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point);
+ Reqs.addCapability(SPIRV::Capability::ArbitraryPrecisionFixedPointINTEL);
+ break;
case SPIRV::OpGroupIMulKHR:
case SPIRV::OpGroupFMulKHR:
case SPIRV::OpGroupBitwiseAndKHR:
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index 65a888529bb58..fe2fe05d3374d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -389,6 +389,7 @@ defm SPV_INTEL_predicated_io : ExtensionOperand<127, [EnvOpenCL]>;
defm SPV_KHR_maximal_reconvergence : ExtensionOperand<128, [EnvVulkan]>;
defm SPV_INTEL_bfloat16_arithmetic
: ExtensionOperand<129, [EnvVulkan, EnvOpenCL]>;
+defm SPV_INTEL_arbitrary_precision_fixed_point : ExtensionOperand<130, [EnvOpenCL]>;
//===----------------------------------------------------------------------===//
// Multiclass used to define Capabilities enum values and at the same time
@@ -608,10 +609,12 @@ defm PredicatedIOINTEL : CapabilityOperand<6257, 0, 0, [SPV_INTEL_predicated_io]
defm Int4TypeINTEL : CapabilityOperand<5112, 0, 0, [SPV_INTEL_int4], []>;
defm Int4CooperativeMatrixINTEL : CapabilityOperand<5114, 0, 0, [SPV_INTEL_int4], [Int4TypeINTEL, CooperativeMatrixKHR]>;
defm TensorFloat32RoundingINTEL : CapabilityOperand<6425, 0, 0, [SPV_INTEL_tensor_float32_conversion], []>;
+<<<<<<< HEAD
defm BFloat16TypeKHR : CapabilityOperand<5116, 0, 0, [SPV_KHR_bfloat16], []>;
defm BFloat16DotProductKHR : CapabilityOperand<5117, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR]>;
defm BFloat16CooperativeMatrixKHR : CapabilityOperand<5118, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR, CooperativeMatrixKHR]>;
defm BlockingPipesALTERA : CapabilityOperand<5945, 0, 0, [SPV_ALTERA_blocking_pipes], []>;
+defm ArbitraryPrecisionFixedPointINTEL : CapabilityOperand<5922, 0, 0, [SPV_INTEL_arbitrary_precision_fixed_point], []>;
//===----------------------------------------------------------------------===//
// Multiclass used to define SourceLanguage enum values and at the same time
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
new file mode 100644
index 0000000000000..0e003d217ace7
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
@@ -0,0 +1,255 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_fixed_point,+SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s
+; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_fixed_point,+SPV_INTEL_arbitrary_precision_integers %s -o - -filetype=obj | spirv-val %}
+
+
+; CHECK-DAG: OpCapability Kernel
+; CHECK-DAG: OpCapability ArbitraryPrecisionIntegersINTEL
+; CHECK-DAG: OpCapability ArbitraryPrecisionFixedPointINTEL
+; CHECK-DAG: OpExtension "SPV_INTEL_arbitrary_precision_fixed_point"
+; CHECK-DAG: OpExtension "SPV_INTEL_arbitrary_precision_integers"
+
+; CHECK-DAG: %[[Ty_8:[0-9]+]] = OpTypeInt 8 0
+; CHECK-DAG: %[[Ty_13:[0-9]+]] = OpTypeInt 13 0
+; CHECK-DAG: %[[Ty_5:[0-9]+]] = OpTypeInt 5 0
+; CHECK-DAG: %[[Ty_3:[0-9]+]] = OpTypeInt 3 0
+; CHECK-DAG: %[[Ty_11:[0-9]+]] = OpTypeInt 11 0
+; CHECK-DAG: %[[Ty_10:[0-9]+]] = OpTypeInt 10 0
+; CHECK-DAG: %[[Ty_17:[0-9]+]] = OpTypeInt 17 0
+; CHECK-DAG: %[[Ty_35:[0-9]+]] = OpTypeInt 35 0
+; CHECK-DAG: %[[Ty_28:[0-9]+]] = OpTypeInt 28 0
+; CHECK-DAG: %[[Ty_31:[0-9]+]] = OpTypeInt 31 0
+; CHECK-DAG: %[[Ty_40:[0-9]+]] = OpTypeInt 40 0
+; CHECK-DAG: %[[Ty_60:[0-9]+]] = OpTypeInt 60 0
+; CHECK-DAG: %[[Ty_16:[0-9]+]] = OpTypeInt 16 0
+; CHECK-DAG: %[[Ty_64:[0-9]+]] = OpTypeInt 64 0
+; CHECK-DAG: %[[Ty_44:[0-9]+]] = OpTypeInt 44 0
+; CHECK-DAG: %[[Ty_34:[0-9]+]] = OpTypeInt 34 0
+; CHECK-DAG: %[[Ty_51:[0-9]+]] = OpTypeInt 51 0
+
+; CHECK: %[[Sqrt_InId:[0-9]+]] = OpLoad %[[Ty_13]]
+; CHECK-NEXT: %[[#]] = OpFixedSqrtINTEL %[[Ty_5]] %[[Sqrt_InId]] 0 2 2 0 0
+
+; CHECK: %[[Recip_InId:[0-9]+]] = OpLoad %[[Ty_3]]
+; CHECK-NEXT: %[[#]] = OpFixedRecipINTEL %[[Ty_8]] %[[Recip_InId]] 1 4 4 0 0
+
+; CHECK: %[[Rsqrt_InId:[0-9]+]] = OpLoad %[[Ty_11]]
+; CHECK-NEXT: %[[#]] = OpFixedRsqrtINTEL %[[Ty_10]] %[[Rsqrt_InId]] 0 8 6 0 0
+
+; CHECK: %[[Sin_InId:[0-9]+]] = OpLoad %[[Ty_17]]
+; CHECK-NEXT: %[[#]] = OpFixedSinINTEL %[[Ty_11]] %[[Sin_InId]] 1 7 5 0 0
+
+; CHECK: %[[Cos_InId:[0-9]+]] = OpLoad %[[Ty_35]]
+; CHECK-NEXT: %[[#]] = OpFixedCosINTEL %[[Ty_28]] %[[Cos_InId]] 0 9 3 0 0
+
+; CHECK: %[[SinCos_InId:[0-9]+]] = OpLoad %[[Ty_31]]
+; CHECK-NEXT: %[[#]] = OpFixedSinCosINTEL %[[Ty_40]] %[[SinCos_InId]] 1 10 12 0 0
+
+; CHECK: %[[SinPi_InId:[0-9]+]] = OpLoad %[[Ty_60]]
+; CHECK-NEXT: %[[#]] = OpFixedSinPiINTEL %[[Ty_5]] %[[SinPi_InId]] 0 2 2 0 0
+
+; CHECK: %[[CosPi_InId:[0-9]+]] = OpLoad %[[Ty_28]]
+; CHECK-NEXT: %[[#]] = OpFixedCosPiINTEL %[[Ty_16]] %[[CosPi_InId]] 0 8 5 0 0
+
+; CHECK: %[[SinCosPi_InId:[0-9]+]] = OpLoad %[[Ty_13]]
+; CHECK-NEXT: %[[#]] = OpFixedSinCosPiINTEL %[[Ty_10]] %[[SinCosPi_InId]] 0 2 2 0 0
+
+; CHECK: %[[Log_InId:[0-9]+]] = OpLoad %[[Ty_64]]
+; CHECK-NEXT: %[[#]] = OpFixedLogINTEL %[[Ty_44]] %[[Log_InId]] 1 24 22 0 0
+
+; CHECK: %[[Exp_InId:[0-9]+]] = OpLoad %[[Ty_44]]
+; CHECK-NEXT: %[[#]] = OpFixedExpINTEL %[[Ty_34]] %[[Exp_InId]] 0 20 20 0 0
+
+; CHECK: %[[SinCos_InId:[0-9]+]] = OpLoad %[[Ty_34]]
+; CHECK-NEXT: %[[SinCos_ResultId:[0-9]+]] = OpFixedSinCosINTEL %[[Ty_51]] %[[SinCos_InId]] 1 3 2 0 0
+; CHECK-NEXT: OpStore %[[#]] %[[SinCos_ResultId]]
+
+; CHECK: %[[ResId:[0-9]+]] = OpLoad %[[Ty_51]]
+; CHECK-NEXT: OpStore %[[PtrId:[0-9]+]] %[[ResId]]
+; CHECK-NEXT: %[[ExpInId2:[0-9]+]] = OpLoad %[[Ty_51]] %[[PtrId]]
+; CHECK-NEXT: %[[#]] = OpFixedExpINTEL %[[Ty_51]] %[[ExpInId2]] 0 20 20 0 0
+
+%"class._ZTSZ4mainE3$_0.anon" = type { i8 }
+
+define dso_local spir_kernel void @_ZTSZ4mainE15kernel_function() !kernel_arg_addr_space !{} !kernel_arg_access_qual !{} !kernel_arg_type !{} !kernel_arg_base_type !{} !kernel_arg_type_qual !{} {
+entry:
+ %0 = alloca %"class._ZTSZ4mainE3$_0.anon", align 1
+ %1 = addrspacecast ptr %0 to ptr addrspace(4)
+ call spir_func void @"_ZZ4mainENK3$_0clEv"(ptr addrspace(4) %1)
+ ret void
+}
+
+define internal spir_func void @"_ZZ4mainENK3$_0clEv"(ptr addrspace(4) %this) align 2 {
+entry:
+ %this.addr = alloca ptr addrspace(4), align 8
+ store ptr addrspace(4) %this, ptr %this.addr, align 8
+ call spir_func void @_Z4sqrtILi13ELi5ELb0ELi2ELi2EEvv()
+ call spir_func void @_Z5recipILi3ELi8ELb1ELi4ELi4EEvv()
+ call spir_func void @_Z5rsqrtILi11ELi10ELb0ELi8ELi6EEvv()
+ call spir_func void @_Z3sinILi17ELi11ELb1ELi7ELi5EEvv()
+ call spir_func void @_Z3cosILi35ELi28ELb0ELi9ELi3EEvv()
+ call spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv()
+ call spir_func void @_Z6sin_piILi60ELi5ELb0ELi2ELi2EEvv()
+ call spir_func void @_Z6cos_piILi28ELi16ELb0ELi8ELi5EEvv()
+ call spir_func void @_Z10sin_cos_piILi13ELi5ELb0ELi2ELi2EEvv()
+ call spir_func void @_Z3logILi64ELi44ELb1ELi24ELi22EEvv()
+ call spir_func void @_Z3expILi44ELi34ELb0ELi20ELi20EEvv()
+ call spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv_()
+ call spir_func void @_Z3expILi51ELi51ELb0ELi20ELi20EEvv()
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z4sqrtILi13ELi5ELb0ELi2ELi2EEvv() {
+entry:
+ %in_ptr = alloca i13, align 2
+ %out_ptr = alloca i5, align 1
+ %in_val = load i13, ptr %in_ptr, align 2
+ %res = call spir_func signext i5 @_Z22__spirv_FixedSqrtINTELILi13ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i13 signext %in_val, i1 zeroext false, i32 2, i32 2, i32 0, i32 0)
+ store i5 %res, ptr %out_ptr, align 1
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z5recipILi3ELi8ELb1ELi4ELi4EEvv() {
+entry:
+ %in_ptr = alloca i3, align 1
+ %out_ptr = alloca i8, align 1
+ %in_val = load i3, ptr %in_ptr, align 1
+ %res = call spir_func signext i8 @_Z23__spirv_FixedRecipINTELILi3ELi8EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i3 signext %in_val, i1 zeroext true, i32 4, i32 4, i32 0, i32 0)
+ store i8 %res, ptr %out_ptr, align 1
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z5rsqrtILi11ELi10ELb0ELi8ELi6EEvv() {
+entry:
+ %in_ptr = alloca i11, align 2
+ %out_ptr = alloca i10, align 2
+ %in_val = load i11, ptr %in_ptr, align 2
+ %res = call spir_func signext i10 @_Z23__spirv_FixedRsqrtINTELILi11ELi10EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i11 signext %in_val, i1 zeroext false, i32 8, i32 6, i32 0, i32 0)
+ store i10 %res, ptr %out_ptr, align 2
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z3sinILi17ELi11ELb1ELi7ELi5EEvv() {
+entry:
+ %in_ptr = alloca i17, align 4
+ %out_ptr = alloca i11, align 2
+ %in_val = load i17, ptr %in_ptr, align 4
+ %res = call spir_func signext i11 @_Z21__spirv_FixedSinINTELILi17ELi11EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i17 signext %in_val, i1 zeroext true, i32 7, i32 5, i32 0, i32 0)
+ store i11 %res, ptr %out_ptr, align 2
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z3cosILi35ELi28ELb0ELi9ELi3EEvv() {
+entry:
+ %in_ptr = alloca i35, align 8
+ %out_ptr = alloca i28, align 4
+ %in_val = load i35, ptr %in_ptr, align 8
+ %res = call spir_func signext i28 @_Z21__spirv_FixedCosINTELILi35ELi28EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i35 signext %in_val, i1 zeroext false, i32 9, i32 3, i32 0, i32 0)
+ store i28 %res, ptr %out_ptr, align 4
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv() {
+entry:
+ %in_ptr = alloca i31, align 4
+ %out_ptr = alloca i40, align 8
+ %in_val = load i31, ptr %in_ptr, align 4
+ %res = call spir_func i40 @_Z24__spirv_FixedSinCosINTELILi31ELi20EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i31 signext %in_val, i1 zeroext true, i32 10, i32 12, i32 0, i32 0)
+ store i40 %res, ptr %out_ptr, align 8
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z6sin_piILi60ELi5ELb0ELi2ELi2EEvv() {
+entry:
+ %in_ptr = alloca i60, align 8
+ %out_ptr = alloca i5, align 1
+ %in_val = load i60, ptr %in_ptr, align 8
+ %res = call spir_func signext i5 @_Z23__spirv_FixedSinPiINTELILi60ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i60 signext %in_val, i1 zeroext false, i32 2, i32 2, i32 0, i32 0)
+ store i5 %res, ptr %out_ptr, align 1
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z6cos_piILi28ELi16ELb0ELi8ELi5EEvv() {
+entry:
+ %in_ptr = alloca i28, align 4
+ %out_ptr = alloca i16, align 2
+ %in_val = load i28, ptr %in_ptr, align 4
+ %res = call spir_func signext i16 @_Z23__spirv_FixedCosPiINTELILi28ELi16EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i28 signext %in_val, i1 zeroext false, i32 8, i32 5, i32 0, i32 0)
+ store i16 %res, ptr %out_ptr, align 2
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z10sin_cos_piILi13ELi5ELb0ELi2ELi2EEvv() {
+entry:
+ %in_ptr = alloca i13, align 2
+ %out_ptr = alloca i10, align 2
+ %in_val = load i13, ptr %in_ptr, align 2
+ %res = call spir_func signext i10 @_Z26__spirv_FixedSinCosPiINTELILi13ELi5EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i13 signext %in_val, i1 zeroext false, i32 2, i32 2, i32 0, i32 0)
+ store i10 %res, ptr %out_ptr, align 2
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z3logILi64ELi44ELb1ELi24ELi22EEvv() {
+entry:
+ %in_ptr = alloca i64, align 8
+ %out_ptr = alloca i44, align 8
+ %in_val = load i64, ptr %in_ptr, align 8
+ %res = call spir_func i44 @_Z21__spirv_FixedLogINTELILi64ELi44EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i64 %in_val, i1 zeroext true, i32 24, i32 22, i32 0, i32 0)
+ store i44 %res, ptr %out_ptr, align 8
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z3expILi44ELi34ELb0ELi20ELi20EEvv() {
+entry:
+ %in_ptr = alloca i44, align 8
+ %out_ptr = alloca i34, align 8
+ %in_val = load i44, ptr %in_ptr, align 8
+ %res = call spir_func i34 @_Z21__spirv_FixedExpINTELILi44ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i44 %in_val, i1 zeroext false, i32 20, i32 20, i32 0, i32 0)
+ store i34 %res, ptr %out_ptr, align 8
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv_() {
+entry:
+ %tmp = alloca i34, align 8
+ %out_ptr = alloca i51, align 8
+ %in_ptr = addrspacecast ptr %tmp to ptr addrspace(4)
+ %out_s = addrspacecast ptr %out_ptr to ptr addrspace(4)
+ %in_val = load i34, ptr addrspace(4) %in_ptr, align 8
+ call spir_func void @_Z24__spirv_FixedSinCosINTELILi34ELi51EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(ptr addrspace(4) sret(i51) align 8 %out_s, i34 %in_val, i1 zeroext true, i32 3, i32 2, i32 0, i32 0)
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z3expILi51ELi51ELb0ELi20ELi20EEvv() {
+entry:
+ %a = alloca i51, align 8
+ %a.ascast = addrspacecast ptr %a to ptr addrspace(4)
+ %ap_fixed_Exp = alloca i51, align 8
+ %ap_fixed_Exp.ascast = addrspacecast ptr %ap_fixed_Exp to ptr addrspace(4)
+ %tmp = alloca i51, align 8
+ %tmp.ascast = addrspacecast ptr %tmp to ptr addrspace(4)
+ %indirect-arg-temp = alloca i51, align 8
+ %0 = load i51, ptr addrspace(4) %a.ascast, align 8
+ store i51 %0, ptr %indirect-arg-temp, align 8
+ call spir_func void @_Z21__spirv_FixedExpINTELILi51ELi51EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(
+ ptr addrspace(4) sret(i51) align 8 %tmp.ascast,
+ ptr byval(i64) align 8 %indirect-arg-temp,
+ i1 zeroext false, i32 20, i32 20, i32 0, i32 0)
+ %1 = load i51, ptr addrspace(4) %tmp.ascast, align 8
+ store i51 %1, ptr addrspace(4) %ap_fixed_Exp.ascast, align 8
+ ret void
+}
+
+declare dso_local spir_func signext i5 @_Z22__spirv_FixedSqrtINTELILi13ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i13 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i13 @_Z22__spirv_FixedSqrtINTELILi5ELi13EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i5 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i8 @_Z23__spirv_FixedRecipINTELILi3ELi8EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i3 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i10 @_Z23__spirv_FixedRsqrtINTELILi11ELi10EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i11 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i11 @_Z21__spirv_FixedSinINTELILi17ELi11EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i17 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i28 @_Z21__spirv_FixedCosINTELILi35ELi28EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i35, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func i40 @_Z24__spirv_FixedSinCosINTELILi31ELi20EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i31 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i5 @_Z23__spirv_FixedSinPiINTELILi60ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i60, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i16 @_Z23__spirv_FixedCosPiINTELILi28ELi16EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i28 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i10 @_Z26__spirv_FixedSinCosPiINTELILi13ELi5EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i13 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func i44 @_Z21__spirv_FixedLogINTELILi64ELi44EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i64, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func i34 @_Z21__spirv_FixedExpINTELILi44ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i44, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func void @_Z24__spirv_FixedSinCosINTELILi34ELi51EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(ptr addrspace(4) sret(i51) align 8, i34, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func void @_Z21__spirv_FixedExpINTELILi51ELi51EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(ptr addrspace(4) sret(i51) align 8, ptr byval(i51) align 8, i1 zeroext, i32, i32, i32, i32)
>From 2e9ea59597e584b9a5d3369b4426924a3392c83b Mon Sep 17 00:00:00 2001
From: Aadesh PremKumar <aadesh.premkumar at multicorewareinc.com>
Date: Fri, 30 May 2025 10:29:06 +0530
Subject: [PATCH 2/6] --Updated files after the conflict resolution
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 86a41ff83e3b9..6af9fcade2252 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -3122,8 +3122,6 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
return generateExtendedBitOpsInst(Call.get(), MIRBuilder, GR);
case SPIRV::BindlessINTEL:
return generateBindlessImageINTELInst(Call.get(), MIRBuilder, GR);
- case SPIRV::ArbitraryPrecisionFixedPoint:
- return generateAPFixedPointInst(Call.get(), MIRBuilder, GR);
case SPIRV::TernaryBitwiseINTEL:
return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
case SPIRV::Block2DLoadStore:
@@ -3134,6 +3132,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
return generatePredicatedLoadStoreInst(Call.get(), MIRBuilder, GR);
case SPIRV::BlockingPipes:
return generateBlockingPipesInst(Call.get(), MIRBuilder, GR);
+ case SPIRV::ArbitraryPrecisionFixedPoint:
+ return generateAPFixedPointInst(Call.get(), MIRBuilder, GR);
}
return false;
}
>From 31db545b296354d1fa9f9929e04e4e978fc60fe0 Mon Sep 17 00:00:00 2001
From: Aadesh PremKumar <aadesh.premkumar at multicorewareinc.com>
Date: Fri, 30 May 2025 10:31:19 +0530
Subject: [PATCH 3/6] --Updated SPIRVInstrInfo.td file
---
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 9a5181964c68c..6dd648db903a4 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -1017,4 +1017,3 @@ def OpFixedLogINTEL: Op<5932, (outs ID:$res), (ins TYPE:$result_type, ID:$input,
"$res = OpFixedLogINTEL $result_type $input $sign $l $rl $q $o">;
def OpFixedExpINTEL: Op<5933, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
"$res = OpFixedExpINTEL $result_type $input $sign $l $rl $q $o">;
-
\ No newline at end of file
>From 82787169e890b5af70dd3d4408b2096179db2990 Mon Sep 17 00:00:00 2001
From: Aadesh PremKumar <aadesh.premkumar at multicorewareinc.com>
Date: Mon, 22 Sep 2025 10:44:16 +0530
Subject: [PATCH 4/6] --Rebased the PR to solve merge conflicts.
---
llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index fe2fe05d3374d..d4140136beb25 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -609,7 +609,6 @@ defm PredicatedIOINTEL : CapabilityOperand<6257, 0, 0, [SPV_INTEL_predicated_io]
defm Int4TypeINTEL : CapabilityOperand<5112, 0, 0, [SPV_INTEL_int4], []>;
defm Int4CooperativeMatrixINTEL : CapabilityOperand<5114, 0, 0, [SPV_INTEL_int4], [Int4TypeINTEL, CooperativeMatrixKHR]>;
defm TensorFloat32RoundingINTEL : CapabilityOperand<6425, 0, 0, [SPV_INTEL_tensor_float32_conversion], []>;
-<<<<<<< HEAD
defm BFloat16TypeKHR : CapabilityOperand<5116, 0, 0, [SPV_KHR_bfloat16], []>;
defm BFloat16DotProductKHR : CapabilityOperand<5117, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR]>;
defm BFloat16CooperativeMatrixKHR : CapabilityOperand<5118, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR, CooperativeMatrixKHR]>;
>From d7f52dcaccac08763d7648ff293b396ab8181864 Mon Sep 17 00:00:00 2001
From: Aadesh PremKumar <aadesh.premkumar at multicorewareinc.com>
Date: Thu, 6 Nov 2025 10:13:46 +0530
Subject: [PATCH 5/6] --Changes in Name of extensions from INTEL to ALTERA.
---
llvm/docs/SPIRVUsage.rst | 14 ++---
llvm/lib/Target/SPIRV/SPIRVBuiltins.td | 24 ++++-----
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 4 +-
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 8 +--
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 52 +++++++++++--------
llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp | 2 +-
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 30 +++++------
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 2 +-
.../lib/Target/SPIRV/SPIRVSymbolicOperands.td | 8 +--
...arbitrary-precision-fixed-point-numbers.ll | 39 +++++++-------
.../SPV_INTEL_arbitrary_precision_integers.ll | 6 +--
.../extensions/SPV_INTEL_int4/negative.ll | 6 +--
...both-allowed-disallowed-extension-error.ll | 6 +--
.../enable-all-extensions-but-one.ll | 4 +-
.../SPIRV/extensions/enable-all-extensions.ll | 2 +-
...-SPV_INTEL_arbitrary_precision_integers.ll | 6 +--
.../llvm-intrinsics/bitreverse_small_type.ll | 8 +--
.../CodeGen/SPIRV/trunc-nonstd-bitwidth.ll | 4 +-
.../mlir/Dialect/SPIRV/IR/SPIRVBase.td | 2 +-
19 files changed, 116 insertions(+), 111 deletions(-)
rename llvm/test/CodeGen/SPIRV/extensions/{SPV_INTEL_arbitrary_precision_fixed_point => SPV_ALTERA_arbitrary_precision_fixed_point}/capability-arbitrary-precision-fixed-point-numbers.ll (88%)
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index 4221b512cbcee..3c1f76a8c0d26 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -30,8 +30,8 @@ Static Compiler Commands
Description: This command compiles an LLVM IL file (`input.ll`) to a SPIR-V binary (`output.spvt`) for a 32-bit architecture.
2. **Compilation with Extensions and Optimization**
- Command: `llc -O1 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_integers input.ll -o output.spvt`
- Description: Compiles an LLVM IL file to SPIR-V with (`-O1`) optimizations, targeting a 64-bit architecture. It enables the SPV_INTEL_arbitrary_precision_integers extension.
+ Command: `llc -O1 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_ALTERA_arbitrary_precision_integers input.ll -o output.spvt`
+ Description: Compiles an LLVM IL file to SPIR-V with (`-O1`) optimizations, targeting a 64-bit architecture. It enables the SPV_ALTERA_arbitrary_precision_integers extension.
3. **Compilation with experimental NonSemantic.Shader.DebugInfo.100 support**
Command: `llc --spv-emit-nonsemantic-debug-info --spirv-ext=+SPV_KHR_non_semantic_info input.ll -o output.spvt`
@@ -136,7 +136,7 @@ extensions to enable or disable, each prefixed with ``+`` or ``-``, respectively
To enable multiple extensions, list them separated by comma. For example, to enable support for atomic operations on floating-point numbers and arbitrary precision integers, use:
-``-spirv-ext=+SPV_EXT_shader_atomic_float_add,+SPV_INTEL_arbitrary_precision_integers``
+``-spirv-ext=+SPV_EXT_shader_atomic_float_add,+SPV_ALTERA_arbitrary_precision_integers``
To enable all extensions, use the following option:
``-spirv-ext=all``
@@ -145,7 +145,7 @@ To enable all KHR extensions, use the following option:
``-spirv-ext=khr``
To enable all extensions except specified, specify ``all`` followed by a list of disallowed extensions. For example:
-``-spirv-ext=all,-SPV_INTEL_arbitrary_precision_integers``
+``-spirv-ext=all,-SPV_ALTERA_arbitrary_precision_integers``
Below is a list of supported SPIR-V extensions, sorted alphabetically by their extension names:
@@ -169,7 +169,7 @@ Below is a list of supported SPIR-V extensions, sorted alphabetically by their e
- Adds atomic min and max instruction on floating-point numbers.
* - ``SPV_INTEL_2d_block_io``
- Adds additional subgroup block prefetch, load, load transposed, load transformed and store instructions to read two-dimensional blocks of data from a two-dimensional region of memory, or to write two-dimensional blocks of data to a two dimensional region of memory.
- * - ``SPV_INTEL_arbitrary_precision_integers``
+ * - ``SPV_ALTERA_arbitrary_precision_integers``
- Allows generating arbitrary width integer types.
* - ``SPV_INTEL_bindless_images``
- Adds instructions to convert convert unsigned integer handles to images, samplers and sampled images.
@@ -243,8 +243,8 @@ Below is a list of supported SPIR-V extensions, sorted alphabetically by their e
- Adds execution mode and capability to enable maximal reconvergence.
* - ``SPV_ALTERA_blocking_pipes``
- Adds new pipe read and write functions that have blocking semantics instead of the non-blocking semantics of the existing pipe read/write functions.
- * - ``SPV_INTEL_arbitrary_precision_fixed_point``
- - Add instructions for fixed point arithmetic. The extension works without SPV_INTEL_arbitrary_precision_integers, but together they allow greater flexibility in representing arbitrary precision data types.
+ * - ``SPV_ALTERA_arbitrary_precision_fixed_point``
+ - Add instructions for fixed point arithmetic. The extension works without SPV_ALTERA_arbitrary_precision_integers, but together they allow greater flexibility in representing arbitrary precision data types.
SPIR-V representation in LLVM IR
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
index bf657503a386a..98440856387c9 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
@@ -1182,18 +1182,18 @@ defm : DemangledNativeBuiltin<"__spirv_WritePipeBlockingINTEL", OpenCL_std, Bloc
defm : DemangledNativeBuiltin<"__spirv_ReadPipeBlockingINTEL", OpenCL_std, BlockingPipes, 0, 0, OpReadPipeBlockingALTERA>;
defm : DemangledNativeBuiltin<"__spirv_ReadClockKHR", OpenCL_std, KernelClock, 1, 1, OpReadClockKHR>;
-//SPV_INTEL_arbitrary_precision_fixed_point
-defm : DemangledNativeBuiltin<"__spirv_FixedSqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSqrtINTEL>;
-defm : DemangledNativeBuiltin<"__spirv_FixedRecipINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRecipINTEL>;
-defm : DemangledNativeBuiltin<"__spirv_FixedRsqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRsqrtINTEL>;
-defm : DemangledNativeBuiltin<"__spirv_FixedSinINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinINTEL>;
-defm : DemangledNativeBuiltin<"__spirv_FixedCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosINTEL>;
-defm : DemangledNativeBuiltin<"__spirv_FixedSinCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosINTEL>;
-defm : DemangledNativeBuiltin<"__spirv_FixedSinPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinPiINTEL>;
-defm : DemangledNativeBuiltin<"__spirv_FixedCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosPiINTEL>;
-defm : DemangledNativeBuiltin<"__spirv_FixedSinCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosPiINTEL>;
-defm : DemangledNativeBuiltin<"__spirv_FixedLogINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedLogINTEL>;
-defm : DemangledNativeBuiltin<"__spirv_FixedExpINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedExpINTEL>;
+//SPV_ALTERA_arbitrary_precision_fixed_point
+defm : DemangledNativeBuiltin<"__spirv_FixedSqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSqrtALTERA>;
+defm : DemangledNativeBuiltin<"__spirv_FixedRecipINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRecipALTERA>;
+defm : DemangledNativeBuiltin<"__spirv_FixedRsqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRsqrtALTERA>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinALTERA>;
+defm : DemangledNativeBuiltin<"__spirv_FixedCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosALTERA>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosALTERA>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinPiALTERA>;
+defm : DemangledNativeBuiltin<"__spirv_FixedCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosPiALTERA>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosPiALTERA>;
+defm : DemangledNativeBuiltin<"__spirv_FixedLogINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedLogALTERA>;
+defm : DemangledNativeBuiltin<"__spirv_FixedExpINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedExpALTERA>;
//===----------------------------------------------------------------------===//
// Class defining an atomic instruction on floating-point numbers.
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 7a9f43b767966..0c19241a7f897 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -51,8 +51,8 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
SPIRV::Extension::Extension::SPV_GOOGLE_hlsl_functionality1},
{"SPV_GOOGLE_user_type",
SPIRV::Extension::Extension::SPV_GOOGLE_user_type},
- {"SPV_INTEL_arbitrary_precision_integers",
- SPIRV::Extension::Extension::SPV_INTEL_arbitrary_precision_integers},
+ {"SPV_ALTERA_arbitrary_precision_integers",
+ SPIRV::Extension::Extension::SPV_ALTERA_arbitrary_precision_integers},
{"SPV_INTEL_cache_controls",
SPIRV::Extension::Extension::SPV_INTEL_cache_controls},
{"SPV_INTEL_float_controls2",
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index 47022b3f89a8b..5d767fc114485 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -153,7 +153,7 @@ unsigned SPIRVGlobalRegistry::adjustOpTypeIntWidth(unsigned Width) const {
report_fatal_error("Unsupported integer width!");
const SPIRVSubtarget &ST = cast<SPIRVSubtarget>(CurMF->getSubtarget());
if (ST.canUseExtension(
- SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers) ||
+ SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers) ||
ST.canUseExtension(SPIRV::Extension::SPV_INTEL_int4))
return Width;
if (Width <= 8)
@@ -181,11 +181,11 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeInt(unsigned Width,
.addImm(SPIRV::Capability::Int4TypeINTEL);
} else if ((!isPowerOf2_32(Width) || Width < 8) &&
ST.canUseExtension(
- SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers)) {
+ SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers)) {
MIRBuilder.buildInstr(SPIRV::OpExtension)
- .addImm(SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers);
+ .addImm(SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers);
MIRBuilder.buildInstr(SPIRV::OpCapability)
- .addImm(SPIRV::Capability::ArbitraryPrecisionIntegersINTEL);
+ .addImm(SPIRV::Capability::ArbitraryPrecisionIntegersALTERA);
}
return MIRBuilder.buildInstr(SPIRV::OpTypeInt)
.addDef(createTypeVReg(MIRBuilder))
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 6dd648db903a4..815d2d7ed854b 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -994,26 +994,32 @@ def OpPredicatedLoadINTEL: Op<6528, (outs ID:$res), (ins TYPE:$resType, ID:$ptr,
def OpPredicatedStoreINTEL: Op<6529, (outs), (ins ID:$ptr, ID:$object, ID:$predicate, variable_ops),
"OpPredicatedStoreINTEL $ptr $object $predicate">;
-//SPV_INTEL_arbitrary_precision_fixed_point
-def OpFixedSqrtINTEL: Op<5923, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
- "$res = OpFixedSqrtINTEL $result_type $input $sign $l $rl $q $o">;
-def OpFixedRecipINTEL: Op<5924, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
- "$res = OpFixedRecipINTEL $result_type $input $sign $l $rl $q $o">;
-def OpFixedRsqrtINTEL: Op<5925, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
- "$res = OpFixedRsqrtINTEL $result_type $input $sign $l $rl $q $o">;
-def OpFixedSinINTEL: Op<5926, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
- "$res = OpFixedSinINTEL $result_type $input $sign $l $rl $q $o">;
-def OpFixedCosINTEL: Op<5927, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
- "$res = OpFixedCosINTEL $result_type $input $sign $l $rl $q $o">;
-def OpFixedSinCosINTEL: Op<5928, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
- "$res = OpFixedSinCosINTEL $result_type $input $sign $l $rl $q $o">;
-def OpFixedSinPiINTEL: Op<5929, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
- "$res = OpFixedSinPiINTEL $result_type $input $sign $l $rl $q $o">;
-def OpFixedCosPiINTEL: Op<5930, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
- "$res = OpFixedCosPiINTEL $result_type $input $sign $l $rl $q $o">;
-def OpFixedSinCosPiINTEL: Op<5931, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
- "$res = OpFixedSinCosPiINTEL $result_type $input $sign $l $rl $q $o">;
-def OpFixedLogINTEL: Op<5932, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
- "$res = OpFixedLogINTEL $result_type $input $sign $l $rl $q $o">;
-def OpFixedExpINTEL: Op<5933, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
- "$res = OpFixedExpINTEL $result_type $input $sign $l $rl $q $o">;
+//SPV_ALTERA_blocking_pipes
+def OpReadPipeBlockingALTERA :Op<5946, (outs), (ins ID:$pipe, ID:$pointer, ID:$packetSize, ID:$packetAlignment),
+ "OpReadPipeBlockingALTERA $pipe $pointer $packetSize $packetAlignment">;
+def OpWritePipeBlockingALTERA :Op<5946, (outs), (ins ID:$pipe, ID:$pointer, ID:$packetSize, ID:$packetAlignment),
+ "OpWritePipeBlockingALTERA $pipe $pointer $packetSize $packetAlignment">;
+
+//SPV_ALTERA_arbitrary_precision_fixed_point
+def OpFixedSqrtALTERA: Op<5923, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSqrtALTERA $result_type $input $sign $l $rl $q $o">;
+def OpFixedRecipALTERA: Op<5924, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedRecipALTERA $result_type $input $sign $l $rl $q $o">;
+def OpFixedRsqrtALTERA: Op<5925, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedRsqrtALTERA $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinALTERA: Op<5926, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinALTERA $result_type $input $sign $l $rl $q $o">;
+def OpFixedCosALTERA: Op<5927, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedCosALTERA $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinCosALTERA: Op<5928, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinCosALTERA $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinPiALTERA: Op<5929, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinPiALTERA $result_type $input $sign $l $rl $q $o">;
+def OpFixedCosPiALTERA: Op<5930, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedCosPiALTERA $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinCosPiALTERA: Op<5931, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinCosPiALTERA $result_type $input $sign $l $rl $q $o">;
+def OpFixedLogALTERA: Op<5932, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedLogALTERA $result_type $input $sign $l $rl $q $o">;
+def OpFixedExpALTERA: Op<5933, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedExpALTERA $result_type $input $sign $l $rl $q $o">;
diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
index 53074ea3b2597..189c03a0ca3f9 100644
--- a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
@@ -128,7 +128,7 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
bool IsExtendedInts =
ST.canUseExtension(
- SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers) ||
+ SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers) ||
ST.canUseExtension(SPIRV::Extension::SPV_KHR_bit_instructions) ||
ST.canUseExtension(SPIRV::Extension::SPV_INTEL_int4);
auto extendedScalarsAndVectors =
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index f9f62066c1628..5a74defb642a3 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1670,26 +1670,26 @@ void addInstrRequirements(const MachineInstr &MI,
Reqs.addCapability(SPIRV::Capability::GroupNonUniformRotateKHR);
Reqs.addCapability(SPIRV::Capability::GroupNonUniform);
break;
- case SPIRV::OpFixedCosINTEL:
- case SPIRV::OpFixedSinINTEL:
- case SPIRV::OpFixedCosPiINTEL:
- case SPIRV::OpFixedSinPiINTEL:
- case SPIRV::OpFixedExpINTEL:
- case SPIRV::OpFixedLogINTEL:
- case SPIRV::OpFixedRecipINTEL:
- case SPIRV::OpFixedSqrtINTEL:
- case SPIRV::OpFixedSinCosINTEL:
- case SPIRV::OpFixedSinCosPiINTEL:
- case SPIRV::OpFixedRsqrtINTEL:
+ case SPIRV::OpFixedCosALTERA:
+ case SPIRV::OpFixedSinALTERA:
+ case SPIRV::OpFixedCosPiALTERA:
+ case SPIRV::OpFixedSinPiALTERA:
+ case SPIRV::OpFixedExpALTERA:
+ case SPIRV::OpFixedLogALTERA:
+ case SPIRV::OpFixedRecipALTERA:
+ case SPIRV::OpFixedSqrtALTERA:
+ case SPIRV::OpFixedSinCosALTERA:
+ case SPIRV::OpFixedSinCosPiALTERA:
+ case SPIRV::OpFixedRsqrtALTERA:
if (!ST.canUseExtension(
- SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point))
+ SPIRV::Extension::SPV_ALTERA_arbitrary_precision_fixed_point))
report_fatal_error("This instruction requires the "
"following SPIR-V extension: "
- "SPV_INTEL_arbitrary_precision_fixed_point",
+ "SPV_ALTERA_arbitrary_precision_fixed_point",
false);
Reqs.addExtension(
- SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point);
- Reqs.addCapability(SPIRV::Capability::ArbitraryPrecisionFixedPointINTEL);
+ SPIRV::Extension::SPV_ALTERA_arbitrary_precision_fixed_point);
+ Reqs.addCapability(SPIRV::Capability::ArbitraryPrecisionFixedPointALTERA);
break;
case SPIRV::OpGroupIMulKHR:
case SPIRV::OpGroupFMulKHR:
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index d538009f0ecbe..527b3a7cb4a61 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -509,7 +509,7 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
bool IsExtendedInts =
ST->canUseExtension(
- SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers) ||
+ SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers) ||
ST->canUseExtension(SPIRV::Extension::SPV_KHR_bit_instructions) ||
ST->canUseExtension(SPIRV::Extension::SPV_INTEL_int4);
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index d4140136beb25..563f811043489 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -318,7 +318,7 @@ defm SPV_INTEL_io_pipes : ExtensionOperand<63, [EnvOpenCL]>;
defm SPV_KHR_ray_tracing : ExtensionOperand<64, [EnvVulkan]>;
defm SPV_KHR_ray_query : ExtensionOperand<65, [EnvVulkan]>;
defm SPV_INTEL_fpga_memory_accesses : ExtensionOperand<66, [EnvOpenCL]>;
-defm SPV_INTEL_arbitrary_precision_integers : ExtensionOperand<67, [EnvOpenCL]>;
+defm SPV_ALTERA_arbitrary_precision_integers : ExtensionOperand<67, [EnvOpenCL]>;
defm SPV_EXT_shader_atomic_float_add
: ExtensionOperand<68, [EnvVulkan, EnvOpenCL]>;
defm SPV_KHR_terminate_invocation : ExtensionOperand<69, [EnvVulkan]>;
@@ -389,7 +389,7 @@ defm SPV_INTEL_predicated_io : ExtensionOperand<127, [EnvOpenCL]>;
defm SPV_KHR_maximal_reconvergence : ExtensionOperand<128, [EnvVulkan]>;
defm SPV_INTEL_bfloat16_arithmetic
: ExtensionOperand<129, [EnvVulkan, EnvOpenCL]>;
-defm SPV_INTEL_arbitrary_precision_fixed_point : ExtensionOperand<130, [EnvOpenCL]>;
+defm SPV_ALTERA_arbitrary_precision_fixed_point : ExtensionOperand<130, [EnvOpenCL]>;
//===----------------------------------------------------------------------===//
// Multiclass used to define Capabilities enum values and at the same time
@@ -549,7 +549,7 @@ defm ComputeDerivativeGroupLinearNV : CapabilityOperand<5350, 0, 0, [], []>;
defm FragmentDensityEXT : CapabilityOperand<5291, 0, 0, [], [Shader]>;
defm PhysicalStorageBufferAddressesEXT : CapabilityOperand<5347, 0, 0, [], [Shader]>;
defm CooperativeMatrixNV : CapabilityOperand<5357, 0, 0, [], [Shader]>;
-defm ArbitraryPrecisionIntegersINTEL : CapabilityOperand<5844, 0, 0, [SPV_INTEL_arbitrary_precision_integers], [Int8, Int16]>;
+defm ArbitraryPrecisionIntegersALTERA : CapabilityOperand<5844, 0, 0, [SPV_ALTERA_arbitrary_precision_integers], [Int8, Int16]>;
defm OptNoneINTEL : CapabilityOperand<6094, 0, 0, [SPV_INTEL_optnone], []>;
defm OptNoneEXT : CapabilityOperand<6094, 0, 0, [SPV_EXT_optnone], []>;
defm BitInstructions : CapabilityOperand<6025, 0, 0, [SPV_KHR_bit_instructions], []>;
@@ -613,7 +613,7 @@ defm BFloat16TypeKHR : CapabilityOperand<5116, 0, 0, [SPV_KHR_bfloat16], []>;
defm BFloat16DotProductKHR : CapabilityOperand<5117, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR]>;
defm BFloat16CooperativeMatrixKHR : CapabilityOperand<5118, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR, CooperativeMatrixKHR]>;
defm BlockingPipesALTERA : CapabilityOperand<5945, 0, 0, [SPV_ALTERA_blocking_pipes], []>;
-defm ArbitraryPrecisionFixedPointINTEL : CapabilityOperand<5922, 0, 0, [SPV_INTEL_arbitrary_precision_fixed_point], []>;
+defm ArbitraryPrecisionFixedPointALTERA : CapabilityOperand<5922, 0, 0, [SPV_ALTERA_arbitrary_precision_fixed_point], []>;
//===----------------------------------------------------------------------===//
// Multiclass used to define SourceLanguage enum values and at the same time
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
similarity index 88%
rename from llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
rename to llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
index 0e003d217ace7..e8bc48ec100b1 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
@@ -1,12 +1,11 @@
-; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_fixed_point,+SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s
-; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_fixed_point,+SPV_INTEL_arbitrary_precision_integers %s -o - -filetype=obj | spirv-val %}
-
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_ALTERA_arbitrary_precision_fixed_point,+SPV_ALTERA_arbitrary_precision_integers %s -o - | FileCheck %s
+; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_ALTERA_arbitrary_precision_fixed_point,+SPV_ALTERA_arbitrary_precision_integers %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: OpCapability Kernel
-; CHECK-DAG: OpCapability ArbitraryPrecisionIntegersINTEL
-; CHECK-DAG: OpCapability ArbitraryPrecisionFixedPointINTEL
-; CHECK-DAG: OpExtension "SPV_INTEL_arbitrary_precision_fixed_point"
-; CHECK-DAG: OpExtension "SPV_INTEL_arbitrary_precision_integers"
+; CHECK-DAG: OpCapability ArbitraryPrecisionIntegersALTERA
+; CHECK-DAG: OpCapability ArbitraryPrecisionFixedPointALTERA
+; CHECK-DAG: OpExtension "SPV_ALTERA_arbitrary_precision_fixed_point"
+; CHECK-DAG: OpExtension "SPV_ALTERA_arbitrary_precision_integers"
; CHECK-DAG: %[[Ty_8:[0-9]+]] = OpTypeInt 8 0
; CHECK-DAG: %[[Ty_13:[0-9]+]] = OpTypeInt 13 0
@@ -27,46 +26,46 @@
; CHECK-DAG: %[[Ty_51:[0-9]+]] = OpTypeInt 51 0
; CHECK: %[[Sqrt_InId:[0-9]+]] = OpLoad %[[Ty_13]]
-; CHECK-NEXT: %[[#]] = OpFixedSqrtINTEL %[[Ty_5]] %[[Sqrt_InId]] 0 2 2 0 0
+; CHECK-NEXT: %[[#]] = OpFixedSqrtALTERA %[[Ty_5]] %[[Sqrt_InId]] 0 2 2 0 0
; CHECK: %[[Recip_InId:[0-9]+]] = OpLoad %[[Ty_3]]
-; CHECK-NEXT: %[[#]] = OpFixedRecipINTEL %[[Ty_8]] %[[Recip_InId]] 1 4 4 0 0
+; CHECK-NEXT: %[[#]] = OpFixedRecipALTERA %[[Ty_8]] %[[Recip_InId]] 1 4 4 0 0
; CHECK: %[[Rsqrt_InId:[0-9]+]] = OpLoad %[[Ty_11]]
-; CHECK-NEXT: %[[#]] = OpFixedRsqrtINTEL %[[Ty_10]] %[[Rsqrt_InId]] 0 8 6 0 0
+; CHECK-NEXT: %[[#]] = OpFixedRsqrtALTERA %[[Ty_10]] %[[Rsqrt_InId]] 0 8 6 0 0
; CHECK: %[[Sin_InId:[0-9]+]] = OpLoad %[[Ty_17]]
-; CHECK-NEXT: %[[#]] = OpFixedSinINTEL %[[Ty_11]] %[[Sin_InId]] 1 7 5 0 0
+; CHECK-NEXT: %[[#]] = OpFixedSinALTERA %[[Ty_11]] %[[Sin_InId]] 1 7 5 0 0
; CHECK: %[[Cos_InId:[0-9]+]] = OpLoad %[[Ty_35]]
-; CHECK-NEXT: %[[#]] = OpFixedCosINTEL %[[Ty_28]] %[[Cos_InId]] 0 9 3 0 0
+; CHECK-NEXT: %[[#]] = OpFixedCosALTERA %[[Ty_28]] %[[Cos_InId]] 0 9 3 0 0
; CHECK: %[[SinCos_InId:[0-9]+]] = OpLoad %[[Ty_31]]
-; CHECK-NEXT: %[[#]] = OpFixedSinCosINTEL %[[Ty_40]] %[[SinCos_InId]] 1 10 12 0 0
+; CHECK-NEXT: %[[#]] = OpFixedSinCosALTERA %[[Ty_40]] %[[SinCos_InId]] 1 10 12 0 0
; CHECK: %[[SinPi_InId:[0-9]+]] = OpLoad %[[Ty_60]]
-; CHECK-NEXT: %[[#]] = OpFixedSinPiINTEL %[[Ty_5]] %[[SinPi_InId]] 0 2 2 0 0
+; CHECK-NEXT: %[[#]] = OpFixedSinPiALTERA %[[Ty_5]] %[[SinPi_InId]] 0 2 2 0 0
; CHECK: %[[CosPi_InId:[0-9]+]] = OpLoad %[[Ty_28]]
-; CHECK-NEXT: %[[#]] = OpFixedCosPiINTEL %[[Ty_16]] %[[CosPi_InId]] 0 8 5 0 0
+; CHECK-NEXT: %[[#]] = OpFixedCosPiALTERA %[[Ty_16]] %[[CosPi_InId]] 0 8 5 0 0
; CHECK: %[[SinCosPi_InId:[0-9]+]] = OpLoad %[[Ty_13]]
-; CHECK-NEXT: %[[#]] = OpFixedSinCosPiINTEL %[[Ty_10]] %[[SinCosPi_InId]] 0 2 2 0 0
+; CHECK-NEXT: %[[#]] = OpFixedSinCosPiALTERA %[[Ty_10]] %[[SinCosPi_InId]] 0 2 2 0 0
; CHECK: %[[Log_InId:[0-9]+]] = OpLoad %[[Ty_64]]
-; CHECK-NEXT: %[[#]] = OpFixedLogINTEL %[[Ty_44]] %[[Log_InId]] 1 24 22 0 0
+; CHECK-NEXT: %[[#]] = OpFixedLogALTERA %[[Ty_44]] %[[Log_InId]] 1 24 22 0 0
; CHECK: %[[Exp_InId:[0-9]+]] = OpLoad %[[Ty_44]]
-; CHECK-NEXT: %[[#]] = OpFixedExpINTEL %[[Ty_34]] %[[Exp_InId]] 0 20 20 0 0
+; CHECK-NEXT: %[[#]] = OpFixedExpALTERA %[[Ty_34]] %[[Exp_InId]] 0 20 20 0 0
; CHECK: %[[SinCos_InId:[0-9]+]] = OpLoad %[[Ty_34]]
-; CHECK-NEXT: %[[SinCos_ResultId:[0-9]+]] = OpFixedSinCosINTEL %[[Ty_51]] %[[SinCos_InId]] 1 3 2 0 0
+; CHECK-NEXT: %[[SinCos_ResultId:[0-9]+]] = OpFixedSinCosALTERA %[[Ty_51]] %[[SinCos_InId]] 1 3 2 0 0
; CHECK-NEXT: OpStore %[[#]] %[[SinCos_ResultId]]
; CHECK: %[[ResId:[0-9]+]] = OpLoad %[[Ty_51]]
; CHECK-NEXT: OpStore %[[PtrId:[0-9]+]] %[[ResId]]
; CHECK-NEXT: %[[ExpInId2:[0-9]+]] = OpLoad %[[Ty_51]] %[[PtrId]]
-; CHECK-NEXT: %[[#]] = OpFixedExpINTEL %[[Ty_51]] %[[ExpInId2]] 0 20 20 0 0
+; CHECK-NEXT: %[[#]] = OpFixedExpALTERA %[[Ty_51]] %[[ExpInId2]] 0 20 20 0 0
%"class._ZTSZ4mainE3$_0.anon" = type { i8 }
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_integers.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_integers.ll
index 41d4b58ed1157..9ea8a5709154c 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_integers.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_integers.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_ALTERA_arbitrary_precision_integers %s -o - | FileCheck %s
define i6 @getConstantI6() {
ret i6 2
@@ -9,8 +9,8 @@ define i13 @getConstantI13() {
}
;; Capabilities:
-; CHECK-DAG: OpExtension "SPV_INTEL_arbitrary_precision_integers"
-; CHECK-DAG: OpCapability ArbitraryPrecisionIntegersINTEL
+; CHECK-DAG: OpExtension "SPV_ALTERA_arbitrary_precision_integers"
+; CHECK-DAG: OpCapability ArbitraryPrecisionIntegersALTERA
; CHECK-NOT: DAG-FENCE
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_int4/negative.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_int4/negative.ll
index 4d5fa52a166f2..fdb2776a7e2ec 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_int4/negative.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_int4/negative.ll
@@ -1,11 +1,11 @@
-; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-INT-4
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_ALTERA_arbitrary_precision_integers %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-INT-4
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-INT-8
; No error would be reported in comparison to Khronos llvm-spirv, because type adjustments to integer size are made
; in case no appropriate extension is enabled. Here we expect that the type is adjusted to 8 bits.
-; CHECK-SPIRV: Capability ArbitraryPrecisionIntegersINTEL
-; CHECK-SPIRV: Extension "SPV_INTEL_arbitrary_precision_integers"
+; CHECK-SPIRV: Capability ArbitraryPrecisionIntegersALTERA
+; CHECK-SPIRV: Extension "SPV_ALTERA_arbitrary_precision_integers"
; CHECK-INT-4: %[[#Int4:]] = OpTypeInt 4 0
; CHECK-INT-8: %[[#Int4:]] = OpTypeInt 8 0
; CHECK: OpTypeFunction %[[#]] %[[#Int4]]
diff --git a/llvm/test/CodeGen/SPIRV/extensions/both-allowed-disallowed-extension-error.ll b/llvm/test/CodeGen/SPIRV/extensions/both-allowed-disallowed-extension-error.ll
index fc07cca4dd240..96dca53b8ba59 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/both-allowed-disallowed-extension-error.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/both-allowed-disallowed-extension-error.ll
@@ -1,6 +1,6 @@
-; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_integers,-SPV_INTEL_arbitrary_precision_integers %s -o %t.spvt 2>&1 | FileCheck %s
-; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=-SPV_INTEL_arbitrary_precision_integers,+SPV_INTEL_arbitrary_precision_integers %s -o %t.spvt 2>&1 | FileCheck %s
-; CHECK: Extension cannot be allowed and disallowed at the same time: SPV_INTEL_arbitrary_precision_integers
+; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_ALTERA_arbitrary_precision_integers,-SPV_ALTERA_arbitrary_precision_integers %s -o %t.spvt 2>&1 | FileCheck %s
+; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=-SPV_ALTERA_arbitrary_precision_integers,+SPV_ALTERA_arbitrary_precision_integers %s -o %t.spvt 2>&1 | FileCheck %s
+; CHECK: Extension cannot be allowed and disallowed at the same time: SPV_ALTERA_arbitrary_precision_integers
define i8 @foo() {
ret i8 2
diff --git a/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll b/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll
index 4db0ba33d52c9..e9b7ffe0bde76 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=all,-SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=all,-SPV_ALTERA_arbitrary_precision_integers %s -o - | FileCheck %s
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=KHR %s -o - | FileCheck %s
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=khr %s -o - | FileCheck %s
@@ -7,5 +7,5 @@ define i6 @foo() {
ret i6 2
}
-; CHECK-NOT: OpExtension "SPV_INTEL_arbitrary_precision_integers"
+; CHECK-NOT: OpExtension "SPV_ALTERA_arbitrary_precision_integers"
; CHECK-DAG: OpExtension "SPV_KHR_bit_instructions"
diff --git a/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions.ll b/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions.ll
index 15905dd1894e2..80b094f462a70 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions.ll
@@ -5,4 +5,4 @@ define i6 @getConstantI6() {
ret i6 2
}
-; CHECK: OpExtension "SPV_INTEL_arbitrary_precision_integers"
+; CHECK: OpExtension "SPV_ALTERA_arbitrary_precision_integers"
diff --git a/llvm/test/CodeGen/SPIRV/extensions/unused-but-allowed-SPV_INTEL_arbitrary_precision_integers.ll b/llvm/test/CodeGen/SPIRV/extensions/unused-but-allowed-SPV_INTEL_arbitrary_precision_integers.ll
index 2c1257471d159..cc3f1ae29a681 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/unused-but-allowed-SPV_INTEL_arbitrary_precision_integers.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/unused-but-allowed-SPV_INTEL_arbitrary_precision_integers.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_ALTERA_arbitrary_precision_integers %s -o - | FileCheck %s
define i8 @getConstantI8() {
ret i8 2
@@ -15,5 +15,5 @@ define i64 @getConstantI64() {
}
;; Capabilities:
-; CHECK-NOT: OpExtension "SPV_INTEL_arbitrary_precision_integers"
-; CHECK-NOT: OpCapability ArbitraryPrecisionIntegersINTEL
+; CHECK-NOT: OpExtension "SPV_ALTERA_arbitrary_precision_integers"
+; CHECK-NOT: OpCapability ArbitraryPrecisionIntegersALTERA
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bitreverse_small_type.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bitreverse_small_type.ll
index 438fff6e94f89..0b311a4fbe30d 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bitreverse_small_type.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bitreverse_small_type.ll
@@ -1,11 +1,11 @@
;; Check that llvm.bitreverse.* intrinsics are lowered for
;; 2/4-bit scalar and vector types.
-; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_integers,+SPV_KHR_bit_instructions %s -o - | FileCheck %s
-; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_integers,+SPV_KHR_bit_instructions %s -o - -filetype=obj | spirv-val %}
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_ALTERA_arbitrary_precision_integers,+SPV_KHR_bit_instructions %s -o - | FileCheck %s
+; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_ALTERA_arbitrary_precision_integers,+SPV_KHR_bit_instructions %s -o - -filetype=obj | spirv-val %}
-; CHECK: OpCapability ArbitraryPrecisionIntegersINTEL
-; CHECK: OpExtension "SPV_INTEL_arbitrary_precision_integers"
+; CHECK: OpCapability ArbitraryPrecisionIntegersALTERA
+; CHECK: OpExtension "SPV_ALTERA_arbitrary_precision_integers"
; CHECK: %[[#I4:]] = OpTypeInt 4 0
; CHECK: %[[#I2:]] = OpTypeInt 2 0
diff --git a/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll b/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll
index 79c2824c3dde1..16cd00b7180a7 100644
--- a/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll
+++ b/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll
@@ -1,12 +1,12 @@
; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOEXT
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s --spirv-ext=+SPV_INTEL_arbitrary_precision_integers -o - | FileCheck %s --check-prefixes=CHECK,CHECK-EXT
+; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s --spirv-ext=+SPV_ALTERA_arbitrary_precision_integers -o - | FileCheck %s --check-prefixes=CHECK,CHECK-EXT
; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOEXT
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s --spirv-ext=+SPV_INTEL_arbitrary_precision_integers -o - | FileCheck %s --check-prefixes=CHECK,CHECK-EXT
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s --spirv-ext=+SPV_ALTERA_arbitrary_precision_integers -o - | FileCheck %s --check-prefixes=CHECK,CHECK-EXT
; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled
; XFAIL: expensive_checks
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
index b628f1a3f7b20..7ac5389c2e198 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
@@ -792,7 +792,7 @@ def SPIRV_C_FPGABufferLocationINTEL : I32EnumAttrCase<"FPGAB
Extension<[SPV_INTEL_fpga_buffer_location]>
];
}
-def SPIRV_C_ArbitraryPrecisionFixedPointINTEL : I32EnumAttrCase<"ArbitraryPrecisionFixedPointINTEL", 5922> {
+def SPIRV_C_ArbitraryPrecisionFixedPointINTEL : I32EnumAttrCase<"ArbitraryPrecisionFixedPointINTEL", 5922> {
list<Availability> availability = [
Extension<[SPV_INTEL_arbitrary_precision_fixed_point]>
];
>From 8bdc9437e8be0d70adb0975f189a23fced198881 Mon Sep 17 00:00:00 2001
From: Aadesh Premkumar <aadesh.premkumar at multicorewareinc.com>
Date: Thu, 6 Nov 2025 18:41:24 +0530
Subject: [PATCH 6/6] Update SPIRVBase.td
---
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
index 7ac5389c2e198..b628f1a3f7b20 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
@@ -792,7 +792,7 @@ def SPIRV_C_FPGABufferLocationINTEL : I32EnumAttrCase<"FPGAB
Extension<[SPV_INTEL_fpga_buffer_location]>
];
}
-def SPIRV_C_ArbitraryPrecisionFixedPointINTEL : I32EnumAttrCase<"ArbitraryPrecisionFixedPointINTEL", 5922> {
+def SPIRV_C_ArbitraryPrecisionFixedPointINTEL : I32EnumAttrCase<"ArbitraryPrecisionFixedPointINTEL", 5922> {
list<Availability> availability = [
Extension<[SPV_INTEL_arbitrary_precision_fixed_point]>
];
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