[llvm] [RISCV] For (2^N +/- 2^M) muls, prefer ADD to SUB (PR #166757)
Piotr Fusik via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 6 03:52:39 PST 2025
https://github.com/pfusik created https://github.com/llvm/llvm-project/pull/166757
ADD is more compressible.
>From 93664d2315d8783e589eae4982aca707fc3e58ff Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Thu, 6 Nov 2025 12:50:20 +0100
Subject: [PATCH] [RISCV] For (2^N +/- 2^M) muls, prefer ADD to SUB
ADD is more compressible.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 8 +-
llvm/test/CodeGen/RISCV/mul.ll | 56 +-
llvm/test/CodeGen/RISCV/pr145360.ll | 16 +-
llvm/test/CodeGen/RISCV/rv32xtheadba.ll | 16 +-
llvm/test/CodeGen/RISCV/rv32zba.ll | 20 +-
llvm/test/CodeGen/RISCV/rv64xtheadba.ll | 24 +-
llvm/test/CodeGen/RISCV/rv64zba.ll | 44 +-
.../CodeGen/RISCV/rvv/calling-conv-fastcc.ll | 23 +-
.../CodeGen/RISCV/rvv/extract-subvector.ll | 6 +-
.../CodeGen/RISCV/rvv/vector-deinterleave.ll | 75 +-
.../CodeGen/RISCV/rvv/vector-interleave.ll | 1240 ++++++++---------
.../RISCV/rvv/vreductions-fp-sdnode.ll | 12 +-
.../CodeGen/RISCV/srem-seteq-illegal-types.ll | 40 +-
llvm/test/CodeGen/RISCV/xqciac.ll | 4 +-
14 files changed, 771 insertions(+), 813 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 995ae75da1c30..411ca744b1e7e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -16477,12 +16477,12 @@ static SDValue expandMulToAddOrSubOfShl(SDNode *N, SelectionDAG &DAG,
uint64_t MulAmtLowBit = MulAmt & (-MulAmt);
ISD::NodeType Op;
uint64_t ShiftAmt1;
- if (isPowerOf2_64(MulAmt + MulAmtLowBit)) {
- Op = ISD::SUB;
- ShiftAmt1 = MulAmt + MulAmtLowBit;
- } else if (isPowerOf2_64(MulAmt - MulAmtLowBit)) {
+ if (isPowerOf2_64(MulAmt - MulAmtLowBit)) {
Op = ISD::ADD;
ShiftAmt1 = MulAmt - MulAmtLowBit;
+ } else if (isPowerOf2_64(MulAmt + MulAmtLowBit)) {
+ Op = ISD::SUB;
+ ShiftAmt1 = MulAmt + MulAmtLowBit;
} else {
return SDValue();
}
diff --git a/llvm/test/CodeGen/RISCV/mul.ll b/llvm/test/CodeGen/RISCV/mul.ll
index 4c9a98cabb15f..4533e14c672e7 100644
--- a/llvm/test/CodeGen/RISCV/mul.ll
+++ b/llvm/test/CodeGen/RISCV/mul.ll
@@ -1185,29 +1185,29 @@ define i32 @muli32_p384(i32 %a) nounwind {
; RV32I-LABEL: muli32_p384:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 7
-; RV32I-NEXT: slli a0, a0, 9
-; RV32I-NEXT: sub a0, a0, a1
+; RV32I-NEXT: slli a0, a0, 8
+; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IM-LABEL: muli32_p384:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a0, 7
-; RV32IM-NEXT: slli a0, a0, 9
-; RV32IM-NEXT: sub a0, a0, a1
+; RV32IM-NEXT: slli a0, a0, 8
+; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret
;
; RV64I-LABEL: muli32_p384:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 7
-; RV64I-NEXT: slli a0, a0, 9
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: slli a0, a0, 8
+; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_p384:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 7
-; RV64IM-NEXT: slli a0, a0, 9
-; RV64IM-NEXT: subw a0, a0, a1
+; RV64IM-NEXT: slli a0, a0, 8
+; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, 384
ret i32 %1
@@ -1217,29 +1217,29 @@ define i32 @muli32_p12288(i32 %a) nounwind {
; RV32I-LABEL: muli32_p12288:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 12
-; RV32I-NEXT: slli a0, a0, 14
-; RV32I-NEXT: sub a0, a0, a1
+; RV32I-NEXT: slli a0, a0, 13
+; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IM-LABEL: muli32_p12288:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a0, 12
-; RV32IM-NEXT: slli a0, a0, 14
-; RV32IM-NEXT: sub a0, a0, a1
+; RV32IM-NEXT: slli a0, a0, 13
+; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret
;
; RV64I-LABEL: muli32_p12288:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 12
-; RV64I-NEXT: slli a0, a0, 14
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: slli a0, a0, 13
+; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_p12288:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 12
-; RV64IM-NEXT: slli a0, a0, 14
-; RV64IM-NEXT: subw a0, a0, a1
+; RV64IM-NEXT: slli a0, a0, 13
+; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, 12288
ret i32 %1
@@ -2117,14 +2117,14 @@ define i64 @muland_demand(i64 %x) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: andi a0, a0, -8
; RV32IM-NEXT: slli a2, a1, 2
-; RV32IM-NEXT: slli a1, a1, 4
-; RV32IM-NEXT: sub a1, a1, a2
+; RV32IM-NEXT: slli a1, a1, 3
+; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: li a2, 12
; RV32IM-NEXT: mulhu a2, a0, a2
; RV32IM-NEXT: add a1, a2, a1
; RV32IM-NEXT: slli a2, a0, 2
-; RV32IM-NEXT: slli a0, a0, 4
-; RV32IM-NEXT: sub a0, a0, a2
+; RV32IM-NEXT: slli a0, a0, 3
+; RV32IM-NEXT: add a0, a0, a2
; RV32IM-NEXT: ret
;
; RV64I-LABEL: muland_demand:
@@ -2133,16 +2133,16 @@ define i64 @muland_demand(i64 %x) nounwind {
; RV64I-NEXT: srli a1, a1, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a1, a0, 2
-; RV64I-NEXT: slli a0, a0, 4
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: slli a0, a0, 3
+; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muland_demand:
; RV64IM: # %bb.0:
; RV64IM-NEXT: andi a0, a0, -8
; RV64IM-NEXT: slli a1, a0, 2
-; RV64IM-NEXT: slli a0, a0, 4
-; RV64IM-NEXT: sub a0, a0, a1
+; RV64IM-NEXT: slli a0, a0, 3
+; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
%and = and i64 %x, 4611686018427387896
%mul = mul i64 %and, 12
@@ -2171,15 +2171,15 @@ define i64 @mulzext_demand(i32 signext %x) nounwind {
; RV64I-LABEL: mulzext_demand:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 32
-; RV64I-NEXT: slli a0, a0, 34
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: slli a0, a0, 33
+; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: mulzext_demand:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 32
-; RV64IM-NEXT: slli a0, a0, 34
-; RV64IM-NEXT: sub a0, a0, a1
+; RV64IM-NEXT: slli a0, a0, 33
+; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
%ext = zext i32 %x to i64
%mul = mul i64 %ext, 12884901888
diff --git a/llvm/test/CodeGen/RISCV/pr145360.ll b/llvm/test/CodeGen/RISCV/pr145360.ll
index 1c77fadbd4b7d..013bab4ce6292 100644
--- a/llvm/test/CodeGen/RISCV/pr145360.ll
+++ b/llvm/test/CodeGen/RISCV/pr145360.ll
@@ -27,11 +27,11 @@ define i32 @unsigned(i32 %0, ptr %1) {
; CHECK-NEXT: slli a4, a3, 32
; CHECK-NEXT: mulhu a2, a2, a4
; CHECK-NEXT: srli a2, a2, 36
-; CHECK-NEXT: slli a4, a2, 5
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: sub a2, a2, a4
+; CHECK-NEXT: slli a4, a2, 3
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: srliw a4, a0, 3
-; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: sub a2, a0, a2
; CHECK-NEXT: mulw a0, a4, a3
; CHECK-NEXT: sw a2, 0(a1)
; CHECK-NEXT: ret
@@ -68,10 +68,10 @@ define i32 @unsigned_div_first(i32 %0, ptr %1) {
; CHECK-NEXT: slli a3, a3, 32
; CHECK-NEXT: mulhu a2, a2, a3
; CHECK-NEXT: srli a2, a2, 36
-; CHECK-NEXT: slli a3, a2, 5
-; CHECK-NEXT: slli a4, a2, 3
-; CHECK-NEXT: sub a4, a4, a3
-; CHECK-NEXT: add a0, a0, a4
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: slli a4, a2, 4
+; CHECK-NEXT: add a3, a4, a3
+; CHECK-NEXT: sub a0, a0, a3
; CHECK-NEXT: sw a0, 0(a1)
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rv32xtheadba.ll b/llvm/test/CodeGen/RISCV/rv32xtheadba.ll
index 0e4a5c07020ee..fd341da86599f 100644
--- a/llvm/test/CodeGen/RISCV/rv32xtheadba.ll
+++ b/llvm/test/CodeGen/RISCV/rv32xtheadba.ll
@@ -98,8 +98,8 @@ define i32 @addmul6(i32 %a, i32 %b) {
; RV32I-LABEL: addmul6:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 1
-; RV32I-NEXT: slli a0, a0, 3
-; RV32I-NEXT: sub a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 2
+; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
@@ -136,8 +136,8 @@ define i32 @addmul12(i32 %a, i32 %b) {
; RV32I-LABEL: addmul12:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 2
-; RV32I-NEXT: slli a0, a0, 4
-; RV32I-NEXT: sub a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 3
+; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
@@ -193,8 +193,8 @@ define i32 @addmul24(i32 %a, i32 %b) {
; RV32I-LABEL: addmul24:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 3
-; RV32I-NEXT: slli a0, a0, 5
-; RV32I-NEXT: sub a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 4
+; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
@@ -269,8 +269,8 @@ define i32 @mul96(i32 %a) {
; RV32I-LABEL: mul96:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 5
-; RV32I-NEXT: slli a0, a0, 7
-; RV32I-NEXT: sub a0, a0, a1
+; RV32I-NEXT: slli a0, a0, 6
+; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32XTHEADBA-LABEL: mul96:
diff --git a/llvm/test/CodeGen/RISCV/rv32zba.ll b/llvm/test/CodeGen/RISCV/rv32zba.ll
index a6dbd94caad4f..ea9d117f2e2e3 100644
--- a/llvm/test/CodeGen/RISCV/rv32zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zba.ll
@@ -85,8 +85,8 @@ define i32 @addmul6(i32 %a, i32 %b) {
; RV32I-LABEL: addmul6:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 1
-; RV32I-NEXT: slli a0, a0, 3
-; RV32I-NEXT: sub a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 2
+; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
@@ -135,8 +135,8 @@ define i32 @addmul12(i32 %a, i32 %b) {
; RV32I-LABEL: addmul12:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 2
-; RV32I-NEXT: slli a0, a0, 4
-; RV32I-NEXT: sub a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 3
+; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
@@ -210,8 +210,8 @@ define i32 @addmul24(i32 %a, i32 %b) {
; RV32I-LABEL: addmul24:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 3
-; RV32I-NEXT: slli a0, a0, 5
-; RV32I-NEXT: sub a0, a0, a2
+; RV32I-NEXT: slli a0, a0, 4
+; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
@@ -310,8 +310,8 @@ define i32 @mul96(i32 %a) {
; RV32I-LABEL: mul96:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 5
-; RV32I-NEXT: slli a0, a0, 7
-; RV32I-NEXT: sub a0, a0, a1
+; RV32I-NEXT: slli a0, a0, 6
+; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32ZBA-LABEL: mul96:
@@ -1272,8 +1272,8 @@ define ptr @shl_add_knownbits(ptr %p, i32 %i) {
; RV32I-NEXT: slli a1, a1, 18
; RV32I-NEXT: srli a1, a1, 18
; RV32I-NEXT: slli a2, a1, 1
-; RV32I-NEXT: slli a1, a1, 3
-; RV32I-NEXT: sub a1, a1, a2
+; RV32I-NEXT: slli a1, a1, 2
+; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: srli a1, a1, 3
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadba.ll b/llvm/test/CodeGen/RISCV/rv64xtheadba.ll
index f4964288e3541..c57dfca1389b6 100644
--- a/llvm/test/CodeGen/RISCV/rv64xtheadba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64xtheadba.ll
@@ -94,8 +94,8 @@ define i64 @addmul6(i64 %a, i64 %b) {
; RV64I-LABEL: addmul6:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a0, 1
-; RV64I-NEXT: slli a0, a0, 3
-; RV64I-NEXT: sub a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 2
+; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
@@ -113,8 +113,8 @@ define i64 @disjointormul6(i64 %a, i64 %b) {
; RV64I-LABEL: disjointormul6:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a0, 1
-; RV64I-NEXT: slli a0, a0, 3
-; RV64I-NEXT: sub a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 2
+; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
@@ -151,8 +151,8 @@ define i64 @addmul12(i64 %a, i64 %b) {
; RV64I-LABEL: addmul12:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a0, 2
-; RV64I-NEXT: slli a0, a0, 4
-; RV64I-NEXT: sub a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 3
+; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
@@ -227,8 +227,8 @@ define i64 @addmul24(i64 %a, i64 %b) {
; RV64I-LABEL: addmul24:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a0, 3
-; RV64I-NEXT: slli a0, a0, 5
-; RV64I-NEXT: sub a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 4
+; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
@@ -527,8 +527,8 @@ define i64 @mul96(i64 %a) {
; RV64I-LABEL: mul96:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 5
-; RV64I-NEXT: slli a0, a0, 7
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: slli a0, a0, 6
+; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64XTHEADBA-LABEL: mul96:
@@ -990,8 +990,8 @@ define signext i32 @mulw192(i32 signext %a) {
; RV64I-LABEL: mulw192:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 6
-; RV64I-NEXT: slli a0, a0, 8
-; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: slli a0, a0, 7
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64XTHEADBA-LABEL: mulw192:
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index d4b228828c04d..cc3a7a195e3b4 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -489,8 +489,8 @@ define i64 @addmul6(i64 %a, i64 %b) {
; RV64I-LABEL: addmul6:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a0, 1
-; RV64I-NEXT: slli a0, a0, 3
-; RV64I-NEXT: sub a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 2
+; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
@@ -514,8 +514,8 @@ define i64 @disjointormul6(i64 %a, i64 %b) {
; RV64I-LABEL: disjointormul6:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a0, 1
-; RV64I-NEXT: slli a0, a0, 3
-; RV64I-NEXT: sub a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 2
+; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
@@ -564,8 +564,8 @@ define i64 @addmul12(i64 %a, i64 %b) {
; RV64I-LABEL: addmul12:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a0, 2
-; RV64I-NEXT: slli a0, a0, 4
-; RV64I-NEXT: sub a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 3
+; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
@@ -692,8 +692,8 @@ define i64 @addmul24(i64 %a, i64 %b) {
; RV64I-LABEL: addmul24:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a0, 3
-; RV64I-NEXT: slli a0, a0, 5
-; RV64I-NEXT: sub a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 4
+; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
@@ -1250,8 +1250,8 @@ define i64 @mul96(i64 %a) {
; RV64I-LABEL: mul96:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 5
-; RV64I-NEXT: slli a0, a0, 7
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: slli a0, a0, 6
+; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBA-LABEL: mul96:
@@ -1490,8 +1490,8 @@ define i64 @zext_mul96(i32 signext %a) {
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a1, a0, 27
-; RV64I-NEXT: srli a0, a0, 25
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: srli a0, a0, 26
+; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBA-LABEL: zext_mul96:
@@ -1568,8 +1568,8 @@ define i64 @zext_mul12884901888(i32 signext %a) {
; RV64I-LABEL: zext_mul12884901888:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 32
-; RV64I-NEXT: slli a0, a0, 34
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: slli a0, a0, 33
+; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBA-LABEL: zext_mul12884901888:
@@ -2180,8 +2180,8 @@ define signext i32 @mulw192(i32 signext %a) {
; RV64I-LABEL: mulw192:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 6
-; RV64I-NEXT: slli a0, a0, 8
-; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: slli a0, a0, 7
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBA-LABEL: mulw192:
@@ -3899,8 +3899,8 @@ define i64 @regression(i32 signext %x, i32 signext %y) {
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a1, a0, 29
-; RV64I-NEXT: srli a0, a0, 27
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: srli a0, a0, 28
+; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBA-LABEL: regression:
@@ -4034,8 +4034,8 @@ define i64 @bext_mul12(i32 %1, i32 %2) {
; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: slli a1, a0, 2
-; RV64I-NEXT: slli a0, a0, 4
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: slli a0, a0, 3
+; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBANOZBB-LABEL: bext_mul12:
@@ -4832,8 +4832,8 @@ define ptr @shl_add_knownbits(ptr %p, i64 %i) {
; RV64I-NEXT: slli a1, a1, 50
; RV64I-NEXT: srli a1, a1, 50
; RV64I-NEXT: slli a2, a1, 1
-; RV64I-NEXT: slli a1, a1, 3
-; RV64I-NEXT: sub a1, a1, a2
+; RV64I-NEXT: slli a1, a1, 2
+; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: srli a1, a1, 3
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll b/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
index bd912193c4fed..39732602cc85e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
@@ -72,9 +72,8 @@ define fastcc <vscale x 64 x i32> @ret_split_nxv64i32(ptr %x) {
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: vl8re32.v v8, (a1)
; CHECK-NEXT: slli a3, a2, 3
-; CHECK-NEXT: slli a4, a2, 5
; CHECK-NEXT: slli a2, a2, 4
-; CHECK-NEXT: sub a4, a4, a3
+; CHECK-NEXT: add a4, a2, a3
; CHECK-NEXT: add a5, a1, a2
; CHECK-NEXT: vl8re32.v v16, (a5)
; CHECK-NEXT: add a5, a1, a3
@@ -112,16 +111,16 @@ define fastcc <vscale x 128 x i32> @ret_split_nxv128i32(ptr %x) {
; CHECK-NEXT: addi a3, a3, 16
; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: slli a3, a2, 3
-; CHECK-NEXT: slli a4, a2, 5
-; CHECK-NEXT: slli a5, a2, 4
+; CHECK-NEXT: slli a4, a2, 4
+; CHECK-NEXT: slli a5, a2, 5
; CHECK-NEXT: slli a2, a2, 6
-; CHECK-NEXT: sub a6, a4, a3
-; CHECK-NEXT: add a7, a4, a3
-; CHECK-NEXT: sub t0, a2, a5
+; CHECK-NEXT: add a6, a4, a3
+; CHECK-NEXT: add a7, a5, a3
+; CHECK-NEXT: add t0, a5, a4
; CHECK-NEXT: sub a2, a2, a3
; CHECK-NEXT: add t1, a1, a3
-; CHECK-NEXT: add t2, a1, a5
-; CHECK-NEXT: add t3, a1, a4
+; CHECK-NEXT: add t2, a1, a4
+; CHECK-NEXT: add t3, a1, a5
; CHECK-NEXT: vl8re32.v v8, (t1)
; CHECK-NEXT: csrr t1, vlenb
; CHECK-NEXT: slli t1, t1, 4
@@ -157,12 +156,12 @@ define fastcc <vscale x 128 x i32> @ret_split_nxv128i32(ptr %x) {
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vs8r.v v0, (a0)
-; CHECK-NEXT: add a4, a0, a4
-; CHECK-NEXT: vs8r.v v16, (a4)
; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: vs8r.v v16, (a5)
+; CHECK-NEXT: add a4, a0, a4
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vs8r.v v16, (a5)
+; CHECK-NEXT: vs8r.v v16, (a4)
; CHECK-NEXT: add a3, a0, a3
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
diff --git a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
index 7c9a283dd54bc..ed0eb810aa04a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
@@ -291,7 +291,8 @@ define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_6(<vscale x 32 x i8> %vec) {
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: ret
@@ -314,7 +315,8 @@ define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_22(<vscale x 32 x i8> %vec) {
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
index ac9f26314a9ab..2590d2b0b77ee 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
@@ -475,16 +475,15 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmerge.vim v22, v10, 1, v0
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a0
@@ -607,12 +606,12 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a1
-; CHECK-NEXT: srli a2, a0, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
+; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v18, v12, 1, v0
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v9, a2
-; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v9, a0
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v20, v12, 1, v0
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
@@ -833,37 +832,37 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v16, v10, 1, v0
-; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a1
-; CHECK-NEXT: srli a2, a0, 1
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vmerge.vim v24, v10, 1, v0
+; CHECK-NEXT: srli a2, a0, 2
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v18, v10, 1, v0
+; CHECK-NEXT: vmerge.vim v26, v10, 1, v0
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v9, a2
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: vslidedown.vx v0, v9, a0
+; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v20, v10, 1, v0
+; CHECK-NEXT: vmerge.vim v28, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v26, v10, 1, v0
+; CHECK-NEXT: vmerge.vim v18, v10, 1, v0
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v9, a0
-; CHECK-NEXT: vs8r.v v16, (a2)
+; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v10, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v10, 1, v0
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a1
+; CHECK-NEXT: vslidedown.vx v0, v8, a2
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v28, v10, 1, v0
-; CHECK-NEXT: vs8r.v v24, (a0)
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vlseg6e8.v v16, (a2)
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v20, v10, 1, v0
+; CHECK-NEXT: vs8r.v v16, (a0)
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vlseg6e8.v v16, (a1)
; CHECK-NEXT: vlseg6e8.v v10, (a0)
; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: vmv2r.v v22, v18
@@ -1061,16 +1060,15 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vim v22, v12, 1, v0
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v9, a0
@@ -1331,16 +1329,15 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmerge.vim v22, v10, 1, v0
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v9, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index ee38257f09cd5..0577fb1ff67bb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -3852,29 +3852,26 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; RV32-NEXT: vmv2r.v v26, v20
; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vmv2r.v v24, v16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 3
-; RV32-NEXT: sub a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
; RV32-NEXT: vmv2r.v v22, v12
-; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv2r.v v20, v8
; RV32-NEXT: vmv1r.v v1, v20
; RV32-NEXT: vmv1r.v v3, v22
; RV32-NEXT: vmv1r.v v5, v24
; RV32-NEXT: vmv1r.v v7, v26
-; RV32-NEXT: add a3, a0, a2
; RV32-NEXT: vmv1r.v v2, v10
-; RV32-NEXT: add a4, a1, a2
-; RV32-NEXT: slli a5, a2, 2
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a2, a1, 3
+; RV32-NEXT: sub a1, a2, a1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv1r.v v4, v14
-; RV32-NEXT: slli a6, a2, 4
-; RV32-NEXT: add a7, a4, a2
+; RV32-NEXT: add a3, a0, a2
+; RV32-NEXT: add a4, a1, a2
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: sub a5, a6, a5
+; RV32-NEXT: add a5, a4, a2
; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: add a6, a7, a2
+; RV32-NEXT: add a6, a5, a2
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vsseg7e8.v v1, (a0)
; RV32-NEXT: vmv1r.v v26, v19
@@ -3893,23 +3890,25 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; RV32-NEXT: vl1r.v v8, (a0)
; RV32-NEXT: vl1r.v v16, (a4)
; RV32-NEXT: vl1r.v v9, (a3)
-; RV32-NEXT: vl1r.v v17, (a7)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a3, 14
; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: vl1r.v v17, (a5)
+; RV32-NEXT: slli a3, a2, 2
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1r.v v12, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1r.v v13, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a3, a2, a3
; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: vl1r.v v14, (a6)
; RV32-NEXT: vl1r.v v15, (a1)
-; RV32-NEXT: add a5, a0, a5
-; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a3, a0, a3
+; RV32-NEXT: vs2r.v v20, (a3)
; RV32-NEXT: vs4r.v v16, (a2)
; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: vl8r.v v16, (a2)
@@ -3934,29 +3933,26 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; RV64-NEXT: vmv2r.v v26, v20
; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vmv2r.v v24, v16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 3
-; RV64-NEXT: sub a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
; RV64-NEXT: vmv2r.v v22, v12
-; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv2r.v v20, v8
; RV64-NEXT: vmv1r.v v1, v20
; RV64-NEXT: vmv1r.v v3, v22
; RV64-NEXT: vmv1r.v v5, v24
; RV64-NEXT: vmv1r.v v7, v26
-; RV64-NEXT: add a3, a0, a2
; RV64-NEXT: vmv1r.v v2, v10
-; RV64-NEXT: add a4, a1, a2
-; RV64-NEXT: slli a5, a2, 2
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a2, a1, 3
+; RV64-NEXT: sub a1, a2, a1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv1r.v v4, v14
-; RV64-NEXT: slli a6, a2, 4
-; RV64-NEXT: add a7, a4, a2
+; RV64-NEXT: add a3, a0, a2
+; RV64-NEXT: add a4, a1, a2
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: sub a5, a6, a5
+; RV64-NEXT: add a5, a4, a2
; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: add a6, a7, a2
+; RV64-NEXT: add a6, a5, a2
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vsseg7e8.v v1, (a0)
; RV64-NEXT: vmv1r.v v26, v19
@@ -3975,23 +3971,25 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; RV64-NEXT: vl1r.v v8, (a0)
; RV64-NEXT: vl1r.v v16, (a4)
; RV64-NEXT: vl1r.v v9, (a3)
-; RV64-NEXT: vl1r.v v17, (a7)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a3, 14
; RV64-NEXT: mul a0, a0, a3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: vl1r.v v17, (a5)
+; RV64-NEXT: slli a3, a2, 2
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1r.v v12, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1r.v v13, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a3, a2, a3
; RV64-NEXT: add a2, a0, a2
; RV64-NEXT: vl1r.v v14, (a6)
; RV64-NEXT: vl1r.v v15, (a1)
-; RV64-NEXT: add a5, a0, a5
-; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a3, a0, a3
+; RV64-NEXT: vs2r.v v20, (a3)
; RV64-NEXT: vs4r.v v16, (a2)
; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: vl8r.v v16, (a2)
@@ -4016,29 +4014,26 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZVBB-RV32-NEXT: vmv2r.v v26, v20
; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vmv2r.v v24, v16
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 3
-; ZVBB-RV32-NEXT: sub a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
; ZVBB-RV32-NEXT: vmv2r.v v22, v12
-; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv2r.v v20, v8
; ZVBB-RV32-NEXT: vmv1r.v v1, v20
; ZVBB-RV32-NEXT: vmv1r.v v3, v22
; ZVBB-RV32-NEXT: vmv1r.v v5, v24
; ZVBB-RV32-NEXT: vmv1r.v v7, v26
-; ZVBB-RV32-NEXT: add a3, a0, a2
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
-; ZVBB-RV32-NEXT: add a4, a1, a2
-; ZVBB-RV32-NEXT: slli a5, a2, 2
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: slli a2, a1, 3
+; ZVBB-RV32-NEXT: sub a1, a2, a1
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
-; ZVBB-RV32-NEXT: slli a6, a2, 4
-; ZVBB-RV32-NEXT: add a7, a4, a2
+; ZVBB-RV32-NEXT: add a3, a0, a2
+; ZVBB-RV32-NEXT: add a4, a1, a2
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: sub a5, a6, a5
+; ZVBB-RV32-NEXT: add a5, a4, a2
; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: add a6, a7, a2
+; ZVBB-RV32-NEXT: add a6, a5, a2
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vsseg7e8.v v1, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
@@ -4057,23 +4052,25 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZVBB-RV32-NEXT: vl1r.v v8, (a0)
; ZVBB-RV32-NEXT: vl1r.v v16, (a4)
; ZVBB-RV32-NEXT: vl1r.v v9, (a3)
-; ZVBB-RV32-NEXT: vl1r.v v17, (a7)
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a3, 14
; ZVBB-RV32-NEXT: mul a0, a0, a3
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: vl1r.v v17, (a5)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1r.v v12, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1r.v v13, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a3, a2, a3
; ZVBB-RV32-NEXT: add a2, a0, a2
; ZVBB-RV32-NEXT: vl1r.v v14, (a6)
; ZVBB-RV32-NEXT: vl1r.v v15, (a1)
-; ZVBB-RV32-NEXT: add a5, a0, a5
-; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a3, a0, a3
+; ZVBB-RV32-NEXT: vs2r.v v20, (a3)
; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
; ZVBB-RV32-NEXT: vl8r.v v16, (a2)
@@ -4098,29 +4095,26 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZVBB-RV64-NEXT: vmv2r.v v26, v20
; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vmv2r.v v24, v16
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 3
-; ZVBB-RV64-NEXT: sub a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
; ZVBB-RV64-NEXT: vmv2r.v v22, v12
-; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv2r.v v20, v8
; ZVBB-RV64-NEXT: vmv1r.v v1, v20
; ZVBB-RV64-NEXT: vmv1r.v v3, v22
; ZVBB-RV64-NEXT: vmv1r.v v5, v24
; ZVBB-RV64-NEXT: vmv1r.v v7, v26
-; ZVBB-RV64-NEXT: add a3, a0, a2
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
-; ZVBB-RV64-NEXT: add a4, a1, a2
-; ZVBB-RV64-NEXT: slli a5, a2, 2
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: slli a2, a1, 3
+; ZVBB-RV64-NEXT: sub a1, a2, a1
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
-; ZVBB-RV64-NEXT: slli a6, a2, 4
-; ZVBB-RV64-NEXT: add a7, a4, a2
+; ZVBB-RV64-NEXT: add a3, a0, a2
+; ZVBB-RV64-NEXT: add a4, a1, a2
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: sub a5, a6, a5
+; ZVBB-RV64-NEXT: add a5, a4, a2
; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: add a6, a7, a2
+; ZVBB-RV64-NEXT: add a6, a5, a2
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vsseg7e8.v v1, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
@@ -4139,23 +4133,25 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZVBB-RV64-NEXT: vl1r.v v8, (a0)
; ZVBB-RV64-NEXT: vl1r.v v16, (a4)
; ZVBB-RV64-NEXT: vl1r.v v9, (a3)
-; ZVBB-RV64-NEXT: vl1r.v v17, (a7)
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a3, 14
; ZVBB-RV64-NEXT: mul a0, a0, a3
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: vl1r.v v17, (a5)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1r.v v12, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1r.v v13, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a3, a2, a3
; ZVBB-RV64-NEXT: add a2, a0, a2
; ZVBB-RV64-NEXT: vl1r.v v14, (a6)
; ZVBB-RV64-NEXT: vl1r.v v15, (a1)
-; ZVBB-RV64-NEXT: add a5, a0, a5
-; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a3, a0, a3
+; ZVBB-RV64-NEXT: vs2r.v v20, (a3)
; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
; ZVBB-RV64-NEXT: vl8r.v v16, (a2)
@@ -4180,29 +4176,26 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZIP-NEXT: vmv2r.v v26, v20
; ZIP-NEXT: addi a0, sp, 64
; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv2r.v v20, v8
; ZIP-NEXT: vmv1r.v v1, v20
; ZIP-NEXT: vmv1r.v v3, v22
; ZIP-NEXT: vmv1r.v v5, v24
; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: add a3, a0, a2
; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: slli a5, a2, 2
+; ZIP-NEXT: csrr a1, vlenb
+; ZIP-NEXT: slli a2, a1, 3
+; ZIP-NEXT: sub a1, a2, a1
+; ZIP-NEXT: add a1, sp, a1
+; ZIP-NEXT: addi a1, a1, 64
+; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: slli a6, a2, 4
-; ZIP-NEXT: add a7, a4, a2
+; ZIP-NEXT: add a3, a0, a2
+; ZIP-NEXT: add a4, a1, a2
; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: sub a5, a6, a5
+; ZIP-NEXT: add a5, a4, a2
; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a7, a2
+; ZIP-NEXT: add a6, a5, a2
; ZIP-NEXT: vmv1r.v v24, v15
; ZIP-NEXT: vsseg7e8.v v1, (a0)
; ZIP-NEXT: vmv1r.v v26, v19
@@ -4221,23 +4214,25 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZIP-NEXT: vl1r.v v8, (a0)
; ZIP-NEXT: vl1r.v v16, (a4)
; ZIP-NEXT: vl1r.v v9, (a3)
-; ZIP-NEXT: vl1r.v v17, (a7)
; ZIP-NEXT: csrr a0, vlenb
; ZIP-NEXT: li a3, 14
; ZIP-NEXT: mul a0, a0, a3
; ZIP-NEXT: add a0, sp, a0
; ZIP-NEXT: addi a0, a0, 64
+; ZIP-NEXT: vl1r.v v17, (a5)
+; ZIP-NEXT: slli a3, a2, 2
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1r.v v12, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1r.v v13, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: slli a2, a2, 3
+; ZIP-NEXT: add a3, a2, a3
; ZIP-NEXT: add a2, a0, a2
; ZIP-NEXT: vl1r.v v14, (a6)
; ZIP-NEXT: vl1r.v v15, (a1)
-; ZIP-NEXT: add a5, a0, a5
-; ZIP-NEXT: vs2r.v v20, (a5)
+; ZIP-NEXT: add a3, a0, a3
+; ZIP-NEXT: vs2r.v v20, (a3)
; ZIP-NEXT: vs4r.v v16, (a2)
; ZIP-NEXT: vs8r.v v8, (a0)
; ZIP-NEXT: vl8r.v v16, (a2)
@@ -4268,29 +4263,26 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; RV32-NEXT: vmv2r.v v26, v20
; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vmv2r.v v24, v16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 3
-; RV32-NEXT: sub a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
; RV32-NEXT: vmv2r.v v22, v12
-; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv2r.v v20, v8
; RV32-NEXT: vmv1r.v v1, v20
; RV32-NEXT: vmv1r.v v3, v22
; RV32-NEXT: vmv1r.v v5, v24
; RV32-NEXT: vmv1r.v v7, v26
-; RV32-NEXT: add a3, a0, a2
; RV32-NEXT: vmv1r.v v2, v10
-; RV32-NEXT: add a4, a1, a2
-; RV32-NEXT: slli a5, a2, 2
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a2, a1, 3
+; RV32-NEXT: sub a1, a2, a1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv1r.v v4, v14
-; RV32-NEXT: slli a6, a2, 4
-; RV32-NEXT: add a7, a4, a2
+; RV32-NEXT: add a3, a0, a2
+; RV32-NEXT: add a4, a1, a2
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: sub a5, a6, a5
+; RV32-NEXT: add a5, a4, a2
; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: add a6, a7, a2
+; RV32-NEXT: add a6, a5, a2
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vsseg7e16.v v1, (a0)
; RV32-NEXT: vmv1r.v v26, v19
@@ -4309,23 +4301,25 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; RV32-NEXT: vl1re16.v v8, (a0)
; RV32-NEXT: vl1re16.v v16, (a4)
; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: vl1re16.v v17, (a7)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a3, 14
; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: vl1re16.v v17, (a5)
+; RV32-NEXT: slli a3, a2, 2
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1re16.v v12, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1re16.v v13, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a3, a2, a3
; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: vl1re16.v v14, (a6)
; RV32-NEXT: vl1re16.v v15, (a1)
-; RV32-NEXT: add a5, a0, a5
-; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a3, a0, a3
+; RV32-NEXT: vs2r.v v20, (a3)
; RV32-NEXT: vs4r.v v16, (a2)
; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: vl8re16.v v16, (a2)
@@ -4350,29 +4344,26 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; RV64-NEXT: vmv2r.v v26, v20
; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vmv2r.v v24, v16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 3
-; RV64-NEXT: sub a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
; RV64-NEXT: vmv2r.v v22, v12
-; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv2r.v v20, v8
; RV64-NEXT: vmv1r.v v1, v20
; RV64-NEXT: vmv1r.v v3, v22
; RV64-NEXT: vmv1r.v v5, v24
; RV64-NEXT: vmv1r.v v7, v26
-; RV64-NEXT: add a3, a0, a2
; RV64-NEXT: vmv1r.v v2, v10
-; RV64-NEXT: add a4, a1, a2
-; RV64-NEXT: slli a5, a2, 2
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a2, a1, 3
+; RV64-NEXT: sub a1, a2, a1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv1r.v v4, v14
-; RV64-NEXT: slli a6, a2, 4
-; RV64-NEXT: add a7, a4, a2
+; RV64-NEXT: add a3, a0, a2
+; RV64-NEXT: add a4, a1, a2
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: sub a5, a6, a5
+; RV64-NEXT: add a5, a4, a2
; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: add a6, a7, a2
+; RV64-NEXT: add a6, a5, a2
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vsseg7e16.v v1, (a0)
; RV64-NEXT: vmv1r.v v26, v19
@@ -4391,23 +4382,25 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; RV64-NEXT: vl1re16.v v8, (a0)
; RV64-NEXT: vl1re16.v v16, (a4)
; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: vl1re16.v v17, (a7)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a3, 14
; RV64-NEXT: mul a0, a0, a3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: vl1re16.v v17, (a5)
+; RV64-NEXT: slli a3, a2, 2
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1re16.v v12, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1re16.v v13, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a3, a2, a3
; RV64-NEXT: add a2, a0, a2
; RV64-NEXT: vl1re16.v v14, (a6)
; RV64-NEXT: vl1re16.v v15, (a1)
-; RV64-NEXT: add a5, a0, a5
-; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a3, a0, a3
+; RV64-NEXT: vs2r.v v20, (a3)
; RV64-NEXT: vs4r.v v16, (a2)
; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: vl8re16.v v16, (a2)
@@ -4432,29 +4425,26 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZVBB-RV32-NEXT: vmv2r.v v26, v20
; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vmv2r.v v24, v16
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 3
-; ZVBB-RV32-NEXT: sub a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
; ZVBB-RV32-NEXT: vmv2r.v v22, v12
-; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv2r.v v20, v8
; ZVBB-RV32-NEXT: vmv1r.v v1, v20
; ZVBB-RV32-NEXT: vmv1r.v v3, v22
; ZVBB-RV32-NEXT: vmv1r.v v5, v24
; ZVBB-RV32-NEXT: vmv1r.v v7, v26
-; ZVBB-RV32-NEXT: add a3, a0, a2
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
-; ZVBB-RV32-NEXT: add a4, a1, a2
-; ZVBB-RV32-NEXT: slli a5, a2, 2
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: slli a2, a1, 3
+; ZVBB-RV32-NEXT: sub a1, a2, a1
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
-; ZVBB-RV32-NEXT: slli a6, a2, 4
-; ZVBB-RV32-NEXT: add a7, a4, a2
+; ZVBB-RV32-NEXT: add a3, a0, a2
+; ZVBB-RV32-NEXT: add a4, a1, a2
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: sub a5, a6, a5
+; ZVBB-RV32-NEXT: add a5, a4, a2
; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: add a6, a7, a2
+; ZVBB-RV32-NEXT: add a6, a5, a2
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
@@ -4473,23 +4463,25 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZVBB-RV32-NEXT: vl1re16.v v8, (a0)
; ZVBB-RV32-NEXT: vl1re16.v v16, (a4)
; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a7)
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a3, 14
; ZVBB-RV32-NEXT: mul a0, a0, a3
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a5)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1re16.v v12, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1re16.v v13, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a3, a2, a3
; ZVBB-RV32-NEXT: add a2, a0, a2
; ZVBB-RV32-NEXT: vl1re16.v v14, (a6)
; ZVBB-RV32-NEXT: vl1re16.v v15, (a1)
-; ZVBB-RV32-NEXT: add a5, a0, a5
-; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a3, a0, a3
+; ZVBB-RV32-NEXT: vs2r.v v20, (a3)
; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
; ZVBB-RV32-NEXT: vl8re16.v v16, (a2)
@@ -4514,29 +4506,26 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZVBB-RV64-NEXT: vmv2r.v v26, v20
; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vmv2r.v v24, v16
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 3
-; ZVBB-RV64-NEXT: sub a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
; ZVBB-RV64-NEXT: vmv2r.v v22, v12
-; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv2r.v v20, v8
; ZVBB-RV64-NEXT: vmv1r.v v1, v20
; ZVBB-RV64-NEXT: vmv1r.v v3, v22
; ZVBB-RV64-NEXT: vmv1r.v v5, v24
; ZVBB-RV64-NEXT: vmv1r.v v7, v26
-; ZVBB-RV64-NEXT: add a3, a0, a2
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
-; ZVBB-RV64-NEXT: add a4, a1, a2
-; ZVBB-RV64-NEXT: slli a5, a2, 2
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: slli a2, a1, 3
+; ZVBB-RV64-NEXT: sub a1, a2, a1
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
-; ZVBB-RV64-NEXT: slli a6, a2, 4
-; ZVBB-RV64-NEXT: add a7, a4, a2
+; ZVBB-RV64-NEXT: add a3, a0, a2
+; ZVBB-RV64-NEXT: add a4, a1, a2
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: sub a5, a6, a5
+; ZVBB-RV64-NEXT: add a5, a4, a2
; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: add a6, a7, a2
+; ZVBB-RV64-NEXT: add a6, a5, a2
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
@@ -4555,23 +4544,25 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZVBB-RV64-NEXT: vl1re16.v v8, (a0)
; ZVBB-RV64-NEXT: vl1re16.v v16, (a4)
; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a7)
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a3, 14
; ZVBB-RV64-NEXT: mul a0, a0, a3
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a5)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1re16.v v12, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1re16.v v13, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a3, a2, a3
; ZVBB-RV64-NEXT: add a2, a0, a2
; ZVBB-RV64-NEXT: vl1re16.v v14, (a6)
; ZVBB-RV64-NEXT: vl1re16.v v15, (a1)
-; ZVBB-RV64-NEXT: add a5, a0, a5
-; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a3, a0, a3
+; ZVBB-RV64-NEXT: vs2r.v v20, (a3)
; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
; ZVBB-RV64-NEXT: vl8re16.v v16, (a2)
@@ -4596,29 +4587,26 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZIP-NEXT: vmv2r.v v26, v20
; ZIP-NEXT: addi a0, sp, 64
; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv2r.v v20, v8
; ZIP-NEXT: vmv1r.v v1, v20
; ZIP-NEXT: vmv1r.v v3, v22
; ZIP-NEXT: vmv1r.v v5, v24
; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: add a3, a0, a2
; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: slli a5, a2, 2
+; ZIP-NEXT: csrr a1, vlenb
+; ZIP-NEXT: slli a2, a1, 3
+; ZIP-NEXT: sub a1, a2, a1
+; ZIP-NEXT: add a1, sp, a1
+; ZIP-NEXT: addi a1, a1, 64
+; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: slli a6, a2, 4
-; ZIP-NEXT: add a7, a4, a2
+; ZIP-NEXT: add a3, a0, a2
+; ZIP-NEXT: add a4, a1, a2
; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: sub a5, a6, a5
+; ZIP-NEXT: add a5, a4, a2
; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a7, a2
+; ZIP-NEXT: add a6, a5, a2
; ZIP-NEXT: vmv1r.v v24, v15
; ZIP-NEXT: vsseg7e16.v v1, (a0)
; ZIP-NEXT: vmv1r.v v26, v19
@@ -4637,23 +4625,25 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZIP-NEXT: vl1re16.v v8, (a0)
; ZIP-NEXT: vl1re16.v v16, (a4)
; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: vl1re16.v v17, (a7)
; ZIP-NEXT: csrr a0, vlenb
; ZIP-NEXT: li a3, 14
; ZIP-NEXT: mul a0, a0, a3
; ZIP-NEXT: add a0, sp, a0
; ZIP-NEXT: addi a0, a0, 64
+; ZIP-NEXT: vl1re16.v v17, (a5)
+; ZIP-NEXT: slli a3, a2, 2
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1re16.v v12, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1re16.v v13, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: slli a2, a2, 3
+; ZIP-NEXT: add a3, a2, a3
; ZIP-NEXT: add a2, a0, a2
; ZIP-NEXT: vl1re16.v v14, (a6)
; ZIP-NEXT: vl1re16.v v15, (a1)
-; ZIP-NEXT: add a5, a0, a5
-; ZIP-NEXT: vs2r.v v20, (a5)
+; ZIP-NEXT: add a3, a0, a3
+; ZIP-NEXT: vs2r.v v20, (a3)
; ZIP-NEXT: vs4r.v v16, (a2)
; ZIP-NEXT: vs8r.v v8, (a0)
; ZIP-NEXT: vl8re16.v v16, (a2)
@@ -4684,29 +4674,26 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; RV32-NEXT: vmv2r.v v26, v20
; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vmv2r.v v24, v16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 3
-; RV32-NEXT: sub a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
; RV32-NEXT: vmv2r.v v22, v12
-; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv2r.v v20, v8
; RV32-NEXT: vmv1r.v v1, v20
; RV32-NEXT: vmv1r.v v3, v22
; RV32-NEXT: vmv1r.v v5, v24
; RV32-NEXT: vmv1r.v v7, v26
-; RV32-NEXT: add a3, a0, a2
; RV32-NEXT: vmv1r.v v2, v10
-; RV32-NEXT: add a4, a1, a2
-; RV32-NEXT: slli a5, a2, 2
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a2, a1, 3
+; RV32-NEXT: sub a1, a2, a1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv1r.v v4, v14
-; RV32-NEXT: slli a6, a2, 4
-; RV32-NEXT: add a7, a4, a2
+; RV32-NEXT: add a3, a0, a2
+; RV32-NEXT: add a4, a1, a2
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: sub a5, a6, a5
+; RV32-NEXT: add a5, a4, a2
; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: add a6, a7, a2
+; RV32-NEXT: add a6, a5, a2
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vsseg7e32.v v1, (a0)
; RV32-NEXT: vmv1r.v v26, v19
@@ -4725,23 +4712,25 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; RV32-NEXT: vl1re32.v v8, (a0)
; RV32-NEXT: vl1re32.v v16, (a4)
; RV32-NEXT: vl1re32.v v9, (a3)
-; RV32-NEXT: vl1re32.v v17, (a7)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a3, 14
; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: vl1re32.v v17, (a5)
+; RV32-NEXT: slli a3, a2, 2
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1re32.v v12, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1re32.v v13, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a3, a2, a3
; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: vl1re32.v v14, (a6)
; RV32-NEXT: vl1re32.v v15, (a1)
-; RV32-NEXT: add a5, a0, a5
-; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a3, a0, a3
+; RV32-NEXT: vs2r.v v20, (a3)
; RV32-NEXT: vs4r.v v16, (a2)
; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: vl8re32.v v16, (a2)
@@ -4766,29 +4755,26 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; RV64-NEXT: vmv2r.v v26, v20
; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vmv2r.v v24, v16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 3
-; RV64-NEXT: sub a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
; RV64-NEXT: vmv2r.v v22, v12
-; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv2r.v v20, v8
; RV64-NEXT: vmv1r.v v1, v20
; RV64-NEXT: vmv1r.v v3, v22
; RV64-NEXT: vmv1r.v v5, v24
; RV64-NEXT: vmv1r.v v7, v26
-; RV64-NEXT: add a3, a0, a2
; RV64-NEXT: vmv1r.v v2, v10
-; RV64-NEXT: add a4, a1, a2
-; RV64-NEXT: slli a5, a2, 2
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a2, a1, 3
+; RV64-NEXT: sub a1, a2, a1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv1r.v v4, v14
-; RV64-NEXT: slli a6, a2, 4
-; RV64-NEXT: add a7, a4, a2
+; RV64-NEXT: add a3, a0, a2
+; RV64-NEXT: add a4, a1, a2
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: sub a5, a6, a5
+; RV64-NEXT: add a5, a4, a2
; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: add a6, a7, a2
+; RV64-NEXT: add a6, a5, a2
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vsseg7e32.v v1, (a0)
; RV64-NEXT: vmv1r.v v26, v19
@@ -4807,23 +4793,25 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; RV64-NEXT: vl1re32.v v8, (a0)
; RV64-NEXT: vl1re32.v v16, (a4)
; RV64-NEXT: vl1re32.v v9, (a3)
-; RV64-NEXT: vl1re32.v v17, (a7)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a3, 14
; RV64-NEXT: mul a0, a0, a3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: vl1re32.v v17, (a5)
+; RV64-NEXT: slli a3, a2, 2
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1re32.v v12, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1re32.v v13, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a3, a2, a3
; RV64-NEXT: add a2, a0, a2
; RV64-NEXT: vl1re32.v v14, (a6)
; RV64-NEXT: vl1re32.v v15, (a1)
-; RV64-NEXT: add a5, a0, a5
-; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a3, a0, a3
+; RV64-NEXT: vs2r.v v20, (a3)
; RV64-NEXT: vs4r.v v16, (a2)
; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: vl8re32.v v16, (a2)
@@ -4848,29 +4836,26 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV32-NEXT: vmv2r.v v26, v20
; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vmv2r.v v24, v16
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 3
-; ZVBB-RV32-NEXT: sub a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
; ZVBB-RV32-NEXT: vmv2r.v v22, v12
-; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv2r.v v20, v8
; ZVBB-RV32-NEXT: vmv1r.v v1, v20
; ZVBB-RV32-NEXT: vmv1r.v v3, v22
; ZVBB-RV32-NEXT: vmv1r.v v5, v24
; ZVBB-RV32-NEXT: vmv1r.v v7, v26
-; ZVBB-RV32-NEXT: add a3, a0, a2
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
-; ZVBB-RV32-NEXT: add a4, a1, a2
-; ZVBB-RV32-NEXT: slli a5, a2, 2
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: slli a2, a1, 3
+; ZVBB-RV32-NEXT: sub a1, a2, a1
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
-; ZVBB-RV32-NEXT: slli a6, a2, 4
-; ZVBB-RV32-NEXT: add a7, a4, a2
+; ZVBB-RV32-NEXT: add a3, a0, a2
+; ZVBB-RV32-NEXT: add a4, a1, a2
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: sub a5, a6, a5
+; ZVBB-RV32-NEXT: add a5, a4, a2
; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: add a6, a7, a2
+; ZVBB-RV32-NEXT: add a6, a5, a2
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vsseg7e32.v v1, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
@@ -4889,23 +4874,25 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV32-NEXT: vl1re32.v v8, (a0)
; ZVBB-RV32-NEXT: vl1re32.v v16, (a4)
; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV32-NEXT: vl1re32.v v17, (a7)
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a3, 14
; ZVBB-RV32-NEXT: mul a0, a0, a3
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: vl1re32.v v17, (a5)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1re32.v v12, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1re32.v v13, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a3, a2, a3
; ZVBB-RV32-NEXT: add a2, a0, a2
; ZVBB-RV32-NEXT: vl1re32.v v14, (a6)
; ZVBB-RV32-NEXT: vl1re32.v v15, (a1)
-; ZVBB-RV32-NEXT: add a5, a0, a5
-; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a3, a0, a3
+; ZVBB-RV32-NEXT: vs2r.v v20, (a3)
; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
; ZVBB-RV32-NEXT: vl8re32.v v16, (a2)
@@ -4930,29 +4917,26 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV64-NEXT: vmv2r.v v26, v20
; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vmv2r.v v24, v16
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 3
-; ZVBB-RV64-NEXT: sub a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
; ZVBB-RV64-NEXT: vmv2r.v v22, v12
-; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv2r.v v20, v8
; ZVBB-RV64-NEXT: vmv1r.v v1, v20
; ZVBB-RV64-NEXT: vmv1r.v v3, v22
; ZVBB-RV64-NEXT: vmv1r.v v5, v24
; ZVBB-RV64-NEXT: vmv1r.v v7, v26
-; ZVBB-RV64-NEXT: add a3, a0, a2
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
-; ZVBB-RV64-NEXT: add a4, a1, a2
-; ZVBB-RV64-NEXT: slli a5, a2, 2
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: slli a2, a1, 3
+; ZVBB-RV64-NEXT: sub a1, a2, a1
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
-; ZVBB-RV64-NEXT: slli a6, a2, 4
-; ZVBB-RV64-NEXT: add a7, a4, a2
+; ZVBB-RV64-NEXT: add a3, a0, a2
+; ZVBB-RV64-NEXT: add a4, a1, a2
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: sub a5, a6, a5
+; ZVBB-RV64-NEXT: add a5, a4, a2
; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: add a6, a7, a2
+; ZVBB-RV64-NEXT: add a6, a5, a2
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vsseg7e32.v v1, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
@@ -4971,23 +4955,25 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV64-NEXT: vl1re32.v v8, (a0)
; ZVBB-RV64-NEXT: vl1re32.v v16, (a4)
; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV64-NEXT: vl1re32.v v17, (a7)
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a3, 14
; ZVBB-RV64-NEXT: mul a0, a0, a3
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: vl1re32.v v17, (a5)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1re32.v v12, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1re32.v v13, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a3, a2, a3
; ZVBB-RV64-NEXT: add a2, a0, a2
; ZVBB-RV64-NEXT: vl1re32.v v14, (a6)
; ZVBB-RV64-NEXT: vl1re32.v v15, (a1)
-; ZVBB-RV64-NEXT: add a5, a0, a5
-; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a3, a0, a3
+; ZVBB-RV64-NEXT: vs2r.v v20, (a3)
; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
; ZVBB-RV64-NEXT: vl8re32.v v16, (a2)
@@ -5012,29 +4998,26 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZIP-NEXT: vmv2r.v v26, v20
; ZIP-NEXT: addi a0, sp, 64
; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv2r.v v20, v8
; ZIP-NEXT: vmv1r.v v1, v20
; ZIP-NEXT: vmv1r.v v3, v22
; ZIP-NEXT: vmv1r.v v5, v24
; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: add a3, a0, a2
; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: slli a5, a2, 2
+; ZIP-NEXT: csrr a1, vlenb
+; ZIP-NEXT: slli a2, a1, 3
+; ZIP-NEXT: sub a1, a2, a1
+; ZIP-NEXT: add a1, sp, a1
+; ZIP-NEXT: addi a1, a1, 64
+; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: slli a6, a2, 4
-; ZIP-NEXT: add a7, a4, a2
+; ZIP-NEXT: add a3, a0, a2
+; ZIP-NEXT: add a4, a1, a2
; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: sub a5, a6, a5
+; ZIP-NEXT: add a5, a4, a2
; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a7, a2
+; ZIP-NEXT: add a6, a5, a2
; ZIP-NEXT: vmv1r.v v24, v15
; ZIP-NEXT: vsseg7e32.v v1, (a0)
; ZIP-NEXT: vmv1r.v v26, v19
@@ -5053,23 +5036,25 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZIP-NEXT: vl1re32.v v8, (a0)
; ZIP-NEXT: vl1re32.v v16, (a4)
; ZIP-NEXT: vl1re32.v v9, (a3)
-; ZIP-NEXT: vl1re32.v v17, (a7)
; ZIP-NEXT: csrr a0, vlenb
; ZIP-NEXT: li a3, 14
; ZIP-NEXT: mul a0, a0, a3
; ZIP-NEXT: add a0, sp, a0
; ZIP-NEXT: addi a0, a0, 64
+; ZIP-NEXT: vl1re32.v v17, (a5)
+; ZIP-NEXT: slli a3, a2, 2
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1re32.v v12, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1re32.v v13, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: slli a2, a2, 3
+; ZIP-NEXT: add a3, a2, a3
; ZIP-NEXT: add a2, a0, a2
; ZIP-NEXT: vl1re32.v v14, (a6)
; ZIP-NEXT: vl1re32.v v15, (a1)
-; ZIP-NEXT: add a5, a0, a5
-; ZIP-NEXT: vs2r.v v20, (a5)
+; ZIP-NEXT: add a3, a0, a3
+; ZIP-NEXT: vs2r.v v20, (a3)
; ZIP-NEXT: vs4r.v v16, (a2)
; ZIP-NEXT: vs8r.v v8, (a0)
; ZIP-NEXT: vl8re32.v v16, (a2)
@@ -5099,29 +5084,26 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; RV32-NEXT: vmv2r.v v26, v20
; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vmv2r.v v24, v16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 3
-; RV32-NEXT: sub a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
; RV32-NEXT: vmv2r.v v22, v12
-; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv2r.v v20, v8
; RV32-NEXT: vmv1r.v v1, v20
; RV32-NEXT: vmv1r.v v3, v22
; RV32-NEXT: vmv1r.v v5, v24
; RV32-NEXT: vmv1r.v v7, v26
-; RV32-NEXT: add a3, a0, a2
; RV32-NEXT: vmv1r.v v2, v10
-; RV32-NEXT: add a4, a1, a2
-; RV32-NEXT: slli a5, a2, 2
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a2, a1, 3
+; RV32-NEXT: sub a1, a2, a1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv1r.v v4, v14
-; RV32-NEXT: slli a6, a2, 4
-; RV32-NEXT: add a7, a4, a2
+; RV32-NEXT: add a3, a0, a2
+; RV32-NEXT: add a4, a1, a2
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: sub a5, a6, a5
+; RV32-NEXT: add a5, a4, a2
; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: add a6, a7, a2
+; RV32-NEXT: add a6, a5, a2
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vsseg7e64.v v1, (a0)
; RV32-NEXT: vmv1r.v v26, v19
@@ -5140,23 +5122,25 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; RV32-NEXT: vl1re64.v v8, (a0)
; RV32-NEXT: vl1re64.v v16, (a4)
; RV32-NEXT: vl1re64.v v9, (a3)
-; RV32-NEXT: vl1re64.v v17, (a7)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a3, 14
; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: vl1re64.v v17, (a5)
+; RV32-NEXT: slli a3, a2, 2
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1re64.v v12, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1re64.v v13, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a3, a2, a3
; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: vl1re64.v v14, (a6)
; RV32-NEXT: vl1re64.v v15, (a1)
-; RV32-NEXT: add a5, a0, a5
-; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a3, a0, a3
+; RV32-NEXT: vs2r.v v20, (a3)
; RV32-NEXT: vs4r.v v16, (a2)
; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: vl8re64.v v16, (a2)
@@ -5181,29 +5165,26 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; RV64-NEXT: vmv2r.v v26, v20
; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vmv2r.v v24, v16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 3
-; RV64-NEXT: sub a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
; RV64-NEXT: vmv2r.v v22, v12
-; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv2r.v v20, v8
; RV64-NEXT: vmv1r.v v1, v20
; RV64-NEXT: vmv1r.v v3, v22
; RV64-NEXT: vmv1r.v v5, v24
; RV64-NEXT: vmv1r.v v7, v26
-; RV64-NEXT: add a3, a0, a2
; RV64-NEXT: vmv1r.v v2, v10
-; RV64-NEXT: add a4, a1, a2
-; RV64-NEXT: slli a5, a2, 2
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a2, a1, 3
+; RV64-NEXT: sub a1, a2, a1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv1r.v v4, v14
-; RV64-NEXT: slli a6, a2, 4
-; RV64-NEXT: add a7, a4, a2
+; RV64-NEXT: add a3, a0, a2
+; RV64-NEXT: add a4, a1, a2
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: sub a5, a6, a5
+; RV64-NEXT: add a5, a4, a2
; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: add a6, a7, a2
+; RV64-NEXT: add a6, a5, a2
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vsseg7e64.v v1, (a0)
; RV64-NEXT: vmv1r.v v26, v19
@@ -5222,23 +5203,25 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; RV64-NEXT: vl1re64.v v8, (a0)
; RV64-NEXT: vl1re64.v v16, (a4)
; RV64-NEXT: vl1re64.v v9, (a3)
-; RV64-NEXT: vl1re64.v v17, (a7)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a3, 14
; RV64-NEXT: mul a0, a0, a3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: vl1re64.v v17, (a5)
+; RV64-NEXT: slli a3, a2, 2
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1re64.v v12, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1re64.v v13, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a3, a2, a3
; RV64-NEXT: add a2, a0, a2
; RV64-NEXT: vl1re64.v v14, (a6)
; RV64-NEXT: vl1re64.v v15, (a1)
-; RV64-NEXT: add a5, a0, a5
-; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a3, a0, a3
+; RV64-NEXT: vs2r.v v20, (a3)
; RV64-NEXT: vs4r.v v16, (a2)
; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: vl8re64.v v16, (a2)
@@ -5263,29 +5246,26 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV32-NEXT: vmv2r.v v26, v20
; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vmv2r.v v24, v16
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 3
-; ZVBB-RV32-NEXT: sub a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
; ZVBB-RV32-NEXT: vmv2r.v v22, v12
-; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv2r.v v20, v8
; ZVBB-RV32-NEXT: vmv1r.v v1, v20
; ZVBB-RV32-NEXT: vmv1r.v v3, v22
; ZVBB-RV32-NEXT: vmv1r.v v5, v24
; ZVBB-RV32-NEXT: vmv1r.v v7, v26
-; ZVBB-RV32-NEXT: add a3, a0, a2
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
-; ZVBB-RV32-NEXT: add a4, a1, a2
-; ZVBB-RV32-NEXT: slli a5, a2, 2
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: slli a2, a1, 3
+; ZVBB-RV32-NEXT: sub a1, a2, a1
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
-; ZVBB-RV32-NEXT: slli a6, a2, 4
-; ZVBB-RV32-NEXT: add a7, a4, a2
+; ZVBB-RV32-NEXT: add a3, a0, a2
+; ZVBB-RV32-NEXT: add a4, a1, a2
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: sub a5, a6, a5
+; ZVBB-RV32-NEXT: add a5, a4, a2
; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: add a6, a7, a2
+; ZVBB-RV32-NEXT: add a6, a5, a2
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vsseg7e64.v v1, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
@@ -5304,23 +5284,25 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV32-NEXT: vl1re64.v v8, (a0)
; ZVBB-RV32-NEXT: vl1re64.v v16, (a4)
; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV32-NEXT: vl1re64.v v17, (a7)
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a3, 14
; ZVBB-RV32-NEXT: mul a0, a0, a3
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: vl1re64.v v17, (a5)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1re64.v v12, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1re64.v v13, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a3, a2, a3
; ZVBB-RV32-NEXT: add a2, a0, a2
; ZVBB-RV32-NEXT: vl1re64.v v14, (a6)
; ZVBB-RV32-NEXT: vl1re64.v v15, (a1)
-; ZVBB-RV32-NEXT: add a5, a0, a5
-; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a3, a0, a3
+; ZVBB-RV32-NEXT: vs2r.v v20, (a3)
; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
; ZVBB-RV32-NEXT: vl8re64.v v16, (a2)
@@ -5345,29 +5327,26 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV64-NEXT: vmv2r.v v26, v20
; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vmv2r.v v24, v16
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 3
-; ZVBB-RV64-NEXT: sub a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
; ZVBB-RV64-NEXT: vmv2r.v v22, v12
-; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv2r.v v20, v8
; ZVBB-RV64-NEXT: vmv1r.v v1, v20
; ZVBB-RV64-NEXT: vmv1r.v v3, v22
; ZVBB-RV64-NEXT: vmv1r.v v5, v24
; ZVBB-RV64-NEXT: vmv1r.v v7, v26
-; ZVBB-RV64-NEXT: add a3, a0, a2
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
-; ZVBB-RV64-NEXT: add a4, a1, a2
-; ZVBB-RV64-NEXT: slli a5, a2, 2
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: slli a2, a1, 3
+; ZVBB-RV64-NEXT: sub a1, a2, a1
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
-; ZVBB-RV64-NEXT: slli a6, a2, 4
-; ZVBB-RV64-NEXT: add a7, a4, a2
+; ZVBB-RV64-NEXT: add a3, a0, a2
+; ZVBB-RV64-NEXT: add a4, a1, a2
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: sub a5, a6, a5
+; ZVBB-RV64-NEXT: add a5, a4, a2
; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: add a6, a7, a2
+; ZVBB-RV64-NEXT: add a6, a5, a2
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vsseg7e64.v v1, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
@@ -5386,23 +5365,25 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV64-NEXT: vl1re64.v v8, (a0)
; ZVBB-RV64-NEXT: vl1re64.v v16, (a4)
; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV64-NEXT: vl1re64.v v17, (a7)
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a3, 14
; ZVBB-RV64-NEXT: mul a0, a0, a3
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: vl1re64.v v17, (a5)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1re64.v v12, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1re64.v v13, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a3, a2, a3
; ZVBB-RV64-NEXT: add a2, a0, a2
; ZVBB-RV64-NEXT: vl1re64.v v14, (a6)
; ZVBB-RV64-NEXT: vl1re64.v v15, (a1)
-; ZVBB-RV64-NEXT: add a5, a0, a5
-; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a3, a0, a3
+; ZVBB-RV64-NEXT: vs2r.v v20, (a3)
; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
; ZVBB-RV64-NEXT: vl8re64.v v16, (a2)
@@ -5427,29 +5408,26 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZIP-NEXT: vmv2r.v v26, v20
; ZIP-NEXT: addi a0, sp, 64
; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv2r.v v20, v8
; ZIP-NEXT: vmv1r.v v1, v20
; ZIP-NEXT: vmv1r.v v3, v22
; ZIP-NEXT: vmv1r.v v5, v24
; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: add a3, a0, a2
; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: slli a5, a2, 2
+; ZIP-NEXT: csrr a1, vlenb
+; ZIP-NEXT: slli a2, a1, 3
+; ZIP-NEXT: sub a1, a2, a1
+; ZIP-NEXT: add a1, sp, a1
+; ZIP-NEXT: addi a1, a1, 64
+; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: slli a6, a2, 4
-; ZIP-NEXT: add a7, a4, a2
+; ZIP-NEXT: add a3, a0, a2
+; ZIP-NEXT: add a4, a1, a2
; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: sub a5, a6, a5
+; ZIP-NEXT: add a5, a4, a2
; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a7, a2
+; ZIP-NEXT: add a6, a5, a2
; ZIP-NEXT: vmv1r.v v24, v15
; ZIP-NEXT: vsseg7e64.v v1, (a0)
; ZIP-NEXT: vmv1r.v v26, v19
@@ -5468,23 +5446,25 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZIP-NEXT: vl1re64.v v8, (a0)
; ZIP-NEXT: vl1re64.v v16, (a4)
; ZIP-NEXT: vl1re64.v v9, (a3)
-; ZIP-NEXT: vl1re64.v v17, (a7)
; ZIP-NEXT: csrr a0, vlenb
; ZIP-NEXT: li a3, 14
; ZIP-NEXT: mul a0, a0, a3
; ZIP-NEXT: add a0, sp, a0
; ZIP-NEXT: addi a0, a0, 64
+; ZIP-NEXT: vl1re64.v v17, (a5)
+; ZIP-NEXT: slli a3, a2, 2
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1re64.v v12, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1re64.v v13, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: slli a2, a2, 3
+; ZIP-NEXT: add a3, a2, a3
; ZIP-NEXT: add a2, a0, a2
; ZIP-NEXT: vl1re64.v v14, (a6)
; ZIP-NEXT: vl1re64.v v15, (a1)
-; ZIP-NEXT: add a5, a0, a5
-; ZIP-NEXT: vs2r.v v20, (a5)
+; ZIP-NEXT: add a3, a0, a3
+; ZIP-NEXT: vs2r.v v20, (a3)
; ZIP-NEXT: vs4r.v v16, (a2)
; ZIP-NEXT: vs8r.v v8, (a0)
; ZIP-NEXT: vl8re64.v v16, (a2)
@@ -11853,29 +11833,26 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; RV32-NEXT: vmv2r.v v26, v20
; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vmv2r.v v24, v16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 3
-; RV32-NEXT: sub a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
; RV32-NEXT: vmv2r.v v22, v12
-; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv2r.v v20, v8
; RV32-NEXT: vmv1r.v v1, v20
; RV32-NEXT: vmv1r.v v3, v22
; RV32-NEXT: vmv1r.v v5, v24
; RV32-NEXT: vmv1r.v v7, v26
-; RV32-NEXT: add a3, a0, a2
; RV32-NEXT: vmv1r.v v2, v10
-; RV32-NEXT: add a4, a1, a2
-; RV32-NEXT: slli a5, a2, 2
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a2, a1, 3
+; RV32-NEXT: sub a1, a2, a1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv1r.v v4, v14
-; RV32-NEXT: slli a6, a2, 4
-; RV32-NEXT: add a7, a4, a2
+; RV32-NEXT: add a3, a0, a2
+; RV32-NEXT: add a4, a1, a2
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: sub a5, a6, a5
+; RV32-NEXT: add a5, a4, a2
; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: add a6, a7, a2
+; RV32-NEXT: add a6, a5, a2
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vsseg7e16.v v1, (a0)
; RV32-NEXT: vmv1r.v v26, v19
@@ -11894,23 +11871,25 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; RV32-NEXT: vl1re16.v v8, (a0)
; RV32-NEXT: vl1re16.v v16, (a4)
; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: vl1re16.v v17, (a7)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a3, 14
; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: vl1re16.v v17, (a5)
+; RV32-NEXT: slli a3, a2, 2
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1re16.v v12, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1re16.v v13, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a3, a2, a3
; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: vl1re16.v v14, (a6)
; RV32-NEXT: vl1re16.v v15, (a1)
-; RV32-NEXT: add a5, a0, a5
-; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a3, a0, a3
+; RV32-NEXT: vs2r.v v20, (a3)
; RV32-NEXT: vs4r.v v16, (a2)
; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: vl8re16.v v16, (a2)
@@ -11935,29 +11914,26 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; RV64-NEXT: vmv2r.v v26, v20
; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vmv2r.v v24, v16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 3
-; RV64-NEXT: sub a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
; RV64-NEXT: vmv2r.v v22, v12
-; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv2r.v v20, v8
; RV64-NEXT: vmv1r.v v1, v20
; RV64-NEXT: vmv1r.v v3, v22
; RV64-NEXT: vmv1r.v v5, v24
; RV64-NEXT: vmv1r.v v7, v26
-; RV64-NEXT: add a3, a0, a2
; RV64-NEXT: vmv1r.v v2, v10
-; RV64-NEXT: add a4, a1, a2
-; RV64-NEXT: slli a5, a2, 2
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a2, a1, 3
+; RV64-NEXT: sub a1, a2, a1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv1r.v v4, v14
-; RV64-NEXT: slli a6, a2, 4
-; RV64-NEXT: add a7, a4, a2
+; RV64-NEXT: add a3, a0, a2
+; RV64-NEXT: add a4, a1, a2
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: sub a5, a6, a5
+; RV64-NEXT: add a5, a4, a2
; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: add a6, a7, a2
+; RV64-NEXT: add a6, a5, a2
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vsseg7e16.v v1, (a0)
; RV64-NEXT: vmv1r.v v26, v19
@@ -11976,23 +11952,25 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; RV64-NEXT: vl1re16.v v8, (a0)
; RV64-NEXT: vl1re16.v v16, (a4)
; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: vl1re16.v v17, (a7)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a3, 14
; RV64-NEXT: mul a0, a0, a3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: vl1re16.v v17, (a5)
+; RV64-NEXT: slli a3, a2, 2
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1re16.v v12, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1re16.v v13, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a3, a2, a3
; RV64-NEXT: add a2, a0, a2
; RV64-NEXT: vl1re16.v v14, (a6)
; RV64-NEXT: vl1re16.v v15, (a1)
-; RV64-NEXT: add a5, a0, a5
-; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a3, a0, a3
+; RV64-NEXT: vs2r.v v20, (a3)
; RV64-NEXT: vs4r.v v16, (a2)
; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: vl8re16.v v16, (a2)
@@ -12017,29 +11995,26 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV32-NEXT: vmv2r.v v26, v20
; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vmv2r.v v24, v16
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 3
-; ZVBB-RV32-NEXT: sub a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
; ZVBB-RV32-NEXT: vmv2r.v v22, v12
-; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv2r.v v20, v8
; ZVBB-RV32-NEXT: vmv1r.v v1, v20
; ZVBB-RV32-NEXT: vmv1r.v v3, v22
; ZVBB-RV32-NEXT: vmv1r.v v5, v24
; ZVBB-RV32-NEXT: vmv1r.v v7, v26
-; ZVBB-RV32-NEXT: add a3, a0, a2
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
-; ZVBB-RV32-NEXT: add a4, a1, a2
-; ZVBB-RV32-NEXT: slli a5, a2, 2
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: slli a2, a1, 3
+; ZVBB-RV32-NEXT: sub a1, a2, a1
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
-; ZVBB-RV32-NEXT: slli a6, a2, 4
-; ZVBB-RV32-NEXT: add a7, a4, a2
+; ZVBB-RV32-NEXT: add a3, a0, a2
+; ZVBB-RV32-NEXT: add a4, a1, a2
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: sub a5, a6, a5
+; ZVBB-RV32-NEXT: add a5, a4, a2
; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: add a6, a7, a2
+; ZVBB-RV32-NEXT: add a6, a5, a2
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
@@ -12058,23 +12033,25 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV32-NEXT: vl1re16.v v8, (a0)
; ZVBB-RV32-NEXT: vl1re16.v v16, (a4)
; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a7)
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a3, 14
; ZVBB-RV32-NEXT: mul a0, a0, a3
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a5)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1re16.v v12, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1re16.v v13, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a3, a2, a3
; ZVBB-RV32-NEXT: add a2, a0, a2
; ZVBB-RV32-NEXT: vl1re16.v v14, (a6)
; ZVBB-RV32-NEXT: vl1re16.v v15, (a1)
-; ZVBB-RV32-NEXT: add a5, a0, a5
-; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a3, a0, a3
+; ZVBB-RV32-NEXT: vs2r.v v20, (a3)
; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
; ZVBB-RV32-NEXT: vl8re16.v v16, (a2)
@@ -12099,29 +12076,26 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV64-NEXT: vmv2r.v v26, v20
; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vmv2r.v v24, v16
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 3
-; ZVBB-RV64-NEXT: sub a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
; ZVBB-RV64-NEXT: vmv2r.v v22, v12
-; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv2r.v v20, v8
; ZVBB-RV64-NEXT: vmv1r.v v1, v20
; ZVBB-RV64-NEXT: vmv1r.v v3, v22
; ZVBB-RV64-NEXT: vmv1r.v v5, v24
; ZVBB-RV64-NEXT: vmv1r.v v7, v26
-; ZVBB-RV64-NEXT: add a3, a0, a2
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
-; ZVBB-RV64-NEXT: add a4, a1, a2
-; ZVBB-RV64-NEXT: slli a5, a2, 2
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: slli a2, a1, 3
+; ZVBB-RV64-NEXT: sub a1, a2, a1
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
-; ZVBB-RV64-NEXT: slli a6, a2, 4
-; ZVBB-RV64-NEXT: add a7, a4, a2
+; ZVBB-RV64-NEXT: add a3, a0, a2
+; ZVBB-RV64-NEXT: add a4, a1, a2
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: sub a5, a6, a5
+; ZVBB-RV64-NEXT: add a5, a4, a2
; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: add a6, a7, a2
+; ZVBB-RV64-NEXT: add a6, a5, a2
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
@@ -12140,23 +12114,25 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV64-NEXT: vl1re16.v v8, (a0)
; ZVBB-RV64-NEXT: vl1re16.v v16, (a4)
; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a7)
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a3, 14
; ZVBB-RV64-NEXT: mul a0, a0, a3
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a5)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1re16.v v12, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1re16.v v13, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a3, a2, a3
; ZVBB-RV64-NEXT: add a2, a0, a2
; ZVBB-RV64-NEXT: vl1re16.v v14, (a6)
; ZVBB-RV64-NEXT: vl1re16.v v15, (a1)
-; ZVBB-RV64-NEXT: add a5, a0, a5
-; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a3, a0, a3
+; ZVBB-RV64-NEXT: vs2r.v v20, (a3)
; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
; ZVBB-RV64-NEXT: vl8re16.v v16, (a2)
@@ -12181,29 +12157,26 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZIP-NEXT: vmv2r.v v26, v20
; ZIP-NEXT: addi a0, sp, 64
; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv2r.v v20, v8
; ZIP-NEXT: vmv1r.v v1, v20
; ZIP-NEXT: vmv1r.v v3, v22
; ZIP-NEXT: vmv1r.v v5, v24
; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: add a3, a0, a2
; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: slli a5, a2, 2
+; ZIP-NEXT: csrr a1, vlenb
+; ZIP-NEXT: slli a2, a1, 3
+; ZIP-NEXT: sub a1, a2, a1
+; ZIP-NEXT: add a1, sp, a1
+; ZIP-NEXT: addi a1, a1, 64
+; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: slli a6, a2, 4
-; ZIP-NEXT: add a7, a4, a2
+; ZIP-NEXT: add a3, a0, a2
+; ZIP-NEXT: add a4, a1, a2
; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: sub a5, a6, a5
+; ZIP-NEXT: add a5, a4, a2
; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a7, a2
+; ZIP-NEXT: add a6, a5, a2
; ZIP-NEXT: vmv1r.v v24, v15
; ZIP-NEXT: vsseg7e16.v v1, (a0)
; ZIP-NEXT: vmv1r.v v26, v19
@@ -12222,23 +12195,25 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZIP-NEXT: vl1re16.v v8, (a0)
; ZIP-NEXT: vl1re16.v v16, (a4)
; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: vl1re16.v v17, (a7)
; ZIP-NEXT: csrr a0, vlenb
; ZIP-NEXT: li a3, 14
; ZIP-NEXT: mul a0, a0, a3
; ZIP-NEXT: add a0, sp, a0
; ZIP-NEXT: addi a0, a0, 64
+; ZIP-NEXT: vl1re16.v v17, (a5)
+; ZIP-NEXT: slli a3, a2, 2
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1re16.v v12, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1re16.v v13, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: slli a2, a2, 3
+; ZIP-NEXT: add a3, a2, a3
; ZIP-NEXT: add a2, a0, a2
; ZIP-NEXT: vl1re16.v v14, (a6)
; ZIP-NEXT: vl1re16.v v15, (a1)
-; ZIP-NEXT: add a5, a0, a5
-; ZIP-NEXT: vs2r.v v20, (a5)
+; ZIP-NEXT: add a3, a0, a3
+; ZIP-NEXT: vs2r.v v20, (a3)
; ZIP-NEXT: vs4r.v v16, (a2)
; ZIP-NEXT: vs8r.v v8, (a0)
; ZIP-NEXT: vl8re16.v v16, (a2)
@@ -12415,29 +12390,26 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; RV32-NEXT: vmv2r.v v26, v20
; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vmv2r.v v24, v16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 3
-; RV32-NEXT: sub a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
; RV32-NEXT: vmv2r.v v22, v12
-; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv2r.v v20, v8
; RV32-NEXT: vmv1r.v v1, v20
; RV32-NEXT: vmv1r.v v3, v22
; RV32-NEXT: vmv1r.v v5, v24
; RV32-NEXT: vmv1r.v v7, v26
+; RV32-NEXT: vmv1r.v v2, v10
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a2, a1, 3
+; RV32-NEXT: sub a1, a2, a1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: add a4, a1, a2
-; RV32-NEXT: slli a5, a2, 2
-; RV32-NEXT: vmv1r.v v4, v14
-; RV32-NEXT: slli a6, a2, 4
-; RV32-NEXT: add a7, a4, a2
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: sub a5, a6, a5
+; RV32-NEXT: add a5, a4, a2
; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: add a6, a7, a2
+; RV32-NEXT: add a6, a5, a2
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vsseg7e16.v v1, (a0)
; RV32-NEXT: vmv1r.v v26, v19
@@ -12456,23 +12428,25 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; RV32-NEXT: vl1re16.v v8, (a0)
; RV32-NEXT: vl1re16.v v16, (a4)
; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: vl1re16.v v17, (a7)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a3, 14
; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: vl1re16.v v17, (a5)
+; RV32-NEXT: slli a3, a2, 2
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1re16.v v12, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1re16.v v13, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a3, a2, a3
; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: vl1re16.v v14, (a6)
; RV32-NEXT: vl1re16.v v15, (a1)
-; RV32-NEXT: add a5, a0, a5
-; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a3, a0, a3
+; RV32-NEXT: vs2r.v v20, (a3)
; RV32-NEXT: vs4r.v v16, (a2)
; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: vl8re16.v v16, (a2)
@@ -12497,29 +12471,26 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; RV64-NEXT: vmv2r.v v26, v20
; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vmv2r.v v24, v16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 3
-; RV64-NEXT: sub a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
; RV64-NEXT: vmv2r.v v22, v12
-; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv2r.v v20, v8
; RV64-NEXT: vmv1r.v v1, v20
; RV64-NEXT: vmv1r.v v3, v22
; RV64-NEXT: vmv1r.v v5, v24
; RV64-NEXT: vmv1r.v v7, v26
-; RV64-NEXT: add a3, a0, a2
; RV64-NEXT: vmv1r.v v2, v10
-; RV64-NEXT: add a4, a1, a2
-; RV64-NEXT: slli a5, a2, 2
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a2, a1, 3
+; RV64-NEXT: sub a1, a2, a1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv1r.v v4, v14
-; RV64-NEXT: slli a6, a2, 4
-; RV64-NEXT: add a7, a4, a2
+; RV64-NEXT: add a3, a0, a2
+; RV64-NEXT: add a4, a1, a2
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: sub a5, a6, a5
+; RV64-NEXT: add a5, a4, a2
; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: add a6, a7, a2
+; RV64-NEXT: add a6, a5, a2
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vsseg7e16.v v1, (a0)
; RV64-NEXT: vmv1r.v v26, v19
@@ -12538,23 +12509,25 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; RV64-NEXT: vl1re16.v v8, (a0)
; RV64-NEXT: vl1re16.v v16, (a4)
; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: vl1re16.v v17, (a7)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a3, 14
; RV64-NEXT: mul a0, a0, a3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: vl1re16.v v17, (a5)
+; RV64-NEXT: slli a3, a2, 2
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1re16.v v12, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1re16.v v13, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a3, a2, a3
; RV64-NEXT: add a2, a0, a2
; RV64-NEXT: vl1re16.v v14, (a6)
; RV64-NEXT: vl1re16.v v15, (a1)
-; RV64-NEXT: add a5, a0, a5
-; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a3, a0, a3
+; RV64-NEXT: vs2r.v v20, (a3)
; RV64-NEXT: vs4r.v v16, (a2)
; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: vl8re16.v v16, (a2)
@@ -12579,29 +12552,26 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZVBB-RV32-NEXT: vmv2r.v v26, v20
; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vmv2r.v v24, v16
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 3
-; ZVBB-RV32-NEXT: sub a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
; ZVBB-RV32-NEXT: vmv2r.v v22, v12
-; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv2r.v v20, v8
; ZVBB-RV32-NEXT: vmv1r.v v1, v20
; ZVBB-RV32-NEXT: vmv1r.v v3, v22
; ZVBB-RV32-NEXT: vmv1r.v v5, v24
; ZVBB-RV32-NEXT: vmv1r.v v7, v26
-; ZVBB-RV32-NEXT: add a3, a0, a2
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
-; ZVBB-RV32-NEXT: add a4, a1, a2
-; ZVBB-RV32-NEXT: slli a5, a2, 2
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: slli a2, a1, 3
+; ZVBB-RV32-NEXT: sub a1, a2, a1
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
-; ZVBB-RV32-NEXT: slli a6, a2, 4
-; ZVBB-RV32-NEXT: add a7, a4, a2
+; ZVBB-RV32-NEXT: add a3, a0, a2
+; ZVBB-RV32-NEXT: add a4, a1, a2
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: sub a5, a6, a5
+; ZVBB-RV32-NEXT: add a5, a4, a2
; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: add a6, a7, a2
+; ZVBB-RV32-NEXT: add a6, a5, a2
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
@@ -12620,23 +12590,25 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZVBB-RV32-NEXT: vl1re16.v v8, (a0)
; ZVBB-RV32-NEXT: vl1re16.v v16, (a4)
; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a7)
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a3, 14
; ZVBB-RV32-NEXT: mul a0, a0, a3
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a5)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1re16.v v12, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1re16.v v13, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a3, a2, a3
; ZVBB-RV32-NEXT: add a2, a0, a2
; ZVBB-RV32-NEXT: vl1re16.v v14, (a6)
; ZVBB-RV32-NEXT: vl1re16.v v15, (a1)
-; ZVBB-RV32-NEXT: add a5, a0, a5
-; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a3, a0, a3
+; ZVBB-RV32-NEXT: vs2r.v v20, (a3)
; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
; ZVBB-RV32-NEXT: vl8re16.v v16, (a2)
@@ -12661,29 +12633,26 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZVBB-RV64-NEXT: vmv2r.v v26, v20
; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vmv2r.v v24, v16
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 3
-; ZVBB-RV64-NEXT: sub a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
; ZVBB-RV64-NEXT: vmv2r.v v22, v12
-; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv2r.v v20, v8
; ZVBB-RV64-NEXT: vmv1r.v v1, v20
; ZVBB-RV64-NEXT: vmv1r.v v3, v22
; ZVBB-RV64-NEXT: vmv1r.v v5, v24
; ZVBB-RV64-NEXT: vmv1r.v v7, v26
-; ZVBB-RV64-NEXT: add a3, a0, a2
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
-; ZVBB-RV64-NEXT: add a4, a1, a2
-; ZVBB-RV64-NEXT: slli a5, a2, 2
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: slli a2, a1, 3
+; ZVBB-RV64-NEXT: sub a1, a2, a1
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
-; ZVBB-RV64-NEXT: slli a6, a2, 4
-; ZVBB-RV64-NEXT: add a7, a4, a2
+; ZVBB-RV64-NEXT: add a3, a0, a2
+; ZVBB-RV64-NEXT: add a4, a1, a2
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: sub a5, a6, a5
+; ZVBB-RV64-NEXT: add a5, a4, a2
; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: add a6, a7, a2
+; ZVBB-RV64-NEXT: add a6, a5, a2
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
@@ -12702,23 +12671,25 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZVBB-RV64-NEXT: vl1re16.v v8, (a0)
; ZVBB-RV64-NEXT: vl1re16.v v16, (a4)
; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a7)
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a3, 14
; ZVBB-RV64-NEXT: mul a0, a0, a3
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a5)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1re16.v v12, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1re16.v v13, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a3, a2, a3
; ZVBB-RV64-NEXT: add a2, a0, a2
; ZVBB-RV64-NEXT: vl1re16.v v14, (a6)
; ZVBB-RV64-NEXT: vl1re16.v v15, (a1)
-; ZVBB-RV64-NEXT: add a5, a0, a5
-; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a3, a0, a3
+; ZVBB-RV64-NEXT: vs2r.v v20, (a3)
; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
; ZVBB-RV64-NEXT: vl8re16.v v16, (a2)
@@ -12743,29 +12714,26 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZIP-NEXT: vmv2r.v v26, v20
; ZIP-NEXT: addi a0, sp, 64
; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv2r.v v20, v8
; ZIP-NEXT: vmv1r.v v1, v20
; ZIP-NEXT: vmv1r.v v3, v22
; ZIP-NEXT: vmv1r.v v5, v24
; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: add a3, a0, a2
; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: slli a5, a2, 2
+; ZIP-NEXT: csrr a1, vlenb
+; ZIP-NEXT: slli a2, a1, 3
+; ZIP-NEXT: sub a1, a2, a1
+; ZIP-NEXT: add a1, sp, a1
+; ZIP-NEXT: addi a1, a1, 64
+; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: slli a6, a2, 4
-; ZIP-NEXT: add a7, a4, a2
+; ZIP-NEXT: add a3, a0, a2
+; ZIP-NEXT: add a4, a1, a2
; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: sub a5, a6, a5
+; ZIP-NEXT: add a5, a4, a2
; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a7, a2
+; ZIP-NEXT: add a6, a5, a2
; ZIP-NEXT: vmv1r.v v24, v15
; ZIP-NEXT: vsseg7e16.v v1, (a0)
; ZIP-NEXT: vmv1r.v v26, v19
@@ -12784,23 +12752,25 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZIP-NEXT: vl1re16.v v8, (a0)
; ZIP-NEXT: vl1re16.v v16, (a4)
; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: vl1re16.v v17, (a7)
; ZIP-NEXT: csrr a0, vlenb
; ZIP-NEXT: li a3, 14
; ZIP-NEXT: mul a0, a0, a3
; ZIP-NEXT: add a0, sp, a0
; ZIP-NEXT: addi a0, a0, 64
+; ZIP-NEXT: vl1re16.v v17, (a5)
+; ZIP-NEXT: slli a3, a2, 2
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1re16.v v12, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1re16.v v13, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: slli a2, a2, 3
+; ZIP-NEXT: add a3, a2, a3
; ZIP-NEXT: add a2, a0, a2
; ZIP-NEXT: vl1re16.v v14, (a6)
; ZIP-NEXT: vl1re16.v v15, (a1)
-; ZIP-NEXT: add a5, a0, a5
-; ZIP-NEXT: vs2r.v v20, (a5)
+; ZIP-NEXT: add a3, a0, a3
+; ZIP-NEXT: vs2r.v v20, (a3)
; ZIP-NEXT: vs4r.v v16, (a2)
; ZIP-NEXT: vs8r.v v8, (a0)
; ZIP-NEXT: vl8re16.v v16, (a2)
@@ -12977,29 +12947,26 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; RV32-NEXT: vmv2r.v v26, v20
; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vmv2r.v v24, v16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 3
-; RV32-NEXT: sub a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
; RV32-NEXT: vmv2r.v v22, v12
-; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv2r.v v20, v8
; RV32-NEXT: vmv1r.v v1, v20
; RV32-NEXT: vmv1r.v v3, v22
; RV32-NEXT: vmv1r.v v5, v24
; RV32-NEXT: vmv1r.v v7, v26
-; RV32-NEXT: add a3, a0, a2
; RV32-NEXT: vmv1r.v v2, v10
-; RV32-NEXT: add a4, a1, a2
-; RV32-NEXT: slli a5, a2, 2
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a2, a1, 3
+; RV32-NEXT: sub a1, a2, a1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv1r.v v4, v14
-; RV32-NEXT: slli a6, a2, 4
-; RV32-NEXT: add a7, a4, a2
+; RV32-NEXT: add a3, a0, a2
+; RV32-NEXT: add a4, a1, a2
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: sub a5, a6, a5
+; RV32-NEXT: add a5, a4, a2
; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: add a6, a7, a2
+; RV32-NEXT: add a6, a5, a2
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vsseg7e32.v v1, (a0)
; RV32-NEXT: vmv1r.v v26, v19
@@ -13018,23 +12985,25 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; RV32-NEXT: vl1re32.v v8, (a0)
; RV32-NEXT: vl1re32.v v16, (a4)
; RV32-NEXT: vl1re32.v v9, (a3)
-; RV32-NEXT: vl1re32.v v17, (a7)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a3, 14
; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: vl1re32.v v17, (a5)
+; RV32-NEXT: slli a3, a2, 2
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1re32.v v12, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1re32.v v13, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a3, a2, a3
; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: vl1re32.v v14, (a6)
; RV32-NEXT: vl1re32.v v15, (a1)
-; RV32-NEXT: add a5, a0, a5
-; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a3, a0, a3
+; RV32-NEXT: vs2r.v v20, (a3)
; RV32-NEXT: vs4r.v v16, (a2)
; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: vl8re32.v v16, (a2)
@@ -13059,29 +13028,26 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; RV64-NEXT: vmv2r.v v26, v20
; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vmv2r.v v24, v16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 3
-; RV64-NEXT: sub a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
; RV64-NEXT: vmv2r.v v22, v12
-; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv2r.v v20, v8
; RV64-NEXT: vmv1r.v v1, v20
; RV64-NEXT: vmv1r.v v3, v22
; RV64-NEXT: vmv1r.v v5, v24
; RV64-NEXT: vmv1r.v v7, v26
-; RV64-NEXT: add a3, a0, a2
; RV64-NEXT: vmv1r.v v2, v10
-; RV64-NEXT: add a4, a1, a2
-; RV64-NEXT: slli a5, a2, 2
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a2, a1, 3
+; RV64-NEXT: sub a1, a2, a1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv1r.v v4, v14
-; RV64-NEXT: slli a6, a2, 4
-; RV64-NEXT: add a7, a4, a2
+; RV64-NEXT: add a3, a0, a2
+; RV64-NEXT: add a4, a1, a2
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: sub a5, a6, a5
+; RV64-NEXT: add a5, a4, a2
; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: add a6, a7, a2
+; RV64-NEXT: add a6, a5, a2
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vsseg7e32.v v1, (a0)
; RV64-NEXT: vmv1r.v v26, v19
@@ -13100,23 +13066,25 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; RV64-NEXT: vl1re32.v v8, (a0)
; RV64-NEXT: vl1re32.v v16, (a4)
; RV64-NEXT: vl1re32.v v9, (a3)
-; RV64-NEXT: vl1re32.v v17, (a7)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a3, 14
; RV64-NEXT: mul a0, a0, a3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: vl1re32.v v17, (a5)
+; RV64-NEXT: slli a3, a2, 2
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1re32.v v12, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1re32.v v13, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a3, a2, a3
; RV64-NEXT: add a2, a0, a2
; RV64-NEXT: vl1re32.v v14, (a6)
; RV64-NEXT: vl1re32.v v15, (a1)
-; RV64-NEXT: add a5, a0, a5
-; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a3, a0, a3
+; RV64-NEXT: vs2r.v v20, (a3)
; RV64-NEXT: vs4r.v v16, (a2)
; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: vl8re32.v v16, (a2)
@@ -13141,29 +13109,26 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV32-NEXT: vmv2r.v v26, v20
; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vmv2r.v v24, v16
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 3
-; ZVBB-RV32-NEXT: sub a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
; ZVBB-RV32-NEXT: vmv2r.v v22, v12
-; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv2r.v v20, v8
; ZVBB-RV32-NEXT: vmv1r.v v1, v20
; ZVBB-RV32-NEXT: vmv1r.v v3, v22
; ZVBB-RV32-NEXT: vmv1r.v v5, v24
; ZVBB-RV32-NEXT: vmv1r.v v7, v26
-; ZVBB-RV32-NEXT: add a3, a0, a2
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
-; ZVBB-RV32-NEXT: add a4, a1, a2
-; ZVBB-RV32-NEXT: slli a5, a2, 2
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: slli a2, a1, 3
+; ZVBB-RV32-NEXT: sub a1, a2, a1
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
-; ZVBB-RV32-NEXT: slli a6, a2, 4
-; ZVBB-RV32-NEXT: add a7, a4, a2
+; ZVBB-RV32-NEXT: add a3, a0, a2
+; ZVBB-RV32-NEXT: add a4, a1, a2
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: sub a5, a6, a5
+; ZVBB-RV32-NEXT: add a5, a4, a2
; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: add a6, a7, a2
+; ZVBB-RV32-NEXT: add a6, a5, a2
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vsseg7e32.v v1, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
@@ -13182,23 +13147,25 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV32-NEXT: vl1re32.v v8, (a0)
; ZVBB-RV32-NEXT: vl1re32.v v16, (a4)
; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV32-NEXT: vl1re32.v v17, (a7)
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a3, 14
; ZVBB-RV32-NEXT: mul a0, a0, a3
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: vl1re32.v v17, (a5)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1re32.v v12, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1re32.v v13, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a3, a2, a3
; ZVBB-RV32-NEXT: add a2, a0, a2
; ZVBB-RV32-NEXT: vl1re32.v v14, (a6)
; ZVBB-RV32-NEXT: vl1re32.v v15, (a1)
-; ZVBB-RV32-NEXT: add a5, a0, a5
-; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a3, a0, a3
+; ZVBB-RV32-NEXT: vs2r.v v20, (a3)
; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
; ZVBB-RV32-NEXT: vl8re32.v v16, (a2)
@@ -13223,29 +13190,26 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV64-NEXT: vmv2r.v v26, v20
; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vmv2r.v v24, v16
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 3
-; ZVBB-RV64-NEXT: sub a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
; ZVBB-RV64-NEXT: vmv2r.v v22, v12
-; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv2r.v v20, v8
; ZVBB-RV64-NEXT: vmv1r.v v1, v20
; ZVBB-RV64-NEXT: vmv1r.v v3, v22
; ZVBB-RV64-NEXT: vmv1r.v v5, v24
; ZVBB-RV64-NEXT: vmv1r.v v7, v26
-; ZVBB-RV64-NEXT: add a3, a0, a2
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
-; ZVBB-RV64-NEXT: add a4, a1, a2
-; ZVBB-RV64-NEXT: slli a5, a2, 2
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: slli a2, a1, 3
+; ZVBB-RV64-NEXT: sub a1, a2, a1
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
-; ZVBB-RV64-NEXT: slli a6, a2, 4
-; ZVBB-RV64-NEXT: add a7, a4, a2
+; ZVBB-RV64-NEXT: add a3, a0, a2
+; ZVBB-RV64-NEXT: add a4, a1, a2
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: sub a5, a6, a5
+; ZVBB-RV64-NEXT: add a5, a4, a2
; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: add a6, a7, a2
+; ZVBB-RV64-NEXT: add a6, a5, a2
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vsseg7e32.v v1, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
@@ -13264,23 +13228,25 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV64-NEXT: vl1re32.v v8, (a0)
; ZVBB-RV64-NEXT: vl1re32.v v16, (a4)
; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV64-NEXT: vl1re32.v v17, (a7)
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a3, 14
; ZVBB-RV64-NEXT: mul a0, a0, a3
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: vl1re32.v v17, (a5)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1re32.v v12, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1re32.v v13, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a3, a2, a3
; ZVBB-RV64-NEXT: add a2, a0, a2
; ZVBB-RV64-NEXT: vl1re32.v v14, (a6)
; ZVBB-RV64-NEXT: vl1re32.v v15, (a1)
-; ZVBB-RV64-NEXT: add a5, a0, a5
-; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a3, a0, a3
+; ZVBB-RV64-NEXT: vs2r.v v20, (a3)
; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
; ZVBB-RV64-NEXT: vl8re32.v v16, (a2)
@@ -13305,29 +13271,26 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZIP-NEXT: vmv2r.v v26, v20
; ZIP-NEXT: addi a0, sp, 64
; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv2r.v v20, v8
; ZIP-NEXT: vmv1r.v v1, v20
; ZIP-NEXT: vmv1r.v v3, v22
; ZIP-NEXT: vmv1r.v v5, v24
; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: add a3, a0, a2
; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: slli a5, a2, 2
+; ZIP-NEXT: csrr a1, vlenb
+; ZIP-NEXT: slli a2, a1, 3
+; ZIP-NEXT: sub a1, a2, a1
+; ZIP-NEXT: add a1, sp, a1
+; ZIP-NEXT: addi a1, a1, 64
+; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: slli a6, a2, 4
-; ZIP-NEXT: add a7, a4, a2
+; ZIP-NEXT: add a3, a0, a2
+; ZIP-NEXT: add a4, a1, a2
; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: sub a5, a6, a5
+; ZIP-NEXT: add a5, a4, a2
; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a7, a2
+; ZIP-NEXT: add a6, a5, a2
; ZIP-NEXT: vmv1r.v v24, v15
; ZIP-NEXT: vsseg7e32.v v1, (a0)
; ZIP-NEXT: vmv1r.v v26, v19
@@ -13346,23 +13309,25 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZIP-NEXT: vl1re32.v v8, (a0)
; ZIP-NEXT: vl1re32.v v16, (a4)
; ZIP-NEXT: vl1re32.v v9, (a3)
-; ZIP-NEXT: vl1re32.v v17, (a7)
; ZIP-NEXT: csrr a0, vlenb
; ZIP-NEXT: li a3, 14
; ZIP-NEXT: mul a0, a0, a3
; ZIP-NEXT: add a0, sp, a0
; ZIP-NEXT: addi a0, a0, 64
+; ZIP-NEXT: vl1re32.v v17, (a5)
+; ZIP-NEXT: slli a3, a2, 2
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1re32.v v12, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1re32.v v13, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: slli a2, a2, 3
+; ZIP-NEXT: add a3, a2, a3
; ZIP-NEXT: add a2, a0, a2
; ZIP-NEXT: vl1re32.v v14, (a6)
; ZIP-NEXT: vl1re32.v v15, (a1)
-; ZIP-NEXT: add a5, a0, a5
-; ZIP-NEXT: vs2r.v v20, (a5)
+; ZIP-NEXT: add a3, a0, a3
+; ZIP-NEXT: vs2r.v v20, (a3)
; ZIP-NEXT: vs4r.v v16, (a2)
; ZIP-NEXT: vs8r.v v8, (a0)
; ZIP-NEXT: vl8re32.v v16, (a2)
@@ -13457,29 +13422,26 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; RV32-NEXT: vmv2r.v v26, v20
; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vmv2r.v v24, v16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 3
-; RV32-NEXT: sub a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
; RV32-NEXT: vmv2r.v v22, v12
-; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv2r.v v20, v8
; RV32-NEXT: vmv1r.v v1, v20
; RV32-NEXT: vmv1r.v v3, v22
; RV32-NEXT: vmv1r.v v5, v24
; RV32-NEXT: vmv1r.v v7, v26
-; RV32-NEXT: add a3, a0, a2
; RV32-NEXT: vmv1r.v v2, v10
-; RV32-NEXT: add a4, a1, a2
-; RV32-NEXT: slli a5, a2, 2
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a2, a1, 3
+; RV32-NEXT: sub a1, a2, a1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vmv1r.v v4, v14
-; RV32-NEXT: slli a6, a2, 4
-; RV32-NEXT: add a7, a4, a2
+; RV32-NEXT: add a3, a0, a2
+; RV32-NEXT: add a4, a1, a2
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: sub a5, a6, a5
+; RV32-NEXT: add a5, a4, a2
; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: add a6, a7, a2
+; RV32-NEXT: add a6, a5, a2
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vsseg7e64.v v1, (a0)
; RV32-NEXT: vmv1r.v v26, v19
@@ -13498,23 +13460,25 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; RV32-NEXT: vl1re64.v v8, (a0)
; RV32-NEXT: vl1re64.v v16, (a4)
; RV32-NEXT: vl1re64.v v9, (a3)
-; RV32-NEXT: vl1re64.v v17, (a7)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a3, 14
; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: vl1re64.v v17, (a5)
+; RV32-NEXT: slli a3, a2, 2
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1re64.v v12, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: vl1re64.v v13, (a6)
; RV32-NEXT: add a6, a6, a2
; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a3, a2, a3
; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: vl1re64.v v14, (a6)
; RV32-NEXT: vl1re64.v v15, (a1)
-; RV32-NEXT: add a5, a0, a5
-; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a3, a0, a3
+; RV32-NEXT: vs2r.v v20, (a3)
; RV32-NEXT: vs4r.v v16, (a2)
; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: vl8re64.v v16, (a2)
@@ -13539,29 +13503,26 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; RV64-NEXT: vmv2r.v v26, v20
; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vmv2r.v v24, v16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 3
-; RV64-NEXT: sub a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
; RV64-NEXT: vmv2r.v v22, v12
-; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv2r.v v20, v8
; RV64-NEXT: vmv1r.v v1, v20
; RV64-NEXT: vmv1r.v v3, v22
; RV64-NEXT: vmv1r.v v5, v24
; RV64-NEXT: vmv1r.v v7, v26
-; RV64-NEXT: add a3, a0, a2
; RV64-NEXT: vmv1r.v v2, v10
-; RV64-NEXT: add a4, a1, a2
-; RV64-NEXT: slli a5, a2, 2
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a2, a1, 3
+; RV64-NEXT: sub a1, a2, a1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vmv1r.v v4, v14
-; RV64-NEXT: slli a6, a2, 4
-; RV64-NEXT: add a7, a4, a2
+; RV64-NEXT: add a3, a0, a2
+; RV64-NEXT: add a4, a1, a2
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: sub a5, a6, a5
+; RV64-NEXT: add a5, a4, a2
; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: add a6, a7, a2
+; RV64-NEXT: add a6, a5, a2
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vsseg7e64.v v1, (a0)
; RV64-NEXT: vmv1r.v v26, v19
@@ -13580,23 +13541,25 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; RV64-NEXT: vl1re64.v v8, (a0)
; RV64-NEXT: vl1re64.v v16, (a4)
; RV64-NEXT: vl1re64.v v9, (a3)
-; RV64-NEXT: vl1re64.v v17, (a7)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a3, 14
; RV64-NEXT: mul a0, a0, a3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: vl1re64.v v17, (a5)
+; RV64-NEXT: slli a3, a2, 2
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1re64.v v12, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: vl1re64.v v13, (a6)
; RV64-NEXT: add a6, a6, a2
; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a3, a2, a3
; RV64-NEXT: add a2, a0, a2
; RV64-NEXT: vl1re64.v v14, (a6)
; RV64-NEXT: vl1re64.v v15, (a1)
-; RV64-NEXT: add a5, a0, a5
-; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a3, a0, a3
+; RV64-NEXT: vs2r.v v20, (a3)
; RV64-NEXT: vs4r.v v16, (a2)
; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: vl8re64.v v16, (a2)
@@ -13621,29 +13584,26 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZVBB-RV32-NEXT: vmv2r.v v26, v20
; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vmv2r.v v24, v16
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 3
-; ZVBB-RV32-NEXT: sub a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
; ZVBB-RV32-NEXT: vmv2r.v v22, v12
-; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv2r.v v20, v8
; ZVBB-RV32-NEXT: vmv1r.v v1, v20
; ZVBB-RV32-NEXT: vmv1r.v v3, v22
; ZVBB-RV32-NEXT: vmv1r.v v5, v24
; ZVBB-RV32-NEXT: vmv1r.v v7, v26
-; ZVBB-RV32-NEXT: add a3, a0, a2
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
-; ZVBB-RV32-NEXT: add a4, a1, a2
-; ZVBB-RV32-NEXT: slli a5, a2, 2
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: slli a2, a1, 3
+; ZVBB-RV32-NEXT: sub a1, a2, a1
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
-; ZVBB-RV32-NEXT: slli a6, a2, 4
-; ZVBB-RV32-NEXT: add a7, a4, a2
+; ZVBB-RV32-NEXT: add a3, a0, a2
+; ZVBB-RV32-NEXT: add a4, a1, a2
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: sub a5, a6, a5
+; ZVBB-RV32-NEXT: add a5, a4, a2
; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: add a6, a7, a2
+; ZVBB-RV32-NEXT: add a6, a5, a2
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vsseg7e64.v v1, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
@@ -13662,23 +13622,25 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZVBB-RV32-NEXT: vl1re64.v v8, (a0)
; ZVBB-RV32-NEXT: vl1re64.v v16, (a4)
; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV32-NEXT: vl1re64.v v17, (a7)
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a3, 14
; ZVBB-RV32-NEXT: mul a0, a0, a3
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: vl1re64.v v17, (a5)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1re64.v v12, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: vl1re64.v v13, (a6)
; ZVBB-RV32-NEXT: add a6, a6, a2
; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a3, a2, a3
; ZVBB-RV32-NEXT: add a2, a0, a2
; ZVBB-RV32-NEXT: vl1re64.v v14, (a6)
; ZVBB-RV32-NEXT: vl1re64.v v15, (a1)
-; ZVBB-RV32-NEXT: add a5, a0, a5
-; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a3, a0, a3
+; ZVBB-RV32-NEXT: vs2r.v v20, (a3)
; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
; ZVBB-RV32-NEXT: vl8re64.v v16, (a2)
@@ -13703,29 +13665,26 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZVBB-RV64-NEXT: vmv2r.v v26, v20
; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vmv2r.v v24, v16
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 3
-; ZVBB-RV64-NEXT: sub a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
; ZVBB-RV64-NEXT: vmv2r.v v22, v12
-; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv2r.v v20, v8
; ZVBB-RV64-NEXT: vmv1r.v v1, v20
; ZVBB-RV64-NEXT: vmv1r.v v3, v22
; ZVBB-RV64-NEXT: vmv1r.v v5, v24
; ZVBB-RV64-NEXT: vmv1r.v v7, v26
-; ZVBB-RV64-NEXT: add a3, a0, a2
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
-; ZVBB-RV64-NEXT: add a4, a1, a2
-; ZVBB-RV64-NEXT: slli a5, a2, 2
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: slli a2, a1, 3
+; ZVBB-RV64-NEXT: sub a1, a2, a1
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
-; ZVBB-RV64-NEXT: slli a6, a2, 4
-; ZVBB-RV64-NEXT: add a7, a4, a2
+; ZVBB-RV64-NEXT: add a3, a0, a2
+; ZVBB-RV64-NEXT: add a4, a1, a2
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: sub a5, a6, a5
+; ZVBB-RV64-NEXT: add a5, a4, a2
; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: add a6, a7, a2
+; ZVBB-RV64-NEXT: add a6, a5, a2
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vsseg7e64.v v1, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
@@ -13744,23 +13703,25 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZVBB-RV64-NEXT: vl1re64.v v8, (a0)
; ZVBB-RV64-NEXT: vl1re64.v v16, (a4)
; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV64-NEXT: vl1re64.v v17, (a7)
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a3, 14
; ZVBB-RV64-NEXT: mul a0, a0, a3
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: vl1re64.v v17, (a5)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1re64.v v12, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: vl1re64.v v13, (a6)
; ZVBB-RV64-NEXT: add a6, a6, a2
; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a3, a2, a3
; ZVBB-RV64-NEXT: add a2, a0, a2
; ZVBB-RV64-NEXT: vl1re64.v v14, (a6)
; ZVBB-RV64-NEXT: vl1re64.v v15, (a1)
-; ZVBB-RV64-NEXT: add a5, a0, a5
-; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a3, a0, a3
+; ZVBB-RV64-NEXT: vs2r.v v20, (a3)
; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
; ZVBB-RV64-NEXT: vl8re64.v v16, (a2)
@@ -13785,29 +13746,26 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZIP-NEXT: vmv2r.v v26, v20
; ZIP-NEXT: addi a0, sp, 64
; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv2r.v v20, v8
; ZIP-NEXT: vmv1r.v v1, v20
; ZIP-NEXT: vmv1r.v v3, v22
; ZIP-NEXT: vmv1r.v v5, v24
; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: add a3, a0, a2
; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: slli a5, a2, 2
+; ZIP-NEXT: csrr a1, vlenb
+; ZIP-NEXT: slli a2, a1, 3
+; ZIP-NEXT: sub a1, a2, a1
+; ZIP-NEXT: add a1, sp, a1
+; ZIP-NEXT: addi a1, a1, 64
+; ZIP-NEXT: csrr a2, vlenb
; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: slli a6, a2, 4
-; ZIP-NEXT: add a7, a4, a2
+; ZIP-NEXT: add a3, a0, a2
+; ZIP-NEXT: add a4, a1, a2
; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: sub a5, a6, a5
+; ZIP-NEXT: add a5, a4, a2
; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a7, a2
+; ZIP-NEXT: add a6, a5, a2
; ZIP-NEXT: vmv1r.v v24, v15
; ZIP-NEXT: vsseg7e64.v v1, (a0)
; ZIP-NEXT: vmv1r.v v26, v19
@@ -13826,23 +13784,25 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZIP-NEXT: vl1re64.v v8, (a0)
; ZIP-NEXT: vl1re64.v v16, (a4)
; ZIP-NEXT: vl1re64.v v9, (a3)
-; ZIP-NEXT: vl1re64.v v17, (a7)
; ZIP-NEXT: csrr a0, vlenb
; ZIP-NEXT: li a3, 14
; ZIP-NEXT: mul a0, a0, a3
; ZIP-NEXT: add a0, sp, a0
; ZIP-NEXT: addi a0, a0, 64
+; ZIP-NEXT: vl1re64.v v17, (a5)
+; ZIP-NEXT: slli a3, a2, 2
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1re64.v v12, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: vl1re64.v v13, (a6)
; ZIP-NEXT: add a6, a6, a2
; ZIP-NEXT: slli a2, a2, 3
+; ZIP-NEXT: add a3, a2, a3
; ZIP-NEXT: add a2, a0, a2
; ZIP-NEXT: vl1re64.v v14, (a6)
; ZIP-NEXT: vl1re64.v v15, (a1)
-; ZIP-NEXT: add a5, a0, a5
-; ZIP-NEXT: vs2r.v v20, (a5)
+; ZIP-NEXT: add a3, a0, a3
+; ZIP-NEXT: vs2r.v v20, (a3)
; ZIP-NEXT: vs4r.v v16, (a2)
; ZIP-NEXT: vs8r.v v8, (a0)
; ZIP-NEXT: vl8re64.v v16, (a2)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
index 861998a2ba51a..54b606082569c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
@@ -907,7 +907,8 @@ define half @vreduce_ord_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) {
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -943,8 +944,7 @@ define half @vreduce_ord_fadd_nxv12f16(<vscale x 12 x half> %v, half %s) {
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 1
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -982,7 +982,8 @@ define half @vreduce_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) {
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: lui a1, 1048568
; CHECK-NEXT: vmv.s.x v11, a1
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -1020,8 +1021,7 @@ define half @vreduce_fmax_nxv12f16(<vscale x 12 x half> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 1
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: li a1, -512
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vmv.s.x v12, a1
diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
index bc23388315de7..06bbe5209df35 100644
--- a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
@@ -169,10 +169,10 @@ define i1 @test_srem_even(i4 %X) nounwind {
; RV32M-NEXT: srli a2, a1, 31
; RV32M-NEXT: srli a1, a1, 4
; RV32M-NEXT: add a1, a1, a2
-; RV32M-NEXT: slli a2, a1, 3
-; RV32M-NEXT: slli a1, a1, 1
-; RV32M-NEXT: sub a1, a1, a2
-; RV32M-NEXT: add a0, a0, a1
+; RV32M-NEXT: slli a2, a1, 1
+; RV32M-NEXT: slli a1, a1, 2
+; RV32M-NEXT: add a1, a1, a2
+; RV32M-NEXT: sub a0, a0, a1
; RV32M-NEXT: andi a0, a0, 15
; RV32M-NEXT: addi a0, a0, -1
; RV32M-NEXT: seqz a0, a0
@@ -187,10 +187,10 @@ define i1 @test_srem_even(i4 %X) nounwind {
; RV64M-NEXT: srli a2, a1, 63
; RV64M-NEXT: srli a1, a1, 4
; RV64M-NEXT: add a1, a1, a2
-; RV64M-NEXT: slli a2, a1, 3
-; RV64M-NEXT: slli a1, a1, 1
-; RV64M-NEXT: sub a1, a1, a2
-; RV64M-NEXT: add a0, a0, a1
+; RV64M-NEXT: slli a2, a1, 1
+; RV64M-NEXT: slli a1, a1, 2
+; RV64M-NEXT: add a1, a1, a2
+; RV64M-NEXT: sub a0, a0, a1
; RV64M-NEXT: andi a0, a0, 15
; RV64M-NEXT: addi a0, a0, -1
; RV64M-NEXT: seqz a0, a0
@@ -205,10 +205,10 @@ define i1 @test_srem_even(i4 %X) nounwind {
; RV32MV-NEXT: srli a2, a1, 31
; RV32MV-NEXT: srli a1, a1, 4
; RV32MV-NEXT: add a1, a1, a2
-; RV32MV-NEXT: slli a2, a1, 3
-; RV32MV-NEXT: slli a1, a1, 1
-; RV32MV-NEXT: sub a1, a1, a2
-; RV32MV-NEXT: add a0, a0, a1
+; RV32MV-NEXT: slli a2, a1, 1
+; RV32MV-NEXT: slli a1, a1, 2
+; RV32MV-NEXT: add a1, a1, a2
+; RV32MV-NEXT: sub a0, a0, a1
; RV32MV-NEXT: andi a0, a0, 15
; RV32MV-NEXT: addi a0, a0, -1
; RV32MV-NEXT: seqz a0, a0
@@ -223,10 +223,10 @@ define i1 @test_srem_even(i4 %X) nounwind {
; RV64MV-NEXT: srli a2, a1, 63
; RV64MV-NEXT: srli a1, a1, 4
; RV64MV-NEXT: add a1, a1, a2
-; RV64MV-NEXT: slli a2, a1, 3
-; RV64MV-NEXT: slli a1, a1, 1
-; RV64MV-NEXT: sub a1, a1, a2
-; RV64MV-NEXT: add a0, a0, a1
+; RV64MV-NEXT: slli a2, a1, 1
+; RV64MV-NEXT: slli a1, a1, 2
+; RV64MV-NEXT: add a1, a1, a2
+; RV64MV-NEXT: sub a0, a0, a1
; RV64MV-NEXT: andi a0, a0, 15
; RV64MV-NEXT: addi a0, a0, -1
; RV64MV-NEXT: seqz a0, a0
@@ -823,16 +823,16 @@ define void @test_srem_vec(ptr %X) nounwind {
; RV64MV-NEXT: srai a4, a4, 1
; RV64MV-NEXT: mulh a6, a3, a6
; RV64MV-NEXT: add a4, a4, a7
-; RV64MV-NEXT: slli a7, a5, 3
-; RV64MV-NEXT: slli a5, a5, 1
-; RV64MV-NEXT: sub a5, a5, a7
+; RV64MV-NEXT: slli a7, a5, 1
+; RV64MV-NEXT: slli a5, a5, 2
+; RV64MV-NEXT: add a5, a5, a7
; RV64MV-NEXT: srli a7, a6, 63
; RV64MV-NEXT: srai a6, a6, 1
; RV64MV-NEXT: add a6, a6, a7
; RV64MV-NEXT: add a2, a2, a4
; RV64MV-NEXT: slli a4, a4, 3
; RV64MV-NEXT: sub a2, a2, a4
-; RV64MV-NEXT: add a1, a1, a5
+; RV64MV-NEXT: sub a1, a1, a5
; RV64MV-NEXT: li a4, -1
; RV64MV-NEXT: srli a4, a4, 31
; RV64MV-NEXT: vsext.vf8 v8, v10
diff --git a/llvm/test/CodeGen/RISCV/xqciac.ll b/llvm/test/CodeGen/RISCV/xqciac.ll
index 918468bdf03d3..92be4c977dd82 100644
--- a/llvm/test/CodeGen/RISCV/xqciac.ll
+++ b/llvm/test/CodeGen/RISCV/xqciac.ll
@@ -172,8 +172,8 @@ define dso_local i32 @pow2minuspow2(i32 %a, i32 %b) local_unnamed_addr #0 {
; RV32IM-LABEL: pow2minuspow2:
; RV32IM: # %bb.0: # %entry
; RV32IM-NEXT: slli a2, a1, 7
-; RV32IM-NEXT: slli a1, a1, 9
-; RV32IM-NEXT: sub a1, a1, a2
+; RV32IM-NEXT: slli a1, a1, 8
+; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: add a0, a1, a0
; RV32IM-NEXT: ret
;
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