[llvm] [SelectionDAG] Fix assertion failure on inline asm register type mismatch (PR #166615)

[Ahmed Nour via llvm-commits]

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@@ -0,0 +1,20 @@
+; RUN: not llc -mtriple=x86_64-unknown-linux-gnu < %s 2>&1 | FileCheck %s
+
+; Test that using MMX register constraint 'y' (64-bit) with a 256-bit vector
+; produces a proper error message instead of an assertion failure.
+
+; CHECK: error: couldn't allocate output register for constraint 'y'
+
+define <8 x i32> @test_mmx_constraint_size_mismatch() {
+entry:
+  %out = tail call <8 x i32> asm "something $0", "=y"()
+  ret <8 x i32> %out
+}
+
+; Also test with a different vector size
+define <4 x i32> @test_mmx_constraint_128bit() {
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ahmednoursphinx wrote:

Can you please elaborate more about the instances we need to test? Currently we have two test cases covering different vector size mismatches: a 256-bit vector (<8 x i32>) and a 128-bit vector (<4 x i32>), both using the MMX 'y' constraint which expects 64-bit operands.

https://github.com/llvm/llvm-project/pull/166615