[compiler-rt] [win/asan] GetInstructionSize: Support some more 2 or 3 byte instruction (PR #166691)

[Maosu Zhao via llvm-commits]

https://github.com/zhaomaosu created https://github.com/llvm/llvm-project/pull/166691

These instructions are seen after asan added new interceptor for wcscpy/wcsncpy/wcscat/wcsncat functions.

>From a927de945a21c5bfee2c421d708bf405d572b1be Mon Sep 17 00:00:00 2001
From: Maosu Zhao <maosu.zhao at intel.com>
Date: Thu, 6 Nov 2025 11:03:33 +0800
Subject: [PATCH] [win/asan] GetInstructionSize: Support some more 2 or 3 byte
 instructions

These instructions are seen after asan added new interceptor for
wcscpy/wcsncpy/wcscat/wcsncat functions.
---
 compiler-rt/lib/interception/interception_win.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index 246a22c56c31a..0c138d3db804c 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -646,6 +646,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
     case 0xC033:  // 33 C0 : xor eax, eax
     case 0xC933:  // 33 C9 : xor ecx, ecx
     case 0xD233:  // 33 D2 : xor edx, edx
+    case 0xff33:  // 33 FF : xor edi, edi
     case 0x9066:  // 66 90 : xchg %ax,%ax (Two-byte NOP)
     case 0xDB84:  // 84 DB : test bl,bl
     case 0xC084:  // 84 C0 : test al,al
@@ -764,6 +765,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
 
   switch (0x00FFFFFF & *(u32 *)address) {
     case 0x10b70f:    // 0f b7 10 : movzx edx, WORD PTR [rax]
+    case 0x02b70f:    // 0f b7 02 : movzx edx, WORD PTR [rdx]
     case 0xc00b4d:    // 4d 0b c0 : or r8, r8
     case 0xc03345:    // 45 33 c0 : xor r8d, r8d
     case 0xc08548:    // 48 85 c0 : test rax, rax
@@ -802,6 +804,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
     case 0xca2b48:    // 48 2b ca : sub rcx, rdx
     case 0xca3b48:    // 48 3b ca : cmp rcx, rdx
     case 0xd12b48:    // 48 2b d1 : sub rdx, rcx
+    case 0xc22b4c:    // 4c 2b c2 : sub r8, rdx
     case 0xd18b48:    // 48 8b d1 : mov rdx, rcx
     case 0xd18b4c:    // 4c 8b d1 : mov r10, rcx
     case 0xd28548:    // 48 85 d2 : test rdx, rdx
@@ -813,6 +816,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
     case 0xd9f748:    // 48 f7 d9 : neg rcx
     case 0xc03145:    // 45 31 c0 : xor r8d,r8d
     case 0xc93145:    // 45 31 c9 : xor r9d,r9d
+    case 0xd23345:    // 45 33 d2 : xor r10d,r10d
     case 0xdb3345:    // 45 33 db : xor r11d, r11d
     case 0xc08445:    // 45 84 c0 : test r8b,r8b
     case 0xd28445:    // 45 84 d2 : test r10b,r10b