[llvm] [SelectionDAG] Fix assertion failure on inline asm register type mismatch (PR #166615)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/lib/Target/X86/X86ISelLowering.cpp --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 9a6a76f73..ecdc3750e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -365,17 +365,17 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
 
     assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
     NumParts = NumRegs; // Silence a compiler warning.
-    
+
     // Check if the register type matches the part type
     if (RegisterVT != PartVT) {
-      diagnosePossiblyInvalidConstraint(
-          *DAG.getContext(), V,
-          "register type (" + EVT(RegisterVT).getEVTString() +
-              ") doesn't match operand type (" + EVT(PartVT).getEVTString() +
-              ")");
+      diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
+                                        "register type (" +
+                                            EVT(RegisterVT).getEVTString() +
+                                            ") doesn't match operand type (" +
+                                            EVT(PartVT).getEVTString() + ")");
       return DAG.getUNDEF(ValueVT);
     }
-    
+
     assert(RegisterVT.getSizeInBits() ==
            Parts[0].getSimpleValueType().getSizeInBits() &&
            "Part type sizes don't match!");
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index de099b286..244cc044b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -61836,7 +61836,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
     case 'y':   // MMX_REGS if MMX allowed.
       if (!Subtarget.hasMMX()) break;
       // MMX registers are 64-bit only
-      if (VT.getSizeInBits() != 64) break;
+      if (VT.getSizeInBits() != 64)
+        break;
       return std::make_pair(0U, &X86::VR64RegClass);
     case 'v':
     case 'x':   // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed

``````````

</details>


https://github.com/llvm/llvm-project/pull/166615