[llvm] ebeb36b - [PowerPC] Implement vsx rotate left word instr (#160754)

[via llvm-commits]

Author: Lei Huang
Date: 2025-11-05T13:22:00-05:00
New Revision: ebeb36b12e4649954a62dfbef7a5b04c5d8e52d7

URL: https://github.com/llvm/llvm-project/commit/ebeb36b12e4649954a62dfbef7a5b04c5d8e52d7
DIFF: https://github.com/llvm/llvm-project/commit/ebeb36b12e4649954a62dfbef7a5b04c5d8e52d7.diff

LOG: [PowerPC] Implement vsx rotate left word instr (#160754)

Implement `xvrlw`.

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCInstrFuture.td
    llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
    llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
    llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 0c2e44e18f463..dfbbba0116f25 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -420,6 +420,9 @@ let Predicates = [HasVSX, IsISAFuture] in {
       : VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
                       "vucmprlh $VRT, $VRA, $VRB", []>;
 
+  def XVRLW: XX3Form_XTAB6<60, 184, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                              "xvrlw $XT, $XA, $XB", []>;
+
   // AES Acceleration Instructions
   def XXAESENCP : XX3Form_XTABp5_M2<194, (outs vsrprc:$XTp),
                                     (ins vsrprc:$XAp, vsrprc:$XBp, u2imm:$M),

diff  --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index 2661ed5b04cc9..b27a50d93f5b9 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -250,6 +250,9 @@
 #CHECK: vucmprhh 1, 3, 6
 0x10,0x23,0x31,0x03
 
+#CHECK: xvrlw 34, 15, 16
+0xf0,0x4f,0x85,0xc1
+
 #CHECK: xxaes192encp 8, 10, 14
 0xf1,0x0b,0x76,0x10
 

diff  --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index 7fb8254ced0ac..72662d9736740 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -244,6 +244,9 @@
 #CHECK: vucmprhh 1, 3, 6
 0x03,0x31,0x23,0x10
 
+#CHECK: xvrlw 34, 15, 16
+0xc1,0x85,0x4f,0xf0
+
 #CHECK: xxaes192encp 8, 10, 14
 0x10,0x76,0x0b,0xf1
 

diff  --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index 40059c440b128..ab72649fc3404 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -355,6 +355,10 @@
 #CHECK-BE: vucmprhh 1, 3, 6               # encoding: [0x10,0x23,0x31,0x03]
 #CHECK-LE: vucmprhh 1, 3, 6               # encoding: [0x03,0x31,0x23,0x10]
 
+           xvrlw 34, 15, 16
+#CHECK-BE: xvrlw 34, 15, 16              # encoding: [0xf0,0x4f,0x85,0xc1]
+#CHECK-LE: xvrlw 34, 15, 16              # encoding: [0xc1,0x85,0x4f,0xf0]
+
            xxaes192encp 8, 10, 14
 #CHECK-BE: xxaes192encp 8, 10, 14         # encoding: [0xf1,0x0b,0x76,0x10]
 #CHECK-LE: xxaes192encp 8, 10, 14         # encoding: [0x10,0x76,0x0b,0xf1]