[llvm] [SPARC] Mark branches as being expensive in early Niagara CPUs (PR #166489)

[Sergei Barannikov via llvm-commits]

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@@ -0,0 +1,42 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O3 < %s -relocation-model=pic -mtriple=sparc -mcpu=v9 | FileCheck --check-prefix=SPARC %s
+; RUN: llc -O3 < %s -relocation-model=pic -mtriple=sparcv9 | FileCheck --check-prefix=SPARC64 %s
+
+;; Early Niagara processors should prefer conditional moves over branches
+;; even when it's predictable.
+
+define i32 @cdiv(i32 %cond, i32 %num) #0 {
+; SPARC-LABEL: cdiv:
+; SPARC:       ! %bb.0: ! %entry
+; SPARC-NEXT:    sethi 1398101, %o2
+; SPARC-NEXT:    or %o2, 342, %o2
+; SPARC-NEXT:    smul %o1, %o2, %o2
+; SPARC-NEXT:    rd %y, %o2
+; SPARC-NEXT:    srl %o2, 31, %o3
+; SPARC-NEXT:    add %o2, %o3, %o2
+; SPARC-NEXT:    cmp %o0, 0
+; SPARC-NEXT:    move %icc, %o2, %o1
+; SPARC-NEXT:    retl
+; SPARC-NEXT:    mov %o1, %o0
+;
+; SPARC64-LABEL: cdiv:
+; SPARC64:       ! %bb.0: ! %entry
+; SPARC64-NEXT:    sra %o1, 0, %o2
+; SPARC64-NEXT:    sethi 1398101, %o3
+; SPARC64-NEXT:    or %o3, 342, %o3
+; SPARC64-NEXT:    mulx %o2, %o3, %o2
+; SPARC64-NEXT:    srlx %o2, 63, %o3
+; SPARC64-NEXT:    srlx %o2, 32, %o2
+; SPARC64-NEXT:    add %o2, %o3, %o2
+; SPARC64-NEXT:    cmp %o0, 0
+; SPARC64-NEXT:    move %icc, %o2, %o1
+; SPARC64-NEXT:    retl
+; SPARC64-NEXT:    mov %o1, %o0
+entry:
+  %div = sdiv i32 %num, 3
+  %cmp = icmp eq i32 %cond, 0
+  %ret = select i1 %cmp, i32 %div, i32 %num
+  ret i32 %ret
+}
+
+attributes #0 = { nounwind "tune-cpu"="niagara" }
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s-barannikov wrote:

(nit) Can the two tests be combined into one with two RUN lines, one of which passing `-mattr=+no-predictor`?

https://github.com/llvm/llvm-project/pull/166489