[llvm] [AArch64][GlobalISel] SIMD fpcvt codegen for rounding nodes (PR #165546)

[via llvm-commits]

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@@ -6799,6 +6799,79 @@ defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, ftrunc, "F
 defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fp_to_sint_sat_gi, fround, "FCVTAS">;
 defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, fround, "FCVTAU">;
 
+// For global-isel we can use register classes to determine
+// which FCVT instruction to use.
+let Predicates = [HasFPRCVT] in {
+def : Pat<(i64 (any_lround f32:$Rn)),
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Lukacma wrote:

I am not exactly sure, I understand your comment. If you are asking whether we should add patterns here for other type of lround, like for example f16 to i64 type, I don't think that is necessary as GlobalISel doesn't support those types anyway yet for these nodes. That's why you see it fallback to SDAG.  

https://github.com/llvm/llvm-project/pull/165546