[llvm] [CodeGen] Add MO_LaneMask type and a new COPY_LANEMASK instruction (PR #151944)
Vikash Gupta via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 5 02:39:42 PST 2025
https://github.com/vg0204 updated https://github.com/llvm/llvm-project/pull/151944
>From 82eeb0d5020b92177b6c311f018399d68156a20d Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Mon, 4 Aug 2025 11:04:28 +0000
Subject: [PATCH 1/8] [CodeGen][NFC] Add laneBitmask as new MachineOperand Type
This patch adds a new MachineOperand type to represent the
laneBitmask as MO_LaneMask that can be used in the instructions
to represent the relevant information associated with the register
operands of the same such as liveness.
---
llvm/docs/MIRLangRef.rst | 1 +
.../llvm/CodeGen/MachineInstrBuilder.h | 5 ++++
llvm/include/llvm/CodeGen/MachineOperand.h | 17 ++++++++++-
llvm/lib/CodeGen/MIRParser/MILexer.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MILexer.h | 1 +
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 29 +++++++++++++++++++
llvm/lib/CodeGen/MIRPrinter.cpp | 3 +-
llvm/lib/CodeGen/MIRVRegNamerUtils.cpp | 1 +
llvm/lib/CodeGen/MachineOperand.cpp | 19 ++++++++++--
llvm/lib/CodeGen/MachineStableHash.cpp | 4 +++
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 1 +
llvm/unittests/CodeGen/MachineOperandTest.cpp | 17 +++++++++++
12 files changed, 94 insertions(+), 5 deletions(-)
diff --git a/llvm/docs/MIRLangRef.rst b/llvm/docs/MIRLangRef.rst
index f7647c898c1e6..9596cb1e023e0 100644
--- a/llvm/docs/MIRLangRef.rst
+++ b/llvm/docs/MIRLangRef.rst
@@ -819,6 +819,7 @@ For an int eq predicate ``ICMP_EQ``, the syntax is:
.. TODO: Describe the syntax of the metadata machine operands, and the
instructions debug location attribute.
.. TODO: Describe the syntax of the register live out machine operands.
+.. TODO: Describe the syntax of the lanemask machine operands.
.. TODO: Describe the syntax of the machine memory operands.
Comments
diff --git a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
index e705d7d99544c..a07fea19a4785 100644
--- a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -292,6 +292,11 @@ class MachineInstrBuilder {
return *this;
}
+ const MachineInstrBuilder &addLaneMask(LaneBitmask LaneMask) const {
+ MI->addOperand(*MF, MachineOperand::CreateLaneMask(LaneMask));
+ return *this;
+ }
+
const MachineInstrBuilder &addSym(MCSymbol *Sym,
unsigned char TargetFlags = 0) const {
MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags));
diff --git a/llvm/include/llvm/CodeGen/MachineOperand.h b/llvm/include/llvm/CodeGen/MachineOperand.h
index 9104e93ed9783..d85da5a4997f1 100644
--- a/llvm/include/llvm/CodeGen/MachineOperand.h
+++ b/llvm/include/llvm/CodeGen/MachineOperand.h
@@ -16,6 +16,7 @@
#include "llvm/ADT/DenseMapInfo.h"
#include "llvm/CodeGen/Register.h"
#include "llvm/IR/Intrinsics.h"
+#include "llvm/MC/LaneBitmask.h"
#include "llvm/Support/Compiler.h"
#include <cassert>
@@ -69,7 +70,8 @@ class MachineOperand {
MO_Predicate, ///< Generic predicate for ISel
MO_ShuffleMask, ///< Other IR Constant for ISel (shuffle masks)
MO_DbgInstrRef, ///< Integer indices referring to an instruction+operand
- MO_Last = MO_DbgInstrRef
+ MO_LaneMask, ///< Mask to represent active parts of registers
+ MO_Last = MO_LaneMask
};
private:
@@ -178,6 +180,7 @@ class MachineOperand {
Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
unsigned Pred; // For MO_Predicate
ArrayRef<int> ShuffleMask; // For MO_ShuffleMask
+ LaneBitmask LaneMask; // For MO_LaneMask
struct { // For MO_Register.
// Register number is in SmallContents.RegNo.
@@ -360,6 +363,7 @@ class MachineOperand {
bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
bool isPredicate() const { return OpKind == MO_Predicate; }
bool isShuffleMask() const { return OpKind == MO_ShuffleMask; }
+ bool isLaneMask() const { return OpKind == MO_LaneMask; }
//===--------------------------------------------------------------------===//
// Accessors for Register Operands
//===--------------------------------------------------------------------===//
@@ -624,6 +628,11 @@ class MachineOperand {
return Contents.ShuffleMask;
}
+ LaneBitmask getLaneMask() const {
+ assert(isLaneMask() && "Wrong MachineOperand accessor");
+ return Contents.LaneMask;
+ }
+
/// Return the offset from the symbol in this operand. This always returns 0
/// for ExternalSymbol operands.
int64_t getOffset() const {
@@ -992,6 +1001,12 @@ class MachineOperand {
return Op;
}
+ static MachineOperand CreateLaneMask(LaneBitmask LaneMask) {
+ MachineOperand Op(MachineOperand::MO_LaneMask);
+ Op.Contents.LaneMask = LaneMask;
+ return Op;
+ }
+
friend class MachineInstr;
friend class MachineRegisterInfo;
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
index 8b72c295416a2..bb714653d79dc 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
@@ -266,6 +266,7 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
.Case("constant-pool", MIToken::kw_constant_pool)
.Case("call-entry", MIToken::kw_call_entry)
.Case("custom", MIToken::kw_custom)
+ .Case("lanemask", MIToken::kw_lanemask)
.Case("liveout", MIToken::kw_liveout)
.Case("landing-pad", MIToken::kw_landing_pad)
.Case("inlineasm-br-indirect-target",
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h
index 0627f176b9e00..8c4fb0e63895a 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.h
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.h
@@ -122,6 +122,7 @@ struct MIToken {
kw_constant_pool,
kw_call_entry,
kw_custom,
+ kw_lanemask,
kw_liveout,
kw_landing_pad,
kw_inlineasm_br_indirect_target,
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 434a579c3be3f..76023d937ad9e 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -496,6 +496,7 @@ class MIParser {
bool parseTargetIndexOperand(MachineOperand &Dest);
bool parseDbgInstrRefOperand(MachineOperand &Dest);
bool parseCustomRegisterMaskOperand(MachineOperand &Dest);
+ bool parseLaneMaskOperand(MachineOperand &Dest);
bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
bool parseMachineOperand(const unsigned OpCode, const unsigned OpIdx,
MachineOperand &Dest,
@@ -2875,6 +2876,32 @@ bool MIParser::parseCustomRegisterMaskOperand(MachineOperand &Dest) {
return false;
}
+bool MIParser::parseLaneMaskOperand(MachineOperand &Dest) {
+ assert(Token.is(MIToken::kw_lanemask));
+
+ lex();
+ if (expectAndConsume(MIToken::lparen))
+ return error("expected syntax lanemask(...)");
+
+ LaneBitmask LaneMask = LaneBitmask::getAll();
+ // Parse lanemask.
+ if (Token.isNot(MIToken::IntegerLiteral) && Token.isNot(MIToken::HexLiteral))
+ return error("expected a lane mask");
+ static_assert(sizeof(LaneBitmask::Type) == sizeof(uint64_t),
+ "Use correct get-function for lane mask");
+ LaneBitmask::Type V;
+ if (getUint64(V))
+ return error("invalid lanemask value");
+ LaneMask = LaneBitmask(V);
+ lex();
+
+ if (expectAndConsume(MIToken::rparen))
+ return error("lanemask should be terminated by ')'.");
+
+ Dest = MachineOperand::CreateLaneMask(LaneMask);
+ return false;
+}
+
bool MIParser::parseLiveoutRegisterMaskOperand(MachineOperand &Dest) {
assert(Token.is(MIToken::kw_liveout));
uint32_t *Mask = MF.allocateRegMask();
@@ -2975,6 +3002,8 @@ bool MIParser::parseMachineOperand(const unsigned OpCode, const unsigned OpIdx,
return parseIntrinsicOperand(Dest);
case MIToken::kw_target_index:
return parseTargetIndexOperand(Dest);
+ case MIToken::kw_lanemask:
+ return parseLaneMaskOperand(Dest);
case MIToken::kw_liveout:
return parseLiveoutRegisterMaskOperand(Dest);
case MIToken::kw_floatpred:
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 1d54d72336860..78795f0427233 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -960,7 +960,8 @@ static void printMIOperand(raw_ostream &OS, MFPrintState &State,
case MachineOperand::MO_Predicate:
case MachineOperand::MO_BlockAddress:
case MachineOperand::MO_DbgInstrRef:
- case MachineOperand::MO_ShuffleMask: {
+ case MachineOperand::MO_ShuffleMask:
+ case MachineOperand::MO_LaneMask: {
unsigned TiedOperandIdx = 0;
if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
diff --git a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
index a22cc91b90542..0afb53e1d8f2c 100644
--- a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
+++ b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
@@ -106,6 +106,7 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
case MachineOperand::MO_ExternalSymbol:
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_BlockAddress:
+ case MachineOperand::MO_LaneMask:
case MachineOperand::MO_RegisterMask:
case MachineOperand::MO_RegisterLiveOut:
case MachineOperand::MO_Metadata:
diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index 8c6d2194433d0..ac1f201bc8b83 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -394,6 +394,8 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
return getPredicate() == Other.getPredicate();
case MachineOperand::MO_ShuffleMask:
return getShuffleMask() == Other.getShuffleMask();
+ case MachineOperand::MO_LaneMask:
+ return getLaneMask() == Other.getLaneMask();
}
llvm_unreachable("Invalid machine operand type");
}
@@ -460,6 +462,9 @@ hash_code llvm::hash_value(const MachineOperand &MO) {
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
case MachineOperand::MO_ShuffleMask:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
+ case MachineOperand::MO_LaneMask:
+ return hash_combine(MO.getType(), MO.getTargetFlags(),
+ MO.getLaneMask().getAsInteger());
}
llvm_unreachable("Invalid machine operand type");
}
@@ -1019,11 +1024,11 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
case MachineOperand::MO_Predicate: {
auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
- OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
- << Pred << ')';
+ OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred(" << Pred
+ << ')';
break;
}
- case MachineOperand::MO_ShuffleMask:
+ case MachineOperand::MO_ShuffleMask: {
OS << "shufflemask(";
ArrayRef<int> Mask = getShuffleMask();
StringRef Separator;
@@ -1038,6 +1043,14 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
OS << ')';
break;
}
+ case MachineOperand::MO_LaneMask: {
+ OS << "lanemask(";
+ LaneBitmask LaneMask = getLaneMask();
+ OS << "0x" << PrintLaneMask(LaneMask);
+ OS << ')';
+ break;
+ }
+ }
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
diff --git a/llvm/lib/CodeGen/MachineStableHash.cpp b/llvm/lib/CodeGen/MachineStableHash.cpp
index 6da708d51b95f..2f5f5aeccb2e4 100644
--- a/llvm/lib/CodeGen/MachineStableHash.cpp
+++ b/llvm/lib/CodeGen/MachineStableHash.cpp
@@ -165,6 +165,10 @@ stable_hash llvm::stableHashValue(const MachineOperand &MO) {
return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
stable_hash_name(SymbolName));
}
+ case MachineOperand::MO_LaneMask: {
+ return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
+ MO.getLaneMask().getAsInteger());
+ }
case MachineOperand::MO_CFIIndex:
return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
MO.getCFIIndex());
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index fffb63738166d..d69c09fcb39db 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -932,6 +932,7 @@ static bool IsAnAddressOperand(const MachineOperand &MO) {
return true;
case MachineOperand::MO_RegisterMask:
case MachineOperand::MO_RegisterLiveOut:
+ case MachineOperand::MO_LaneMask:
return false;
case MachineOperand::MO_Metadata:
case MachineOperand::MO_MCSymbol:
diff --git a/llvm/unittests/CodeGen/MachineOperandTest.cpp b/llvm/unittests/CodeGen/MachineOperandTest.cpp
index 0373c7a0f629b..60afdad846a13 100644
--- a/llvm/unittests/CodeGen/MachineOperandTest.cpp
+++ b/llvm/unittests/CodeGen/MachineOperandTest.cpp
@@ -288,6 +288,23 @@ TEST(MachineOperandTest, PrintGlobalAddress) {
}
}
+TEST(MachineOperandTest, PrintLaneMask) {
+ // Create a MachineOperand with a lanemask and print it.
+ LaneBitmask LaneMask = LaneBitmask(12);
+ MachineOperand MO = MachineOperand::CreateLaneMask(LaneMask);
+
+ // Checking some preconditions on the newly created
+ // MachineOperand.
+ ASSERT_TRUE(MO.isLaneMask());
+ ASSERT_TRUE(MO.getLaneMask() == LaneMask);
+
+ std::string str;
+ // Print a MachineOperand that is lanemask as in HEX representation.
+ raw_string_ostream OS(str);
+ MO.print(OS, /*TRI=*/nullptr);
+ ASSERT_TRUE(str == "lanemask(0x000000000000000C)");
+}
+
TEST(MachineOperandTest, PrintRegisterLiveOut) {
// Create a MachineOperand with a register live out list and print it.
uint32_t Mask = 0;
>From 027a64bf93d20f97db96045a15cdf7bd15c3c4ba Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Wed, 6 Aug 2025 11:15:38 +0000
Subject: [PATCH 2/8] [CodeGen]Added support for COPY_LANEMASK instruction
This new instruction takes laneMask as an operand with
respect to the input operand storing the essential information.
---
llvm/include/llvm/CodeGen/MachineInstr.h | 4 ++-
llvm/include/llvm/Support/TargetOpcodes.def | 5 ++++
llvm/include/llvm/Target/Target.td | 7 +++++
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 6 ++--
llvm/lib/CodeGen/MachineVerifier.cpp | 28 +++++++++++++++++++
.../parse-lanemask-operand-invalid-0.mir | 13 +++++++++
.../parse-lanemask-operand-invalid-1.mir | 13 +++++++++
.../parse-lanemask-operand-invalid-2.mir | 13 +++++++++
.../MIR/AMDGPU/parse-lanemask-operand.mir | 17 +++++++++++
.../verifier-copyLanemask0.mir | 24 ++++++++++++++++
.../verifier-copyLanemask1.mir | 28 +++++++++++++++++++
11 files changed, 154 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-0.mir
create mode 100644 llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-1.mir
create mode 100644 llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-2.mir
create mode 100644 llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir
create mode 100644 llvm/test/MachineVerifier/verifier-copyLanemask0.mir
create mode 100644 llvm/test/MachineVerifier/verifier-copyLanemask1.mir
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index 4fcb7f36e0238..c2bd6abe3c719 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -1429,7 +1429,8 @@ class MachineInstr
}
bool isCopy() const {
- return getOpcode() == TargetOpcode::COPY;
+ return (getOpcode() == TargetOpcode::COPY ||
+ getOpcode() == TargetOpcode::COPY_LANEMASK);
}
bool isFullCopy() const {
@@ -1465,6 +1466,7 @@ class MachineInstr
case TargetOpcode::PHI:
case TargetOpcode::G_PHI:
case TargetOpcode::COPY:
+ case TargetOpcode::COPY_LANEMASK:
case TargetOpcode::INSERT_SUBREG:
case TargetOpcode::SUBREG_TO_REG:
case TargetOpcode::REG_SEQUENCE:
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index e55314568d683..4647b3062ef5b 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -114,6 +114,11 @@ HANDLE_TARGET_OPCODE(REG_SEQUENCE)
/// used to copy between subregisters of virtual registers.
HANDLE_TARGET_OPCODE(COPY)
+/// COPY_LANEMASK - Target-independent register copy for active mask in
+/// register as represented by the lanemask. This instruction can only be
+/// used to copy between physical registers.
+HANDLE_TARGET_OPCODE(COPY_LANEMASK)
+
/// BUNDLE - This instruction represents an instruction bundle. Instructions
/// which immediately follow a BUNDLE instruction which are marked with
/// 'InsideBundle' flag are inside the bundle.
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 13175177edd3e..68643729dd4a1 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -1351,6 +1351,13 @@ def COPY : StandardPseudoInstruction {
let isAsCheapAsAMove = true;
let hasNoSchedulingInfo = false;
}
+def COPY_LANEMASK : StandardPseudoInstruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src, unknown:$lanemask);
+ let AsmString = "";
+ let hasSideEffects = false;
+ let isAsCheapAsAMove = true;
+}
def BUNDLE : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 76023d937ad9e..c5cd09b78f0d4 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -2881,14 +2881,14 @@ bool MIParser::parseLaneMaskOperand(MachineOperand &Dest) {
lex();
if (expectAndConsume(MIToken::lparen))
- return error("expected syntax lanemask(...)");
+ return error("lanemask should begin with '('.");
LaneBitmask LaneMask = LaneBitmask::getAll();
// Parse lanemask.
if (Token.isNot(MIToken::IntegerLiteral) && Token.isNot(MIToken::HexLiteral))
- return error("expected a lane mask");
+ return error("expected a valid lane mask value.");
static_assert(sizeof(LaneBitmask::Type) == sizeof(uint64_t),
- "Use correct get-function for lane mask");
+ "Use correct get-function for lane mask.");
LaneBitmask::Type V;
if (getUint64(V))
return error("invalid lanemask value");
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index fdf10480b6e05..b9a45b9e567c6 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2428,6 +2428,34 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
}
break;
}
+ case TargetOpcode::COPY_LANEMASK: {
+ const MachineOperand &DstOp = MI->getOperand(0);
+ const MachineOperand &SrcOp = MI->getOperand(1);
+ const MachineOperand &LaneMaskOp = MI->getOperand(2);
+ const Register SrcReg = SrcOp.getReg();
+ const Register DstReg = DstOp.getReg();
+ const LaneBitmask LaneMask = LaneMaskOp.getLaneMask();
+
+ if (!SrcReg.isPhysical() || !DstReg.isPhysical()) {
+ if (!SrcReg.isPhysical()) {
+ report("Copy with lanemask Instruction uses virtual register", &SrcOp,
+ 1);
+ }
+ if (!DstReg.isPhysical()) {
+ report("Copy with lanemask Instruction uses virtual register", &DstOp,
+ 0);
+ }
+ break;
+ }
+
+ if (LaneMask.none())
+ report("Lanemask takes up the zero value", MI);
+
+ if (LaneMask.all())
+ report("Copy Instruction can be used instead of copy with lanemask", MI);
+
+ break;
+ }
case TargetOpcode::STATEPOINT: {
StatepointOpers SO(MI);
if (!MI->getOperand(SO.getIDPos()).isImm() ||
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-0.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-0.mir
new file mode 100644
index 0000000000000..5bb397e8bcd08
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-0.mir
@@ -0,0 +1,13 @@
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+
+---
+name: test_missing_rparen
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK: [[@LINE+1]]:47: lanemask should be terminated by ')'.
+ $vgpr1 = COPY_LANEMASK $vgpr0, lanemask(16
+ S_ENDPGM 0
+...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-1.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-1.mir
new file mode 100644
index 0000000000000..bb4ca36e29511
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-1.mir
@@ -0,0 +1,13 @@
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+
+---
+name: test_missing_lparen
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK: [[@LINE+1]]:45: lanemask should begin with '('.
+ $vgpr1 = COPY_LANEMASK $vgpr0, lanemask 14)
+ S_ENDPGM 0
+...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-2.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-2.mir
new file mode 100644
index 0000000000000..fe520056f475c
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-2.mir
@@ -0,0 +1,13 @@
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+
+---
+name: test_wrong_lanemask_type
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK: [[@LINE+1]]:45: expected a valid lane mask value.
+ $vgpr1 = COPY_LANEMASK $vgpr0, lanemask(undef)
+ S_ENDPGM 0
+...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir
new file mode 100644
index 0000000000000..92c58826a5031
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir
@@ -0,0 +1,17 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
+
+# This test checks for the correctness of the MIR parser for lanemask
+
+# CHECK-LABEL: name: test_lanemask_operand
+# CHECK: COPY_LANEMASK $vgpr0, lanemask(0x0000000000000020)
+---
+name: test_lanemask_operand
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ $vgpr1 = COPY_LANEMASK $vgpr0, lanemask(32)
+ S_ENDPGM 0
+...
+
diff --git a/llvm/test/MachineVerifier/verifier-copyLanemask0.mir b/llvm/test/MachineVerifier/verifier-copyLanemask0.mir
new file mode 100644
index 0000000000000..88d368c98ba32
--- /dev/null
+++ b/llvm/test/MachineVerifier/verifier-copyLanemask0.mir
@@ -0,0 +1,24 @@
+# RUN: not --crash llc -o - -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: amdgpu-registered-target
+
+# CHECK: *** Bad machine code: Lanemask takes up the zero value ***
+# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
+# CHECK-NEXT: - basic block: %bb.0
+# CHECK-NEXT: - instruction: $vgpr2 = COPY_LANEMASK $vgpr0, lanemask(0x0000000000000000)
+
+# CHECK: *** Bad machine code: Copy Instruction can be used instead of copy with lanemask ***
+# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
+# CHECK-NEXT: - basic block: %bb.0
+# CHECK-NEXT: - instruction: $vgpr3 = COPY_LANEMASK $vgpr1, lanemask(0xFFFFFFFFFFFFFFFF)
+
+---
+name: test_copy_lanemask_instruction_0
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ $vgpr2 = COPY_LANEMASK $vgpr0, lanemask(0)
+ $vgpr3 = COPY_LANEMASK $vgpr1, lanemask(0xFFFFFFFFFFFFFFFF)
+ S_ENDPGM 0
+...
diff --git a/llvm/test/MachineVerifier/verifier-copyLanemask1.mir b/llvm/test/MachineVerifier/verifier-copyLanemask1.mir
new file mode 100644
index 0000000000000..b4386dcae7760
--- /dev/null
+++ b/llvm/test/MachineVerifier/verifier-copyLanemask1.mir
@@ -0,0 +1,28 @@
+# RUN: not --crash llc -o - -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: amdgpu-registered-target
+
+# CHECK: *** Bad machine code: Copy with lanemask Instruction uses virtual register ***
+# CHECK-NEXT: - function: test_copy_lanemask_instruction_1
+# CHECK-NEXT: - basic block: %bb.0
+# CHECK-NEXT: - instruction: $vgpr2 = COPY_LANEMASK %0:vgpr_32, lanemask(0x0000000000000018)
+# CHECK-NEXT: - operand 1: %0:vgpr_32
+
+# CHECK: *** Bad machine code: Copy with lanemask Instruction uses virtual register ***
+# CHECK-NEXT: - function: test_copy_lanemask_instruction_1
+# CHECK-NEXT: - basic block: %bb.0
+# CHECK-NEXT: - instruction: %1:vgpr_32 = COPY_LANEMASK $vgpr1, lanemask(0x00000000000000FF)
+# CHECK-NEXT: - operand 0: %1:vgpr_32
+
+---
+name: test_copy_lanemask_instruction_1
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ %0:vgpr_32 = COPY $vgpr0
+ $vgpr2 = COPY_LANEMASK %0, lanemask(24)
+ %1:vgpr_32 = COPY_LANEMASK $vgpr1, lanemask(0x000000000000FF)
+ S_ENDPGM 0
+...
+
>From 0738d354a923888fbf134517787899c1c45d67f2 Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Wed, 6 Aug 2025 11:54:12 +0000
Subject: [PATCH 3/8] Updated the existing LIT tests to accomodate this patch.
---
llvm/include/llvm/CodeGen/MIR2Vec.h | 2 +-
llvm/include/llvm/CodeGen/MachineOperand.h | 4 +-
.../GlobalISel/legalizer-info-validation.mir | 6 +-
.../Inputs/reference_x86_vocab_print.txt | 2 +
.../reference_x86_vocab_wo=0.5_print.txt | 2 +
.../GlobalISel/legalizer-info-validation.mir | 18 +-
.../match-table-cxx.td | 2 +-
llvm/test/TableGen/get-named-operand-idx.td | 3 +-
.../llvm-ir2vec/output/reference_triplets.txt | 56 +-
.../output/reference_x86_entities.txt | 13930 ++++++++--------
10 files changed, 7016 insertions(+), 7009 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MIR2Vec.h b/llvm/include/llvm/CodeGen/MIR2Vec.h
index 18b12901c1862..9035c10d2ac25 100644
--- a/llvm/include/llvm/CodeGen/MIR2Vec.h
+++ b/llvm/include/llvm/CodeGen/MIR2Vec.h
@@ -139,7 +139,7 @@ class MIRVocabulary {
"FrameIndex", "ConstantPoolIndex", "TargetIndex", "JumpTableIndex",
"ExternalSymbol", "GlobalAddress", "BlockAddress", "RegisterMask",
"RegisterLiveOut", "Metadata", "MCSymbol", "CFIIndex",
- "IntrinsicID", "Predicate", "ShuffleMask"};
+ "IntrinsicID", "Predicate", "ShuffleMask", "LaneMask"};
static_assert(std::size(CommonOperandNames) == MachineOperand::MO_Last - 1 &&
"Common operand names size changed, update accordingly");
diff --git a/llvm/include/llvm/CodeGen/MachineOperand.h b/llvm/include/llvm/CodeGen/MachineOperand.h
index d85da5a4997f1..dd8928813c8e1 100644
--- a/llvm/include/llvm/CodeGen/MachineOperand.h
+++ b/llvm/include/llvm/CodeGen/MachineOperand.h
@@ -69,8 +69,8 @@ class MachineOperand {
MO_IntrinsicID, ///< Intrinsic ID for ISel
MO_Predicate, ///< Generic predicate for ISel
MO_ShuffleMask, ///< Other IR Constant for ISel (shuffle masks)
- MO_DbgInstrRef, ///< Integer indices referring to an instruction+operand
- MO_LaneMask, ///< Mask to represent active parts of registers
+ MO_DbgInstrRef, ///< Integer indices referring to an instruction+operand
+ MO_LaneMask, ///< Mask to represent active parts of registers
MO_Last = MO_LaneMask
};
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 896603d6eb20d..8eb522e038328 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -70,12 +70,12 @@
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
#
-# DEBUG-NEXT: G_ABDS (opcode [[G_ABDS:[0-9]+]]): 1 type index, 0 imm indices
+# DEBUG-NEXT: G_ABDS (opcode 66): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
-# DEBUG-NEXT: G_ABDU (opcode [[G_ABDU:[0-9]+]]): 1 type index, 0 imm indices
-# DEBUG-NEXT: .. opcode [[G_ABDU]] is aliased to [[G_ABDS]]
+# DEBUG-NEXT: G_ABDU (opcode 67): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
index 000c67efb1de7..876904bd2839e 100644
--- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
+++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
@@ -186,6 +186,7 @@ Key: CONVERGENCECTRL_ENTRY: [ 0.00 0.00 ]
Key: CONVERGENCECTRL_GLUE: [ 0.00 0.00 ]
Key: CONVERGENCECTRL_LOOP: [ 0.00 0.00 ]
Key: COPY: [ 0.00 0.00 ]
+Key: COPY_LANEMASK: [ 0.00 0.00 ]
Key: COPY_TO_REGCLASS: [ 0.00 0.00 ]
Key: CPUID: [ 0.00 0.00 ]
Key: CQO: [ 0.00 0.00 ]
@@ -6879,6 +6880,7 @@ Key: CFIIndex: [ 0.00 0.00 ]
Key: IntrinsicID: [ 0.00 0.00 ]
Key: Predicate: [ 0.00 0.00 ]
Key: ShuffleMask: [ 0.00 0.00 ]
+Key: LaneMask: [ 0.00 0.00 ]
Key: PhyReg_GR8: [ 0.00 0.00 ]
Key: PhyReg_GRH8: [ 0.00 0.00 ]
Key: PhyReg_GR8_NOREX2: [ 0.00 0.00 ]
diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
index bb72886f73bfd..ba00cad8be84b 100644
--- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
+++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
@@ -186,6 +186,7 @@ Key: CONVERGENCECTRL_ENTRY: [ 0.00 0.00 ]
Key: CONVERGENCECTRL_GLUE: [ 0.00 0.00 ]
Key: CONVERGENCECTRL_LOOP: [ 0.00 0.00 ]
Key: COPY: [ 0.00 0.00 ]
+Key: COPY_LANEMASK: [ 0.00 0.00 ]
Key: COPY_TO_REGCLASS: [ 0.00 0.00 ]
Key: CPUID: [ 0.00 0.00 ]
Key: CQO: [ 0.00 0.00 ]
@@ -6879,6 +6880,7 @@ Key: CFIIndex: [ 0.00 0.00 ]
Key: IntrinsicID: [ 0.00 0.00 ]
Key: Predicate: [ 0.00 0.00 ]
Key: ShuffleMask: [ 0.00 0.00 ]
+Key: LaneMask: [ 0.00 0.00 ]
Key: PhyReg_GR8: [ 0.00 0.00 ]
Key: PhyReg_GRH8: [ 0.00 0.00 ]
Key: PhyReg_GR8_NOREX2: [ 0.00 0.00 ]
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
index da7546e12e58b..1f79811473579 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
@@ -72,14 +72,14 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
-# DEBUG-NEXT: G_ABDS (opcode [[G_ABDS:[0-9]+]]): 1 type index, 0 imm indices
-# DEBUG-NEXT:.. type index coverage check SKIPPED: user-defined predicate detected
-# DEBUG-NEXT:.. imm index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: G_ABDS (opcode 66): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
-# DEBUG-NEXT:G_ABDU (opcode [[G_ABDU:[0-9]+]]): 1 type index, 0 imm indices
-# DEBUG-NEXT:.. opcode [[G_ABDU]] is aliased to [[G_ABDS]]
-# DEBUG-NEXT:.. type index coverage check SKIPPED: user-defined predicate detected
-# DEBUG-NEXT:.. imm index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: G_ABDU (opcode 67): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. opcode 67 is aliased to 66
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_IMPLICIT_DEF (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
@@ -611,11 +611,11 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_FMINIMUMNUM (opcode {{[0-9]+}}): 1 type index, 0 imm indices
-# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. opcode 221 is aliased to 184
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_FMAXIMUMNUM (opcode {{[0-9]+}}): 1 type index, 0 imm indices
-# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. opcode 222 is aliased to 184
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_GET_FPENV (opcode {{[0-9]+}}): 1 type index, 0 imm indices
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
index 18960b43ab97d..3170f2c06c00b 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
@@ -96,7 +96,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const {
// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = {
-// CHECK-NEXT: /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(99), GIMT_Encode2(211), /*)*//*default:*//*Label 5*/ GIMT_Encode4(524),
+// CHECK-NEXT: /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(100), GIMT_Encode2(212), /*)*//*default:*//*Label 5*/ GIMT_Encode4(524),
// CHECK-NEXT: /* 10 */ /*TargetOpcode::G_STORE*//*Label 0*/ GIMT_Encode4(458), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
// CHECK-NEXT: /* 182 */ /*TargetOpcode::G_SEXT*//*Label 1*/ GIMT_Encode4(476), GIMT_Encode4(0),
// CHECK-NEXT: /* 190 */ /*TargetOpcode::G_ZEXT*//*Label 2*/ GIMT_Encode4(488), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
diff --git a/llvm/test/TableGen/get-named-operand-idx.td b/llvm/test/TableGen/get-named-operand-idx.td
index e6f6331cd9c48..a10cdd9696a4e 100644
--- a/llvm/test/TableGen/get-named-operand-idx.td
+++ b/llvm/test/TableGen/get-named-operand-idx.td
@@ -89,7 +89,8 @@ def InstD : InstBase {
// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 2, 0,
+// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 2,
+// CHECK-NEXT: 0,
// CHECK-NEXT: };
// CHECK-NEXT: return InstructionIndex[Opcode];
// CHECK-NEXT: }
diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
index 141a56ad10903..fee1f68c48a1a 100644
--- a/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
+++ b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
@@ -1,33 +1,33 @@
MAX_RELATION=4
-187 7051 1
-187 6948 2
+187 7053 1
+187 6950 2
187 187 0
-187 7051 1
-187 6949 2
+187 7053 1
+187 6951 2
187 10 0
-10 7051 1
-10 7051 2
-10 7051 3
-10 6941 4
+10 7053 1
+10 7053 2
+10 7053 3
+10 6943 4
10 187 0
-187 6932 1
-187 7051 2
-187 1543 0
-1543 6862 1
-1543 6932 2
-187 7051 1
-187 6948 2
+187 6934 1
+187 7053 2
+187 1544 0
+1544 6863 1
+1544 6934 2
+187 7053 1
+187 6950 2
187 187 0
-187 7051 1
-187 6949 2
-187 601 0
-601 7051 1
-601 7051 2
-601 7051 3
-601 6941 4
-601 187 0
-187 6932 1
-187 7051 2
-187 1543 0
-1543 6862 1
-1543 6932 2
+187 7053 1
+187 6951 2
+187 602 0
+602 7053 1
+602 7053 2
+602 7053 3
+602 6943 4
+602 187 0
+187 6934 1
+187 7053 2
+187 1544 0
+1544 6863 1
+1544 6934 2
diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
index dbbbbc746a769..fbfe1195a0fab 100644
--- a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
+++ b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
@@ -1,4 +1,4 @@
-7151
+7153
AAA 0
AAD 1
AADD 2
@@ -187,6966 +187,6968 @@ CONVERGENCECTRL_ENTRY 184
CONVERGENCECTRL_GLUE 185
CONVERGENCECTRL_LOOP 186
COPY 187
-COPY_TO_REGCLASS 188
-CPUID 189
-CQO 190
-CRC 191
-CS_PREFIX 192
-CTEST 193
-CVTDQ 194
-CVTPD 195
-CVTPS 196
-CVTSD 197
-CVTSI 198
-CVTSS 199
-CVTTPD 200
-CVTTPS 201
-CVTTSD 202
-CVTTSS 203
-CWD 204
-CWDE 205
-DAA 206
-DAS 207
-DATA 208
-DBG_INSTR_REF 209
-DBG_LABEL 210
-DBG_PHI 211
-DBG_VALUE 212
-DBG_VALUE_LIST 213
-DEC 214
-DIV 215
-DIVPDrm 216
-DIVPDrr 217
-DIVPSrm 218
-DIVPSrr 219
-DIVR_F 220
-DIVR_FI 221
-DIVR_FPrST 222
-DIVR_FST 223
-DIVR_Fp 224
-DIVR_FpI 225
-DIVR_FrST 226
-DIVSDrm 227
-DIVSDrm_Int 228
-DIVSDrr 229
-DIVSDrr_Int 230
-DIVSSrm 231
-DIVSSrm_Int 232
-DIVSSrr 233
-DIVSSrr_Int 234
-DIV_F 235
-DIV_FI 236
-DIV_FPrST 237
-DIV_FST 238
-DIV_Fp 239
-DIV_FpI 240
-DIV_FrST 241
-DPPDrmi 242
-DPPDrri 243
-DPPSrmi 244
-DPPSrri 245
-DS_PREFIX 246
-DYN_ALLOCA 247
-EH_LABEL 248
-EH_RETURN 249
-EH_SjLj_LongJmp 250
-EH_SjLj_SetJmp 251
-EH_SjLj_Setup 252
-ENCLS 253
-ENCLU 254
-ENCLV 255
-ENCODEKEY 256
-ENDBR 257
-ENQCMD 258
-ENQCMDS 259
-ENTER 260
-ERETS 261
-ERETU 262
-ES_PREFIX 263
-EXTRACTPSmri 264
-EXTRACTPSrri 265
-EXTRACT_SUBREG 266
-EXTRQ 267
-EXTRQI 268
-F 269
-FAKE_USE 270
-FARCALL 271
-FARJMP 272
-FAULTING_OP 273
-FBLDm 274
-FBSTPm 275
-FCOM 276
-FCOMP 277
-FCOMPP 278
-FCOS 279
-FDECSTP 280
-FEMMS 281
-FENTRY_CALL 282
-FFREE 283
-FFREEP 284
-FICOM 285
-FICOMP 286
-FINCSTP 287
-FLDCW 288
-FLDENVm 289
-FLDL 290
-FLDLG 291
-FLDLN 292
-FLDPI 293
-FNCLEX 294
-FNINIT 295
-FNOP 296
-FNSTCW 297
-FNSTSW 298
-FNSTSWm 299
-FP 300
-FPATAN 301
-FPREM 302
-FPTAN 303
-FRNDINT 304
-FRSTORm 305
-FSAVEm 306
-FSCALE 307
-FSIN 308
-FSINCOS 309
-FSTENVm 310
-FS_PREFIX 311
-FXRSTOR 312
-FXSAVE 313
-FXTRACT 314
-FYL 315
-FsFLD 316
-GC_LABEL 317
-GETSEC 318
-GF 319
-GS_PREFIX 320
-G_ABDS 321
-G_ABDU 322
-G_ABS 323
-G_ADD 324
-G_ADDRSPACE_CAST 325
-G_AND 326
-G_ANYEXT 327
-G_ASHR 328
-G_ASSERT_ALIGN 329
-G_ASSERT_SEXT 330
-G_ASSERT_ZEXT 331
-G_ATOMICRMW_ADD 332
-G_ATOMICRMW_AND 333
-G_ATOMICRMW_FADD 334
-G_ATOMICRMW_FMAX 335
-G_ATOMICRMW_FMAXIMUM 336
-G_ATOMICRMW_FMIN 337
-G_ATOMICRMW_FMINIMUM 338
-G_ATOMICRMW_FSUB 339
-G_ATOMICRMW_MAX 340
-G_ATOMICRMW_MIN 341
-G_ATOMICRMW_NAND 342
-G_ATOMICRMW_OR 343
-G_ATOMICRMW_SUB 344
-G_ATOMICRMW_UDEC_WRAP 345
-G_ATOMICRMW_UINC_WRAP 346
-G_ATOMICRMW_UMAX 347
-G_ATOMICRMW_UMIN 348
-G_ATOMICRMW_USUB_COND 349
-G_ATOMICRMW_USUB_SAT 350
-G_ATOMICRMW_XCHG 351
-G_ATOMICRMW_XOR 352
-G_ATOMIC_CMPXCHG 353
-G_ATOMIC_CMPXCHG_WITH_SUCCESS 354
-G_BITCAST 355
-G_BITREVERSE 356
-G_BLOCK_ADDR 357
-G_BR 358
-G_BRCOND 359
-G_BRINDIRECT 360
-G_BRJT 361
-G_BSWAP 362
-G_BUILD_VECTOR 363
-G_BUILD_VECTOR_TRUNC 364
-G_BZERO 365
-G_CONCAT_VECTORS 366
-G_CONSTANT 367
-G_CONSTANT_FOLD_BARRIER 368
-G_CONSTANT_POOL 369
-G_CTLZ 370
-G_CTLZ_ZERO_UNDEF 371
-G_CTPOP 372
-G_CTTZ 373
-G_CTTZ_ZERO_UNDEF 374
-G_DEBUGTRAP 375
-G_DYN_STACKALLOC 376
-G_EXTRACT 377
-G_EXTRACT_SUBVECTOR 378
-G_EXTRACT_VECTOR_ELT 379
-G_FABS 380
-G_FACOS 381
-G_FADD 382
-G_FASIN 383
-G_FATAN 384
-G_FCANONICALIZE 385
-G_FCEIL 386
-G_FCMP 387
-G_FCONSTANT 388
-G_FCOPYSIGN 389
-G_FCOS 390
-G_FCOSH 391
-G_FDIV 392
-G_FENCE 393
-G_FEXP 394
-G_FFLOOR 395
-G_FFREXP 396
-G_FILD 397
-G_FIST 398
-G_FLDCW 399
-G_FLDEXP 400
-G_FLOG 401
-G_FMA 402
-G_FMAD 403
-G_FMAXIMUM 404
-G_FMAXIMUMNUM 405
-G_FMAXNUM 406
-G_FMAXNUM_IEEE 407
-G_FMINIMUM 408
-G_FMINIMUMNUM 409
-G_FMINNUM 410
-G_FMINNUM_IEEE 411
-G_FMODF 412
-G_FMUL 413
-G_FNEARBYINT 414
-G_FNEG 415
-G_FNSTCW 416
-G_FPEXT 417
-G_FPOW 418
-G_FPOWI 419
-G_FPTOSI 420
-G_FPTOSI_SAT 421
-G_FPTOUI 422
-G_FPTOUI_SAT 423
-G_FPTRUNC 424
-G_FRAME_INDEX 425
-G_FREEZE 426
-G_FREM 427
-G_FRINT 428
-G_FSHL 429
-G_FSHR 430
-G_FSIN 431
-G_FSINCOS 432
-G_FSINH 433
-G_FSQRT 434
-G_FSUB 435
-G_FTAN 436
-G_FTANH 437
-G_GET_FPENV 438
-G_GET_FPMODE 439
-G_GET_ROUNDING 440
-G_GLOBAL_VALUE 441
-G_ICMP 442
-G_IMPLICIT_DEF 443
-G_INDEXED_LOAD 444
-G_INDEXED_SEXTLOAD 445
-G_INDEXED_STORE 446
-G_INDEXED_ZEXTLOAD 447
-G_INSERT 448
-G_INSERT_SUBVECTOR 449
-G_INSERT_VECTOR_ELT 450
-G_INTRINSIC 451
-G_INTRINSIC_CONVERGENT 452
-G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS 453
-G_INTRINSIC_FPTRUNC_ROUND 454
-G_INTRINSIC_LLRINT 455
-G_INTRINSIC_LRINT 456
-G_INTRINSIC_ROUND 457
-G_INTRINSIC_ROUNDEVEN 458
-G_INTRINSIC_TRUNC 459
-G_INTRINSIC_W_SIDE_EFFECTS 460
-G_INTTOPTR 461
-G_INVOKE_REGION_START 462
-G_IS_FPCLASS 463
-G_JUMP_TABLE 464
-G_LLROUND 465
-G_LOAD 466
-G_LROUND 467
-G_LSHR 468
-G_MEMCPY 469
-G_MEMCPY_INLINE 470
-G_MEMMOVE 471
-G_MEMSET 472
-G_MERGE_VALUES 473
-G_MUL 474
-G_OR 475
-G_PHI 476
-G_PREFETCH 477
-G_PTRAUTH_GLOBAL_VALUE 478
-G_PTRMASK 479
-G_PTRTOINT 480
-G_PTR_ADD 481
-G_READCYCLECOUNTER 482
-G_READSTEADYCOUNTER 483
-G_READ_REGISTER 484
-G_RESET_FPENV 485
-G_RESET_FPMODE 486
-G_ROTL 487
-G_ROTR 488
-G_SADDE 489
-G_SADDO 490
-G_SADDSAT 491
-G_SBFX 492
-G_SCMP 493
-G_SDIV 494
-G_SDIVFIX 495
-G_SDIVFIXSAT 496
-G_SDIVREM 497
-G_SELECT 498
-G_SET_FPENV 499
-G_SET_FPMODE 500
-G_SET_ROUNDING 501
-G_SEXT 502
-G_SEXTLOAD 503
-G_SEXT_INREG 504
-G_SHL 505
-G_SHUFFLE_VECTOR 506
-G_SITOFP 507
-G_SMAX 508
-G_SMIN 509
-G_SMULFIX 510
-G_SMULFIXSAT 511
-G_SMULH 512
-G_SMULO 513
-G_SPLAT_VECTOR 514
-G_SREM 515
-G_SSHLSAT 516
-G_SSUBE 517
-G_SSUBO 518
-G_SSUBSAT 519
-G_STACKRESTORE 520
-G_STACKSAVE 521
-G_STEP_VECTOR 522
-G_STORE 523
-G_STRICT_FADD 524
-G_STRICT_FDIV 525
-G_STRICT_FLDEXP 526
-G_STRICT_FMA 527
-G_STRICT_FMUL 528
-G_STRICT_FREM 529
-G_STRICT_FSQRT 530
-G_STRICT_FSUB 531
-G_SUB 532
-G_TRAP 533
-G_TRUNC 534
-G_TRUNC_SSAT_S 535
-G_TRUNC_SSAT_U 536
-G_TRUNC_USAT_U 537
-G_UADDE 538
-G_UADDO 539
-G_UADDSAT 540
-G_UBFX 541
-G_UBSANTRAP 542
-G_UCMP 543
-G_UDIV 544
-G_UDIVFIX 545
-G_UDIVFIXSAT 546
-G_UDIVREM 547
-G_UITOFP 548
-G_UMAX 549
-G_UMIN 550
-G_UMULFIX 551
-G_UMULFIXSAT 552
-G_UMULH 553
-G_UMULO 554
-G_UNMERGE_VALUES 555
-G_UREM 556
-G_USHLSAT 557
-G_USUBE 558
-G_USUBO 559
-G_USUBSAT 560
-G_VAARG 561
-G_VASTART 562
-G_VECREDUCE_ADD 563
-G_VECREDUCE_AND 564
-G_VECREDUCE_FADD 565
-G_VECREDUCE_FMAX 566
-G_VECREDUCE_FMAXIMUM 567
-G_VECREDUCE_FMIN 568
-G_VECREDUCE_FMINIMUM 569
-G_VECREDUCE_FMUL 570
-G_VECREDUCE_MUL 571
-G_VECREDUCE_OR 572
-G_VECREDUCE_SEQ_FADD 573
-G_VECREDUCE_SEQ_FMUL 574
-G_VECREDUCE_SMAX 575
-G_VECREDUCE_SMIN 576
-G_VECREDUCE_UMAX 577
-G_VECREDUCE_UMIN 578
-G_VECREDUCE_XOR 579
-G_VECTOR_COMPRESS 580
-G_VSCALE 581
-G_WRITE_REGISTER 582
-G_XOR 583
-G_ZEXT 584
-G_ZEXTLOAD 585
-HADDPDrm 586
-HADDPDrr 587
-HADDPSrm 588
-HADDPSrr 589
-HLT 590
-HRESET 591
-HSUBPDrm 592
-HSUBPDrr 593
-HSUBPSrm 594
-HSUBPSrr 595
-ICALL_BRANCH_FUNNEL 596
-IDIV 597
-ILD_F 598
-ILD_Fp 599
-IMPLICIT_DEF 600
-IMUL 601
-IMULZU 602
-IN 603
-INC 604
-INCSSPD 605
-INCSSPQ 606
-INDIRECT_THUNK_CALL 607
-INDIRECT_THUNK_TCRETURN 608
-INIT_UNDEF 609
-INLINEASM 610
-INLINEASM_BR 611
-INSB 612
-INSERTPSrmi 613
-INSERTPSrri 614
-INSERTQ 615
-INSERTQI 616
-INSERT_SUBREG 617
-INSL 618
-INSW 619
-INT 620
-INTO 621
-INVD 622
-INVEPT 623
-INVLPG 624
-INVLPGA 625
-INVLPGB 626
-INVPCID 627
-INVVPID 628
-IRET 629
-ISTT_FP 630
-ISTT_Fp 631
-IST_F 632
-IST_FP 633
-IST_Fp 634
-Int_eh_sjlj_setup_dispatch 635
-JCC 636
-JCXZ 637
-JECXZ 638
-JMP 639
-JMPABS 640
-JRCXZ 641
-JUMP_TABLE_DEBUG_INFO 642
-KADDBkk 643
-KADDDkk 644
-KADDQkk 645
-KADDWkk 646
-KANDBkk 647
-KANDDkk 648
-KANDNBkk 649
-KANDNDkk 650
-KANDNQkk 651
-KANDNWkk 652
-KANDQkk 653
-KANDWkk 654
-KCFI_CHECK 655
-KILL 656
-KMOVBkk 657
-KMOVBkk_EVEX 658
-KMOVBkm 659
-KMOVBkm_EVEX 660
-KMOVBkr 661
-KMOVBkr_EVEX 662
-KMOVBmk 663
-KMOVBmk_EVEX 664
-KMOVBrk 665
-KMOVBrk_EVEX 666
-KMOVDkk 667
-KMOVDkk_EVEX 668
-KMOVDkm 669
-KMOVDkm_EVEX 670
-KMOVDkr 671
-KMOVDkr_EVEX 672
-KMOVDmk 673
-KMOVDmk_EVEX 674
-KMOVDrk 675
-KMOVDrk_EVEX 676
-KMOVQkk 677
-KMOVQkk_EVEX 678
-KMOVQkm 679
-KMOVQkm_EVEX 680
-KMOVQkr 681
-KMOVQkr_EVEX 682
-KMOVQmk 683
-KMOVQmk_EVEX 684
-KMOVQrk 685
-KMOVQrk_EVEX 686
-KMOVWkk 687
-KMOVWkk_EVEX 688
-KMOVWkm 689
-KMOVWkm_EVEX 690
-KMOVWkr 691
-KMOVWkr_EVEX 692
-KMOVWmk 693
-KMOVWmk_EVEX 694
-KMOVWrk 695
-KMOVWrk_EVEX 696
-KNOTBkk 697
-KNOTDkk 698
-KNOTQkk 699
-KNOTWkk 700
-KORBkk 701
-KORDkk 702
-KORQkk 703
-KORTESTBkk 704
-KORTESTDkk 705
-KORTESTQkk 706
-KORTESTWkk 707
-KORWkk 708
-KSET 709
-KSHIFTLBki 710
-KSHIFTLDki 711
-KSHIFTLQki 712
-KSHIFTLWki 713
-KSHIFTRBki 714
-KSHIFTRDki 715
-KSHIFTRQki 716
-KSHIFTRWki 717
-KTESTBkk 718
-KTESTDkk 719
-KTESTQkk 720
-KTESTWkk 721
-KUNPCKBWkk 722
-KUNPCKDQkk 723
-KUNPCKWDkk 724
-KXNORBkk 725
-KXNORDkk 726
-KXNORQkk 727
-KXNORWkk 728
-KXORBkk 729
-KXORDkk 730
-KXORQkk 731
-KXORWkk 732
-LAHF 733
-LAR 734
-LCMPXCHG 735
-LDDQUrm 736
-LDMXCSR 737
-LDS 738
-LDTILECFG 739
-LDTILECFG_EVEX 740
-LD_F 741
-LD_Fp 742
-LD_Frr 743
-LEA 744
-LEAVE 745
-LES 746
-LFENCE 747
-LFS 748
-LGDT 749
-LGS 750
-LIDT 751
-LIFETIME_END 752
-LIFETIME_START 753
-LKGS 754
-LLDT 755
-LLWPCB 756
-LMSW 757
-LOADIWKEY 758
-LOAD_STACK_GUARD 759
-LOCAL_ESCAPE 760
-LOCK_ADD 761
-LOCK_AND 762
-LOCK_BTC 763
-LOCK_BTC_RM 764
-LOCK_BTR 765
-LOCK_BTR_RM 766
-LOCK_BTS 767
-LOCK_BTS_RM 768
-LOCK_DEC 769
-LOCK_INC 770
-LOCK_OR 771
-LOCK_PREFIX 772
-LOCK_SUB 773
-LOCK_XOR 774
-LODSB 775
-LODSL 776
-LODSQ 777
-LODSW 778
-LOOP 779
-LOOPE 780
-LOOPNE 781
-LRET 782
-LRETI 783
-LSL 784
-LSS 785
-LTRm 786
-LTRr 787
-LWPINS 788
-LWPVAL 789
-LXADD 790
-LZCNT 791
-MASKMOVDQU 792
-MASKPAIR 793
-MAXCPDrm 794
-MAXCPDrr 795
-MAXCPSrm 796
-MAXCPSrr 797
-MAXCSDrm 798
-MAXCSDrr 799
-MAXCSSrm 800
-MAXCSSrr 801
-MAXPDrm 802
-MAXPDrr 803
-MAXPSrm 804
-MAXPSrr 805
-MAXSDrm 806
-MAXSDrm_Int 807
-MAXSDrr 808
-MAXSDrr_Int 809
-MAXSSrm 810
-MAXSSrm_Int 811
-MAXSSrr 812
-MAXSSrr_Int 813
-MEMBARRIER 814
-MFENCE 815
-MINCPDrm 816
-MINCPDrr 817
-MINCPSrm 818
-MINCPSrr 819
-MINCSDrm 820
-MINCSDrr 821
-MINCSSrm 822
-MINCSSrr 823
-MINPDrm 824
-MINPDrr 825
-MINPSrm 826
-MINPSrr 827
-MINSDrm 828
-MINSDrm_Int 829
-MINSDrr 830
-MINSDrr_Int 831
-MINSSrm 832
-MINSSrm_Int 833
-MINSSrr 834
-MINSSrr_Int 835
-MMX_CVTPD 836
-MMX_CVTPI 837
-MMX_CVTPS 838
-MMX_CVTTPD 839
-MMX_CVTTPS 840
-MMX_EMMS 841
-MMX_MASKMOVQ 842
-MMX_MOVD 843
-MMX_MOVDQ 844
-MMX_MOVFR 845
-MMX_MOVNTQmr 846
-MMX_MOVQ 847
-MMX_PABSBrm 848
-MMX_PABSBrr 849
-MMX_PABSDrm 850
-MMX_PABSDrr 851
-MMX_PABSWrm 852
-MMX_PABSWrr 853
-MMX_PACKSSDWrm 854
-MMX_PACKSSDWrr 855
-MMX_PACKSSWBrm 856
-MMX_PACKSSWBrr 857
-MMX_PACKUSWBrm 858
-MMX_PACKUSWBrr 859
-MMX_PADDBrm 860
-MMX_PADDBrr 861
-MMX_PADDDrm 862
-MMX_PADDDrr 863
-MMX_PADDQrm 864
-MMX_PADDQrr 865
-MMX_PADDSBrm 866
-MMX_PADDSBrr 867
-MMX_PADDSWrm 868
-MMX_PADDSWrr 869
-MMX_PADDUSBrm 870
-MMX_PADDUSBrr 871
-MMX_PADDUSWrm 872
-MMX_PADDUSWrr 873
-MMX_PADDWrm 874
-MMX_PADDWrr 875
-MMX_PALIGNRrmi 876
-MMX_PALIGNRrri 877
-MMX_PANDNrm 878
-MMX_PANDNrr 879
-MMX_PANDrm 880
-MMX_PANDrr 881
-MMX_PAVGBrm 882
-MMX_PAVGBrr 883
-MMX_PAVGWrm 884
-MMX_PAVGWrr 885
-MMX_PCMPEQBrm 886
-MMX_PCMPEQBrr 887
-MMX_PCMPEQDrm 888
-MMX_PCMPEQDrr 889
-MMX_PCMPEQWrm 890
-MMX_PCMPEQWrr 891
-MMX_PCMPGTBrm 892
-MMX_PCMPGTBrr 893
-MMX_PCMPGTDrm 894
-MMX_PCMPGTDrr 895
-MMX_PCMPGTWrm 896
-MMX_PCMPGTWrr 897
-MMX_PEXTRWrri 898
-MMX_PHADDDrm 899
-MMX_PHADDDrr 900
-MMX_PHADDSWrm 901
-MMX_PHADDSWrr 902
-MMX_PHADDWrm 903
-MMX_PHADDWrr 904
-MMX_PHSUBDrm 905
-MMX_PHSUBDrr 906
-MMX_PHSUBSWrm 907
-MMX_PHSUBSWrr 908
-MMX_PHSUBWrm 909
-MMX_PHSUBWrr 910
-MMX_PINSRWrmi 911
-MMX_PINSRWrri 912
-MMX_PMADDUBSWrm 913
-MMX_PMADDUBSWrr 914
-MMX_PMADDWDrm 915
-MMX_PMADDWDrr 916
-MMX_PMAXSWrm 917
-MMX_PMAXSWrr 918
-MMX_PMAXUBrm 919
-MMX_PMAXUBrr 920
-MMX_PMINSWrm 921
-MMX_PMINSWrr 922
-MMX_PMINUBrm 923
-MMX_PMINUBrr 924
-MMX_PMOVMSKBrr 925
-MMX_PMULHRSWrm 926
-MMX_PMULHRSWrr 927
-MMX_PMULHUWrm 928
-MMX_PMULHUWrr 929
-MMX_PMULHWrm 930
-MMX_PMULHWrr 931
-MMX_PMULLWrm 932
-MMX_PMULLWrr 933
-MMX_PMULUDQrm 934
-MMX_PMULUDQrr 935
-MMX_PORrm 936
-MMX_PORrr 937
-MMX_PSADBWrm 938
-MMX_PSADBWrr 939
-MMX_PSHUFBrm 940
-MMX_PSHUFBrr 941
-MMX_PSHUFWmi 942
-MMX_PSHUFWri 943
-MMX_PSIGNBrm 944
-MMX_PSIGNBrr 945
-MMX_PSIGNDrm 946
-MMX_PSIGNDrr 947
-MMX_PSIGNWrm 948
-MMX_PSIGNWrr 949
-MMX_PSLLDri 950
-MMX_PSLLDrm 951
-MMX_PSLLDrr 952
-MMX_PSLLQri 953
-MMX_PSLLQrm 954
-MMX_PSLLQrr 955
-MMX_PSLLWri 956
-MMX_PSLLWrm 957
-MMX_PSLLWrr 958
-MMX_PSRADri 959
-MMX_PSRADrm 960
-MMX_PSRADrr 961
-MMX_PSRAWri 962
-MMX_PSRAWrm 963
-MMX_PSRAWrr 964
-MMX_PSRLDri 965
-MMX_PSRLDrm 966
-MMX_PSRLDrr 967
-MMX_PSRLQri 968
-MMX_PSRLQrm 969
-MMX_PSRLQrr 970
-MMX_PSRLWri 971
-MMX_PSRLWrm 972
-MMX_PSRLWrr 973
-MMX_PSUBBrm 974
-MMX_PSUBBrr 975
-MMX_PSUBDrm 976
-MMX_PSUBDrr 977
-MMX_PSUBQrm 978
-MMX_PSUBQrr 979
-MMX_PSUBSBrm 980
-MMX_PSUBSBrr 981
-MMX_PSUBSWrm 982
-MMX_PSUBSWrr 983
-MMX_PSUBUSBrm 984
-MMX_PSUBUSBrr 985
-MMX_PSUBUSWrm 986
-MMX_PSUBUSWrr 987
-MMX_PSUBWrm 988
-MMX_PSUBWrr 989
-MMX_PUNPCKHBWrm 990
-MMX_PUNPCKHBWrr 991
-MMX_PUNPCKHDQrm 992
-MMX_PUNPCKHDQrr 993
-MMX_PUNPCKHWDrm 994
-MMX_PUNPCKHWDrr 995
-MMX_PUNPCKLBWrm 996
-MMX_PUNPCKLBWrr 997
-MMX_PUNPCKLDQrm 998
-MMX_PUNPCKLDQrr 999
-MMX_PUNPCKLWDrm 1000
-MMX_PUNPCKLWDrr 1001
-MMX_PXORrm 1002
-MMX_PXORrr 1003
-MMX_SET 1004
-MONITOR 1005
-MONITORX 1006
-MONTMUL 1007
-MORESTACK_RET 1008
-MORESTACK_RET_RESTORE_R 1009
-MOV 1010
-MOVAPDmr 1011
-MOVAPDrm 1012
-MOVAPDrr 1013
-MOVAPDrr_REV 1014
-MOVAPSmr 1015
-MOVAPSrm 1016
-MOVAPSrr 1017
-MOVAPSrr_REV 1018
-MOVBE 1019
-MOVDDUPrm 1020
-MOVDDUPrr 1021
-MOVDI 1022
-MOVDIR 1023
-MOVDIRI 1024
-MOVDQAmr 1025
-MOVDQArm 1026
-MOVDQArr 1027
-MOVDQArr_REV 1028
-MOVDQUmr 1029
-MOVDQUrm 1030
-MOVDQUrr 1031
-MOVDQUrr_REV 1032
-MOVHLPSrr 1033
-MOVHPDmr 1034
-MOVHPDrm 1035
-MOVHPSmr 1036
-MOVHPSrm 1037
-MOVLHPSrr 1038
-MOVLPDmr 1039
-MOVLPDrm 1040
-MOVLPSmr 1041
-MOVLPSrm 1042
-MOVMSKPDrr 1043
-MOVMSKPSrr 1044
-MOVNTDQArm 1045
-MOVNTDQmr 1046
-MOVNTI 1047
-MOVNTImr 1048
-MOVNTPDmr 1049
-MOVNTPSmr 1050
-MOVNTSD 1051
-MOVNTSS 1052
-MOVPC 1053
-MOVPDI 1054
-MOVPQI 1055
-MOVPQIto 1056
-MOVQI 1057
-MOVRS 1058
-MOVSB 1059
-MOVSDmr 1060
-MOVSDrm 1061
-MOVSDrm_alt 1062
-MOVSDrr 1063
-MOVSDrr_REV 1064
-MOVSDto 1065
-MOVSHDUPrm 1066
-MOVSHDUPrr 1067
-MOVSHPmr 1068
-MOVSHPrm 1069
-MOVSL 1070
-MOVSLDUPrm 1071
-MOVSLDUPrr 1072
-MOVSQ 1073
-MOVSS 1074
-MOVSSmr 1075
-MOVSSrm 1076
-MOVSSrm_alt 1077
-MOVSSrr 1078
-MOVSSrr_REV 1079
-MOVSW 1080
-MOVSX 1081
-MOVUPDmr 1082
-MOVUPDrm 1083
-MOVUPDrr 1084
-MOVUPDrr_REV 1085
-MOVUPSmr 1086
-MOVUPSrm 1087
-MOVUPSrr 1088
-MOVUPSrr_REV 1089
-MOVZPQILo 1090
-MOVZX 1091
-MPSADBWrmi 1092
-MPSADBWrri 1093
-MUL 1094
-MULPDrm 1095
-MULPDrr 1096
-MULPSrm 1097
-MULPSrr 1098
-MULSDrm 1099
-MULSDrm_Int 1100
-MULSDrr 1101
-MULSDrr_Int 1102
-MULSSrm 1103
-MULSSrm_Int 1104
-MULSSrr 1105
-MULSSrr_Int 1106
-MULX 1107
-MUL_F 1108
-MUL_FI 1109
-MUL_FPrST 1110
-MUL_FST 1111
-MUL_Fp 1112
-MUL_FpI 1113
-MUL_FrST 1114
-MWAITX 1115
-MWAITX_SAVE_RBX 1116
-MWAITXrrr 1117
-MWAITrr 1118
-NEG 1119
-NOOP 1120
-NOOPL 1121
-NOOPLr 1122
-NOOPQ 1123
-NOOPQr 1124
-NOOPW 1125
-NOOPWr 1126
-NOT 1127
-OR 1128
-ORPDrm 1129
-ORPDrr 1130
-ORPSrm 1131
-ORPSrr 1132
-OUT 1133
-OUTSB 1134
-OUTSL 1135
-OUTSW 1136
-PABSBrm 1137
-PABSBrr 1138
-PABSDrm 1139
-PABSDrr 1140
-PABSWrm 1141
-PABSWrr 1142
-PACKSSDWrm 1143
-PACKSSDWrr 1144
-PACKSSWBrm 1145
-PACKSSWBrr 1146
-PACKUSDWrm 1147
-PACKUSDWrr 1148
-PACKUSWBrm 1149
-PACKUSWBrr 1150
-PADDBrm 1151
-PADDBrr 1152
-PADDDrm 1153
-PADDDrr 1154
-PADDQrm 1155
-PADDQrr 1156
-PADDSBrm 1157
-PADDSBrr 1158
-PADDSWrm 1159
-PADDSWrr 1160
-PADDUSBrm 1161
-PADDUSBrr 1162
-PADDUSWrm 1163
-PADDUSWrr 1164
-PADDWrm 1165
-PADDWrr 1166
-PALIGNRrmi 1167
-PALIGNRrri 1168
-PANDNrm 1169
-PANDNrr 1170
-PANDrm 1171
-PANDrr 1172
-PATCHABLE_EVENT_CALL 1173
-PATCHABLE_FUNCTION_ENTER 1174
-PATCHABLE_FUNCTION_EXIT 1175
-PATCHABLE_OP 1176
-PATCHABLE_RET 1177
-PATCHABLE_TAIL_CALL 1178
-PATCHABLE_TYPED_EVENT_CALL 1179
-PATCHPOINT 1180
-PAUSE 1181
-PAVGBrm 1182
-PAVGBrr 1183
-PAVGUSBrm 1184
-PAVGUSBrr 1185
-PAVGWrm 1186
-PAVGWrr 1187
-PBLENDVBrm 1188
-PBLENDVBrr 1189
-PBLENDWrmi 1190
-PBLENDWrri 1191
-PBNDKB 1192
-PCLMULQDQrmi 1193
-PCLMULQDQrri 1194
-PCMPEQBrm 1195
-PCMPEQBrr 1196
-PCMPEQDrm 1197
-PCMPEQDrr 1198
-PCMPEQQrm 1199
-PCMPEQQrr 1200
-PCMPEQWrm 1201
-PCMPEQWrr 1202
-PCMPESTRIrmi 1203
-PCMPESTRIrri 1204
-PCMPESTRMrmi 1205
-PCMPESTRMrri 1206
-PCMPGTBrm 1207
-PCMPGTBrr 1208
-PCMPGTDrm 1209
-PCMPGTDrr 1210
-PCMPGTQrm 1211
-PCMPGTQrr 1212
-PCMPGTWrm 1213
-PCMPGTWrr 1214
-PCMPISTRIrmi 1215
-PCMPISTRIrri 1216
-PCMPISTRMrmi 1217
-PCMPISTRMrri 1218
-PCONFIG 1219
-PDEP 1220
-PEXT 1221
-PEXTRBmri 1222
-PEXTRBrri 1223
-PEXTRDmri 1224
-PEXTRDrri 1225
-PEXTRQmri 1226
-PEXTRQrri 1227
-PEXTRWmri 1228
-PEXTRWrri 1229
-PEXTRWrri_REV 1230
-PF 1231
-PFACCrm 1232
-PFACCrr 1233
-PFADDrm 1234
-PFADDrr 1235
-PFCMPEQrm 1236
-PFCMPEQrr 1237
-PFCMPGErm 1238
-PFCMPGErr 1239
-PFCMPGTrm 1240
-PFCMPGTrr 1241
-PFMAXrm 1242
-PFMAXrr 1243
-PFMINrm 1244
-PFMINrr 1245
-PFMULrm 1246
-PFMULrr 1247
-PFNACCrm 1248
-PFNACCrr 1249
-PFPNACCrm 1250
-PFPNACCrr 1251
-PFRCPIT 1252
-PFRCPrm 1253
-PFRCPrr 1254
-PFRSQIT 1255
-PFRSQRTrm 1256
-PFRSQRTrr 1257
-PFSUBRrm 1258
-PFSUBRrr 1259
-PFSUBrm 1260
-PFSUBrr 1261
-PHADDDrm 1262
-PHADDDrr 1263
-PHADDSWrm 1264
-PHADDSWrr 1265
-PHADDWrm 1266
-PHADDWrr 1267
-PHI 1268
-PHMINPOSUWrm 1269
-PHMINPOSUWrr 1270
-PHSUBDrm 1271
-PHSUBDrr 1272
-PHSUBSWrm 1273
-PHSUBSWrr 1274
-PHSUBWrm 1275
-PHSUBWrr 1276
-PI 1277
-PINSRBrmi 1278
-PINSRBrri 1279
-PINSRDrmi 1280
-PINSRDrri 1281
-PINSRQrmi 1282
-PINSRQrri 1283
-PINSRWrmi 1284
-PINSRWrri 1285
-PLDTILECFGV 1286
-PLEA 1287
-PMADDUBSWrm 1288
-PMADDUBSWrr 1289
-PMADDWDrm 1290
-PMADDWDrr 1291
-PMAXSBrm 1292
-PMAXSBrr 1293
-PMAXSDrm 1294
-PMAXSDrr 1295
-PMAXSWrm 1296
-PMAXSWrr 1297
-PMAXUBrm 1298
-PMAXUBrr 1299
-PMAXUDrm 1300
-PMAXUDrr 1301
-PMAXUWrm 1302
-PMAXUWrr 1303
-PMINSBrm 1304
-PMINSBrr 1305
-PMINSDrm 1306
-PMINSDrr 1307
-PMINSWrm 1308
-PMINSWrr 1309
-PMINUBrm 1310
-PMINUBrr 1311
-PMINUDrm 1312
-PMINUDrr 1313
-PMINUWrm 1314
-PMINUWrr 1315
-PMOVMSKBrr 1316
-PMOVSXBDrm 1317
-PMOVSXBDrr 1318
-PMOVSXBQrm 1319
-PMOVSXBQrr 1320
-PMOVSXBWrm 1321
-PMOVSXBWrr 1322
-PMOVSXDQrm 1323
-PMOVSXDQrr 1324
-PMOVSXWDrm 1325
-PMOVSXWDrr 1326
-PMOVSXWQrm 1327
-PMOVSXWQrr 1328
-PMOVZXBDrm 1329
-PMOVZXBDrr 1330
-PMOVZXBQrm 1331
-PMOVZXBQrr 1332
-PMOVZXBWrm 1333
-PMOVZXBWrr 1334
-PMOVZXDQrm 1335
-PMOVZXDQrr 1336
-PMOVZXWDrm 1337
-PMOVZXWDrr 1338
-PMOVZXWQrm 1339
-PMOVZXWQrr 1340
-PMULDQrm 1341
-PMULDQrr 1342
-PMULHRSWrm 1343
-PMULHRSWrr 1344
-PMULHRWrm 1345
-PMULHRWrr 1346
-PMULHUWrm 1347
-PMULHUWrr 1348
-PMULHWrm 1349
-PMULHWrr 1350
-PMULLDrm 1351
-PMULLDrr 1352
-PMULLWrm 1353
-PMULLWrr 1354
-PMULUDQrm 1355
-PMULUDQrr 1356
-POP 1357
-POPA 1358
-POPCNT 1359
-POPDS 1360
-POPES 1361
-POPF 1362
-POPFS 1363
-POPGS 1364
-POPP 1365
-POPSS 1366
-PORrm 1367
-PORrr 1368
-PREALLOCATED_ARG 1369
-PREALLOCATED_SETUP 1370
-PREFETCH 1371
-PREFETCHIT 1372
-PREFETCHNTA 1373
-PREFETCHRST 1374
-PREFETCHT 1375
-PREFETCHW 1376
-PREFETCHWT 1377
-PROBED_ALLOCA 1378
-PSADBWrm 1379
-PSADBWrr 1380
-PSEUDO_PROBE 1381
-PSHUFBrm 1382
-PSHUFBrr 1383
-PSHUFDmi 1384
-PSHUFDri 1385
-PSHUFHWmi 1386
-PSHUFHWri 1387
-PSHUFLWmi 1388
-PSHUFLWri 1389
-PSIGNBrm 1390
-PSIGNBrr 1391
-PSIGNDrm 1392
-PSIGNDrr 1393
-PSIGNWrm 1394
-PSIGNWrr 1395
-PSLLDQri 1396
-PSLLDri 1397
-PSLLDrm 1398
-PSLLDrr 1399
-PSLLQri 1400
-PSLLQrm 1401
-PSLLQrr 1402
-PSLLWri 1403
-PSLLWrm 1404
-PSLLWrr 1405
-PSMASH 1406
-PSRADri 1407
-PSRADrm 1408
-PSRADrr 1409
-PSRAWri 1410
-PSRAWrm 1411
-PSRAWrr 1412
-PSRLDQri 1413
-PSRLDri 1414
-PSRLDrm 1415
-PSRLDrr 1416
-PSRLQri 1417
-PSRLQrm 1418
-PSRLQrr 1419
-PSRLWri 1420
-PSRLWrm 1421
-PSRLWrr 1422
-PSUBBrm 1423
-PSUBBrr 1424
-PSUBDrm 1425
-PSUBDrr 1426
-PSUBQrm 1427
-PSUBQrr 1428
-PSUBSBrm 1429
-PSUBSBrr 1430
-PSUBSWrm 1431
-PSUBSWrr 1432
-PSUBUSBrm 1433
-PSUBUSBrr 1434
-PSUBUSWrm 1435
-PSUBUSWrr 1436
-PSUBWrm 1437
-PSUBWrr 1438
-PSWAPDrm 1439
-PSWAPDrr 1440
-PTCMMIMFP 1441
-PTCMMRLFP 1442
-PTCVTROWD 1443
-PTCVTROWPS 1444
-PTDPBF 1445
-PTDPBHF 1446
-PTDPBSSD 1447
-PTDPBSSDV 1448
-PTDPBSUD 1449
-PTDPBSUDV 1450
-PTDPBUSD 1451
-PTDPBUSDV 1452
-PTDPBUUD 1453
-PTDPBUUDV 1454
-PTDPFP 1455
-PTDPHBF 1456
-PTDPHF 1457
-PTESTrm 1458
-PTESTrr 1459
-PTILELOADD 1460
-PTILELOADDRS 1461
-PTILELOADDRST 1462
-PTILELOADDRSV 1463
-PTILELOADDT 1464
-PTILELOADDV 1465
-PTILEMOVROWrre 1466
-PTILEMOVROWrreV 1467
-PTILEMOVROWrri 1468
-PTILEMOVROWrriV 1469
-PTILESTORED 1470
-PTILESTOREDV 1471
-PTILEZERO 1472
-PTILEZEROV 1473
-PTMMULTF 1474
-PTWRITE 1475
-PTWRITEm 1476
-PTWRITEr 1477
-PUNPCKHBWrm 1478
-PUNPCKHBWrr 1479
-PUNPCKHDQrm 1480
-PUNPCKHDQrr 1481
-PUNPCKHQDQrm 1482
-PUNPCKHQDQrr 1483
-PUNPCKHWDrm 1484
-PUNPCKHWDrr 1485
-PUNPCKLBWrm 1486
-PUNPCKLBWrr 1487
-PUNPCKLDQrm 1488
-PUNPCKLDQrr 1489
-PUNPCKLQDQrm 1490
-PUNPCKLQDQrr 1491
-PUNPCKLWDrm 1492
-PUNPCKLWDrr 1493
-PUSH 1494
-PUSHA 1495
-PUSHCS 1496
-PUSHDS 1497
-PUSHES 1498
-PUSHF 1499
-PUSHFS 1500
-PUSHGS 1501
-PUSHP 1502
-PUSHSS 1503
-PVALIDATE 1504
-PXORrm 1505
-PXORrr 1506
-RCL 1507
-RCPPSm 1508
-RCPPSr 1509
-RCPSSm 1510
-RCPSSm_Int 1511
-RCPSSr 1512
-RCPSSr_Int 1513
-RCR 1514
-RDFLAGS 1515
-RDFSBASE 1516
-RDGSBASE 1517
-RDMSR 1518
-RDMSRLIST 1519
-RDMSRri 1520
-RDMSRri_EVEX 1521
-RDPID 1522
-RDPKRUr 1523
-RDPMC 1524
-RDPRU 1525
-RDRAND 1526
-RDSEED 1527
-RDSSPD 1528
-RDSSPQ 1529
-RDTSC 1530
-RDTSCP 1531
-REG_SEQUENCE 1532
-REPNE_PREFIX 1533
-REP_MOVSB 1534
-REP_MOVSD 1535
-REP_MOVSQ 1536
-REP_MOVSW 1537
-REP_PREFIX 1538
-REP_STOSB 1539
-REP_STOSD 1540
-REP_STOSQ 1541
-REP_STOSW 1542
-RET 1543
-RETI 1544
-REX 1545
-RMPADJUST 1546
-RMPQUERY 1547
-RMPUPDATE 1548
-ROL 1549
-ROR 1550
-RORX 1551
-ROUNDPDmi 1552
-ROUNDPDri 1553
-ROUNDPSmi 1554
-ROUNDPSri 1555
-ROUNDSDmi 1556
-ROUNDSDmi_Int 1557
-ROUNDSDri 1558
-ROUNDSDri_Int 1559
-ROUNDSSmi 1560
-ROUNDSSmi_Int 1561
-ROUNDSSri 1562
-ROUNDSSri_Int 1563
-RSM 1564
-RSQRTPSm 1565
-RSQRTPSr 1566
-RSQRTSSm 1567
-RSQRTSSm_Int 1568
-RSQRTSSr 1569
-RSQRTSSr_Int 1570
-RSTORSSP 1571
-SAHF 1572
-SALC 1573
-SAR 1574
-SARX 1575
-SAVEPREVSSP 1576
-SBB 1577
-SCASB 1578
-SCASL 1579
-SCASQ 1580
-SCASW 1581
-SEAMCALL 1582
-SEAMOPS 1583
-SEAMRET 1584
-SEG_ALLOCA 1585
-SEH_BeginEpilogue 1586
-SEH_EndEpilogue 1587
-SEH_EndPrologue 1588
-SEH_PushFrame 1589
-SEH_PushReg 1590
-SEH_SaveReg 1591
-SEH_SaveXMM 1592
-SEH_SetFrame 1593
-SEH_StackAlign 1594
-SEH_StackAlloc 1595
-SEH_UnwindV 1596
-SEH_UnwindVersion 1597
-SENDUIPI 1598
-SERIALIZE 1599
-SETB_C 1600
-SETCCm 1601
-SETCCm_EVEX 1602
-SETCCr 1603
-SETCCr_EVEX 1604
-SETSSBSY 1605
-SETZUCCm 1606
-SETZUCCr 1607
-SFENCE 1608
-SGDT 1609
-SHA 1610
-SHL 1611
-SHLD 1612
-SHLDROT 1613
-SHLX 1614
-SHR 1615
-SHRD 1616
-SHRDROT 1617
-SHRX 1618
-SHUFPDrmi 1619
-SHUFPDrri 1620
-SHUFPSrmi 1621
-SHUFPSrri 1622
-SIDT 1623
-SKINIT 1624
-SLDT 1625
-SLWPCB 1626
-SMSW 1627
-SQRTPDm 1628
-SQRTPDr 1629
-SQRTPSm 1630
-SQRTPSr 1631
-SQRTSDm 1632
-SQRTSDm_Int 1633
-SQRTSDr 1634
-SQRTSDr_Int 1635
-SQRTSSm 1636
-SQRTSSm_Int 1637
-SQRTSSr 1638
-SQRTSSr_Int 1639
-SQRT_F 1640
-SQRT_Fp 1641
-SS_PREFIX 1642
-STAC 1643
-STACKALLOC_W_PROBING 1644
-STACKMAP 1645
-STATEPOINT 1646
-STC 1647
-STD 1648
-STGI 1649
-STI 1650
-STMXCSR 1651
-STOSB 1652
-STOSL 1653
-STOSQ 1654
-STOSW 1655
-STR 1656
-STRm 1657
-STTILECFG 1658
-STTILECFG_EVEX 1659
-STUI 1660
-ST_F 1661
-ST_FP 1662
-ST_FPrr 1663
-ST_Fp 1664
-ST_FpP 1665
-ST_Frr 1666
-SUB 1667
-SUBPDrm 1668
-SUBPDrr 1669
-SUBPSrm 1670
-SUBPSrr 1671
-SUBREG_TO_REG 1672
-SUBR_F 1673
-SUBR_FI 1674
-SUBR_FPrST 1675
-SUBR_FST 1676
-SUBR_Fp 1677
-SUBR_FpI 1678
-SUBR_FrST 1679
-SUBSDrm 1680
-SUBSDrm_Int 1681
-SUBSDrr 1682
-SUBSDrr_Int 1683
-SUBSSrm 1684
-SUBSSrm_Int 1685
-SUBSSrr 1686
-SUBSSrr_Int 1687
-SUB_F 1688
-SUB_FI 1689
-SUB_FPrST 1690
-SUB_FST 1691
-SUB_Fp 1692
-SUB_FpI 1693
-SUB_FrST 1694
-SWAPGS 1695
-SYSCALL 1696
-SYSENTER 1697
-SYSEXIT 1698
-SYSRET 1699
-T 1700
-TAILJMPd 1701
-TAILJMPd_CC 1702
-TAILJMPm 1703
-TAILJMPr 1704
-TCMMIMFP 1705
-TCMMRLFP 1706
-TCRETURN_HIPE 1707
-TCRETURN_WIN 1708
-TCRETURN_WINmi 1709
-TCRETURNdi 1710
-TCRETURNdicc 1711
-TCRETURNmi 1712
-TCRETURNri 1713
-TCVTROWD 1714
-TCVTROWPS 1715
-TDCALL 1716
-TDPBF 1717
-TDPBHF 1718
-TDPBSSD 1719
-TDPBSUD 1720
-TDPBUSD 1721
-TDPBUUD 1722
-TDPFP 1723
-TDPHBF 1724
-TDPHF 1725
-TEST 1726
-TESTUI 1727
-TILELOADD 1728
-TILELOADDRS 1729
-TILELOADDRST 1730
-TILELOADDRS_EVEX 1731
-TILELOADDT 1732
-TILELOADD_EVEX 1733
-TILEMOVROWrre 1734
-TILEMOVROWrri 1735
-TILERELEASE 1736
-TILESTORED 1737
-TILESTORED_EVEX 1738
-TILEZERO 1739
-TLBSYNC 1740
-TLSCall 1741
-TLS_addr 1742
-TLS_addrX 1743
-TLS_base_addr 1744
-TLS_base_addrX 1745
-TLS_desc 1746
-TMMULTF 1747
-TPAUSE 1748
-TRAP 1749
-TST_F 1750
-TST_Fp 1751
-TZCNT 1752
-TZMSK 1753
-UBSAN_UD 1754
-UCOMISDrm 1755
-UCOMISDrm_Int 1756
-UCOMISDrr 1757
-UCOMISDrr_Int 1758
-UCOMISSrm 1759
-UCOMISSrm_Int 1760
-UCOMISSrr 1761
-UCOMISSrr_Int 1762
-UCOM_FIPr 1763
-UCOM_FIr 1764
-UCOM_FPPr 1765
-UCOM_FPr 1766
-UCOM_FpIr 1767
-UCOM_Fpr 1768
-UCOM_Fr 1769
-UD 1770
-UIRET 1771
-UMONITOR 1772
-UMWAIT 1773
-UNPCKHPDrm 1774
-UNPCKHPDrr 1775
-UNPCKHPSrm 1776
-UNPCKHPSrr 1777
-UNPCKLPDrm 1778
-UNPCKLPDrr 1779
-UNPCKLPSrm 1780
-UNPCKLPSrr 1781
-URDMSRri 1782
-URDMSRri_EVEX 1783
-URDMSRrr 1784
-URDMSRrr_EVEX 1785
-UWRMSRir 1786
-UWRMSRir_EVEX 1787
-UWRMSRrr 1788
-UWRMSRrr_EVEX 1789
-V 1790
-VAARG 1791
-VAARG_X 1792
-VADDBF 1793
-VADDPDYrm 1794
-VADDPDYrr 1795
-VADDPDZ 1796
-VADDPDZrm 1797
-VADDPDZrmb 1798
-VADDPDZrmbk 1799
-VADDPDZrmbkz 1800
-VADDPDZrmk 1801
-VADDPDZrmkz 1802
-VADDPDZrr 1803
-VADDPDZrrb 1804
-VADDPDZrrbk 1805
-VADDPDZrrbkz 1806
-VADDPDZrrk 1807
-VADDPDZrrkz 1808
-VADDPDrm 1809
-VADDPDrr 1810
-VADDPHZ 1811
-VADDPHZrm 1812
-VADDPHZrmb 1813
-VADDPHZrmbk 1814
-VADDPHZrmbkz 1815
-VADDPHZrmk 1816
-VADDPHZrmkz 1817
-VADDPHZrr 1818
-VADDPHZrrb 1819
-VADDPHZrrbk 1820
-VADDPHZrrbkz 1821
-VADDPHZrrk 1822
-VADDPHZrrkz 1823
-VADDPSYrm 1824
-VADDPSYrr 1825
-VADDPSZ 1826
-VADDPSZrm 1827
-VADDPSZrmb 1828
-VADDPSZrmbk 1829
-VADDPSZrmbkz 1830
-VADDPSZrmk 1831
-VADDPSZrmkz 1832
-VADDPSZrr 1833
-VADDPSZrrb 1834
-VADDPSZrrbk 1835
-VADDPSZrrbkz 1836
-VADDPSZrrk 1837
-VADDPSZrrkz 1838
-VADDPSrm 1839
-VADDPSrr 1840
-VADDSDZrm 1841
-VADDSDZrm_Int 1842
-VADDSDZrmk_Int 1843
-VADDSDZrmkz_Int 1844
-VADDSDZrr 1845
-VADDSDZrr_Int 1846
-VADDSDZrrb_Int 1847
-VADDSDZrrbk_Int 1848
-VADDSDZrrbkz_Int 1849
-VADDSDZrrk_Int 1850
-VADDSDZrrkz_Int 1851
-VADDSDrm 1852
-VADDSDrm_Int 1853
-VADDSDrr 1854
-VADDSDrr_Int 1855
-VADDSHZrm 1856
-VADDSHZrm_Int 1857
-VADDSHZrmk_Int 1858
-VADDSHZrmkz_Int 1859
-VADDSHZrr 1860
-VADDSHZrr_Int 1861
-VADDSHZrrb_Int 1862
-VADDSHZrrbk_Int 1863
-VADDSHZrrbkz_Int 1864
-VADDSHZrrk_Int 1865
-VADDSHZrrkz_Int 1866
-VADDSSZrm 1867
-VADDSSZrm_Int 1868
-VADDSSZrmk_Int 1869
-VADDSSZrmkz_Int 1870
-VADDSSZrr 1871
-VADDSSZrr_Int 1872
-VADDSSZrrb_Int 1873
-VADDSSZrrbk_Int 1874
-VADDSSZrrbkz_Int 1875
-VADDSSZrrk_Int 1876
-VADDSSZrrkz_Int 1877
-VADDSSrm 1878
-VADDSSrm_Int 1879
-VADDSSrr 1880
-VADDSSrr_Int 1881
-VADDSUBPDYrm 1882
-VADDSUBPDYrr 1883
-VADDSUBPDrm 1884
-VADDSUBPDrr 1885
-VADDSUBPSYrm 1886
-VADDSUBPSYrr 1887
-VADDSUBPSrm 1888
-VADDSUBPSrr 1889
-VAESDECLASTYrm 1890
-VAESDECLASTYrr 1891
-VAESDECLASTZ 1892
-VAESDECLASTZrm 1893
-VAESDECLASTZrr 1894
-VAESDECLASTrm 1895
-VAESDECLASTrr 1896
-VAESDECYrm 1897
-VAESDECYrr 1898
-VAESDECZ 1899
-VAESDECZrm 1900
-VAESDECZrr 1901
-VAESDECrm 1902
-VAESDECrr 1903
-VAESENCLASTYrm 1904
-VAESENCLASTYrr 1905
-VAESENCLASTZ 1906
-VAESENCLASTZrm 1907
-VAESENCLASTZrr 1908
-VAESENCLASTrm 1909
-VAESENCLASTrr 1910
-VAESENCYrm 1911
-VAESENCYrr 1912
-VAESENCZ 1913
-VAESENCZrm 1914
-VAESENCZrr 1915
-VAESENCrm 1916
-VAESENCrr 1917
-VAESIMCrm 1918
-VAESIMCrr 1919
-VAESKEYGENASSISTrmi 1920
-VAESKEYGENASSISTrri 1921
-VALIGNDZ 1922
-VALIGNDZrmbi 1923
-VALIGNDZrmbik 1924
-VALIGNDZrmbikz 1925
-VALIGNDZrmi 1926
-VALIGNDZrmik 1927
-VALIGNDZrmikz 1928
-VALIGNDZrri 1929
-VALIGNDZrrik 1930
-VALIGNDZrrikz 1931
-VALIGNQZ 1932
-VALIGNQZrmbi 1933
-VALIGNQZrmbik 1934
-VALIGNQZrmbikz 1935
-VALIGNQZrmi 1936
-VALIGNQZrmik 1937
-VALIGNQZrmikz 1938
-VALIGNQZrri 1939
-VALIGNQZrrik 1940
-VALIGNQZrrikz 1941
-VANDNPDYrm 1942
-VANDNPDYrr 1943
-VANDNPDZ 1944
-VANDNPDZrm 1945
-VANDNPDZrmb 1946
-VANDNPDZrmbk 1947
-VANDNPDZrmbkz 1948
-VANDNPDZrmk 1949
-VANDNPDZrmkz 1950
-VANDNPDZrr 1951
-VANDNPDZrrk 1952
-VANDNPDZrrkz 1953
-VANDNPDrm 1954
-VANDNPDrr 1955
-VANDNPSYrm 1956
-VANDNPSYrr 1957
-VANDNPSZ 1958
-VANDNPSZrm 1959
-VANDNPSZrmb 1960
-VANDNPSZrmbk 1961
-VANDNPSZrmbkz 1962
-VANDNPSZrmk 1963
-VANDNPSZrmkz 1964
-VANDNPSZrr 1965
-VANDNPSZrrk 1966
-VANDNPSZrrkz 1967
-VANDNPSrm 1968
-VANDNPSrr 1969
-VANDPDYrm 1970
-VANDPDYrr 1971
-VANDPDZ 1972
-VANDPDZrm 1973
-VANDPDZrmb 1974
-VANDPDZrmbk 1975
-VANDPDZrmbkz 1976
-VANDPDZrmk 1977
-VANDPDZrmkz 1978
-VANDPDZrr 1979
-VANDPDZrrk 1980
-VANDPDZrrkz 1981
-VANDPDrm 1982
-VANDPDrr 1983
-VANDPSYrm 1984
-VANDPSYrr 1985
-VANDPSZ 1986
-VANDPSZrm 1987
-VANDPSZrmb 1988
-VANDPSZrmbk 1989
-VANDPSZrmbkz 1990
-VANDPSZrmk 1991
-VANDPSZrmkz 1992
-VANDPSZrr 1993
-VANDPSZrrk 1994
-VANDPSZrrkz 1995
-VANDPSrm 1996
-VANDPSrr 1997
-VASTART_SAVE_XMM_REGS 1998
-VBCSTNEBF 1999
-VBCSTNESH 2000
-VBLENDMPDZ 2001
-VBLENDMPDZrm 2002
-VBLENDMPDZrmb 2003
-VBLENDMPDZrmbk 2004
-VBLENDMPDZrmbkz 2005
-VBLENDMPDZrmk 2006
-VBLENDMPDZrmkz 2007
-VBLENDMPDZrr 2008
-VBLENDMPDZrrk 2009
-VBLENDMPDZrrkz 2010
-VBLENDMPSZ 2011
-VBLENDMPSZrm 2012
-VBLENDMPSZrmb 2013
-VBLENDMPSZrmbk 2014
-VBLENDMPSZrmbkz 2015
-VBLENDMPSZrmk 2016
-VBLENDMPSZrmkz 2017
-VBLENDMPSZrr 2018
-VBLENDMPSZrrk 2019
-VBLENDMPSZrrkz 2020
-VBLENDPDYrmi 2021
-VBLENDPDYrri 2022
-VBLENDPDrmi 2023
-VBLENDPDrri 2024
-VBLENDPSYrmi 2025
-VBLENDPSYrri 2026
-VBLENDPSrmi 2027
-VBLENDPSrri 2028
-VBLENDVPDYrmr 2029
-VBLENDVPDYrrr 2030
-VBLENDVPDrmr 2031
-VBLENDVPDrrr 2032
-VBLENDVPSYrmr 2033
-VBLENDVPSYrrr 2034
-VBLENDVPSrmr 2035
-VBLENDVPSrrr 2036
-VBROADCASTF 2037
-VBROADCASTI 2038
-VBROADCASTSDYrm 2039
-VBROADCASTSDYrr 2040
-VBROADCASTSDZ 2041
-VBROADCASTSDZrm 2042
-VBROADCASTSDZrmk 2043
-VBROADCASTSDZrmkz 2044
-VBROADCASTSDZrr 2045
-VBROADCASTSDZrrk 2046
-VBROADCASTSDZrrkz 2047
-VBROADCASTSSYrm 2048
-VBROADCASTSSYrr 2049
-VBROADCASTSSZ 2050
-VBROADCASTSSZrm 2051
-VBROADCASTSSZrmk 2052
-VBROADCASTSSZrmkz 2053
-VBROADCASTSSZrr 2054
-VBROADCASTSSZrrk 2055
-VBROADCASTSSZrrkz 2056
-VBROADCASTSSrm 2057
-VBROADCASTSSrr 2058
-VCMPBF 2059
-VCMPPDYrmi 2060
-VCMPPDYrri 2061
-VCMPPDZ 2062
-VCMPPDZrmbi 2063
-VCMPPDZrmbik 2064
-VCMPPDZrmi 2065
-VCMPPDZrmik 2066
-VCMPPDZrri 2067
-VCMPPDZrrib 2068
-VCMPPDZrribk 2069
-VCMPPDZrrik 2070
-VCMPPDrmi 2071
-VCMPPDrri 2072
-VCMPPHZ 2073
-VCMPPHZrmbi 2074
-VCMPPHZrmbik 2075
-VCMPPHZrmi 2076
-VCMPPHZrmik 2077
-VCMPPHZrri 2078
-VCMPPHZrrib 2079
-VCMPPHZrribk 2080
-VCMPPHZrrik 2081
-VCMPPSYrmi 2082
-VCMPPSYrri 2083
-VCMPPSZ 2084
-VCMPPSZrmbi 2085
-VCMPPSZrmbik 2086
-VCMPPSZrmi 2087
-VCMPPSZrmik 2088
-VCMPPSZrri 2089
-VCMPPSZrrib 2090
-VCMPPSZrribk 2091
-VCMPPSZrrik 2092
-VCMPPSrmi 2093
-VCMPPSrri 2094
-VCMPSDZrmi 2095
-VCMPSDZrmi_Int 2096
-VCMPSDZrmik_Int 2097
-VCMPSDZrri 2098
-VCMPSDZrri_Int 2099
-VCMPSDZrrib_Int 2100
-VCMPSDZrribk_Int 2101
-VCMPSDZrrik_Int 2102
-VCMPSDrmi 2103
-VCMPSDrmi_Int 2104
-VCMPSDrri 2105
-VCMPSDrri_Int 2106
-VCMPSHZrmi 2107
-VCMPSHZrmi_Int 2108
-VCMPSHZrmik_Int 2109
-VCMPSHZrri 2110
-VCMPSHZrri_Int 2111
-VCMPSHZrrib_Int 2112
-VCMPSHZrribk_Int 2113
-VCMPSHZrrik_Int 2114
-VCMPSSZrmi 2115
-VCMPSSZrmi_Int 2116
-VCMPSSZrmik_Int 2117
-VCMPSSZrri 2118
-VCMPSSZrri_Int 2119
-VCMPSSZrrib_Int 2120
-VCMPSSZrribk_Int 2121
-VCMPSSZrrik_Int 2122
-VCMPSSrmi 2123
-VCMPSSrmi_Int 2124
-VCMPSSrri 2125
-VCMPSSrri_Int 2126
-VCOMISBF 2127
-VCOMISDZrm 2128
-VCOMISDZrm_Int 2129
-VCOMISDZrr 2130
-VCOMISDZrr_Int 2131
-VCOMISDZrrb 2132
-VCOMISDrm 2133
-VCOMISDrm_Int 2134
-VCOMISDrr 2135
-VCOMISDrr_Int 2136
-VCOMISHZrm 2137
-VCOMISHZrm_Int 2138
-VCOMISHZrr 2139
-VCOMISHZrr_Int 2140
-VCOMISHZrrb 2141
-VCOMISSZrm 2142
-VCOMISSZrm_Int 2143
-VCOMISSZrr 2144
-VCOMISSZrr_Int 2145
-VCOMISSZrrb 2146
-VCOMISSrm 2147
-VCOMISSrm_Int 2148
-VCOMISSrr 2149
-VCOMISSrr_Int 2150
-VCOMPRESSPDZ 2151
-VCOMPRESSPDZmr 2152
-VCOMPRESSPDZmrk 2153
-VCOMPRESSPDZrr 2154
-VCOMPRESSPDZrrk 2155
-VCOMPRESSPDZrrkz 2156
-VCOMPRESSPSZ 2157
-VCOMPRESSPSZmr 2158
-VCOMPRESSPSZmrk 2159
-VCOMPRESSPSZrr 2160
-VCOMPRESSPSZrrk 2161
-VCOMPRESSPSZrrkz 2162
-VCOMXSDZrm_Int 2163
-VCOMXSDZrr_Int 2164
-VCOMXSDZrrb_Int 2165
-VCOMXSHZrm_Int 2166
-VCOMXSHZrr_Int 2167
-VCOMXSHZrrb_Int 2168
-VCOMXSSZrm_Int 2169
-VCOMXSSZrr_Int 2170
-VCOMXSSZrrb_Int 2171
-VCVT 2172
-VCVTBF 2173
-VCVTBIASPH 2174
-VCVTDQ 2175
-VCVTHF 2176
-VCVTNE 2177
-VCVTNEEBF 2178
-VCVTNEEPH 2179
-VCVTNEOBF 2180
-VCVTNEOPH 2181
-VCVTNEPS 2182
-VCVTPD 2183
-VCVTPH 2184
-VCVTPS 2185
-VCVTQQ 2186
-VCVTSD 2187
-VCVTSH 2188
-VCVTSI 2189
-VCVTSS 2190
-VCVTTBF 2191
-VCVTTPD 2192
-VCVTTPH 2193
-VCVTTPS 2194
-VCVTTSD 2195
-VCVTTSH 2196
-VCVTTSS 2197
-VCVTUDQ 2198
-VCVTUQQ 2199
-VCVTUSI 2200
-VCVTUW 2201
-VCVTW 2202
-VDBPSADBWZ 2203
-VDBPSADBWZrmi 2204
-VDBPSADBWZrmik 2205
-VDBPSADBWZrmikz 2206
-VDBPSADBWZrri 2207
-VDBPSADBWZrrik 2208
-VDBPSADBWZrrikz 2209
-VDIVBF 2210
-VDIVPDYrm 2211
-VDIVPDYrr 2212
-VDIVPDZ 2213
-VDIVPDZrm 2214
-VDIVPDZrmb 2215
-VDIVPDZrmbk 2216
-VDIVPDZrmbkz 2217
-VDIVPDZrmk 2218
-VDIVPDZrmkz 2219
-VDIVPDZrr 2220
-VDIVPDZrrb 2221
-VDIVPDZrrbk 2222
-VDIVPDZrrbkz 2223
-VDIVPDZrrk 2224
-VDIVPDZrrkz 2225
-VDIVPDrm 2226
-VDIVPDrr 2227
-VDIVPHZ 2228
-VDIVPHZrm 2229
-VDIVPHZrmb 2230
-VDIVPHZrmbk 2231
-VDIVPHZrmbkz 2232
-VDIVPHZrmk 2233
-VDIVPHZrmkz 2234
-VDIVPHZrr 2235
-VDIVPHZrrb 2236
-VDIVPHZrrbk 2237
-VDIVPHZrrbkz 2238
-VDIVPHZrrk 2239
-VDIVPHZrrkz 2240
-VDIVPSYrm 2241
-VDIVPSYrr 2242
-VDIVPSZ 2243
-VDIVPSZrm 2244
-VDIVPSZrmb 2245
-VDIVPSZrmbk 2246
-VDIVPSZrmbkz 2247
-VDIVPSZrmk 2248
-VDIVPSZrmkz 2249
-VDIVPSZrr 2250
-VDIVPSZrrb 2251
-VDIVPSZrrbk 2252
-VDIVPSZrrbkz 2253
-VDIVPSZrrk 2254
-VDIVPSZrrkz 2255
-VDIVPSrm 2256
-VDIVPSrr 2257
-VDIVSDZrm 2258
-VDIVSDZrm_Int 2259
-VDIVSDZrmk_Int 2260
-VDIVSDZrmkz_Int 2261
-VDIVSDZrr 2262
-VDIVSDZrr_Int 2263
-VDIVSDZrrb_Int 2264
-VDIVSDZrrbk_Int 2265
-VDIVSDZrrbkz_Int 2266
-VDIVSDZrrk_Int 2267
-VDIVSDZrrkz_Int 2268
-VDIVSDrm 2269
-VDIVSDrm_Int 2270
-VDIVSDrr 2271
-VDIVSDrr_Int 2272
-VDIVSHZrm 2273
-VDIVSHZrm_Int 2274
-VDIVSHZrmk_Int 2275
-VDIVSHZrmkz_Int 2276
-VDIVSHZrr 2277
-VDIVSHZrr_Int 2278
-VDIVSHZrrb_Int 2279
-VDIVSHZrrbk_Int 2280
-VDIVSHZrrbkz_Int 2281
-VDIVSHZrrk_Int 2282
-VDIVSHZrrkz_Int 2283
-VDIVSSZrm 2284
-VDIVSSZrm_Int 2285
-VDIVSSZrmk_Int 2286
-VDIVSSZrmkz_Int 2287
-VDIVSSZrr 2288
-VDIVSSZrr_Int 2289
-VDIVSSZrrb_Int 2290
-VDIVSSZrrbk_Int 2291
-VDIVSSZrrbkz_Int 2292
-VDIVSSZrrk_Int 2293
-VDIVSSZrrkz_Int 2294
-VDIVSSrm 2295
-VDIVSSrm_Int 2296
-VDIVSSrr 2297
-VDIVSSrr_Int 2298
-VDPBF 2299
-VDPPDrmi 2300
-VDPPDrri 2301
-VDPPHPSZ 2302
-VDPPHPSZm 2303
-VDPPHPSZmb 2304
-VDPPHPSZmbk 2305
-VDPPHPSZmbkz 2306
-VDPPHPSZmk 2307
-VDPPHPSZmkz 2308
-VDPPHPSZr 2309
-VDPPHPSZrk 2310
-VDPPHPSZrkz 2311
-VDPPSYrmi 2312
-VDPPSYrri 2313
-VDPPSrmi 2314
-VDPPSrri 2315
-VERRm 2316
-VERRr 2317
-VERWm 2318
-VERWr 2319
-VEXP 2320
-VEXPANDPDZ 2321
-VEXPANDPDZrm 2322
-VEXPANDPDZrmk 2323
-VEXPANDPDZrmkz 2324
-VEXPANDPDZrr 2325
-VEXPANDPDZrrk 2326
-VEXPANDPDZrrkz 2327
-VEXPANDPSZ 2328
-VEXPANDPSZrm 2329
-VEXPANDPSZrmk 2330
-VEXPANDPSZrmkz 2331
-VEXPANDPSZrr 2332
-VEXPANDPSZrrk 2333
-VEXPANDPSZrrkz 2334
-VEXTRACTF 2335
-VEXTRACTI 2336
-VEXTRACTPSZmri 2337
-VEXTRACTPSZrri 2338
-VEXTRACTPSmri 2339
-VEXTRACTPSrri 2340
-VFCMADDCPHZ 2341
-VFCMADDCPHZm 2342
-VFCMADDCPHZmb 2343
-VFCMADDCPHZmbk 2344
-VFCMADDCPHZmbkz 2345
-VFCMADDCPHZmk 2346
-VFCMADDCPHZmkz 2347
-VFCMADDCPHZr 2348
-VFCMADDCPHZrb 2349
-VFCMADDCPHZrbk 2350
-VFCMADDCPHZrbkz 2351
-VFCMADDCPHZrk 2352
-VFCMADDCPHZrkz 2353
-VFCMADDCSHZm 2354
-VFCMADDCSHZmk 2355
-VFCMADDCSHZmkz 2356
-VFCMADDCSHZr 2357
-VFCMADDCSHZrb 2358
-VFCMADDCSHZrbk 2359
-VFCMADDCSHZrbkz 2360
-VFCMADDCSHZrk 2361
-VFCMADDCSHZrkz 2362
-VFCMULCPHZ 2363
-VFCMULCPHZrm 2364
-VFCMULCPHZrmb 2365
-VFCMULCPHZrmbk 2366
-VFCMULCPHZrmbkz 2367
-VFCMULCPHZrmk 2368
-VFCMULCPHZrmkz 2369
-VFCMULCPHZrr 2370
-VFCMULCPHZrrb 2371
-VFCMULCPHZrrbk 2372
-VFCMULCPHZrrbkz 2373
-VFCMULCPHZrrk 2374
-VFCMULCPHZrrkz 2375
-VFCMULCSHZrm 2376
-VFCMULCSHZrmk 2377
-VFCMULCSHZrmkz 2378
-VFCMULCSHZrr 2379
-VFCMULCSHZrrb 2380
-VFCMULCSHZrrbk 2381
-VFCMULCSHZrrbkz 2382
-VFCMULCSHZrrk 2383
-VFCMULCSHZrrkz 2384
-VFIXUPIMMPDZ 2385
-VFIXUPIMMPDZrmbi 2386
-VFIXUPIMMPDZrmbik 2387
-VFIXUPIMMPDZrmbikz 2388
-VFIXUPIMMPDZrmi 2389
-VFIXUPIMMPDZrmik 2390
-VFIXUPIMMPDZrmikz 2391
-VFIXUPIMMPDZrri 2392
-VFIXUPIMMPDZrrib 2393
-VFIXUPIMMPDZrribk 2394
-VFIXUPIMMPDZrribkz 2395
-VFIXUPIMMPDZrrik 2396
-VFIXUPIMMPDZrrikz 2397
-VFIXUPIMMPSZ 2398
-VFIXUPIMMPSZrmbi 2399
-VFIXUPIMMPSZrmbik 2400
-VFIXUPIMMPSZrmbikz 2401
-VFIXUPIMMPSZrmi 2402
-VFIXUPIMMPSZrmik 2403
-VFIXUPIMMPSZrmikz 2404
-VFIXUPIMMPSZrri 2405
-VFIXUPIMMPSZrrib 2406
-VFIXUPIMMPSZrribk 2407
-VFIXUPIMMPSZrribkz 2408
-VFIXUPIMMPSZrrik 2409
-VFIXUPIMMPSZrrikz 2410
-VFIXUPIMMSDZrmi 2411
-VFIXUPIMMSDZrmik 2412
-VFIXUPIMMSDZrmikz 2413
-VFIXUPIMMSDZrri 2414
-VFIXUPIMMSDZrrib 2415
-VFIXUPIMMSDZrribk 2416
-VFIXUPIMMSDZrribkz 2417
-VFIXUPIMMSDZrrik 2418
-VFIXUPIMMSDZrrikz 2419
-VFIXUPIMMSSZrmi 2420
-VFIXUPIMMSSZrmik 2421
-VFIXUPIMMSSZrmikz 2422
-VFIXUPIMMSSZrri 2423
-VFIXUPIMMSSZrrib 2424
-VFIXUPIMMSSZrribk 2425
-VFIXUPIMMSSZrribkz 2426
-VFIXUPIMMSSZrrik 2427
-VFIXUPIMMSSZrrikz 2428
-VFMADD 2429
-VFMADDCPHZ 2430
-VFMADDCPHZm 2431
-VFMADDCPHZmb 2432
-VFMADDCPHZmbk 2433
-VFMADDCPHZmbkz 2434
-VFMADDCPHZmk 2435
-VFMADDCPHZmkz 2436
-VFMADDCPHZr 2437
-VFMADDCPHZrb 2438
-VFMADDCPHZrbk 2439
-VFMADDCPHZrbkz 2440
-VFMADDCPHZrk 2441
-VFMADDCPHZrkz 2442
-VFMADDCSHZm 2443
-VFMADDCSHZmk 2444
-VFMADDCSHZmkz 2445
-VFMADDCSHZr 2446
-VFMADDCSHZrb 2447
-VFMADDCSHZrbk 2448
-VFMADDCSHZrbkz 2449
-VFMADDCSHZrk 2450
-VFMADDCSHZrkz 2451
-VFMADDPD 2452
-VFMADDPS 2453
-VFMADDSD 2454
-VFMADDSS 2455
-VFMADDSUB 2456
-VFMADDSUBPD 2457
-VFMADDSUBPS 2458
-VFMSUB 2459
-VFMSUBADD 2460
-VFMSUBADDPD 2461
-VFMSUBADDPS 2462
-VFMSUBPD 2463
-VFMSUBPS 2464
-VFMSUBSD 2465
-VFMSUBSS 2466
-VFMULCPHZ 2467
-VFMULCPHZrm 2468
-VFMULCPHZrmb 2469
-VFMULCPHZrmbk 2470
-VFMULCPHZrmbkz 2471
-VFMULCPHZrmk 2472
-VFMULCPHZrmkz 2473
-VFMULCPHZrr 2474
-VFMULCPHZrrb 2475
-VFMULCPHZrrbk 2476
-VFMULCPHZrrbkz 2477
-VFMULCPHZrrk 2478
-VFMULCPHZrrkz 2479
-VFMULCSHZrm 2480
-VFMULCSHZrmk 2481
-VFMULCSHZrmkz 2482
-VFMULCSHZrr 2483
-VFMULCSHZrrb 2484
-VFMULCSHZrrbk 2485
-VFMULCSHZrrbkz 2486
-VFMULCSHZrrk 2487
-VFMULCSHZrrkz 2488
-VFNMADD 2489
-VFNMADDPD 2490
-VFNMADDPS 2491
-VFNMADDSD 2492
-VFNMADDSS 2493
-VFNMSUB 2494
-VFNMSUBPD 2495
-VFNMSUBPS 2496
-VFNMSUBSD 2497
-VFNMSUBSS 2498
-VFPCLASSBF 2499
-VFPCLASSPDZ 2500
-VFPCLASSPDZmbi 2501
-VFPCLASSPDZmbik 2502
-VFPCLASSPDZmi 2503
-VFPCLASSPDZmik 2504
-VFPCLASSPDZri 2505
-VFPCLASSPDZrik 2506
-VFPCLASSPHZ 2507
-VFPCLASSPHZmbi 2508
-VFPCLASSPHZmbik 2509
-VFPCLASSPHZmi 2510
-VFPCLASSPHZmik 2511
-VFPCLASSPHZri 2512
-VFPCLASSPHZrik 2513
-VFPCLASSPSZ 2514
-VFPCLASSPSZmbi 2515
-VFPCLASSPSZmbik 2516
-VFPCLASSPSZmi 2517
-VFPCLASSPSZmik 2518
-VFPCLASSPSZri 2519
-VFPCLASSPSZrik 2520
-VFPCLASSSDZmi 2521
-VFPCLASSSDZmik 2522
-VFPCLASSSDZri 2523
-VFPCLASSSDZrik 2524
-VFPCLASSSHZmi 2525
-VFPCLASSSHZmik 2526
-VFPCLASSSHZri 2527
-VFPCLASSSHZrik 2528
-VFPCLASSSSZmi 2529
-VFPCLASSSSZmik 2530
-VFPCLASSSSZri 2531
-VFPCLASSSSZrik 2532
-VFRCZPDYrm 2533
-VFRCZPDYrr 2534
-VFRCZPDrm 2535
-VFRCZPDrr 2536
-VFRCZPSYrm 2537
-VFRCZPSYrr 2538
-VFRCZPSrm 2539
-VFRCZPSrr 2540
-VFRCZSDrm 2541
-VFRCZSDrr 2542
-VFRCZSSrm 2543
-VFRCZSSrr 2544
-VGATHERDPDYrm 2545
-VGATHERDPDZ 2546
-VGATHERDPDZrm 2547
-VGATHERDPDrm 2548
-VGATHERDPSYrm 2549
-VGATHERDPSZ 2550
-VGATHERDPSZrm 2551
-VGATHERDPSrm 2552
-VGATHERPF 2553
-VGATHERQPDYrm 2554
-VGATHERQPDZ 2555
-VGATHERQPDZrm 2556
-VGATHERQPDrm 2557
-VGATHERQPSYrm 2558
-VGATHERQPSZ 2559
-VGATHERQPSZrm 2560
-VGATHERQPSrm 2561
-VGETEXPBF 2562
-VGETEXPPDZ 2563
-VGETEXPPDZm 2564
-VGETEXPPDZmb 2565
-VGETEXPPDZmbk 2566
-VGETEXPPDZmbkz 2567
-VGETEXPPDZmk 2568
-VGETEXPPDZmkz 2569
-VGETEXPPDZr 2570
-VGETEXPPDZrb 2571
-VGETEXPPDZrbk 2572
-VGETEXPPDZrbkz 2573
-VGETEXPPDZrk 2574
-VGETEXPPDZrkz 2575
-VGETEXPPHZ 2576
-VGETEXPPHZm 2577
-VGETEXPPHZmb 2578
-VGETEXPPHZmbk 2579
-VGETEXPPHZmbkz 2580
-VGETEXPPHZmk 2581
-VGETEXPPHZmkz 2582
-VGETEXPPHZr 2583
-VGETEXPPHZrb 2584
-VGETEXPPHZrbk 2585
-VGETEXPPHZrbkz 2586
-VGETEXPPHZrk 2587
-VGETEXPPHZrkz 2588
-VGETEXPPSZ 2589
-VGETEXPPSZm 2590
-VGETEXPPSZmb 2591
-VGETEXPPSZmbk 2592
-VGETEXPPSZmbkz 2593
-VGETEXPPSZmk 2594
-VGETEXPPSZmkz 2595
-VGETEXPPSZr 2596
-VGETEXPPSZrb 2597
-VGETEXPPSZrbk 2598
-VGETEXPPSZrbkz 2599
-VGETEXPPSZrk 2600
-VGETEXPPSZrkz 2601
-VGETEXPSDZm 2602
-VGETEXPSDZmk 2603
-VGETEXPSDZmkz 2604
-VGETEXPSDZr 2605
-VGETEXPSDZrb 2606
-VGETEXPSDZrbk 2607
-VGETEXPSDZrbkz 2608
-VGETEXPSDZrk 2609
-VGETEXPSDZrkz 2610
-VGETEXPSHZm 2611
-VGETEXPSHZmk 2612
-VGETEXPSHZmkz 2613
-VGETEXPSHZr 2614
-VGETEXPSHZrb 2615
-VGETEXPSHZrbk 2616
-VGETEXPSHZrbkz 2617
-VGETEXPSHZrk 2618
-VGETEXPSHZrkz 2619
-VGETEXPSSZm 2620
-VGETEXPSSZmk 2621
-VGETEXPSSZmkz 2622
-VGETEXPSSZr 2623
-VGETEXPSSZrb 2624
-VGETEXPSSZrbk 2625
-VGETEXPSSZrbkz 2626
-VGETEXPSSZrk 2627
-VGETEXPSSZrkz 2628
-VGETMANTBF 2629
-VGETMANTPDZ 2630
-VGETMANTPDZrmbi 2631
-VGETMANTPDZrmbik 2632
-VGETMANTPDZrmbikz 2633
-VGETMANTPDZrmi 2634
-VGETMANTPDZrmik 2635
-VGETMANTPDZrmikz 2636
-VGETMANTPDZrri 2637
-VGETMANTPDZrrib 2638
-VGETMANTPDZrribk 2639
-VGETMANTPDZrribkz 2640
-VGETMANTPDZrrik 2641
-VGETMANTPDZrrikz 2642
-VGETMANTPHZ 2643
-VGETMANTPHZrmbi 2644
-VGETMANTPHZrmbik 2645
-VGETMANTPHZrmbikz 2646
-VGETMANTPHZrmi 2647
-VGETMANTPHZrmik 2648
-VGETMANTPHZrmikz 2649
-VGETMANTPHZrri 2650
-VGETMANTPHZrrib 2651
-VGETMANTPHZrribk 2652
-VGETMANTPHZrribkz 2653
-VGETMANTPHZrrik 2654
-VGETMANTPHZrrikz 2655
-VGETMANTPSZ 2656
-VGETMANTPSZrmbi 2657
-VGETMANTPSZrmbik 2658
-VGETMANTPSZrmbikz 2659
-VGETMANTPSZrmi 2660
-VGETMANTPSZrmik 2661
-VGETMANTPSZrmikz 2662
-VGETMANTPSZrri 2663
-VGETMANTPSZrrib 2664
-VGETMANTPSZrribk 2665
-VGETMANTPSZrribkz 2666
-VGETMANTPSZrrik 2667
-VGETMANTPSZrrikz 2668
-VGETMANTSDZrmi 2669
-VGETMANTSDZrmik 2670
-VGETMANTSDZrmikz 2671
-VGETMANTSDZrri 2672
-VGETMANTSDZrrib 2673
-VGETMANTSDZrribk 2674
-VGETMANTSDZrribkz 2675
-VGETMANTSDZrrik 2676
-VGETMANTSDZrrikz 2677
-VGETMANTSHZrmi 2678
-VGETMANTSHZrmik 2679
-VGETMANTSHZrmikz 2680
-VGETMANTSHZrri 2681
-VGETMANTSHZrrib 2682
-VGETMANTSHZrribk 2683
-VGETMANTSHZrribkz 2684
-VGETMANTSHZrrik 2685
-VGETMANTSHZrrikz 2686
-VGETMANTSSZrmi 2687
-VGETMANTSSZrmik 2688
-VGETMANTSSZrmikz 2689
-VGETMANTSSZrri 2690
-VGETMANTSSZrrib 2691
-VGETMANTSSZrribk 2692
-VGETMANTSSZrribkz 2693
-VGETMANTSSZrrik 2694
-VGETMANTSSZrrikz 2695
-VGF 2696
-VHADDPDYrm 2697
-VHADDPDYrr 2698
-VHADDPDrm 2699
-VHADDPDrr 2700
-VHADDPSYrm 2701
-VHADDPSYrr 2702
-VHADDPSrm 2703
-VHADDPSrr 2704
-VHSUBPDYrm 2705
-VHSUBPDYrr 2706
-VHSUBPDrm 2707
-VHSUBPDrr 2708
-VHSUBPSYrm 2709
-VHSUBPSYrr 2710
-VHSUBPSrm 2711
-VHSUBPSrr 2712
-VINSERTF 2713
-VINSERTI 2714
-VINSERTPSZrmi 2715
-VINSERTPSZrri 2716
-VINSERTPSrmi 2717
-VINSERTPSrri 2718
-VLDDQUYrm 2719
-VLDDQUrm 2720
-VLDMXCSR 2721
-VMASKMOVDQU 2722
-VMASKMOVPDYmr 2723
-VMASKMOVPDYrm 2724
-VMASKMOVPDmr 2725
-VMASKMOVPDrm 2726
-VMASKMOVPSYmr 2727
-VMASKMOVPSYrm 2728
-VMASKMOVPSmr 2729
-VMASKMOVPSrm 2730
-VMAXBF 2731
-VMAXCPDYrm 2732
-VMAXCPDYrr 2733
-VMAXCPDZ 2734
-VMAXCPDZrm 2735
-VMAXCPDZrmb 2736
-VMAXCPDZrmbk 2737
-VMAXCPDZrmbkz 2738
-VMAXCPDZrmk 2739
-VMAXCPDZrmkz 2740
-VMAXCPDZrr 2741
-VMAXCPDZrrk 2742
-VMAXCPDZrrkz 2743
-VMAXCPDrm 2744
-VMAXCPDrr 2745
-VMAXCPHZ 2746
-VMAXCPHZrm 2747
-VMAXCPHZrmb 2748
-VMAXCPHZrmbk 2749
-VMAXCPHZrmbkz 2750
-VMAXCPHZrmk 2751
-VMAXCPHZrmkz 2752
-VMAXCPHZrr 2753
-VMAXCPHZrrk 2754
-VMAXCPHZrrkz 2755
-VMAXCPSYrm 2756
-VMAXCPSYrr 2757
-VMAXCPSZ 2758
-VMAXCPSZrm 2759
-VMAXCPSZrmb 2760
-VMAXCPSZrmbk 2761
-VMAXCPSZrmbkz 2762
-VMAXCPSZrmk 2763
-VMAXCPSZrmkz 2764
-VMAXCPSZrr 2765
-VMAXCPSZrrk 2766
-VMAXCPSZrrkz 2767
-VMAXCPSrm 2768
-VMAXCPSrr 2769
-VMAXCSDZrm 2770
-VMAXCSDZrr 2771
-VMAXCSDrm 2772
-VMAXCSDrr 2773
-VMAXCSHZrm 2774
-VMAXCSHZrr 2775
-VMAXCSSZrm 2776
-VMAXCSSZrr 2777
-VMAXCSSrm 2778
-VMAXCSSrr 2779
-VMAXPDYrm 2780
-VMAXPDYrr 2781
-VMAXPDZ 2782
-VMAXPDZrm 2783
-VMAXPDZrmb 2784
-VMAXPDZrmbk 2785
-VMAXPDZrmbkz 2786
-VMAXPDZrmk 2787
-VMAXPDZrmkz 2788
-VMAXPDZrr 2789
-VMAXPDZrrb 2790
-VMAXPDZrrbk 2791
-VMAXPDZrrbkz 2792
-VMAXPDZrrk 2793
-VMAXPDZrrkz 2794
-VMAXPDrm 2795
-VMAXPDrr 2796
-VMAXPHZ 2797
-VMAXPHZrm 2798
-VMAXPHZrmb 2799
-VMAXPHZrmbk 2800
-VMAXPHZrmbkz 2801
-VMAXPHZrmk 2802
-VMAXPHZrmkz 2803
-VMAXPHZrr 2804
-VMAXPHZrrb 2805
-VMAXPHZrrbk 2806
-VMAXPHZrrbkz 2807
-VMAXPHZrrk 2808
-VMAXPHZrrkz 2809
-VMAXPSYrm 2810
-VMAXPSYrr 2811
-VMAXPSZ 2812
-VMAXPSZrm 2813
-VMAXPSZrmb 2814
-VMAXPSZrmbk 2815
-VMAXPSZrmbkz 2816
-VMAXPSZrmk 2817
-VMAXPSZrmkz 2818
-VMAXPSZrr 2819
-VMAXPSZrrb 2820
-VMAXPSZrrbk 2821
-VMAXPSZrrbkz 2822
-VMAXPSZrrk 2823
-VMAXPSZrrkz 2824
-VMAXPSrm 2825
-VMAXPSrr 2826
-VMAXSDZrm 2827
-VMAXSDZrm_Int 2828
-VMAXSDZrmk_Int 2829
-VMAXSDZrmkz_Int 2830
-VMAXSDZrr 2831
-VMAXSDZrr_Int 2832
-VMAXSDZrrb_Int 2833
-VMAXSDZrrbk_Int 2834
-VMAXSDZrrbkz_Int 2835
-VMAXSDZrrk_Int 2836
-VMAXSDZrrkz_Int 2837
-VMAXSDrm 2838
-VMAXSDrm_Int 2839
-VMAXSDrr 2840
-VMAXSDrr_Int 2841
-VMAXSHZrm 2842
-VMAXSHZrm_Int 2843
-VMAXSHZrmk_Int 2844
-VMAXSHZrmkz_Int 2845
-VMAXSHZrr 2846
-VMAXSHZrr_Int 2847
-VMAXSHZrrb_Int 2848
-VMAXSHZrrbk_Int 2849
-VMAXSHZrrbkz_Int 2850
-VMAXSHZrrk_Int 2851
-VMAXSHZrrkz_Int 2852
-VMAXSSZrm 2853
-VMAXSSZrm_Int 2854
-VMAXSSZrmk_Int 2855
-VMAXSSZrmkz_Int 2856
-VMAXSSZrr 2857
-VMAXSSZrr_Int 2858
-VMAXSSZrrb_Int 2859
-VMAXSSZrrbk_Int 2860
-VMAXSSZrrbkz_Int 2861
-VMAXSSZrrk_Int 2862
-VMAXSSZrrkz_Int 2863
-VMAXSSrm 2864
-VMAXSSrm_Int 2865
-VMAXSSrr 2866
-VMAXSSrr_Int 2867
-VMCALL 2868
-VMCLEARm 2869
-VMFUNC 2870
-VMINBF 2871
-VMINCPDYrm 2872
-VMINCPDYrr 2873
-VMINCPDZ 2874
-VMINCPDZrm 2875
-VMINCPDZrmb 2876
-VMINCPDZrmbk 2877
-VMINCPDZrmbkz 2878
-VMINCPDZrmk 2879
-VMINCPDZrmkz 2880
-VMINCPDZrr 2881
-VMINCPDZrrk 2882
-VMINCPDZrrkz 2883
-VMINCPDrm 2884
-VMINCPDrr 2885
-VMINCPHZ 2886
-VMINCPHZrm 2887
-VMINCPHZrmb 2888
-VMINCPHZrmbk 2889
-VMINCPHZrmbkz 2890
-VMINCPHZrmk 2891
-VMINCPHZrmkz 2892
-VMINCPHZrr 2893
-VMINCPHZrrk 2894
-VMINCPHZrrkz 2895
-VMINCPSYrm 2896
-VMINCPSYrr 2897
-VMINCPSZ 2898
-VMINCPSZrm 2899
-VMINCPSZrmb 2900
-VMINCPSZrmbk 2901
-VMINCPSZrmbkz 2902
-VMINCPSZrmk 2903
-VMINCPSZrmkz 2904
-VMINCPSZrr 2905
-VMINCPSZrrk 2906
-VMINCPSZrrkz 2907
-VMINCPSrm 2908
-VMINCPSrr 2909
-VMINCSDZrm 2910
-VMINCSDZrr 2911
-VMINCSDrm 2912
-VMINCSDrr 2913
-VMINCSHZrm 2914
-VMINCSHZrr 2915
-VMINCSSZrm 2916
-VMINCSSZrr 2917
-VMINCSSrm 2918
-VMINCSSrr 2919
-VMINMAXBF 2920
-VMINMAXPDZ 2921
-VMINMAXPDZrmbi 2922
-VMINMAXPDZrmbik 2923
-VMINMAXPDZrmbikz 2924
-VMINMAXPDZrmi 2925
-VMINMAXPDZrmik 2926
-VMINMAXPDZrmikz 2927
-VMINMAXPDZrri 2928
-VMINMAXPDZrrib 2929
-VMINMAXPDZrribk 2930
-VMINMAXPDZrribkz 2931
-VMINMAXPDZrrik 2932
-VMINMAXPDZrrikz 2933
-VMINMAXPHZ 2934
-VMINMAXPHZrmbi 2935
-VMINMAXPHZrmbik 2936
-VMINMAXPHZrmbikz 2937
-VMINMAXPHZrmi 2938
-VMINMAXPHZrmik 2939
-VMINMAXPHZrmikz 2940
-VMINMAXPHZrri 2941
-VMINMAXPHZrrib 2942
-VMINMAXPHZrribk 2943
-VMINMAXPHZrribkz 2944
-VMINMAXPHZrrik 2945
-VMINMAXPHZrrikz 2946
-VMINMAXPSZ 2947
-VMINMAXPSZrmbi 2948
-VMINMAXPSZrmbik 2949
-VMINMAXPSZrmbikz 2950
-VMINMAXPSZrmi 2951
-VMINMAXPSZrmik 2952
-VMINMAXPSZrmikz 2953
-VMINMAXPSZrri 2954
-VMINMAXPSZrrib 2955
-VMINMAXPSZrribk 2956
-VMINMAXPSZrribkz 2957
-VMINMAXPSZrrik 2958
-VMINMAXPSZrrikz 2959
-VMINMAXSDrmi 2960
-VMINMAXSDrmi_Int 2961
-VMINMAXSDrmik_Int 2962
-VMINMAXSDrmikz_Int 2963
-VMINMAXSDrri 2964
-VMINMAXSDrri_Int 2965
-VMINMAXSDrrib_Int 2966
-VMINMAXSDrribk_Int 2967
-VMINMAXSDrribkz_Int 2968
-VMINMAXSDrrik_Int 2969
-VMINMAXSDrrikz_Int 2970
-VMINMAXSHrmi 2971
-VMINMAXSHrmi_Int 2972
-VMINMAXSHrmik_Int 2973
-VMINMAXSHrmikz_Int 2974
-VMINMAXSHrri 2975
-VMINMAXSHrri_Int 2976
-VMINMAXSHrrib_Int 2977
-VMINMAXSHrribk_Int 2978
-VMINMAXSHrribkz_Int 2979
-VMINMAXSHrrik_Int 2980
-VMINMAXSHrrikz_Int 2981
-VMINMAXSSrmi 2982
-VMINMAXSSrmi_Int 2983
-VMINMAXSSrmik_Int 2984
-VMINMAXSSrmikz_Int 2985
-VMINMAXSSrri 2986
-VMINMAXSSrri_Int 2987
-VMINMAXSSrrib_Int 2988
-VMINMAXSSrribk_Int 2989
-VMINMAXSSrribkz_Int 2990
-VMINMAXSSrrik_Int 2991
-VMINMAXSSrrikz_Int 2992
-VMINPDYrm 2993
-VMINPDYrr 2994
-VMINPDZ 2995
-VMINPDZrm 2996
-VMINPDZrmb 2997
-VMINPDZrmbk 2998
-VMINPDZrmbkz 2999
-VMINPDZrmk 3000
-VMINPDZrmkz 3001
-VMINPDZrr 3002
-VMINPDZrrb 3003
-VMINPDZrrbk 3004
-VMINPDZrrbkz 3005
-VMINPDZrrk 3006
-VMINPDZrrkz 3007
-VMINPDrm 3008
-VMINPDrr 3009
-VMINPHZ 3010
-VMINPHZrm 3011
-VMINPHZrmb 3012
-VMINPHZrmbk 3013
-VMINPHZrmbkz 3014
-VMINPHZrmk 3015
-VMINPHZrmkz 3016
-VMINPHZrr 3017
-VMINPHZrrb 3018
-VMINPHZrrbk 3019
-VMINPHZrrbkz 3020
-VMINPHZrrk 3021
-VMINPHZrrkz 3022
-VMINPSYrm 3023
-VMINPSYrr 3024
-VMINPSZ 3025
-VMINPSZrm 3026
-VMINPSZrmb 3027
-VMINPSZrmbk 3028
-VMINPSZrmbkz 3029
-VMINPSZrmk 3030
-VMINPSZrmkz 3031
-VMINPSZrr 3032
-VMINPSZrrb 3033
-VMINPSZrrbk 3034
-VMINPSZrrbkz 3035
-VMINPSZrrk 3036
-VMINPSZrrkz 3037
-VMINPSrm 3038
-VMINPSrr 3039
-VMINSDZrm 3040
-VMINSDZrm_Int 3041
-VMINSDZrmk_Int 3042
-VMINSDZrmkz_Int 3043
-VMINSDZrr 3044
-VMINSDZrr_Int 3045
-VMINSDZrrb_Int 3046
-VMINSDZrrbk_Int 3047
-VMINSDZrrbkz_Int 3048
-VMINSDZrrk_Int 3049
-VMINSDZrrkz_Int 3050
-VMINSDrm 3051
-VMINSDrm_Int 3052
-VMINSDrr 3053
-VMINSDrr_Int 3054
-VMINSHZrm 3055
-VMINSHZrm_Int 3056
-VMINSHZrmk_Int 3057
-VMINSHZrmkz_Int 3058
-VMINSHZrr 3059
-VMINSHZrr_Int 3060
-VMINSHZrrb_Int 3061
-VMINSHZrrbk_Int 3062
-VMINSHZrrbkz_Int 3063
-VMINSHZrrk_Int 3064
-VMINSHZrrkz_Int 3065
-VMINSSZrm 3066
-VMINSSZrm_Int 3067
-VMINSSZrmk_Int 3068
-VMINSSZrmkz_Int 3069
-VMINSSZrr 3070
-VMINSSZrr_Int 3071
-VMINSSZrrb_Int 3072
-VMINSSZrrbk_Int 3073
-VMINSSZrrbkz_Int 3074
-VMINSSZrrk_Int 3075
-VMINSSZrrkz_Int 3076
-VMINSSrm 3077
-VMINSSrm_Int 3078
-VMINSSrr 3079
-VMINSSrr_Int 3080
-VMLAUNCH 3081
-VMLOAD 3082
-VMMCALL 3083
-VMOV 3084
-VMOVAPDYmr 3085
-VMOVAPDYrm 3086
-VMOVAPDYrr 3087
-VMOVAPDYrr_REV 3088
-VMOVAPDZ 3089
-VMOVAPDZmr 3090
-VMOVAPDZmrk 3091
-VMOVAPDZrm 3092
-VMOVAPDZrmk 3093
-VMOVAPDZrmkz 3094
-VMOVAPDZrr 3095
-VMOVAPDZrr_REV 3096
-VMOVAPDZrrk 3097
-VMOVAPDZrrk_REV 3098
-VMOVAPDZrrkz 3099
-VMOVAPDZrrkz_REV 3100
-VMOVAPDmr 3101
-VMOVAPDrm 3102
-VMOVAPDrr 3103
-VMOVAPDrr_REV 3104
-VMOVAPSYmr 3105
-VMOVAPSYrm 3106
-VMOVAPSYrr 3107
-VMOVAPSYrr_REV 3108
-VMOVAPSZ 3109
-VMOVAPSZmr 3110
-VMOVAPSZmrk 3111
-VMOVAPSZrm 3112
-VMOVAPSZrmk 3113
-VMOVAPSZrmkz 3114
-VMOVAPSZrr 3115
-VMOVAPSZrr_REV 3116
-VMOVAPSZrrk 3117
-VMOVAPSZrrk_REV 3118
-VMOVAPSZrrkz 3119
-VMOVAPSZrrkz_REV 3120
-VMOVAPSmr 3121
-VMOVAPSrm 3122
-VMOVAPSrr 3123
-VMOVAPSrr_REV 3124
-VMOVDDUPYrm 3125
-VMOVDDUPYrr 3126
-VMOVDDUPZ 3127
-VMOVDDUPZrm 3128
-VMOVDDUPZrmk 3129
-VMOVDDUPZrmkz 3130
-VMOVDDUPZrr 3131
-VMOVDDUPZrrk 3132
-VMOVDDUPZrrkz 3133
-VMOVDDUPrm 3134
-VMOVDDUPrr 3135
-VMOVDI 3136
-VMOVDQA 3137
-VMOVDQAYmr 3138
-VMOVDQAYrm 3139
-VMOVDQAYrr 3140
-VMOVDQAYrr_REV 3141
-VMOVDQAmr 3142
-VMOVDQArm 3143
-VMOVDQArr 3144
-VMOVDQArr_REV 3145
-VMOVDQU 3146
-VMOVDQUYmr 3147
-VMOVDQUYrm 3148
-VMOVDQUYrr 3149
-VMOVDQUYrr_REV 3150
-VMOVDQUmr 3151
-VMOVDQUrm 3152
-VMOVDQUrr 3153
-VMOVDQUrr_REV 3154
-VMOVHLPSZrr 3155
-VMOVHLPSrr 3156
-VMOVHPDZ 3157
-VMOVHPDmr 3158
-VMOVHPDrm 3159
-VMOVHPSZ 3160
-VMOVHPSmr 3161
-VMOVHPSrm 3162
-VMOVLHPSZrr 3163
-VMOVLHPSrr 3164
-VMOVLPDZ 3165
-VMOVLPDmr 3166
-VMOVLPDrm 3167
-VMOVLPSZ 3168
-VMOVLPSmr 3169
-VMOVLPSrm 3170
-VMOVMSKPDYrr 3171
-VMOVMSKPDrr 3172
-VMOVMSKPSYrr 3173
-VMOVMSKPSrr 3174
-VMOVNTDQAYrm 3175
-VMOVNTDQAZ 3176
-VMOVNTDQAZrm 3177
-VMOVNTDQArm 3178
-VMOVNTDQYmr 3179
-VMOVNTDQZ 3180
-VMOVNTDQZmr 3181
-VMOVNTDQmr 3182
-VMOVNTPDYmr 3183
-VMOVNTPDZ 3184
-VMOVNTPDZmr 3185
-VMOVNTPDmr 3186
-VMOVNTPSYmr 3187
-VMOVNTPSZ 3188
-VMOVNTPSZmr 3189
-VMOVNTPSmr 3190
-VMOVPDI 3191
-VMOVPQI 3192
-VMOVPQIto 3193
-VMOVQI 3194
-VMOVRSBZ 3195
-VMOVRSBZm 3196
-VMOVRSBZmk 3197
-VMOVRSBZmkz 3198
-VMOVRSDZ 3199
-VMOVRSDZm 3200
-VMOVRSDZmk 3201
-VMOVRSDZmkz 3202
-VMOVRSQZ 3203
-VMOVRSQZm 3204
-VMOVRSQZmk 3205
-VMOVRSQZmkz 3206
-VMOVRSWZ 3207
-VMOVRSWZm 3208
-VMOVRSWZmk 3209
-VMOVRSWZmkz 3210
-VMOVSDZmr 3211
-VMOVSDZmrk 3212
-VMOVSDZrm 3213
-VMOVSDZrm_alt 3214
-VMOVSDZrmk 3215
-VMOVSDZrmkz 3216
-VMOVSDZrr 3217
-VMOVSDZrr_REV 3218
-VMOVSDZrrk 3219
-VMOVSDZrrk_REV 3220
-VMOVSDZrrkz 3221
-VMOVSDZrrkz_REV 3222
-VMOVSDmr 3223
-VMOVSDrm 3224
-VMOVSDrm_alt 3225
-VMOVSDrr 3226
-VMOVSDrr_REV 3227
-VMOVSDto 3228
-VMOVSH 3229
-VMOVSHDUPYrm 3230
-VMOVSHDUPYrr 3231
-VMOVSHDUPZ 3232
-VMOVSHDUPZrm 3233
-VMOVSHDUPZrmk 3234
-VMOVSHDUPZrmkz 3235
-VMOVSHDUPZrr 3236
-VMOVSHDUPZrrk 3237
-VMOVSHDUPZrrkz 3238
-VMOVSHDUPrm 3239
-VMOVSHDUPrr 3240
-VMOVSHZmr 3241
-VMOVSHZmrk 3242
-VMOVSHZrm 3243
-VMOVSHZrm_alt 3244
-VMOVSHZrmk 3245
-VMOVSHZrmkz 3246
-VMOVSHZrr 3247
-VMOVSHZrr_REV 3248
-VMOVSHZrrk 3249
-VMOVSHZrrk_REV 3250
-VMOVSHZrrkz 3251
-VMOVSHZrrkz_REV 3252
-VMOVSHtoW 3253
-VMOVSLDUPYrm 3254
-VMOVSLDUPYrr 3255
-VMOVSLDUPZ 3256
-VMOVSLDUPZrm 3257
-VMOVSLDUPZrmk 3258
-VMOVSLDUPZrmkz 3259
-VMOVSLDUPZrr 3260
-VMOVSLDUPZrrk 3261
-VMOVSLDUPZrrkz 3262
-VMOVSLDUPrm 3263
-VMOVSLDUPrr 3264
-VMOVSS 3265
-VMOVSSZmr 3266
-VMOVSSZmrk 3267
-VMOVSSZrm 3268
-VMOVSSZrm_alt 3269
-VMOVSSZrmk 3270
-VMOVSSZrmkz 3271
-VMOVSSZrr 3272
-VMOVSSZrr_REV 3273
-VMOVSSZrrk 3274
-VMOVSSZrrk_REV 3275
-VMOVSSZrrkz 3276
-VMOVSSZrrkz_REV 3277
-VMOVSSmr 3278
-VMOVSSrm 3279
-VMOVSSrm_alt 3280
-VMOVSSrr 3281
-VMOVSSrr_REV 3282
-VMOVUPDYmr 3283
-VMOVUPDYrm 3284
-VMOVUPDYrr 3285
-VMOVUPDYrr_REV 3286
-VMOVUPDZ 3287
-VMOVUPDZmr 3288
-VMOVUPDZmrk 3289
-VMOVUPDZrm 3290
-VMOVUPDZrmk 3291
-VMOVUPDZrmkz 3292
-VMOVUPDZrr 3293
-VMOVUPDZrr_REV 3294
-VMOVUPDZrrk 3295
-VMOVUPDZrrk_REV 3296
-VMOVUPDZrrkz 3297
-VMOVUPDZrrkz_REV 3298
-VMOVUPDmr 3299
-VMOVUPDrm 3300
-VMOVUPDrr 3301
-VMOVUPDrr_REV 3302
-VMOVUPSYmr 3303
-VMOVUPSYrm 3304
-VMOVUPSYrr 3305
-VMOVUPSYrr_REV 3306
-VMOVUPSZ 3307
-VMOVUPSZmr 3308
-VMOVUPSZmrk 3309
-VMOVUPSZrm 3310
-VMOVUPSZrmk 3311
-VMOVUPSZrmkz 3312
-VMOVUPSZrr 3313
-VMOVUPSZrr_REV 3314
-VMOVUPSZrrk 3315
-VMOVUPSZrrk_REV 3316
-VMOVUPSZrrkz 3317
-VMOVUPSZrrkz_REV 3318
-VMOVUPSmr 3319
-VMOVUPSrm 3320
-VMOVUPSrr 3321
-VMOVUPSrr_REV 3322
-VMOVW 3323
-VMOVWmr 3324
-VMOVWrm 3325
-VMOVZPDILo 3326
-VMOVZPQILo 3327
-VMOVZPWILo 3328
-VMPSADBWYrmi 3329
-VMPSADBWYrri 3330
-VMPSADBWZ 3331
-VMPSADBWZrmi 3332
-VMPSADBWZrmik 3333
-VMPSADBWZrmikz 3334
-VMPSADBWZrri 3335
-VMPSADBWZrrik 3336
-VMPSADBWZrrikz 3337
-VMPSADBWrmi 3338
-VMPSADBWrri 3339
-VMPTRLDm 3340
-VMPTRSTm 3341
-VMREAD 3342
-VMRESUME 3343
-VMRUN 3344
-VMSAVE 3345
-VMULBF 3346
-VMULPDYrm 3347
-VMULPDYrr 3348
-VMULPDZ 3349
-VMULPDZrm 3350
-VMULPDZrmb 3351
-VMULPDZrmbk 3352
-VMULPDZrmbkz 3353
-VMULPDZrmk 3354
-VMULPDZrmkz 3355
-VMULPDZrr 3356
-VMULPDZrrb 3357
-VMULPDZrrbk 3358
-VMULPDZrrbkz 3359
-VMULPDZrrk 3360
-VMULPDZrrkz 3361
-VMULPDrm 3362
-VMULPDrr 3363
-VMULPHZ 3364
-VMULPHZrm 3365
-VMULPHZrmb 3366
-VMULPHZrmbk 3367
-VMULPHZrmbkz 3368
-VMULPHZrmk 3369
-VMULPHZrmkz 3370
-VMULPHZrr 3371
-VMULPHZrrb 3372
-VMULPHZrrbk 3373
-VMULPHZrrbkz 3374
-VMULPHZrrk 3375
-VMULPHZrrkz 3376
-VMULPSYrm 3377
-VMULPSYrr 3378
-VMULPSZ 3379
-VMULPSZrm 3380
-VMULPSZrmb 3381
-VMULPSZrmbk 3382
-VMULPSZrmbkz 3383
-VMULPSZrmk 3384
-VMULPSZrmkz 3385
-VMULPSZrr 3386
-VMULPSZrrb 3387
-VMULPSZrrbk 3388
-VMULPSZrrbkz 3389
-VMULPSZrrk 3390
-VMULPSZrrkz 3391
-VMULPSrm 3392
-VMULPSrr 3393
-VMULSDZrm 3394
-VMULSDZrm_Int 3395
-VMULSDZrmk_Int 3396
-VMULSDZrmkz_Int 3397
-VMULSDZrr 3398
-VMULSDZrr_Int 3399
-VMULSDZrrb_Int 3400
-VMULSDZrrbk_Int 3401
-VMULSDZrrbkz_Int 3402
-VMULSDZrrk_Int 3403
-VMULSDZrrkz_Int 3404
-VMULSDrm 3405
-VMULSDrm_Int 3406
-VMULSDrr 3407
-VMULSDrr_Int 3408
-VMULSHZrm 3409
-VMULSHZrm_Int 3410
-VMULSHZrmk_Int 3411
-VMULSHZrmkz_Int 3412
-VMULSHZrr 3413
-VMULSHZrr_Int 3414
-VMULSHZrrb_Int 3415
-VMULSHZrrbk_Int 3416
-VMULSHZrrbkz_Int 3417
-VMULSHZrrk_Int 3418
-VMULSHZrrkz_Int 3419
-VMULSSZrm 3420
-VMULSSZrm_Int 3421
-VMULSSZrmk_Int 3422
-VMULSSZrmkz_Int 3423
-VMULSSZrr 3424
-VMULSSZrr_Int 3425
-VMULSSZrrb_Int 3426
-VMULSSZrrbk_Int 3427
-VMULSSZrrbkz_Int 3428
-VMULSSZrrk_Int 3429
-VMULSSZrrkz_Int 3430
-VMULSSrm 3431
-VMULSSrm_Int 3432
-VMULSSrr 3433
-VMULSSrr_Int 3434
-VMWRITE 3435
-VMXOFF 3436
-VMXON 3437
-VORPDYrm 3438
-VORPDYrr 3439
-VORPDZ 3440
-VORPDZrm 3441
-VORPDZrmb 3442
-VORPDZrmbk 3443
-VORPDZrmbkz 3444
-VORPDZrmk 3445
-VORPDZrmkz 3446
-VORPDZrr 3447
-VORPDZrrk 3448
-VORPDZrrkz 3449
-VORPDrm 3450
-VORPDrr 3451
-VORPSYrm 3452
-VORPSYrr 3453
-VORPSZ 3454
-VORPSZrm 3455
-VORPSZrmb 3456
-VORPSZrmbk 3457
-VORPSZrmbkz 3458
-VORPSZrmk 3459
-VORPSZrmkz 3460
-VORPSZrr 3461
-VORPSZrrk 3462
-VORPSZrrkz 3463
-VORPSrm 3464
-VORPSrr 3465
-VP 3466
-VPABSBYrm 3467
-VPABSBYrr 3468
-VPABSBZ 3469
-VPABSBZrm 3470
-VPABSBZrmk 3471
-VPABSBZrmkz 3472
-VPABSBZrr 3473
-VPABSBZrrk 3474
-VPABSBZrrkz 3475
-VPABSBrm 3476
-VPABSBrr 3477
-VPABSDYrm 3478
-VPABSDYrr 3479
-VPABSDZ 3480
-VPABSDZrm 3481
-VPABSDZrmb 3482
-VPABSDZrmbk 3483
-VPABSDZrmbkz 3484
-VPABSDZrmk 3485
-VPABSDZrmkz 3486
-VPABSDZrr 3487
-VPABSDZrrk 3488
-VPABSDZrrkz 3489
-VPABSDrm 3490
-VPABSDrr 3491
-VPABSQZ 3492
-VPABSQZrm 3493
-VPABSQZrmb 3494
-VPABSQZrmbk 3495
-VPABSQZrmbkz 3496
-VPABSQZrmk 3497
-VPABSQZrmkz 3498
-VPABSQZrr 3499
-VPABSQZrrk 3500
-VPABSQZrrkz 3501
-VPABSWYrm 3502
-VPABSWYrr 3503
-VPABSWZ 3504
-VPABSWZrm 3505
-VPABSWZrmk 3506
-VPABSWZrmkz 3507
-VPABSWZrr 3508
-VPABSWZrrk 3509
-VPABSWZrrkz 3510
-VPABSWrm 3511
-VPABSWrr 3512
-VPACKSSDWYrm 3513
-VPACKSSDWYrr 3514
-VPACKSSDWZ 3515
-VPACKSSDWZrm 3516
-VPACKSSDWZrmb 3517
-VPACKSSDWZrmbk 3518
-VPACKSSDWZrmbkz 3519
-VPACKSSDWZrmk 3520
-VPACKSSDWZrmkz 3521
-VPACKSSDWZrr 3522
-VPACKSSDWZrrk 3523
-VPACKSSDWZrrkz 3524
-VPACKSSDWrm 3525
-VPACKSSDWrr 3526
-VPACKSSWBYrm 3527
-VPACKSSWBYrr 3528
-VPACKSSWBZ 3529
-VPACKSSWBZrm 3530
-VPACKSSWBZrmk 3531
-VPACKSSWBZrmkz 3532
-VPACKSSWBZrr 3533
-VPACKSSWBZrrk 3534
-VPACKSSWBZrrkz 3535
-VPACKSSWBrm 3536
-VPACKSSWBrr 3537
-VPACKUSDWYrm 3538
-VPACKUSDWYrr 3539
-VPACKUSDWZ 3540
-VPACKUSDWZrm 3541
-VPACKUSDWZrmb 3542
-VPACKUSDWZrmbk 3543
-VPACKUSDWZrmbkz 3544
-VPACKUSDWZrmk 3545
-VPACKUSDWZrmkz 3546
-VPACKUSDWZrr 3547
-VPACKUSDWZrrk 3548
-VPACKUSDWZrrkz 3549
-VPACKUSDWrm 3550
-VPACKUSDWrr 3551
-VPACKUSWBYrm 3552
-VPACKUSWBYrr 3553
-VPACKUSWBZ 3554
-VPACKUSWBZrm 3555
-VPACKUSWBZrmk 3556
-VPACKUSWBZrmkz 3557
-VPACKUSWBZrr 3558
-VPACKUSWBZrrk 3559
-VPACKUSWBZrrkz 3560
-VPACKUSWBrm 3561
-VPACKUSWBrr 3562
-VPADDBYrm 3563
-VPADDBYrr 3564
-VPADDBZ 3565
-VPADDBZrm 3566
-VPADDBZrmk 3567
-VPADDBZrmkz 3568
-VPADDBZrr 3569
-VPADDBZrrk 3570
-VPADDBZrrkz 3571
-VPADDBrm 3572
-VPADDBrr 3573
-VPADDDYrm 3574
-VPADDDYrr 3575
-VPADDDZ 3576
-VPADDDZrm 3577
-VPADDDZrmb 3578
-VPADDDZrmbk 3579
-VPADDDZrmbkz 3580
-VPADDDZrmk 3581
-VPADDDZrmkz 3582
-VPADDDZrr 3583
-VPADDDZrrk 3584
-VPADDDZrrkz 3585
-VPADDDrm 3586
-VPADDDrr 3587
-VPADDQYrm 3588
-VPADDQYrr 3589
-VPADDQZ 3590
-VPADDQZrm 3591
-VPADDQZrmb 3592
-VPADDQZrmbk 3593
-VPADDQZrmbkz 3594
-VPADDQZrmk 3595
-VPADDQZrmkz 3596
-VPADDQZrr 3597
-VPADDQZrrk 3598
-VPADDQZrrkz 3599
-VPADDQrm 3600
-VPADDQrr 3601
-VPADDSBYrm 3602
-VPADDSBYrr 3603
-VPADDSBZ 3604
-VPADDSBZrm 3605
-VPADDSBZrmk 3606
-VPADDSBZrmkz 3607
-VPADDSBZrr 3608
-VPADDSBZrrk 3609
-VPADDSBZrrkz 3610
-VPADDSBrm 3611
-VPADDSBrr 3612
-VPADDSWYrm 3613
-VPADDSWYrr 3614
-VPADDSWZ 3615
-VPADDSWZrm 3616
-VPADDSWZrmk 3617
-VPADDSWZrmkz 3618
-VPADDSWZrr 3619
-VPADDSWZrrk 3620
-VPADDSWZrrkz 3621
-VPADDSWrm 3622
-VPADDSWrr 3623
-VPADDUSBYrm 3624
-VPADDUSBYrr 3625
-VPADDUSBZ 3626
-VPADDUSBZrm 3627
-VPADDUSBZrmk 3628
-VPADDUSBZrmkz 3629
-VPADDUSBZrr 3630
-VPADDUSBZrrk 3631
-VPADDUSBZrrkz 3632
-VPADDUSBrm 3633
-VPADDUSBrr 3634
-VPADDUSWYrm 3635
-VPADDUSWYrr 3636
-VPADDUSWZ 3637
-VPADDUSWZrm 3638
-VPADDUSWZrmk 3639
-VPADDUSWZrmkz 3640
-VPADDUSWZrr 3641
-VPADDUSWZrrk 3642
-VPADDUSWZrrkz 3643
-VPADDUSWrm 3644
-VPADDUSWrr 3645
-VPADDWYrm 3646
-VPADDWYrr 3647
-VPADDWZ 3648
-VPADDWZrm 3649
-VPADDWZrmk 3650
-VPADDWZrmkz 3651
-VPADDWZrr 3652
-VPADDWZrrk 3653
-VPADDWZrrkz 3654
-VPADDWrm 3655
-VPADDWrr 3656
-VPALIGNRYrmi 3657
-VPALIGNRYrri 3658
-VPALIGNRZ 3659
-VPALIGNRZrmi 3660
-VPALIGNRZrmik 3661
-VPALIGNRZrmikz 3662
-VPALIGNRZrri 3663
-VPALIGNRZrrik 3664
-VPALIGNRZrrikz 3665
-VPALIGNRrmi 3666
-VPALIGNRrri 3667
-VPANDDZ 3668
-VPANDDZrm 3669
-VPANDDZrmb 3670
-VPANDDZrmbk 3671
-VPANDDZrmbkz 3672
-VPANDDZrmk 3673
-VPANDDZrmkz 3674
-VPANDDZrr 3675
-VPANDDZrrk 3676
-VPANDDZrrkz 3677
-VPANDNDZ 3678
-VPANDNDZrm 3679
-VPANDNDZrmb 3680
-VPANDNDZrmbk 3681
-VPANDNDZrmbkz 3682
-VPANDNDZrmk 3683
-VPANDNDZrmkz 3684
-VPANDNDZrr 3685
-VPANDNDZrrk 3686
-VPANDNDZrrkz 3687
-VPANDNQZ 3688
-VPANDNQZrm 3689
-VPANDNQZrmb 3690
-VPANDNQZrmbk 3691
-VPANDNQZrmbkz 3692
-VPANDNQZrmk 3693
-VPANDNQZrmkz 3694
-VPANDNQZrr 3695
-VPANDNQZrrk 3696
-VPANDNQZrrkz 3697
-VPANDNYrm 3698
-VPANDNYrr 3699
-VPANDNrm 3700
-VPANDNrr 3701
-VPANDQZ 3702
-VPANDQZrm 3703
-VPANDQZrmb 3704
-VPANDQZrmbk 3705
-VPANDQZrmbkz 3706
-VPANDQZrmk 3707
-VPANDQZrmkz 3708
-VPANDQZrr 3709
-VPANDQZrrk 3710
-VPANDQZrrkz 3711
-VPANDYrm 3712
-VPANDYrr 3713
-VPANDrm 3714
-VPANDrr 3715
-VPAVGBYrm 3716
-VPAVGBYrr 3717
-VPAVGBZ 3718
-VPAVGBZrm 3719
-VPAVGBZrmk 3720
-VPAVGBZrmkz 3721
-VPAVGBZrr 3722
-VPAVGBZrrk 3723
-VPAVGBZrrkz 3724
-VPAVGBrm 3725
-VPAVGBrr 3726
-VPAVGWYrm 3727
-VPAVGWYrr 3728
-VPAVGWZ 3729
-VPAVGWZrm 3730
-VPAVGWZrmk 3731
-VPAVGWZrmkz 3732
-VPAVGWZrr 3733
-VPAVGWZrrk 3734
-VPAVGWZrrkz 3735
-VPAVGWrm 3736
-VPAVGWrr 3737
-VPBLENDDYrmi 3738
-VPBLENDDYrri 3739
-VPBLENDDrmi 3740
-VPBLENDDrri 3741
-VPBLENDMBZ 3742
-VPBLENDMBZrm 3743
-VPBLENDMBZrmk 3744
-VPBLENDMBZrmkz 3745
-VPBLENDMBZrr 3746
-VPBLENDMBZrrk 3747
-VPBLENDMBZrrkz 3748
-VPBLENDMDZ 3749
-VPBLENDMDZrm 3750
-VPBLENDMDZrmb 3751
-VPBLENDMDZrmbk 3752
-VPBLENDMDZrmbkz 3753
-VPBLENDMDZrmk 3754
-VPBLENDMDZrmkz 3755
-VPBLENDMDZrr 3756
-VPBLENDMDZrrk 3757
-VPBLENDMDZrrkz 3758
-VPBLENDMQZ 3759
-VPBLENDMQZrm 3760
-VPBLENDMQZrmb 3761
-VPBLENDMQZrmbk 3762
-VPBLENDMQZrmbkz 3763
-VPBLENDMQZrmk 3764
-VPBLENDMQZrmkz 3765
-VPBLENDMQZrr 3766
-VPBLENDMQZrrk 3767
-VPBLENDMQZrrkz 3768
-VPBLENDMWZ 3769
-VPBLENDMWZrm 3770
-VPBLENDMWZrmk 3771
-VPBLENDMWZrmkz 3772
-VPBLENDMWZrr 3773
-VPBLENDMWZrrk 3774
-VPBLENDMWZrrkz 3775
-VPBLENDVBYrmr 3776
-VPBLENDVBYrrr 3777
-VPBLENDVBrmr 3778
-VPBLENDVBrrr 3779
-VPBLENDWYrmi 3780
-VPBLENDWYrri 3781
-VPBLENDWrmi 3782
-VPBLENDWrri 3783
-VPBROADCASTBYrm 3784
-VPBROADCASTBYrr 3785
-VPBROADCASTBZ 3786
-VPBROADCASTBZrm 3787
-VPBROADCASTBZrmk 3788
-VPBROADCASTBZrmkz 3789
-VPBROADCASTBZrr 3790
-VPBROADCASTBZrrk 3791
-VPBROADCASTBZrrkz 3792
-VPBROADCASTBrZ 3793
-VPBROADCASTBrZrr 3794
-VPBROADCASTBrZrrk 3795
-VPBROADCASTBrZrrkz 3796
-VPBROADCASTBrm 3797
-VPBROADCASTBrr 3798
-VPBROADCASTDYrm 3799
-VPBROADCASTDYrr 3800
-VPBROADCASTDZ 3801
-VPBROADCASTDZrm 3802
-VPBROADCASTDZrmk 3803
-VPBROADCASTDZrmkz 3804
-VPBROADCASTDZrr 3805
-VPBROADCASTDZrrk 3806
-VPBROADCASTDZrrkz 3807
-VPBROADCASTDrZ 3808
-VPBROADCASTDrZrr 3809
-VPBROADCASTDrZrrk 3810
-VPBROADCASTDrZrrkz 3811
-VPBROADCASTDrm 3812
-VPBROADCASTDrr 3813
-VPBROADCASTMB 3814
-VPBROADCASTMW 3815
-VPBROADCASTQYrm 3816
-VPBROADCASTQYrr 3817
-VPBROADCASTQZ 3818
-VPBROADCASTQZrm 3819
-VPBROADCASTQZrmk 3820
-VPBROADCASTQZrmkz 3821
-VPBROADCASTQZrr 3822
-VPBROADCASTQZrrk 3823
-VPBROADCASTQZrrkz 3824
-VPBROADCASTQrZ 3825
-VPBROADCASTQrZrr 3826
-VPBROADCASTQrZrrk 3827
-VPBROADCASTQrZrrkz 3828
-VPBROADCASTQrm 3829
-VPBROADCASTQrr 3830
-VPBROADCASTWYrm 3831
-VPBROADCASTWYrr 3832
-VPBROADCASTWZ 3833
-VPBROADCASTWZrm 3834
-VPBROADCASTWZrmk 3835
-VPBROADCASTWZrmkz 3836
-VPBROADCASTWZrr 3837
-VPBROADCASTWZrrk 3838
-VPBROADCASTWZrrkz 3839
-VPBROADCASTWrZ 3840
-VPBROADCASTWrZrr 3841
-VPBROADCASTWrZrrk 3842
-VPBROADCASTWrZrrkz 3843
-VPBROADCASTWrm 3844
-VPBROADCASTWrr 3845
-VPCLMULQDQYrmi 3846
-VPCLMULQDQYrri 3847
-VPCLMULQDQZ 3848
-VPCLMULQDQZrmi 3849
-VPCLMULQDQZrri 3850
-VPCLMULQDQrmi 3851
-VPCLMULQDQrri 3852
-VPCMOVYrmr 3853
-VPCMOVYrrm 3854
-VPCMOVYrrr 3855
-VPCMOVYrrr_REV 3856
-VPCMOVrmr 3857
-VPCMOVrrm 3858
-VPCMOVrrr 3859
-VPCMOVrrr_REV 3860
-VPCMPBZ 3861
-VPCMPBZrmi 3862
-VPCMPBZrmik 3863
-VPCMPBZrri 3864
-VPCMPBZrrik 3865
-VPCMPDZ 3866
-VPCMPDZrmbi 3867
-VPCMPDZrmbik 3868
-VPCMPDZrmi 3869
-VPCMPDZrmik 3870
-VPCMPDZrri 3871
-VPCMPDZrrik 3872
-VPCMPEQBYrm 3873
-VPCMPEQBYrr 3874
-VPCMPEQBZ 3875
-VPCMPEQBZrm 3876
-VPCMPEQBZrmk 3877
-VPCMPEQBZrr 3878
-VPCMPEQBZrrk 3879
-VPCMPEQBrm 3880
-VPCMPEQBrr 3881
-VPCMPEQDYrm 3882
-VPCMPEQDYrr 3883
-VPCMPEQDZ 3884
-VPCMPEQDZrm 3885
-VPCMPEQDZrmb 3886
-VPCMPEQDZrmbk 3887
-VPCMPEQDZrmk 3888
-VPCMPEQDZrr 3889
-VPCMPEQDZrrk 3890
-VPCMPEQDrm 3891
-VPCMPEQDrr 3892
-VPCMPEQQYrm 3893
-VPCMPEQQYrr 3894
-VPCMPEQQZ 3895
-VPCMPEQQZrm 3896
-VPCMPEQQZrmb 3897
-VPCMPEQQZrmbk 3898
-VPCMPEQQZrmk 3899
-VPCMPEQQZrr 3900
-VPCMPEQQZrrk 3901
-VPCMPEQQrm 3902
-VPCMPEQQrr 3903
-VPCMPEQWYrm 3904
-VPCMPEQWYrr 3905
-VPCMPEQWZ 3906
-VPCMPEQWZrm 3907
-VPCMPEQWZrmk 3908
-VPCMPEQWZrr 3909
-VPCMPEQWZrrk 3910
-VPCMPEQWrm 3911
-VPCMPEQWrr 3912
-VPCMPESTRIrmi 3913
-VPCMPESTRIrri 3914
-VPCMPESTRMrmi 3915
-VPCMPESTRMrri 3916
-VPCMPGTBYrm 3917
-VPCMPGTBYrr 3918
-VPCMPGTBZ 3919
-VPCMPGTBZrm 3920
-VPCMPGTBZrmk 3921
-VPCMPGTBZrr 3922
-VPCMPGTBZrrk 3923
-VPCMPGTBrm 3924
-VPCMPGTBrr 3925
-VPCMPGTDYrm 3926
-VPCMPGTDYrr 3927
-VPCMPGTDZ 3928
-VPCMPGTDZrm 3929
-VPCMPGTDZrmb 3930
-VPCMPGTDZrmbk 3931
-VPCMPGTDZrmk 3932
-VPCMPGTDZrr 3933
-VPCMPGTDZrrk 3934
-VPCMPGTDrm 3935
-VPCMPGTDrr 3936
-VPCMPGTQYrm 3937
-VPCMPGTQYrr 3938
-VPCMPGTQZ 3939
-VPCMPGTQZrm 3940
-VPCMPGTQZrmb 3941
-VPCMPGTQZrmbk 3942
-VPCMPGTQZrmk 3943
-VPCMPGTQZrr 3944
-VPCMPGTQZrrk 3945
-VPCMPGTQrm 3946
-VPCMPGTQrr 3947
-VPCMPGTWYrm 3948
-VPCMPGTWYrr 3949
-VPCMPGTWZ 3950
-VPCMPGTWZrm 3951
-VPCMPGTWZrmk 3952
-VPCMPGTWZrr 3953
-VPCMPGTWZrrk 3954
-VPCMPGTWrm 3955
-VPCMPGTWrr 3956
-VPCMPISTRIrmi 3957
-VPCMPISTRIrri 3958
-VPCMPISTRMrmi 3959
-VPCMPISTRMrri 3960
-VPCMPQZ 3961
-VPCMPQZrmbi 3962
-VPCMPQZrmbik 3963
-VPCMPQZrmi 3964
-VPCMPQZrmik 3965
-VPCMPQZrri 3966
-VPCMPQZrrik 3967
-VPCMPUBZ 3968
-VPCMPUBZrmi 3969
-VPCMPUBZrmik 3970
-VPCMPUBZrri 3971
-VPCMPUBZrrik 3972
-VPCMPUDZ 3973
-VPCMPUDZrmbi 3974
-VPCMPUDZrmbik 3975
-VPCMPUDZrmi 3976
-VPCMPUDZrmik 3977
-VPCMPUDZrri 3978
-VPCMPUDZrrik 3979
-VPCMPUQZ 3980
-VPCMPUQZrmbi 3981
-VPCMPUQZrmbik 3982
-VPCMPUQZrmi 3983
-VPCMPUQZrmik 3984
-VPCMPUQZrri 3985
-VPCMPUQZrrik 3986
-VPCMPUWZ 3987
-VPCMPUWZrmi 3988
-VPCMPUWZrmik 3989
-VPCMPUWZrri 3990
-VPCMPUWZrrik 3991
-VPCMPWZ 3992
-VPCMPWZrmi 3993
-VPCMPWZrmik 3994
-VPCMPWZrri 3995
-VPCMPWZrrik 3996
-VPCOMBmi 3997
-VPCOMBri 3998
-VPCOMDmi 3999
-VPCOMDri 4000
-VPCOMPRESSBZ 4001
-VPCOMPRESSBZmr 4002
-VPCOMPRESSBZmrk 4003
-VPCOMPRESSBZrr 4004
-VPCOMPRESSBZrrk 4005
-VPCOMPRESSBZrrkz 4006
-VPCOMPRESSDZ 4007
-VPCOMPRESSDZmr 4008
-VPCOMPRESSDZmrk 4009
-VPCOMPRESSDZrr 4010
-VPCOMPRESSDZrrk 4011
-VPCOMPRESSDZrrkz 4012
-VPCOMPRESSQZ 4013
-VPCOMPRESSQZmr 4014
-VPCOMPRESSQZmrk 4015
-VPCOMPRESSQZrr 4016
-VPCOMPRESSQZrrk 4017
-VPCOMPRESSQZrrkz 4018
-VPCOMPRESSWZ 4019
-VPCOMPRESSWZmr 4020
-VPCOMPRESSWZmrk 4021
-VPCOMPRESSWZrr 4022
-VPCOMPRESSWZrrk 4023
-VPCOMPRESSWZrrkz 4024
-VPCOMQmi 4025
-VPCOMQri 4026
-VPCOMUBmi 4027
-VPCOMUBri 4028
-VPCOMUDmi 4029
-VPCOMUDri 4030
-VPCOMUQmi 4031
-VPCOMUQri 4032
-VPCOMUWmi 4033
-VPCOMUWri 4034
-VPCOMWmi 4035
-VPCOMWri 4036
-VPCONFLICTDZ 4037
-VPCONFLICTDZrm 4038
-VPCONFLICTDZrmb 4039
-VPCONFLICTDZrmbk 4040
-VPCONFLICTDZrmbkz 4041
-VPCONFLICTDZrmk 4042
-VPCONFLICTDZrmkz 4043
-VPCONFLICTDZrr 4044
-VPCONFLICTDZrrk 4045
-VPCONFLICTDZrrkz 4046
-VPCONFLICTQZ 4047
-VPCONFLICTQZrm 4048
-VPCONFLICTQZrmb 4049
-VPCONFLICTQZrmbk 4050
-VPCONFLICTQZrmbkz 4051
-VPCONFLICTQZrmk 4052
-VPCONFLICTQZrmkz 4053
-VPCONFLICTQZrr 4054
-VPCONFLICTQZrrk 4055
-VPCONFLICTQZrrkz 4056
-VPDPBSSDSYrm 4057
-VPDPBSSDSYrr 4058
-VPDPBSSDSZ 4059
-VPDPBSSDSZrm 4060
-VPDPBSSDSZrmb 4061
-VPDPBSSDSZrmbk 4062
-VPDPBSSDSZrmbkz 4063
-VPDPBSSDSZrmk 4064
-VPDPBSSDSZrmkz 4065
-VPDPBSSDSZrr 4066
-VPDPBSSDSZrrk 4067
-VPDPBSSDSZrrkz 4068
-VPDPBSSDSrm 4069
-VPDPBSSDSrr 4070
-VPDPBSSDYrm 4071
-VPDPBSSDYrr 4072
-VPDPBSSDZ 4073
-VPDPBSSDZrm 4074
-VPDPBSSDZrmb 4075
-VPDPBSSDZrmbk 4076
-VPDPBSSDZrmbkz 4077
-VPDPBSSDZrmk 4078
-VPDPBSSDZrmkz 4079
-VPDPBSSDZrr 4080
-VPDPBSSDZrrk 4081
-VPDPBSSDZrrkz 4082
-VPDPBSSDrm 4083
-VPDPBSSDrr 4084
-VPDPBSUDSYrm 4085
-VPDPBSUDSYrr 4086
-VPDPBSUDSZ 4087
-VPDPBSUDSZrm 4088
-VPDPBSUDSZrmb 4089
-VPDPBSUDSZrmbk 4090
-VPDPBSUDSZrmbkz 4091
-VPDPBSUDSZrmk 4092
-VPDPBSUDSZrmkz 4093
-VPDPBSUDSZrr 4094
-VPDPBSUDSZrrk 4095
-VPDPBSUDSZrrkz 4096
-VPDPBSUDSrm 4097
-VPDPBSUDSrr 4098
-VPDPBSUDYrm 4099
-VPDPBSUDYrr 4100
-VPDPBSUDZ 4101
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-VPDPBUSDSZrrk 4123
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-VPERMPDZmbik 4361
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-VPERMPSZrmk 4385
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-VPERMQZmbikz 4395
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-VPERMQZmik 4397
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-VPERMQZrikz 4401
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-VPERMQZrmk 4406
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-VPGATHERDDrm 4468
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-VPGATHERDQZrm 4471
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-VPGATHERQDYrm 4473
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-VRANGESDZrrikz 6168
-VRANGESSZrmi 6169
-VRANGESSZrmik 6170
-VRANGESSZrmikz 6171
-VRANGESSZrri 6172
-VRANGESSZrrib 6173
-VRANGESSZrribk 6174
-VRANGESSZrribkz 6175
-VRANGESSZrrik 6176
-VRANGESSZrrikz 6177
-VRCP 6178
-VRCPBF 6179
-VRCPPHZ 6180
-VRCPPHZm 6181
-VRCPPHZmb 6182
-VRCPPHZmbk 6183
-VRCPPHZmbkz 6184
-VRCPPHZmk 6185
-VRCPPHZmkz 6186
-VRCPPHZr 6187
-VRCPPHZrk 6188
-VRCPPHZrkz 6189
-VRCPPSYm 6190
-VRCPPSYr 6191
-VRCPPSm 6192
-VRCPPSr 6193
-VRCPSHZrm 6194
-VRCPSHZrmk 6195
-VRCPSHZrmkz 6196
-VRCPSHZrr 6197
-VRCPSHZrrk 6198
-VRCPSHZrrkz 6199
-VRCPSSm 6200
-VRCPSSm_Int 6201
-VRCPSSr 6202
-VRCPSSr_Int 6203
-VREDUCEBF 6204
-VREDUCEPDZ 6205
-VREDUCEPDZrmbi 6206
-VREDUCEPDZrmbik 6207
-VREDUCEPDZrmbikz 6208
-VREDUCEPDZrmi 6209
-VREDUCEPDZrmik 6210
-VREDUCEPDZrmikz 6211
-VREDUCEPDZrri 6212
-VREDUCEPDZrrib 6213
-VREDUCEPDZrribk 6214
-VREDUCEPDZrribkz 6215
-VREDUCEPDZrrik 6216
-VREDUCEPDZrrikz 6217
-VREDUCEPHZ 6218
-VREDUCEPHZrmbi 6219
-VREDUCEPHZrmbik 6220
-VREDUCEPHZrmbikz 6221
-VREDUCEPHZrmi 6222
-VREDUCEPHZrmik 6223
-VREDUCEPHZrmikz 6224
-VREDUCEPHZrri 6225
-VREDUCEPHZrrib 6226
-VREDUCEPHZrribk 6227
-VREDUCEPHZrribkz 6228
-VREDUCEPHZrrik 6229
-VREDUCEPHZrrikz 6230
-VREDUCEPSZ 6231
-VREDUCEPSZrmbi 6232
-VREDUCEPSZrmbik 6233
-VREDUCEPSZrmbikz 6234
-VREDUCEPSZrmi 6235
-VREDUCEPSZrmik 6236
-VREDUCEPSZrmikz 6237
-VREDUCEPSZrri 6238
-VREDUCEPSZrrib 6239
-VREDUCEPSZrribk 6240
-VREDUCEPSZrribkz 6241
-VREDUCEPSZrrik 6242
-VREDUCEPSZrrikz 6243
-VREDUCESDZrmi 6244
-VREDUCESDZrmik 6245
-VREDUCESDZrmikz 6246
-VREDUCESDZrri 6247
-VREDUCESDZrrib 6248
-VREDUCESDZrribk 6249
-VREDUCESDZrribkz 6250
-VREDUCESDZrrik 6251
-VREDUCESDZrrikz 6252
-VREDUCESHZrmi 6253
-VREDUCESHZrmik 6254
-VREDUCESHZrmikz 6255
-VREDUCESHZrri 6256
-VREDUCESHZrrib 6257
-VREDUCESHZrribk 6258
-VREDUCESHZrribkz 6259
-VREDUCESHZrrik 6260
-VREDUCESHZrrikz 6261
-VREDUCESSZrmi 6262
-VREDUCESSZrmik 6263
-VREDUCESSZrmikz 6264
-VREDUCESSZrri 6265
-VREDUCESSZrrib 6266
-VREDUCESSZrribk 6267
-VREDUCESSZrribkz 6268
-VREDUCESSZrrik 6269
-VREDUCESSZrrikz 6270
-VRNDSCALEBF 6271
-VRNDSCALEPDZ 6272
-VRNDSCALEPDZrmbi 6273
-VRNDSCALEPDZrmbik 6274
-VRNDSCALEPDZrmbikz 6275
-VRNDSCALEPDZrmi 6276
-VRNDSCALEPDZrmik 6277
-VRNDSCALEPDZrmikz 6278
-VRNDSCALEPDZrri 6279
-VRNDSCALEPDZrrib 6280
-VRNDSCALEPDZrribk 6281
-VRNDSCALEPDZrribkz 6282
-VRNDSCALEPDZrrik 6283
-VRNDSCALEPDZrrikz 6284
-VRNDSCALEPHZ 6285
-VRNDSCALEPHZrmbi 6286
-VRNDSCALEPHZrmbik 6287
-VRNDSCALEPHZrmbikz 6288
-VRNDSCALEPHZrmi 6289
-VRNDSCALEPHZrmik 6290
-VRNDSCALEPHZrmikz 6291
-VRNDSCALEPHZrri 6292
-VRNDSCALEPHZrrib 6293
-VRNDSCALEPHZrribk 6294
-VRNDSCALEPHZrribkz 6295
-VRNDSCALEPHZrrik 6296
-VRNDSCALEPHZrrikz 6297
-VRNDSCALEPSZ 6298
-VRNDSCALEPSZrmbi 6299
-VRNDSCALEPSZrmbik 6300
-VRNDSCALEPSZrmbikz 6301
-VRNDSCALEPSZrmi 6302
-VRNDSCALEPSZrmik 6303
-VRNDSCALEPSZrmikz 6304
-VRNDSCALEPSZrri 6305
-VRNDSCALEPSZrrib 6306
-VRNDSCALEPSZrribk 6307
-VRNDSCALEPSZrribkz 6308
-VRNDSCALEPSZrrik 6309
-VRNDSCALEPSZrrikz 6310
-VRNDSCALESDZrmi 6311
-VRNDSCALESDZrmi_Int 6312
-VRNDSCALESDZrmik_Int 6313
-VRNDSCALESDZrmikz_Int 6314
-VRNDSCALESDZrri 6315
-VRNDSCALESDZrri_Int 6316
-VRNDSCALESDZrrib_Int 6317
-VRNDSCALESDZrribk_Int 6318
-VRNDSCALESDZrribkz_Int 6319
-VRNDSCALESDZrrik_Int 6320
-VRNDSCALESDZrrikz_Int 6321
-VRNDSCALESHZrmi 6322
-VRNDSCALESHZrmi_Int 6323
-VRNDSCALESHZrmik_Int 6324
-VRNDSCALESHZrmikz_Int 6325
-VRNDSCALESHZrri 6326
-VRNDSCALESHZrri_Int 6327
-VRNDSCALESHZrrib_Int 6328
-VRNDSCALESHZrribk_Int 6329
-VRNDSCALESHZrribkz_Int 6330
-VRNDSCALESHZrrik_Int 6331
-VRNDSCALESHZrrikz_Int 6332
-VRNDSCALESSZrmi 6333
-VRNDSCALESSZrmi_Int 6334
-VRNDSCALESSZrmik_Int 6335
-VRNDSCALESSZrmikz_Int 6336
-VRNDSCALESSZrri 6337
-VRNDSCALESSZrri_Int 6338
-VRNDSCALESSZrrib_Int 6339
-VRNDSCALESSZrribk_Int 6340
-VRNDSCALESSZrribkz_Int 6341
-VRNDSCALESSZrrik_Int 6342
-VRNDSCALESSZrrikz_Int 6343
-VROUNDPDYmi 6344
-VROUNDPDYri 6345
-VROUNDPDmi 6346
-VROUNDPDri 6347
-VROUNDPSYmi 6348
-VROUNDPSYri 6349
-VROUNDPSmi 6350
-VROUNDPSri 6351
-VROUNDSDmi 6352
-VROUNDSDmi_Int 6353
-VROUNDSDri 6354
-VROUNDSDri_Int 6355
-VROUNDSSmi 6356
-VROUNDSSmi_Int 6357
-VROUNDSSri 6358
-VROUNDSSri_Int 6359
-VRSQRT 6360
-VRSQRTBF 6361
-VRSQRTPHZ 6362
-VRSQRTPHZm 6363
-VRSQRTPHZmb 6364
-VRSQRTPHZmbk 6365
-VRSQRTPHZmbkz 6366
-VRSQRTPHZmk 6367
-VRSQRTPHZmkz 6368
-VRSQRTPHZr 6369
-VRSQRTPHZrk 6370
-VRSQRTPHZrkz 6371
-VRSQRTPSYm 6372
-VRSQRTPSYr 6373
-VRSQRTPSm 6374
-VRSQRTPSr 6375
-VRSQRTSHZrm 6376
-VRSQRTSHZrmk 6377
-VRSQRTSHZrmkz 6378
-VRSQRTSHZrr 6379
-VRSQRTSHZrrk 6380
-VRSQRTSHZrrkz 6381
-VRSQRTSSm 6382
-VRSQRTSSm_Int 6383
-VRSQRTSSr 6384
-VRSQRTSSr_Int 6385
-VSCALEFBF 6386
-VSCALEFPDZ 6387
-VSCALEFPDZrm 6388
-VSCALEFPDZrmb 6389
-VSCALEFPDZrmbk 6390
-VSCALEFPDZrmbkz 6391
-VSCALEFPDZrmk 6392
-VSCALEFPDZrmkz 6393
-VSCALEFPDZrr 6394
-VSCALEFPDZrrb 6395
-VSCALEFPDZrrbk 6396
-VSCALEFPDZrrbkz 6397
-VSCALEFPDZrrk 6398
-VSCALEFPDZrrkz 6399
-VSCALEFPHZ 6400
-VSCALEFPHZrm 6401
-VSCALEFPHZrmb 6402
-VSCALEFPHZrmbk 6403
-VSCALEFPHZrmbkz 6404
-VSCALEFPHZrmk 6405
-VSCALEFPHZrmkz 6406
-VSCALEFPHZrr 6407
-VSCALEFPHZrrb 6408
-VSCALEFPHZrrbk 6409
-VSCALEFPHZrrbkz 6410
-VSCALEFPHZrrk 6411
-VSCALEFPHZrrkz 6412
-VSCALEFPSZ 6413
-VSCALEFPSZrm 6414
-VSCALEFPSZrmb 6415
-VSCALEFPSZrmbk 6416
-VSCALEFPSZrmbkz 6417
-VSCALEFPSZrmk 6418
-VSCALEFPSZrmkz 6419
-VSCALEFPSZrr 6420
-VSCALEFPSZrrb 6421
-VSCALEFPSZrrbk 6422
-VSCALEFPSZrrbkz 6423
-VSCALEFPSZrrk 6424
-VSCALEFPSZrrkz 6425
-VSCALEFSDZrm 6426
-VSCALEFSDZrmk 6427
-VSCALEFSDZrmkz 6428
-VSCALEFSDZrr 6429
-VSCALEFSDZrrb_Int 6430
-VSCALEFSDZrrbk_Int 6431
-VSCALEFSDZrrbkz_Int 6432
-VSCALEFSDZrrk 6433
-VSCALEFSDZrrkz 6434
-VSCALEFSHZrm 6435
-VSCALEFSHZrmk 6436
-VSCALEFSHZrmkz 6437
-VSCALEFSHZrr 6438
-VSCALEFSHZrrb_Int 6439
-VSCALEFSHZrrbk_Int 6440
-VSCALEFSHZrrbkz_Int 6441
-VSCALEFSHZrrk 6442
-VSCALEFSHZrrkz 6443
-VSCALEFSSZrm 6444
-VSCALEFSSZrmk 6445
-VSCALEFSSZrmkz 6446
-VSCALEFSSZrr 6447
-VSCALEFSSZrrb_Int 6448
-VSCALEFSSZrrbk_Int 6449
-VSCALEFSSZrrbkz_Int 6450
-VSCALEFSSZrrk 6451
-VSCALEFSSZrrkz 6452
-VSCATTERDPDZ 6453
-VSCATTERDPDZmr 6454
-VSCATTERDPSZ 6455
-VSCATTERDPSZmr 6456
-VSCATTERPF 6457
-VSCATTERQPDZ 6458
-VSCATTERQPDZmr 6459
-VSCATTERQPSZ 6460
-VSCATTERQPSZmr 6461
-VSHA 6462
-VSHUFF 6463
-VSHUFI 6464
-VSHUFPDYrmi 6465
-VSHUFPDYrri 6466
-VSHUFPDZ 6467
-VSHUFPDZrmbi 6468
-VSHUFPDZrmbik 6469
-VSHUFPDZrmbikz 6470
-VSHUFPDZrmi 6471
-VSHUFPDZrmik 6472
-VSHUFPDZrmikz 6473
-VSHUFPDZrri 6474
-VSHUFPDZrrik 6475
-VSHUFPDZrrikz 6476
-VSHUFPDrmi 6477
-VSHUFPDrri 6478
-VSHUFPSYrmi 6479
-VSHUFPSYrri 6480
-VSHUFPSZ 6481
-VSHUFPSZrmbi 6482
-VSHUFPSZrmbik 6483
-VSHUFPSZrmbikz 6484
-VSHUFPSZrmi 6485
-VSHUFPSZrmik 6486
-VSHUFPSZrmikz 6487
-VSHUFPSZrri 6488
-VSHUFPSZrrik 6489
-VSHUFPSZrrikz 6490
-VSHUFPSrmi 6491
-VSHUFPSrri 6492
-VSM 6493
-VSQRTBF 6494
-VSQRTPDYm 6495
-VSQRTPDYr 6496
-VSQRTPDZ 6497
-VSQRTPDZm 6498
-VSQRTPDZmb 6499
-VSQRTPDZmbk 6500
-VSQRTPDZmbkz 6501
-VSQRTPDZmk 6502
-VSQRTPDZmkz 6503
-VSQRTPDZr 6504
-VSQRTPDZrb 6505
-VSQRTPDZrbk 6506
-VSQRTPDZrbkz 6507
-VSQRTPDZrk 6508
-VSQRTPDZrkz 6509
-VSQRTPDm 6510
-VSQRTPDr 6511
-VSQRTPHZ 6512
-VSQRTPHZm 6513
-VSQRTPHZmb 6514
-VSQRTPHZmbk 6515
-VSQRTPHZmbkz 6516
-VSQRTPHZmk 6517
-VSQRTPHZmkz 6518
-VSQRTPHZr 6519
-VSQRTPHZrb 6520
-VSQRTPHZrbk 6521
-VSQRTPHZrbkz 6522
-VSQRTPHZrk 6523
-VSQRTPHZrkz 6524
-VSQRTPSYm 6525
-VSQRTPSYr 6526
-VSQRTPSZ 6527
-VSQRTPSZm 6528
-VSQRTPSZmb 6529
-VSQRTPSZmbk 6530
-VSQRTPSZmbkz 6531
-VSQRTPSZmk 6532
-VSQRTPSZmkz 6533
-VSQRTPSZr 6534
-VSQRTPSZrb 6535
-VSQRTPSZrbk 6536
-VSQRTPSZrbkz 6537
-VSQRTPSZrk 6538
-VSQRTPSZrkz 6539
-VSQRTPSm 6540
-VSQRTPSr 6541
-VSQRTSDZm 6542
-VSQRTSDZm_Int 6543
-VSQRTSDZmk_Int 6544
-VSQRTSDZmkz_Int 6545
-VSQRTSDZr 6546
-VSQRTSDZr_Int 6547
-VSQRTSDZrb_Int 6548
-VSQRTSDZrbk_Int 6549
-VSQRTSDZrbkz_Int 6550
-VSQRTSDZrk_Int 6551
-VSQRTSDZrkz_Int 6552
-VSQRTSDm 6553
-VSQRTSDm_Int 6554
-VSQRTSDr 6555
-VSQRTSDr_Int 6556
-VSQRTSHZm 6557
-VSQRTSHZm_Int 6558
-VSQRTSHZmk_Int 6559
-VSQRTSHZmkz_Int 6560
-VSQRTSHZr 6561
-VSQRTSHZr_Int 6562
-VSQRTSHZrb_Int 6563
-VSQRTSHZrbk_Int 6564
-VSQRTSHZrbkz_Int 6565
-VSQRTSHZrk_Int 6566
-VSQRTSHZrkz_Int 6567
-VSQRTSSZm 6568
-VSQRTSSZm_Int 6569
-VSQRTSSZmk_Int 6570
-VSQRTSSZmkz_Int 6571
-VSQRTSSZr 6572
-VSQRTSSZr_Int 6573
-VSQRTSSZrb_Int 6574
-VSQRTSSZrbk_Int 6575
-VSQRTSSZrbkz_Int 6576
-VSQRTSSZrk_Int 6577
-VSQRTSSZrkz_Int 6578
-VSQRTSSm 6579
-VSQRTSSm_Int 6580
-VSQRTSSr 6581
-VSQRTSSr_Int 6582
-VSTMXCSR 6583
-VSUBBF 6584
-VSUBPDYrm 6585
-VSUBPDYrr 6586
-VSUBPDZ 6587
-VSUBPDZrm 6588
-VSUBPDZrmb 6589
-VSUBPDZrmbk 6590
-VSUBPDZrmbkz 6591
-VSUBPDZrmk 6592
-VSUBPDZrmkz 6593
-VSUBPDZrr 6594
-VSUBPDZrrb 6595
-VSUBPDZrrbk 6596
-VSUBPDZrrbkz 6597
-VSUBPDZrrk 6598
-VSUBPDZrrkz 6599
-VSUBPDrm 6600
-VSUBPDrr 6601
-VSUBPHZ 6602
-VSUBPHZrm 6603
-VSUBPHZrmb 6604
-VSUBPHZrmbk 6605
-VSUBPHZrmbkz 6606
-VSUBPHZrmk 6607
-VSUBPHZrmkz 6608
-VSUBPHZrr 6609
-VSUBPHZrrb 6610
-VSUBPHZrrbk 6611
-VSUBPHZrrbkz 6612
-VSUBPHZrrk 6613
-VSUBPHZrrkz 6614
-VSUBPSYrm 6615
-VSUBPSYrr 6616
-VSUBPSZ 6617
-VSUBPSZrm 6618
-VSUBPSZrmb 6619
-VSUBPSZrmbk 6620
-VSUBPSZrmbkz 6621
-VSUBPSZrmk 6622
-VSUBPSZrmkz 6623
-VSUBPSZrr 6624
-VSUBPSZrrb 6625
-VSUBPSZrrbk 6626
-VSUBPSZrrbkz 6627
-VSUBPSZrrk 6628
-VSUBPSZrrkz 6629
-VSUBPSrm 6630
-VSUBPSrr 6631
-VSUBSDZrm 6632
-VSUBSDZrm_Int 6633
-VSUBSDZrmk_Int 6634
-VSUBSDZrmkz_Int 6635
-VSUBSDZrr 6636
-VSUBSDZrr_Int 6637
-VSUBSDZrrb_Int 6638
-VSUBSDZrrbk_Int 6639
-VSUBSDZrrbkz_Int 6640
-VSUBSDZrrk_Int 6641
-VSUBSDZrrkz_Int 6642
-VSUBSDrm 6643
-VSUBSDrm_Int 6644
-VSUBSDrr 6645
-VSUBSDrr_Int 6646
-VSUBSHZrm 6647
-VSUBSHZrm_Int 6648
-VSUBSHZrmk_Int 6649
-VSUBSHZrmkz_Int 6650
-VSUBSHZrr 6651
-VSUBSHZrr_Int 6652
-VSUBSHZrrb_Int 6653
-VSUBSHZrrbk_Int 6654
-VSUBSHZrrbkz_Int 6655
-VSUBSHZrrk_Int 6656
-VSUBSHZrrkz_Int 6657
-VSUBSSZrm 6658
-VSUBSSZrm_Int 6659
-VSUBSSZrmk_Int 6660
-VSUBSSZrmkz_Int 6661
-VSUBSSZrr 6662
-VSUBSSZrr_Int 6663
-VSUBSSZrrb_Int 6664
-VSUBSSZrrbk_Int 6665
-VSUBSSZrrbkz_Int 6666
-VSUBSSZrrk_Int 6667
-VSUBSSZrrkz_Int 6668
-VSUBSSrm 6669
-VSUBSSrm_Int 6670
-VSUBSSrr 6671
-VSUBSSrr_Int 6672
-VTESTPDYrm 6673
-VTESTPDYrr 6674
-VTESTPDrm 6675
-VTESTPDrr 6676
-VTESTPSYrm 6677
-VTESTPSYrr 6678
-VTESTPSrm 6679
-VTESTPSrr 6680
-VUCOMISDZrm 6681
-VUCOMISDZrm_Int 6682
-VUCOMISDZrr 6683
-VUCOMISDZrr_Int 6684
-VUCOMISDZrrb 6685
-VUCOMISDrm 6686
-VUCOMISDrm_Int 6687
-VUCOMISDrr 6688
-VUCOMISDrr_Int 6689
-VUCOMISHZrm 6690
-VUCOMISHZrm_Int 6691
-VUCOMISHZrr 6692
-VUCOMISHZrr_Int 6693
-VUCOMISHZrrb 6694
-VUCOMISSZrm 6695
-VUCOMISSZrm_Int 6696
-VUCOMISSZrr 6697
-VUCOMISSZrr_Int 6698
-VUCOMISSZrrb 6699
-VUCOMISSrm 6700
-VUCOMISSrm_Int 6701
-VUCOMISSrr 6702
-VUCOMISSrr_Int 6703
-VUCOMXSDZrm 6704
-VUCOMXSDZrm_Int 6705
-VUCOMXSDZrr 6706
-VUCOMXSDZrr_Int 6707
-VUCOMXSDZrrb_Int 6708
-VUCOMXSHZrm 6709
-VUCOMXSHZrm_Int 6710
-VUCOMXSHZrr 6711
-VUCOMXSHZrr_Int 6712
-VUCOMXSHZrrb_Int 6713
-VUCOMXSSZrm 6714
-VUCOMXSSZrm_Int 6715
-VUCOMXSSZrr 6716
-VUCOMXSSZrr_Int 6717
-VUCOMXSSZrrb_Int 6718
-VUNPCKHPDYrm 6719
-VUNPCKHPDYrr 6720
-VUNPCKHPDZ 6721
-VUNPCKHPDZrm 6722
-VUNPCKHPDZrmb 6723
-VUNPCKHPDZrmbk 6724
-VUNPCKHPDZrmbkz 6725
-VUNPCKHPDZrmk 6726
-VUNPCKHPDZrmkz 6727
-VUNPCKHPDZrr 6728
-VUNPCKHPDZrrk 6729
-VUNPCKHPDZrrkz 6730
-VUNPCKHPDrm 6731
-VUNPCKHPDrr 6732
-VUNPCKHPSYrm 6733
-VUNPCKHPSYrr 6734
-VUNPCKHPSZ 6735
-VUNPCKHPSZrm 6736
-VUNPCKHPSZrmb 6737
-VUNPCKHPSZrmbk 6738
-VUNPCKHPSZrmbkz 6739
-VUNPCKHPSZrmk 6740
-VUNPCKHPSZrmkz 6741
-VUNPCKHPSZrr 6742
-VUNPCKHPSZrrk 6743
-VUNPCKHPSZrrkz 6744
-VUNPCKHPSrm 6745
-VUNPCKHPSrr 6746
-VUNPCKLPDYrm 6747
-VUNPCKLPDYrr 6748
-VUNPCKLPDZ 6749
-VUNPCKLPDZrm 6750
-VUNPCKLPDZrmb 6751
-VUNPCKLPDZrmbk 6752
-VUNPCKLPDZrmbkz 6753
-VUNPCKLPDZrmk 6754
-VUNPCKLPDZrmkz 6755
-VUNPCKLPDZrr 6756
-VUNPCKLPDZrrk 6757
-VUNPCKLPDZrrkz 6758
-VUNPCKLPDrm 6759
-VUNPCKLPDrr 6760
-VUNPCKLPSYrm 6761
-VUNPCKLPSYrr 6762
-VUNPCKLPSZ 6763
-VUNPCKLPSZrm 6764
-VUNPCKLPSZrmb 6765
-VUNPCKLPSZrmbk 6766
-VUNPCKLPSZrmbkz 6767
-VUNPCKLPSZrmk 6768
-VUNPCKLPSZrmkz 6769
-VUNPCKLPSZrr 6770
-VUNPCKLPSZrrk 6771
-VUNPCKLPSZrrkz 6772
-VUNPCKLPSrm 6773
-VUNPCKLPSrr 6774
-VXORPDYrm 6775
-VXORPDYrr 6776
-VXORPDZ 6777
-VXORPDZrm 6778
-VXORPDZrmb 6779
-VXORPDZrmbk 6780
-VXORPDZrmbkz 6781
-VXORPDZrmk 6782
-VXORPDZrmkz 6783
-VXORPDZrr 6784
-VXORPDZrrk 6785
-VXORPDZrrkz 6786
-VXORPDrm 6787
-VXORPDrr 6788
-VXORPSYrm 6789
-VXORPSYrr 6790
-VXORPSZ 6791
-VXORPSZrm 6792
-VXORPSZrmb 6793
-VXORPSZrmbk 6794
-VXORPSZrmbkz 6795
-VXORPSZrmk 6796
-VXORPSZrmkz 6797
-VXORPSZrr 6798
-VXORPSZrrk 6799
-VXORPSZrrkz 6800
-VXORPSrm 6801
-VXORPSrr 6802
-VZEROALL 6803
-VZEROUPPER 6804
-V_SET 6805
-V_SETALLONES 6806
-WAIT 6807
-WBINVD 6808
-WBNOINVD 6809
-WRFLAGS 6810
-WRFSBASE 6811
-WRGSBASE 6812
-WRMSR 6813
-WRMSRLIST 6814
-WRMSRNS 6815
-WRMSRNSir 6816
-WRMSRNSir_EVEX 6817
-WRPKRUr 6818
-WRSSD 6819
-WRSSD_EVEX 6820
-WRSSQ 6821
-WRSSQ_EVEX 6822
-WRUSSD 6823
-WRUSSD_EVEX 6824
-WRUSSQ 6825
-WRUSSQ_EVEX 6826
-XABORT 6827
-XABORT_DEF 6828
-XACQUIRE_PREFIX 6829
-XADD 6830
-XAM_F 6831
-XAM_Fp 6832
-XBEGIN 6833
-XCHG 6834
-XCH_F 6835
-XCRYPTCBC 6836
-XCRYPTCFB 6837
-XCRYPTCTR 6838
-XCRYPTECB 6839
-XCRYPTOFB 6840
-XEND 6841
-XGETBV 6842
-XLAT 6843
-XOR 6844
-XORPDrm 6845
-XORPDrr 6846
-XORPSrm 6847
-XORPSrr 6848
-XRELEASE_PREFIX 6849
-XRESLDTRK 6850
-XRSTOR 6851
-XRSTORS 6852
-XSAVE 6853
-XSAVEC 6854
-XSAVEOPT 6855
-XSAVES 6856
-XSETBV 6857
-XSHA 6858
-XSTORE 6859
-XSUSLDTRK 6860
-XTEST 6861
-Immediate 6862
-CImmediate 6863
-FPImmediate 6864
-MBB 6865
-FrameIndex 6866
-ConstantPoolIndex 6867
-TargetIndex 6868
-JumpTableIndex 6869
-ExternalSymbol 6870
-GlobalAddress 6871
-BlockAddress 6872
-RegisterMask 6873
-RegisterLiveOut 6874
-Metadata 6875
-MCSymbol 6876
-CFIIndex 6877
-IntrinsicID 6878
-Predicate 6879
-ShuffleMask 6880
-PhyReg_GR8 6881
-PhyReg_GRH8 6882
-PhyReg_GR8_NOREX2 6883
-PhyReg_GR8_NOREX 6884
-PhyReg_GR8_ABCD_H 6885
-PhyReg_GR8_ABCD_L 6886
-PhyReg_GRH16 6887
-PhyReg_GR16 6888
-PhyReg_GR16_NOREX2 6889
-PhyReg_GR16_NOREX 6890
-PhyReg_VK1 6891
-PhyReg_VK16 6892
-PhyReg_VK2 6893
-PhyReg_VK4 6894
-PhyReg_VK8 6895
-PhyReg_VK16WM 6896
-PhyReg_VK1WM 6897
-PhyReg_VK2WM 6898
-PhyReg_VK4WM 6899
-PhyReg_VK8WM 6900
-PhyReg_SEGMENT_REG 6901
-PhyReg_GR16_ABCD 6902
-PhyReg_FPCCR 6903
-PhyReg_FR16X 6904
-PhyReg_FR16 6905
-PhyReg_VK16PAIR 6906
-PhyReg_VK1PAIR 6907
-PhyReg_VK2PAIR 6908
-PhyReg_VK4PAIR 6909
-PhyReg_VK8PAIR 6910
-PhyReg_VK1PAIR_with_sub_mask_0_in_VK1WM 6911
-PhyReg_LOW32_ADDR_ACCESS_RBP 6912
-PhyReg_LOW32_ADDR_ACCESS 6913
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 6914
-PhyReg_FR32X 6915
-PhyReg_GR32 6916
-PhyReg_GR32_NOSP 6917
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 6918
-PhyReg_DEBUG_REG 6919
-PhyReg_FR32 6920
-PhyReg_GR32_NOREX2 6921
-PhyReg_GR32_NOREX2_NOSP 6922
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 6923
-PhyReg_GR32_NOREX 6924
-PhyReg_VK32 6925
-PhyReg_GR32_NOREX_NOSP 6926
-PhyReg_RFP32 6927
-PhyReg_VK32WM 6928
-PhyReg_GR32_ABCD 6929
-PhyReg_GR32_TC 6930
-PhyReg_GR32_ABCD_and_GR32_TC 6931
-PhyReg_GR32_AD 6932
-PhyReg_GR32_ArgRef 6933
-PhyReg_GR32_BPSP 6934
-PhyReg_GR32_BSI 6935
-PhyReg_GR32_CB 6936
-PhyReg_GR32_DC 6937
-PhyReg_GR32_DIBP 6938
-PhyReg_GR32_SIDI 6939
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 6940
-PhyReg_CCR 6941
-PhyReg_DFCCR 6942
-PhyReg_GR32_ABCD_and_GR32_BSI 6943
-PhyReg_GR32_AD_and_GR32_ArgRef 6944
-PhyReg_GR32_ArgRef_and_GR32_CB 6945
-PhyReg_GR32_BPSP_and_GR32_DIBP 6946
-PhyReg_GR32_BPSP_and_GR32_TC 6947
-PhyReg_GR32_BSI_and_GR32_SIDI 6948
-PhyReg_GR32_DIBP_and_GR32_SIDI 6949
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 6950
-PhyReg_LOW32_ADDR_ACCESS_with_sub_32bit 6951
-PhyReg_RFP64 6952
-PhyReg_GR64 6953
-PhyReg_FR64X 6954
-PhyReg_GR64_with_sub_8bit 6955
-PhyReg_GR64_NOSP 6956
-PhyReg_GR64_NOREX2 6957
-PhyReg_CONTROL_REG 6958
-PhyReg_FR64 6959
-PhyReg_GR64_with_sub_16bit_in_GR16_NOREX2 6960
-PhyReg_GR64_NOREX2_NOSP 6961
-PhyReg_GR64PLTSafe 6962
-PhyReg_GR64_TC 6963
-PhyReg_GR64_NOREX 6964
-PhyReg_GR64_TCW64 6965
-PhyReg_GR64_TC_with_sub_8bit 6966
-PhyReg_GR64_NOREX2_NOSP_and_GR64_TC 6967
-PhyReg_GR64_TCW64_with_sub_8bit 6968
-PhyReg_GR64_TC_and_GR64_TCW64 6969
-PhyReg_GR64_with_sub_16bit_in_GR16_NOREX 6970
-PhyReg_VK64 6971
-PhyReg_VR64 6972
-PhyReg_GR64PLTSafe_and_GR64_TC 6973
-PhyReg_GR64_NOREX2_NOSP_and_GR64_TCW64 6974
-PhyReg_GR64_NOREX_NOSP 6975
-PhyReg_GR64_NOREX_and_GR64_TC 6976
-PhyReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 6977
-PhyReg_VK64WM 6978
-PhyReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 6979
-PhyReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 6980
-PhyReg_GR64PLTSafe_and_GR64_TCW64 6981
-PhyReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 6982
-PhyReg_GR64_NOREX_and_GR64_TCW64 6983
-PhyReg_GR64_ABCD 6984
-PhyReg_GR64_with_sub_32bit_in_GR32_TC 6985
-PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 6986
-PhyReg_GR64_AD 6987
-PhyReg_GR64_ArgRef 6988
-PhyReg_GR64_and_LOW32_ADDR_ACCESS_RBP 6989
-PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef 6990
-PhyReg_GR64_with_sub_32bit_in_GR32_BPSP 6991
-PhyReg_GR64_with_sub_32bit_in_GR32_BSI 6992
-PhyReg_GR64_with_sub_32bit_in_GR32_CB 6993
-PhyReg_GR64_with_sub_32bit_in_GR32_DIBP 6994
-PhyReg_GR64_with_sub_32bit_in_GR32_SIDI 6995
-PhyReg_GR64_A 6996
-PhyReg_GR64_ArgRef_and_GR64_TC 6997
-PhyReg_GR64_and_LOW32_ADDR_ACCESS 6998
-PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 6999
-PhyReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7000
-PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7001
-PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7002
-PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7003
-PhyReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7004
-PhyReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7005
-PhyReg_RST 7006
-PhyReg_RFP80 7007
-PhyReg_RFP80_7 7008
-PhyReg_VR128X 7009
-PhyReg_VR128 7010
-PhyReg_VR256X 7011
-PhyReg_VR256 7012
-PhyReg_VR512 7013
-PhyReg_VR512_0_15 7014
-PhyReg_TILE 7015
-VirtReg_GR8 7016
-VirtReg_GRH8 7017
-VirtReg_GR8_NOREX2 7018
-VirtReg_GR8_NOREX 7019
-VirtReg_GR8_ABCD_H 7020
-VirtReg_GR8_ABCD_L 7021
-VirtReg_GRH16 7022
-VirtReg_GR16 7023
-VirtReg_GR16_NOREX2 7024
-VirtReg_GR16_NOREX 7025
-VirtReg_VK1 7026
-VirtReg_VK16 7027
-VirtReg_VK2 7028
-VirtReg_VK4 7029
-VirtReg_VK8 7030
-VirtReg_VK16WM 7031
-VirtReg_VK1WM 7032
-VirtReg_VK2WM 7033
-VirtReg_VK4WM 7034
-VirtReg_VK8WM 7035
-VirtReg_SEGMENT_REG 7036
-VirtReg_GR16_ABCD 7037
-VirtReg_FPCCR 7038
-VirtReg_FR16X 7039
-VirtReg_FR16 7040
-VirtReg_VK16PAIR 7041
-VirtReg_VK1PAIR 7042
-VirtReg_VK2PAIR 7043
-VirtReg_VK4PAIR 7044
-VirtReg_VK8PAIR 7045
-VirtReg_VK1PAIR_with_sub_mask_0_in_VK1WM 7046
-VirtReg_LOW32_ADDR_ACCESS_RBP 7047
-VirtReg_LOW32_ADDR_ACCESS 7048
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 7049
-VirtReg_FR32X 7050
-VirtReg_GR32 7051
-VirtReg_GR32_NOSP 7052
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 7053
-VirtReg_DEBUG_REG 7054
-VirtReg_FR32 7055
-VirtReg_GR32_NOREX2 7056
-VirtReg_GR32_NOREX2_NOSP 7057
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 7058
-VirtReg_GR32_NOREX 7059
-VirtReg_VK32 7060
-VirtReg_GR32_NOREX_NOSP 7061
-VirtReg_RFP32 7062
-VirtReg_VK32WM 7063
-VirtReg_GR32_ABCD 7064
-VirtReg_GR32_TC 7065
-VirtReg_GR32_ABCD_and_GR32_TC 7066
-VirtReg_GR32_AD 7067
-VirtReg_GR32_ArgRef 7068
-VirtReg_GR32_BPSP 7069
-VirtReg_GR32_BSI 7070
-VirtReg_GR32_CB 7071
-VirtReg_GR32_DC 7072
-VirtReg_GR32_DIBP 7073
-VirtReg_GR32_SIDI 7074
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 7075
-VirtReg_CCR 7076
-VirtReg_DFCCR 7077
-VirtReg_GR32_ABCD_and_GR32_BSI 7078
-VirtReg_GR32_AD_and_GR32_ArgRef 7079
-VirtReg_GR32_ArgRef_and_GR32_CB 7080
-VirtReg_GR32_BPSP_and_GR32_DIBP 7081
-VirtReg_GR32_BPSP_and_GR32_TC 7082
-VirtReg_GR32_BSI_and_GR32_SIDI 7083
-VirtReg_GR32_DIBP_and_GR32_SIDI 7084
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 7085
-VirtReg_LOW32_ADDR_ACCESS_with_sub_32bit 7086
-VirtReg_RFP64 7087
-VirtReg_GR64 7088
-VirtReg_FR64X 7089
-VirtReg_GR64_with_sub_8bit 7090
-VirtReg_GR64_NOSP 7091
-VirtReg_GR64_NOREX2 7092
-VirtReg_CONTROL_REG 7093
-VirtReg_FR64 7094
-VirtReg_GR64_with_sub_16bit_in_GR16_NOREX2 7095
-VirtReg_GR64_NOREX2_NOSP 7096
-VirtReg_GR64PLTSafe 7097
-VirtReg_GR64_TC 7098
-VirtReg_GR64_NOREX 7099
-VirtReg_GR64_TCW64 7100
-VirtReg_GR64_TC_with_sub_8bit 7101
-VirtReg_GR64_NOREX2_NOSP_and_GR64_TC 7102
-VirtReg_GR64_TCW64_with_sub_8bit 7103
-VirtReg_GR64_TC_and_GR64_TCW64 7104
-VirtReg_GR64_with_sub_16bit_in_GR16_NOREX 7105
-VirtReg_VK64 7106
-VirtReg_VR64 7107
-VirtReg_GR64PLTSafe_and_GR64_TC 7108
-VirtReg_GR64_NOREX2_NOSP_and_GR64_TCW64 7109
-VirtReg_GR64_NOREX_NOSP 7110
-VirtReg_GR64_NOREX_and_GR64_TC 7111
-VirtReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 7112
-VirtReg_VK64WM 7113
-VirtReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 7114
-VirtReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7115
-VirtReg_GR64PLTSafe_and_GR64_TCW64 7116
-VirtReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7117
-VirtReg_GR64_NOREX_and_GR64_TCW64 7118
-VirtReg_GR64_ABCD 7119
-VirtReg_GR64_with_sub_32bit_in_GR32_TC 7120
-VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7121
-VirtReg_GR64_AD 7122
-VirtReg_GR64_ArgRef 7123
-VirtReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7124
-VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef 7125
-VirtReg_GR64_with_sub_32bit_in_GR32_BPSP 7126
-VirtReg_GR64_with_sub_32bit_in_GR32_BSI 7127
-VirtReg_GR64_with_sub_32bit_in_GR32_CB 7128
-VirtReg_GR64_with_sub_32bit_in_GR32_DIBP 7129
-VirtReg_GR64_with_sub_32bit_in_GR32_SIDI 7130
-VirtReg_GR64_A 7131
-VirtReg_GR64_ArgRef_and_GR64_TC 7132
-VirtReg_GR64_and_LOW32_ADDR_ACCESS 7133
-VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7134
-VirtReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7135
-VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7136
-VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7137
-VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7138
-VirtReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7139
-VirtReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7140
-VirtReg_RST 7141
-VirtReg_RFP80 7142
-VirtReg_RFP80_7 7143
-VirtReg_VR128X 7144
-VirtReg_VR128 7145
-VirtReg_VR256X 7146
-VirtReg_VR256 7147
-VirtReg_VR512 7148
-VirtReg_VR512_0_15 7149
-VirtReg_TILE 7150
+COPY_LANEMASK 188
+COPY_TO_REGCLASS 189
+CPUID 190
+CQO 191
+CRC 192
+CS_PREFIX 193
+CTEST 194
+CVTDQ 195
+CVTPD 196
+CVTPS 197
+CVTSD 198
+CVTSI 199
+CVTSS 200
+CVTTPD 201
+CVTTPS 202
+CVTTSD 203
+CVTTSS 204
+CWD 205
+CWDE 206
+DAA 207
+DAS 208
+DATA 209
+DBG_INSTR_REF 210
+DBG_LABEL 211
+DBG_PHI 212
+DBG_VALUE 213
+DBG_VALUE_LIST 214
+DEC 215
+DIV 216
+DIVPDrm 217
+DIVPDrr 218
+DIVPSrm 219
+DIVPSrr 220
+DIVR_F 221
+DIVR_FI 222
+DIVR_FPrST 223
+DIVR_FST 224
+DIVR_Fp 225
+DIVR_FpI 226
+DIVR_FrST 227
+DIVSDrm 228
+DIVSDrm_Int 229
+DIVSDrr 230
+DIVSDrr_Int 231
+DIVSSrm 232
+DIVSSrm_Int 233
+DIVSSrr 234
+DIVSSrr_Int 235
+DIV_F 236
+DIV_FI 237
+DIV_FPrST 238
+DIV_FST 239
+DIV_Fp 240
+DIV_FpI 241
+DIV_FrST 242
+DPPDrmi 243
+DPPDrri 244
+DPPSrmi 245
+DPPSrri 246
+DS_PREFIX 247
+DYN_ALLOCA 248
+EH_LABEL 249
+EH_RETURN 250
+EH_SjLj_LongJmp 251
+EH_SjLj_SetJmp 252
+EH_SjLj_Setup 253
+ENCLS 254
+ENCLU 255
+ENCLV 256
+ENCODEKEY 257
+ENDBR 258
+ENQCMD 259
+ENQCMDS 260
+ENTER 261
+ERETS 262
+ERETU 263
+ES_PREFIX 264
+EXTRACTPSmri 265
+EXTRACTPSrri 266
+EXTRACT_SUBREG 267
+EXTRQ 268
+EXTRQI 269
+F 270
+FAKE_USE 271
+FARCALL 272
+FARJMP 273
+FAULTING_OP 274
+FBLDm 275
+FBSTPm 276
+FCOM 277
+FCOMP 278
+FCOMPP 279
+FCOS 280
+FDECSTP 281
+FEMMS 282
+FENTRY_CALL 283
+FFREE 284
+FFREEP 285
+FICOM 286
+FICOMP 287
+FINCSTP 288
+FLDCW 289
+FLDENVm 290
+FLDL 291
+FLDLG 292
+FLDLN 293
+FLDPI 294
+FNCLEX 295
+FNINIT 296
+FNOP 297
+FNSTCW 298
+FNSTSW 299
+FNSTSWm 300
+FP 301
+FPATAN 302
+FPREM 303
+FPTAN 304
+FRNDINT 305
+FRSTORm 306
+FSAVEm 307
+FSCALE 308
+FSIN 309
+FSINCOS 310
+FSTENVm 311
+FS_PREFIX 312
+FXRSTOR 313
+FXSAVE 314
+FXTRACT 315
+FYL 316
+FsFLD 317
+GC_LABEL 318
+GETSEC 319
+GF 320
+GS_PREFIX 321
+G_ABDS 322
+G_ABDU 323
+G_ABS 324
+G_ADD 325
+G_ADDRSPACE_CAST 326
+G_AND 327
+G_ANYEXT 328
+G_ASHR 329
+G_ASSERT_ALIGN 330
+G_ASSERT_SEXT 331
+G_ASSERT_ZEXT 332
+G_ATOMICRMW_ADD 333
+G_ATOMICRMW_AND 334
+G_ATOMICRMW_FADD 335
+G_ATOMICRMW_FMAX 336
+G_ATOMICRMW_FMAXIMUM 337
+G_ATOMICRMW_FMIN 338
+G_ATOMICRMW_FMINIMUM 339
+G_ATOMICRMW_FSUB 340
+G_ATOMICRMW_MAX 341
+G_ATOMICRMW_MIN 342
+G_ATOMICRMW_NAND 343
+G_ATOMICRMW_OR 344
+G_ATOMICRMW_SUB 345
+G_ATOMICRMW_UDEC_WRAP 346
+G_ATOMICRMW_UINC_WRAP 347
+G_ATOMICRMW_UMAX 348
+G_ATOMICRMW_UMIN 349
+G_ATOMICRMW_USUB_COND 350
+G_ATOMICRMW_USUB_SAT 351
+G_ATOMICRMW_XCHG 352
+G_ATOMICRMW_XOR 353
+G_ATOMIC_CMPXCHG 354
+G_ATOMIC_CMPXCHG_WITH_SUCCESS 355
+G_BITCAST 356
+G_BITREVERSE 357
+G_BLOCK_ADDR 358
+G_BR 359
+G_BRCOND 360
+G_BRINDIRECT 361
+G_BRJT 362
+G_BSWAP 363
+G_BUILD_VECTOR 364
+G_BUILD_VECTOR_TRUNC 365
+G_BZERO 366
+G_CONCAT_VECTORS 367
+G_CONSTANT 368
+G_CONSTANT_FOLD_BARRIER 369
+G_CONSTANT_POOL 370
+G_CTLZ 371
+G_CTLZ_ZERO_UNDEF 372
+G_CTPOP 373
+G_CTTZ 374
+G_CTTZ_ZERO_UNDEF 375
+G_DEBUGTRAP 376
+G_DYN_STACKALLOC 377
+G_EXTRACT 378
+G_EXTRACT_SUBVECTOR 379
+G_EXTRACT_VECTOR_ELT 380
+G_FABS 381
+G_FACOS 382
+G_FADD 383
+G_FASIN 384
+G_FATAN 385
+G_FCANONICALIZE 386
+G_FCEIL 387
+G_FCMP 388
+G_FCONSTANT 389
+G_FCOPYSIGN 390
+G_FCOS 391
+G_FCOSH 392
+G_FDIV 393
+G_FENCE 394
+G_FEXP 395
+G_FFLOOR 396
+G_FFREXP 397
+G_FILD 398
+G_FIST 399
+G_FLDCW 400
+G_FLDEXP 401
+G_FLOG 402
+G_FMA 403
+G_FMAD 404
+G_FMAXIMUM 405
+G_FMAXIMUMNUM 406
+G_FMAXNUM 407
+G_FMAXNUM_IEEE 408
+G_FMINIMUM 409
+G_FMINIMUMNUM 410
+G_FMINNUM 411
+G_FMINNUM_IEEE 412
+G_FMODF 413
+G_FMUL 414
+G_FNEARBYINT 415
+G_FNEG 416
+G_FNSTCW 417
+G_FPEXT 418
+G_FPOW 419
+G_FPOWI 420
+G_FPTOSI 421
+G_FPTOSI_SAT 422
+G_FPTOUI 423
+G_FPTOUI_SAT 424
+G_FPTRUNC 425
+G_FRAME_INDEX 426
+G_FREEZE 427
+G_FREM 428
+G_FRINT 429
+G_FSHL 430
+G_FSHR 431
+G_FSIN 432
+G_FSINCOS 433
+G_FSINH 434
+G_FSQRT 435
+G_FSUB 436
+G_FTAN 437
+G_FTANH 438
+G_GET_FPENV 439
+G_GET_FPMODE 440
+G_GET_ROUNDING 441
+G_GLOBAL_VALUE 442
+G_ICMP 443
+G_IMPLICIT_DEF 444
+G_INDEXED_LOAD 445
+G_INDEXED_SEXTLOAD 446
+G_INDEXED_STORE 447
+G_INDEXED_ZEXTLOAD 448
+G_INSERT 449
+G_INSERT_SUBVECTOR 450
+G_INSERT_VECTOR_ELT 451
+G_INTRINSIC 452
+G_INTRINSIC_CONVERGENT 453
+G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS 454
+G_INTRINSIC_FPTRUNC_ROUND 455
+G_INTRINSIC_LLRINT 456
+G_INTRINSIC_LRINT 457
+G_INTRINSIC_ROUND 458
+G_INTRINSIC_ROUNDEVEN 459
+G_INTRINSIC_TRUNC 460
+G_INTRINSIC_W_SIDE_EFFECTS 461
+G_INTTOPTR 462
+G_INVOKE_REGION_START 463
+G_IS_FPCLASS 464
+G_JUMP_TABLE 465
+G_LLROUND 466
+G_LOAD 467
+G_LROUND 468
+G_LSHR 469
+G_MEMCPY 470
+G_MEMCPY_INLINE 471
+G_MEMMOVE 472
+G_MEMSET 473
+G_MERGE_VALUES 474
+G_MUL 475
+G_OR 476
+G_PHI 477
+G_PREFETCH 478
+G_PTRAUTH_GLOBAL_VALUE 479
+G_PTRMASK 480
+G_PTRTOINT 481
+G_PTR_ADD 482
+G_READCYCLECOUNTER 483
+G_READSTEADYCOUNTER 484
+G_READ_REGISTER 485
+G_RESET_FPENV 486
+G_RESET_FPMODE 487
+G_ROTL 488
+G_ROTR 489
+G_SADDE 490
+G_SADDO 491
+G_SADDSAT 492
+G_SBFX 493
+G_SCMP 494
+G_SDIV 495
+G_SDIVFIX 496
+G_SDIVFIXSAT 497
+G_SDIVREM 498
+G_SELECT 499
+G_SET_FPENV 500
+G_SET_FPMODE 501
+G_SET_ROUNDING 502
+G_SEXT 503
+G_SEXTLOAD 504
+G_SEXT_INREG 505
+G_SHL 506
+G_SHUFFLE_VECTOR 507
+G_SITOFP 508
+G_SMAX 509
+G_SMIN 510
+G_SMULFIX 511
+G_SMULFIXSAT 512
+G_SMULH 513
+G_SMULO 514
+G_SPLAT_VECTOR 515
+G_SREM 516
+G_SSHLSAT 517
+G_SSUBE 518
+G_SSUBO 519
+G_SSUBSAT 520
+G_STACKRESTORE 521
+G_STACKSAVE 522
+G_STEP_VECTOR 523
+G_STORE 524
+G_STRICT_FADD 525
+G_STRICT_FDIV 526
+G_STRICT_FLDEXP 527
+G_STRICT_FMA 528
+G_STRICT_FMUL 529
+G_STRICT_FREM 530
+G_STRICT_FSQRT 531
+G_STRICT_FSUB 532
+G_SUB 533
+G_TRAP 534
+G_TRUNC 535
+G_TRUNC_SSAT_S 536
+G_TRUNC_SSAT_U 537
+G_TRUNC_USAT_U 538
+G_UADDE 539
+G_UADDO 540
+G_UADDSAT 541
+G_UBFX 542
+G_UBSANTRAP 543
+G_UCMP 544
+G_UDIV 545
+G_UDIVFIX 546
+G_UDIVFIXSAT 547
+G_UDIVREM 548
+G_UITOFP 549
+G_UMAX 550
+G_UMIN 551
+G_UMULFIX 552
+G_UMULFIXSAT 553
+G_UMULH 554
+G_UMULO 555
+G_UNMERGE_VALUES 556
+G_UREM 557
+G_USHLSAT 558
+G_USUBE 559
+G_USUBO 560
+G_USUBSAT 561
+G_VAARG 562
+G_VASTART 563
+G_VECREDUCE_ADD 564
+G_VECREDUCE_AND 565
+G_VECREDUCE_FADD 566
+G_VECREDUCE_FMAX 567
+G_VECREDUCE_FMAXIMUM 568
+G_VECREDUCE_FMIN 569
+G_VECREDUCE_FMINIMUM 570
+G_VECREDUCE_FMUL 571
+G_VECREDUCE_MUL 572
+G_VECREDUCE_OR 573
+G_VECREDUCE_SEQ_FADD 574
+G_VECREDUCE_SEQ_FMUL 575
+G_VECREDUCE_SMAX 576
+G_VECREDUCE_SMIN 577
+G_VECREDUCE_UMAX 578
+G_VECREDUCE_UMIN 579
+G_VECREDUCE_XOR 580
+G_VECTOR_COMPRESS 581
+G_VSCALE 582
+G_WRITE_REGISTER 583
+G_XOR 584
+G_ZEXT 585
+G_ZEXTLOAD 586
+HADDPDrm 587
+HADDPDrr 588
+HADDPSrm 589
+HADDPSrr 590
+HLT 591
+HRESET 592
+HSUBPDrm 593
+HSUBPDrr 594
+HSUBPSrm 595
+HSUBPSrr 596
+ICALL_BRANCH_FUNNEL 597
+IDIV 598
+ILD_F 599
+ILD_Fp 600
+IMPLICIT_DEF 601
+IMUL 602
+IMULZU 603
+IN 604
+INC 605
+INCSSPD 606
+INCSSPQ 607
+INDIRECT_THUNK_CALL 608
+INDIRECT_THUNK_TCRETURN 609
+INIT_UNDEF 610
+INLINEASM 611
+INLINEASM_BR 612
+INSB 613
+INSERTPSrmi 614
+INSERTPSrri 615
+INSERTQ 616
+INSERTQI 617
+INSERT_SUBREG 618
+INSL 619
+INSW 620
+INT 621
+INTO 622
+INVD 623
+INVEPT 624
+INVLPG 625
+INVLPGA 626
+INVLPGB 627
+INVPCID 628
+INVVPID 629
+IRET 630
+ISTT_FP 631
+ISTT_Fp 632
+IST_F 633
+IST_FP 634
+IST_Fp 635
+Int_eh_sjlj_setup_dispatch 636
+JCC 637
+JCXZ 638
+JECXZ 639
+JMP 640
+JMPABS 641
+JRCXZ 642
+JUMP_TABLE_DEBUG_INFO 643
+KADDBkk 644
+KADDDkk 645
+KADDQkk 646
+KADDWkk 647
+KANDBkk 648
+KANDDkk 649
+KANDNBkk 650
+KANDNDkk 651
+KANDNQkk 652
+KANDNWkk 653
+KANDQkk 654
+KANDWkk 655
+KCFI_CHECK 656
+KILL 657
+KMOVBkk 658
+KMOVBkk_EVEX 659
+KMOVBkm 660
+KMOVBkm_EVEX 661
+KMOVBkr 662
+KMOVBkr_EVEX 663
+KMOVBmk 664
+KMOVBmk_EVEX 665
+KMOVBrk 666
+KMOVBrk_EVEX 667
+KMOVDkk 668
+KMOVDkk_EVEX 669
+KMOVDkm 670
+KMOVDkm_EVEX 671
+KMOVDkr 672
+KMOVDkr_EVEX 673
+KMOVDmk 674
+KMOVDmk_EVEX 675
+KMOVDrk 676
+KMOVDrk_EVEX 677
+KMOVQkk 678
+KMOVQkk_EVEX 679
+KMOVQkm 680
+KMOVQkm_EVEX 681
+KMOVQkr 682
+KMOVQkr_EVEX 683
+KMOVQmk 684
+KMOVQmk_EVEX 685
+KMOVQrk 686
+KMOVQrk_EVEX 687
+KMOVWkk 688
+KMOVWkk_EVEX 689
+KMOVWkm 690
+KMOVWkm_EVEX 691
+KMOVWkr 692
+KMOVWkr_EVEX 693
+KMOVWmk 694
+KMOVWmk_EVEX 695
+KMOVWrk 696
+KMOVWrk_EVEX 697
+KNOTBkk 698
+KNOTDkk 699
+KNOTQkk 700
+KNOTWkk 701
+KORBkk 702
+KORDkk 703
+KORQkk 704
+KORTESTBkk 705
+KORTESTDkk 706
+KORTESTQkk 707
+KORTESTWkk 708
+KORWkk 709
+KSET 710
+KSHIFTLBki 711
+KSHIFTLDki 712
+KSHIFTLQki 713
+KSHIFTLWki 714
+KSHIFTRBki 715
+KSHIFTRDki 716
+KSHIFTRQki 717
+KSHIFTRWki 718
+KTESTBkk 719
+KTESTDkk 720
+KTESTQkk 721
+KTESTWkk 722
+KUNPCKBWkk 723
+KUNPCKDQkk 724
+KUNPCKWDkk 725
+KXNORBkk 726
+KXNORDkk 727
+KXNORQkk 728
+KXNORWkk 729
+KXORBkk 730
+KXORDkk 731
+KXORQkk 732
+KXORWkk 733
+LAHF 734
+LAR 735
+LCMPXCHG 736
+LDDQUrm 737
+LDMXCSR 738
+LDS 739
+LDTILECFG 740
+LDTILECFG_EVEX 741
+LD_F 742
+LD_Fp 743
+LD_Frr 744
+LEA 745
+LEAVE 746
+LES 747
+LFENCE 748
+LFS 749
+LGDT 750
+LGS 751
+LIDT 752
+LIFETIME_END 753
+LIFETIME_START 754
+LKGS 755
+LLDT 756
+LLWPCB 757
+LMSW 758
+LOADIWKEY 759
+LOAD_STACK_GUARD 760
+LOCAL_ESCAPE 761
+LOCK_ADD 762
+LOCK_AND 763
+LOCK_BTC 764
+LOCK_BTC_RM 765
+LOCK_BTR 766
+LOCK_BTR_RM 767
+LOCK_BTS 768
+LOCK_BTS_RM 769
+LOCK_DEC 770
+LOCK_INC 771
+LOCK_OR 772
+LOCK_PREFIX 773
+LOCK_SUB 774
+LOCK_XOR 775
+LODSB 776
+LODSL 777
+LODSQ 778
+LODSW 779
+LOOP 780
+LOOPE 781
+LOOPNE 782
+LRET 783
+LRETI 784
+LSL 785
+LSS 786
+LTRm 787
+LTRr 788
+LWPINS 789
+LWPVAL 790
+LXADD 791
+LZCNT 792
+MASKMOVDQU 793
+MASKPAIR 794
+MAXCPDrm 795
+MAXCPDrr 796
+MAXCPSrm 797
+MAXCPSrr 798
+MAXCSDrm 799
+MAXCSDrr 800
+MAXCSSrm 801
+MAXCSSrr 802
+MAXPDrm 803
+MAXPDrr 804
+MAXPSrm 805
+MAXPSrr 806
+MAXSDrm 807
+MAXSDrm_Int 808
+MAXSDrr 809
+MAXSDrr_Int 810
+MAXSSrm 811
+MAXSSrm_Int 812
+MAXSSrr 813
+MAXSSrr_Int 814
+MEMBARRIER 815
+MFENCE 816
+MINCPDrm 817
+MINCPDrr 818
+MINCPSrm 819
+MINCPSrr 820
+MINCSDrm 821
+MINCSDrr 822
+MINCSSrm 823
+MINCSSrr 824
+MINPDrm 825
+MINPDrr 826
+MINPSrm 827
+MINPSrr 828
+MINSDrm 829
+MINSDrm_Int 830
+MINSDrr 831
+MINSDrr_Int 832
+MINSSrm 833
+MINSSrm_Int 834
+MINSSrr 835
+MINSSrr_Int 836
+MMX_CVTPD 837
+MMX_CVTPI 838
+MMX_CVTPS 839
+MMX_CVTTPD 840
+MMX_CVTTPS 841
+MMX_EMMS 842
+MMX_MASKMOVQ 843
+MMX_MOVD 844
+MMX_MOVDQ 845
+MMX_MOVFR 846
+MMX_MOVNTQmr 847
+MMX_MOVQ 848
+MMX_PABSBrm 849
+MMX_PABSBrr 850
+MMX_PABSDrm 851
+MMX_PABSDrr 852
+MMX_PABSWrm 853
+MMX_PABSWrr 854
+MMX_PACKSSDWrm 855
+MMX_PACKSSDWrr 856
+MMX_PACKSSWBrm 857
+MMX_PACKSSWBrr 858
+MMX_PACKUSWBrm 859
+MMX_PACKUSWBrr 860
+MMX_PADDBrm 861
+MMX_PADDBrr 862
+MMX_PADDDrm 863
+MMX_PADDDrr 864
+MMX_PADDQrm 865
+MMX_PADDQrr 866
+MMX_PADDSBrm 867
+MMX_PADDSBrr 868
+MMX_PADDSWrm 869
+MMX_PADDSWrr 870
+MMX_PADDUSBrm 871
+MMX_PADDUSBrr 872
+MMX_PADDUSWrm 873
+MMX_PADDUSWrr 874
+MMX_PADDWrm 875
+MMX_PADDWrr 876
+MMX_PALIGNRrmi 877
+MMX_PALIGNRrri 878
+MMX_PANDNrm 879
+MMX_PANDNrr 880
+MMX_PANDrm 881
+MMX_PANDrr 882
+MMX_PAVGBrm 883
+MMX_PAVGBrr 884
+MMX_PAVGWrm 885
+MMX_PAVGWrr 886
+MMX_PCMPEQBrm 887
+MMX_PCMPEQBrr 888
+MMX_PCMPEQDrm 889
+MMX_PCMPEQDrr 890
+MMX_PCMPEQWrm 891
+MMX_PCMPEQWrr 892
+MMX_PCMPGTBrm 893
+MMX_PCMPGTBrr 894
+MMX_PCMPGTDrm 895
+MMX_PCMPGTDrr 896
+MMX_PCMPGTWrm 897
+MMX_PCMPGTWrr 898
+MMX_PEXTRWrri 899
+MMX_PHADDDrm 900
+MMX_PHADDDrr 901
+MMX_PHADDSWrm 902
+MMX_PHADDSWrr 903
+MMX_PHADDWrm 904
+MMX_PHADDWrr 905
+MMX_PHSUBDrm 906
+MMX_PHSUBDrr 907
+MMX_PHSUBSWrm 908
+MMX_PHSUBSWrr 909
+MMX_PHSUBWrm 910
+MMX_PHSUBWrr 911
+MMX_PINSRWrmi 912
+MMX_PINSRWrri 913
+MMX_PMADDUBSWrm 914
+MMX_PMADDUBSWrr 915
+MMX_PMADDWDrm 916
+MMX_PMADDWDrr 917
+MMX_PMAXSWrm 918
+MMX_PMAXSWrr 919
+MMX_PMAXUBrm 920
+MMX_PMAXUBrr 921
+MMX_PMINSWrm 922
+MMX_PMINSWrr 923
+MMX_PMINUBrm 924
+MMX_PMINUBrr 925
+MMX_PMOVMSKBrr 926
+MMX_PMULHRSWrm 927
+MMX_PMULHRSWrr 928
+MMX_PMULHUWrm 929
+MMX_PMULHUWrr 930
+MMX_PMULHWrm 931
+MMX_PMULHWrr 932
+MMX_PMULLWrm 933
+MMX_PMULLWrr 934
+MMX_PMULUDQrm 935
+MMX_PMULUDQrr 936
+MMX_PORrm 937
+MMX_PORrr 938
+MMX_PSADBWrm 939
+MMX_PSADBWrr 940
+MMX_PSHUFBrm 941
+MMX_PSHUFBrr 942
+MMX_PSHUFWmi 943
+MMX_PSHUFWri 944
+MMX_PSIGNBrm 945
+MMX_PSIGNBrr 946
+MMX_PSIGNDrm 947
+MMX_PSIGNDrr 948
+MMX_PSIGNWrm 949
+MMX_PSIGNWrr 950
+MMX_PSLLDri 951
+MMX_PSLLDrm 952
+MMX_PSLLDrr 953
+MMX_PSLLQri 954
+MMX_PSLLQrm 955
+MMX_PSLLQrr 956
+MMX_PSLLWri 957
+MMX_PSLLWrm 958
+MMX_PSLLWrr 959
+MMX_PSRADri 960
+MMX_PSRADrm 961
+MMX_PSRADrr 962
+MMX_PSRAWri 963
+MMX_PSRAWrm 964
+MMX_PSRAWrr 965
+MMX_PSRLDri 966
+MMX_PSRLDrm 967
+MMX_PSRLDrr 968
+MMX_PSRLQri 969
+MMX_PSRLQrm 970
+MMX_PSRLQrr 971
+MMX_PSRLWri 972
+MMX_PSRLWrm 973
+MMX_PSRLWrr 974
+MMX_PSUBBrm 975
+MMX_PSUBBrr 976
+MMX_PSUBDrm 977
+MMX_PSUBDrr 978
+MMX_PSUBQrm 979
+MMX_PSUBQrr 980
+MMX_PSUBSBrm 981
+MMX_PSUBSBrr 982
+MMX_PSUBSWrm 983
+MMX_PSUBSWrr 984
+MMX_PSUBUSBrm 985
+MMX_PSUBUSBrr 986
+MMX_PSUBUSWrm 987
+MMX_PSUBUSWrr 988
+MMX_PSUBWrm 989
+MMX_PSUBWrr 990
+MMX_PUNPCKHBWrm 991
+MMX_PUNPCKHBWrr 992
+MMX_PUNPCKHDQrm 993
+MMX_PUNPCKHDQrr 994
+MMX_PUNPCKHWDrm 995
+MMX_PUNPCKHWDrr 996
+MMX_PUNPCKLBWrm 997
+MMX_PUNPCKLBWrr 998
+MMX_PUNPCKLDQrm 999
+MMX_PUNPCKLDQrr 1000
+MMX_PUNPCKLWDrm 1001
+MMX_PUNPCKLWDrr 1002
+MMX_PXORrm 1003
+MMX_PXORrr 1004
+MMX_SET 1005
+MONITOR 1006
+MONITORX 1007
+MONTMUL 1008
+MORESTACK_RET 1009
+MORESTACK_RET_RESTORE_R 1010
+MOV 1011
+MOVAPDmr 1012
+MOVAPDrm 1013
+MOVAPDrr 1014
+MOVAPDrr_REV 1015
+MOVAPSmr 1016
+MOVAPSrm 1017
+MOVAPSrr 1018
+MOVAPSrr_REV 1019
+MOVBE 1020
+MOVDDUPrm 1021
+MOVDDUPrr 1022
+MOVDI 1023
+MOVDIR 1024
+MOVDIRI 1025
+MOVDQAmr 1026
+MOVDQArm 1027
+MOVDQArr 1028
+MOVDQArr_REV 1029
+MOVDQUmr 1030
+MOVDQUrm 1031
+MOVDQUrr 1032
+MOVDQUrr_REV 1033
+MOVHLPSrr 1034
+MOVHPDmr 1035
+MOVHPDrm 1036
+MOVHPSmr 1037
+MOVHPSrm 1038
+MOVLHPSrr 1039
+MOVLPDmr 1040
+MOVLPDrm 1041
+MOVLPSmr 1042
+MOVLPSrm 1043
+MOVMSKPDrr 1044
+MOVMSKPSrr 1045
+MOVNTDQArm 1046
+MOVNTDQmr 1047
+MOVNTI 1048
+MOVNTImr 1049
+MOVNTPDmr 1050
+MOVNTPSmr 1051
+MOVNTSD 1052
+MOVNTSS 1053
+MOVPC 1054
+MOVPDI 1055
+MOVPQI 1056
+MOVPQIto 1057
+MOVQI 1058
+MOVRS 1059
+MOVSB 1060
+MOVSDmr 1061
+MOVSDrm 1062
+MOVSDrm_alt 1063
+MOVSDrr 1064
+MOVSDrr_REV 1065
+MOVSDto 1066
+MOVSHDUPrm 1067
+MOVSHDUPrr 1068
+MOVSHPmr 1069
+MOVSHPrm 1070
+MOVSL 1071
+MOVSLDUPrm 1072
+MOVSLDUPrr 1073
+MOVSQ 1074
+MOVSS 1075
+MOVSSmr 1076
+MOVSSrm 1077
+MOVSSrm_alt 1078
+MOVSSrr 1079
+MOVSSrr_REV 1080
+MOVSW 1081
+MOVSX 1082
+MOVUPDmr 1083
+MOVUPDrm 1084
+MOVUPDrr 1085
+MOVUPDrr_REV 1086
+MOVUPSmr 1087
+MOVUPSrm 1088
+MOVUPSrr 1089
+MOVUPSrr_REV 1090
+MOVZPQILo 1091
+MOVZX 1092
+MPSADBWrmi 1093
+MPSADBWrri 1094
+MUL 1095
+MULPDrm 1096
+MULPDrr 1097
+MULPSrm 1098
+MULPSrr 1099
+MULSDrm 1100
+MULSDrm_Int 1101
+MULSDrr 1102
+MULSDrr_Int 1103
+MULSSrm 1104
+MULSSrm_Int 1105
+MULSSrr 1106
+MULSSrr_Int 1107
+MULX 1108
+MUL_F 1109
+MUL_FI 1110
+MUL_FPrST 1111
+MUL_FST 1112
+MUL_Fp 1113
+MUL_FpI 1114
+MUL_FrST 1115
+MWAITX 1116
+MWAITX_SAVE_RBX 1117
+MWAITXrrr 1118
+MWAITrr 1119
+NEG 1120
+NOOP 1121
+NOOPL 1122
+NOOPLr 1123
+NOOPQ 1124
+NOOPQr 1125
+NOOPW 1126
+NOOPWr 1127
+NOT 1128
+OR 1129
+ORPDrm 1130
+ORPDrr 1131
+ORPSrm 1132
+ORPSrr 1133
+OUT 1134
+OUTSB 1135
+OUTSL 1136
+OUTSW 1137
+PABSBrm 1138
+PABSBrr 1139
+PABSDrm 1140
+PABSDrr 1141
+PABSWrm 1142
+PABSWrr 1143
+PACKSSDWrm 1144
+PACKSSDWrr 1145
+PACKSSWBrm 1146
+PACKSSWBrr 1147
+PACKUSDWrm 1148
+PACKUSDWrr 1149
+PACKUSWBrm 1150
+PACKUSWBrr 1151
+PADDBrm 1152
+PADDBrr 1153
+PADDDrm 1154
+PADDDrr 1155
+PADDQrm 1156
+PADDQrr 1157
+PADDSBrm 1158
+PADDSBrr 1159
+PADDSWrm 1160
+PADDSWrr 1161
+PADDUSBrm 1162
+PADDUSBrr 1163
+PADDUSWrm 1164
+PADDUSWrr 1165
+PADDWrm 1166
+PADDWrr 1167
+PALIGNRrmi 1168
+PALIGNRrri 1169
+PANDNrm 1170
+PANDNrr 1171
+PANDrm 1172
+PANDrr 1173
+PATCHABLE_EVENT_CALL 1174
+PATCHABLE_FUNCTION_ENTER 1175
+PATCHABLE_FUNCTION_EXIT 1176
+PATCHABLE_OP 1177
+PATCHABLE_RET 1178
+PATCHABLE_TAIL_CALL 1179
+PATCHABLE_TYPED_EVENT_CALL 1180
+PATCHPOINT 1181
+PAUSE 1182
+PAVGBrm 1183
+PAVGBrr 1184
+PAVGUSBrm 1185
+PAVGUSBrr 1186
+PAVGWrm 1187
+PAVGWrr 1188
+PBLENDVBrm 1189
+PBLENDVBrr 1190
+PBLENDWrmi 1191
+PBLENDWrri 1192
+PBNDKB 1193
+PCLMULQDQrmi 1194
+PCLMULQDQrri 1195
+PCMPEQBrm 1196
+PCMPEQBrr 1197
+PCMPEQDrm 1198
+PCMPEQDrr 1199
+PCMPEQQrm 1200
+PCMPEQQrr 1201
+PCMPEQWrm 1202
+PCMPEQWrr 1203
+PCMPESTRIrmi 1204
+PCMPESTRIrri 1205
+PCMPESTRMrmi 1206
+PCMPESTRMrri 1207
+PCMPGTBrm 1208
+PCMPGTBrr 1209
+PCMPGTDrm 1210
+PCMPGTDrr 1211
+PCMPGTQrm 1212
+PCMPGTQrr 1213
+PCMPGTWrm 1214
+PCMPGTWrr 1215
+PCMPISTRIrmi 1216
+PCMPISTRIrri 1217
+PCMPISTRMrmi 1218
+PCMPISTRMrri 1219
+PCONFIG 1220
+PDEP 1221
+PEXT 1222
+PEXTRBmri 1223
+PEXTRBrri 1224
+PEXTRDmri 1225
+PEXTRDrri 1226
+PEXTRQmri 1227
+PEXTRQrri 1228
+PEXTRWmri 1229
+PEXTRWrri 1230
+PEXTRWrri_REV 1231
+PF 1232
+PFACCrm 1233
+PFACCrr 1234
+PFADDrm 1235
+PFADDrr 1236
+PFCMPEQrm 1237
+PFCMPEQrr 1238
+PFCMPGErm 1239
+PFCMPGErr 1240
+PFCMPGTrm 1241
+PFCMPGTrr 1242
+PFMAXrm 1243
+PFMAXrr 1244
+PFMINrm 1245
+PFMINrr 1246
+PFMULrm 1247
+PFMULrr 1248
+PFNACCrm 1249
+PFNACCrr 1250
+PFPNACCrm 1251
+PFPNACCrr 1252
+PFRCPIT 1253
+PFRCPrm 1254
+PFRCPrr 1255
+PFRSQIT 1256
+PFRSQRTrm 1257
+PFRSQRTrr 1258
+PFSUBRrm 1259
+PFSUBRrr 1260
+PFSUBrm 1261
+PFSUBrr 1262
+PHADDDrm 1263
+PHADDDrr 1264
+PHADDSWrm 1265
+PHADDSWrr 1266
+PHADDWrm 1267
+PHADDWrr 1268
+PHI 1269
+PHMINPOSUWrm 1270
+PHMINPOSUWrr 1271
+PHSUBDrm 1272
+PHSUBDrr 1273
+PHSUBSWrm 1274
+PHSUBSWrr 1275
+PHSUBWrm 1276
+PHSUBWrr 1277
+PI 1278
+PINSRBrmi 1279
+PINSRBrri 1280
+PINSRDrmi 1281
+PINSRDrri 1282
+PINSRQrmi 1283
+PINSRQrri 1284
+PINSRWrmi 1285
+PINSRWrri 1286
+PLDTILECFGV 1287
+PLEA 1288
+PMADDUBSWrm 1289
+PMADDUBSWrr 1290
+PMADDWDrm 1291
+PMADDWDrr 1292
+PMAXSBrm 1293
+PMAXSBrr 1294
+PMAXSDrm 1295
+PMAXSDrr 1296
+PMAXSWrm 1297
+PMAXSWrr 1298
+PMAXUBrm 1299
+PMAXUBrr 1300
+PMAXUDrm 1301
+PMAXUDrr 1302
+PMAXUWrm 1303
+PMAXUWrr 1304
+PMINSBrm 1305
+PMINSBrr 1306
+PMINSDrm 1307
+PMINSDrr 1308
+PMINSWrm 1309
+PMINSWrr 1310
+PMINUBrm 1311
+PMINUBrr 1312
+PMINUDrm 1313
+PMINUDrr 1314
+PMINUWrm 1315
+PMINUWrr 1316
+PMOVMSKBrr 1317
+PMOVSXBDrm 1318
+PMOVSXBDrr 1319
+PMOVSXBQrm 1320
+PMOVSXBQrr 1321
+PMOVSXBWrm 1322
+PMOVSXBWrr 1323
+PMOVSXDQrm 1324
+PMOVSXDQrr 1325
+PMOVSXWDrm 1326
+PMOVSXWDrr 1327
+PMOVSXWQrm 1328
+PMOVSXWQrr 1329
+PMOVZXBDrm 1330
+PMOVZXBDrr 1331
+PMOVZXBQrm 1332
+PMOVZXBQrr 1333
+PMOVZXBWrm 1334
+PMOVZXBWrr 1335
+PMOVZXDQrm 1336
+PMOVZXDQrr 1337
+PMOVZXWDrm 1338
+PMOVZXWDrr 1339
+PMOVZXWQrm 1340
+PMOVZXWQrr 1341
+PMULDQrm 1342
+PMULDQrr 1343
+PMULHRSWrm 1344
+PMULHRSWrr 1345
+PMULHRWrm 1346
+PMULHRWrr 1347
+PMULHUWrm 1348
+PMULHUWrr 1349
+PMULHWrm 1350
+PMULHWrr 1351
+PMULLDrm 1352
+PMULLDrr 1353
+PMULLWrm 1354
+PMULLWrr 1355
+PMULUDQrm 1356
+PMULUDQrr 1357
+POP 1358
+POPA 1359
+POPCNT 1360
+POPDS 1361
+POPES 1362
+POPF 1363
+POPFS 1364
+POPGS 1365
+POPP 1366
+POPSS 1367
+PORrm 1368
+PORrr 1369
+PREALLOCATED_ARG 1370
+PREALLOCATED_SETUP 1371
+PREFETCH 1372
+PREFETCHIT 1373
+PREFETCHNTA 1374
+PREFETCHRST 1375
+PREFETCHT 1376
+PREFETCHW 1377
+PREFETCHWT 1378
+PROBED_ALLOCA 1379
+PSADBWrm 1380
+PSADBWrr 1381
+PSEUDO_PROBE 1382
+PSHUFBrm 1383
+PSHUFBrr 1384
+PSHUFDmi 1385
+PSHUFDri 1386
+PSHUFHWmi 1387
+PSHUFHWri 1388
+PSHUFLWmi 1389
+PSHUFLWri 1390
+PSIGNBrm 1391
+PSIGNBrr 1392
+PSIGNDrm 1393
+PSIGNDrr 1394
+PSIGNWrm 1395
+PSIGNWrr 1396
+PSLLDQri 1397
+PSLLDri 1398
+PSLLDrm 1399
+PSLLDrr 1400
+PSLLQri 1401
+PSLLQrm 1402
+PSLLQrr 1403
+PSLLWri 1404
+PSLLWrm 1405
+PSLLWrr 1406
+PSMASH 1407
+PSRADri 1408
+PSRADrm 1409
+PSRADrr 1410
+PSRAWri 1411
+PSRAWrm 1412
+PSRAWrr 1413
+PSRLDQri 1414
+PSRLDri 1415
+PSRLDrm 1416
+PSRLDrr 1417
+PSRLQri 1418
+PSRLQrm 1419
+PSRLQrr 1420
+PSRLWri 1421
+PSRLWrm 1422
+PSRLWrr 1423
+PSUBBrm 1424
+PSUBBrr 1425
+PSUBDrm 1426
+PSUBDrr 1427
+PSUBQrm 1428
+PSUBQrr 1429
+PSUBSBrm 1430
+PSUBSBrr 1431
+PSUBSWrm 1432
+PSUBSWrr 1433
+PSUBUSBrm 1434
+PSUBUSBrr 1435
+PSUBUSWrm 1436
+PSUBUSWrr 1437
+PSUBWrm 1438
+PSUBWrr 1439
+PSWAPDrm 1440
+PSWAPDrr 1441
+PTCMMIMFP 1442
+PTCMMRLFP 1443
+PTCVTROWD 1444
+PTCVTROWPS 1445
+PTDPBF 1446
+PTDPBHF 1447
+PTDPBSSD 1448
+PTDPBSSDV 1449
+PTDPBSUD 1450
+PTDPBSUDV 1451
+PTDPBUSD 1452
+PTDPBUSDV 1453
+PTDPBUUD 1454
+PTDPBUUDV 1455
+PTDPFP 1456
+PTDPHBF 1457
+PTDPHF 1458
+PTESTrm 1459
+PTESTrr 1460
+PTILELOADD 1461
+PTILELOADDRS 1462
+PTILELOADDRST 1463
+PTILELOADDRSV 1464
+PTILELOADDT 1465
+PTILELOADDV 1466
+PTILEMOVROWrre 1467
+PTILEMOVROWrreV 1468
+PTILEMOVROWrri 1469
+PTILEMOVROWrriV 1470
+PTILESTORED 1471
+PTILESTOREDV 1472
+PTILEZERO 1473
+PTILEZEROV 1474
+PTMMULTF 1475
+PTWRITE 1476
+PTWRITEm 1477
+PTWRITEr 1478
+PUNPCKHBWrm 1479
+PUNPCKHBWrr 1480
+PUNPCKHDQrm 1481
+PUNPCKHDQrr 1482
+PUNPCKHQDQrm 1483
+PUNPCKHQDQrr 1484
+PUNPCKHWDrm 1485
+PUNPCKHWDrr 1486
+PUNPCKLBWrm 1487
+PUNPCKLBWrr 1488
+PUNPCKLDQrm 1489
+PUNPCKLDQrr 1490
+PUNPCKLQDQrm 1491
+PUNPCKLQDQrr 1492
+PUNPCKLWDrm 1493
+PUNPCKLWDrr 1494
+PUSH 1495
+PUSHA 1496
+PUSHCS 1497
+PUSHDS 1498
+PUSHES 1499
+PUSHF 1500
+PUSHFS 1501
+PUSHGS 1502
+PUSHP 1503
+PUSHSS 1504
+PVALIDATE 1505
+PXORrm 1506
+PXORrr 1507
+RCL 1508
+RCPPSm 1509
+RCPPSr 1510
+RCPSSm 1511
+RCPSSm_Int 1512
+RCPSSr 1513
+RCPSSr_Int 1514
+RCR 1515
+RDFLAGS 1516
+RDFSBASE 1517
+RDGSBASE 1518
+RDMSR 1519
+RDMSRLIST 1520
+RDMSRri 1521
+RDMSRri_EVEX 1522
+RDPID 1523
+RDPKRUr 1524
+RDPMC 1525
+RDPRU 1526
+RDRAND 1527
+RDSEED 1528
+RDSSPD 1529
+RDSSPQ 1530
+RDTSC 1531
+RDTSCP 1532
+REG_SEQUENCE 1533
+REPNE_PREFIX 1534
+REP_MOVSB 1535
+REP_MOVSD 1536
+REP_MOVSQ 1537
+REP_MOVSW 1538
+REP_PREFIX 1539
+REP_STOSB 1540
+REP_STOSD 1541
+REP_STOSQ 1542
+REP_STOSW 1543
+RET 1544
+RETI 1545
+REX 1546
+RMPADJUST 1547
+RMPQUERY 1548
+RMPUPDATE 1549
+ROL 1550
+ROR 1551
+RORX 1552
+ROUNDPDmi 1553
+ROUNDPDri 1554
+ROUNDPSmi 1555
+ROUNDPSri 1556
+ROUNDSDmi 1557
+ROUNDSDmi_Int 1558
+ROUNDSDri 1559
+ROUNDSDri_Int 1560
+ROUNDSSmi 1561
+ROUNDSSmi_Int 1562
+ROUNDSSri 1563
+ROUNDSSri_Int 1564
+RSM 1565
+RSQRTPSm 1566
+RSQRTPSr 1567
+RSQRTSSm 1568
+RSQRTSSm_Int 1569
+RSQRTSSr 1570
+RSQRTSSr_Int 1571
+RSTORSSP 1572
+SAHF 1573
+SALC 1574
+SAR 1575
+SARX 1576
+SAVEPREVSSP 1577
+SBB 1578
+SCASB 1579
+SCASL 1580
+SCASQ 1581
+SCASW 1582
+SEAMCALL 1583
+SEAMOPS 1584
+SEAMRET 1585
+SEG_ALLOCA 1586
+SEH_BeginEpilogue 1587
+SEH_EndEpilogue 1588
+SEH_EndPrologue 1589
+SEH_PushFrame 1590
+SEH_PushReg 1591
+SEH_SaveReg 1592
+SEH_SaveXMM 1593
+SEH_SetFrame 1594
+SEH_StackAlign 1595
+SEH_StackAlloc 1596
+SEH_UnwindV 1597
+SEH_UnwindVersion 1598
+SENDUIPI 1599
+SERIALIZE 1600
+SETB_C 1601
+SETCCm 1602
+SETCCm_EVEX 1603
+SETCCr 1604
+SETCCr_EVEX 1605
+SETSSBSY 1606
+SETZUCCm 1607
+SETZUCCr 1608
+SFENCE 1609
+SGDT 1610
+SHA 1611
+SHL 1612
+SHLD 1613
+SHLDROT 1614
+SHLX 1615
+SHR 1616
+SHRD 1617
+SHRDROT 1618
+SHRX 1619
+SHUFPDrmi 1620
+SHUFPDrri 1621
+SHUFPSrmi 1622
+SHUFPSrri 1623
+SIDT 1624
+SKINIT 1625
+SLDT 1626
+SLWPCB 1627
+SMSW 1628
+SQRTPDm 1629
+SQRTPDr 1630
+SQRTPSm 1631
+SQRTPSr 1632
+SQRTSDm 1633
+SQRTSDm_Int 1634
+SQRTSDr 1635
+SQRTSDr_Int 1636
+SQRTSSm 1637
+SQRTSSm_Int 1638
+SQRTSSr 1639
+SQRTSSr_Int 1640
+SQRT_F 1641
+SQRT_Fp 1642
+SS_PREFIX 1643
+STAC 1644
+STACKALLOC_W_PROBING 1645
+STACKMAP 1646
+STATEPOINT 1647
+STC 1648
+STD 1649
+STGI 1650
+STI 1651
+STMXCSR 1652
+STOSB 1653
+STOSL 1654
+STOSQ 1655
+STOSW 1656
+STR 1657
+STRm 1658
+STTILECFG 1659
+STTILECFG_EVEX 1660
+STUI 1661
+ST_F 1662
+ST_FP 1663
+ST_FPrr 1664
+ST_Fp 1665
+ST_FpP 1666
+ST_Frr 1667
+SUB 1668
+SUBPDrm 1669
+SUBPDrr 1670
+SUBPSrm 1671
+SUBPSrr 1672
+SUBREG_TO_REG 1673
+SUBR_F 1674
+SUBR_FI 1675
+SUBR_FPrST 1676
+SUBR_FST 1677
+SUBR_Fp 1678
+SUBR_FpI 1679
+SUBR_FrST 1680
+SUBSDrm 1681
+SUBSDrm_Int 1682
+SUBSDrr 1683
+SUBSDrr_Int 1684
+SUBSSrm 1685
+SUBSSrm_Int 1686
+SUBSSrr 1687
+SUBSSrr_Int 1688
+SUB_F 1689
+SUB_FI 1690
+SUB_FPrST 1691
+SUB_FST 1692
+SUB_Fp 1693
+SUB_FpI 1694
+SUB_FrST 1695
+SWAPGS 1696
+SYSCALL 1697
+SYSENTER 1698
+SYSEXIT 1699
+SYSRET 1700
+T 1701
+TAILJMPd 1702
+TAILJMPd_CC 1703
+TAILJMPm 1704
+TAILJMPr 1705
+TCMMIMFP 1706
+TCMMRLFP 1707
+TCRETURN_HIPE 1708
+TCRETURN_WIN 1709
+TCRETURN_WINmi 1710
+TCRETURNdi 1711
+TCRETURNdicc 1712
+TCRETURNmi 1713
+TCRETURNri 1714
+TCVTROWD 1715
+TCVTROWPS 1716
+TDCALL 1717
+TDPBF 1718
+TDPBHF 1719
+TDPBSSD 1720
+TDPBSUD 1721
+TDPBUSD 1722
+TDPBUUD 1723
+TDPFP 1724
+TDPHBF 1725
+TDPHF 1726
+TEST 1727
+TESTUI 1728
+TILELOADD 1729
+TILELOADDRS 1730
+TILELOADDRST 1731
+TILELOADDRS_EVEX 1732
+TILELOADDT 1733
+TILELOADD_EVEX 1734
+TILEMOVROWrre 1735
+TILEMOVROWrri 1736
+TILERELEASE 1737
+TILESTORED 1738
+TILESTORED_EVEX 1739
+TILEZERO 1740
+TLBSYNC 1741
+TLSCall 1742
+TLS_addr 1743
+TLS_addrX 1744
+TLS_base_addr 1745
+TLS_base_addrX 1746
+TLS_desc 1747
+TMMULTF 1748
+TPAUSE 1749
+TRAP 1750
+TST_F 1751
+TST_Fp 1752
+TZCNT 1753
+TZMSK 1754
+UBSAN_UD 1755
+UCOMISDrm 1756
+UCOMISDrm_Int 1757
+UCOMISDrr 1758
+UCOMISDrr_Int 1759
+UCOMISSrm 1760
+UCOMISSrm_Int 1761
+UCOMISSrr 1762
+UCOMISSrr_Int 1763
+UCOM_FIPr 1764
+UCOM_FIr 1765
+UCOM_FPPr 1766
+UCOM_FPr 1767
+UCOM_FpIr 1768
+UCOM_Fpr 1769
+UCOM_Fr 1770
+UD 1771
+UIRET 1772
+UMONITOR 1773
+UMWAIT 1774
+UNPCKHPDrm 1775
+UNPCKHPDrr 1776
+UNPCKHPSrm 1777
+UNPCKHPSrr 1778
+UNPCKLPDrm 1779
+UNPCKLPDrr 1780
+UNPCKLPSrm 1781
+UNPCKLPSrr 1782
+URDMSRri 1783
+URDMSRri_EVEX 1784
+URDMSRrr 1785
+URDMSRrr_EVEX 1786
+UWRMSRir 1787
+UWRMSRir_EVEX 1788
+UWRMSRrr 1789
+UWRMSRrr_EVEX 1790
+V 1791
+VAARG 1792
+VAARG_X 1793
+VADDBF 1794
+VADDPDYrm 1795
+VADDPDYrr 1796
+VADDPDZ 1797
+VADDPDZrm 1798
+VADDPDZrmb 1799
+VADDPDZrmbk 1800
+VADDPDZrmbkz 1801
+VADDPDZrmk 1802
+VADDPDZrmkz 1803
+VADDPDZrr 1804
+VADDPDZrrb 1805
+VADDPDZrrbk 1806
+VADDPDZrrbkz 1807
+VADDPDZrrk 1808
+VADDPDZrrkz 1809
+VADDPDrm 1810
+VADDPDrr 1811
+VADDPHZ 1812
+VADDPHZrm 1813
+VADDPHZrmb 1814
+VADDPHZrmbk 1815
+VADDPHZrmbkz 1816
+VADDPHZrmk 1817
+VADDPHZrmkz 1818
+VADDPHZrr 1819
+VADDPHZrrb 1820
+VADDPHZrrbk 1821
+VADDPHZrrbkz 1822
+VADDPHZrrk 1823
+VADDPHZrrkz 1824
+VADDPSYrm 1825
+VADDPSYrr 1826
+VADDPSZ 1827
+VADDPSZrm 1828
+VADDPSZrmb 1829
+VADDPSZrmbk 1830
+VADDPSZrmbkz 1831
+VADDPSZrmk 1832
+VADDPSZrmkz 1833
+VADDPSZrr 1834
+VADDPSZrrb 1835
+VADDPSZrrbk 1836
+VADDPSZrrbkz 1837
+VADDPSZrrk 1838
+VADDPSZrrkz 1839
+VADDPSrm 1840
+VADDPSrr 1841
+VADDSDZrm 1842
+VADDSDZrm_Int 1843
+VADDSDZrmk_Int 1844
+VADDSDZrmkz_Int 1845
+VADDSDZrr 1846
+VADDSDZrr_Int 1847
+VADDSDZrrb_Int 1848
+VADDSDZrrbk_Int 1849
+VADDSDZrrbkz_Int 1850
+VADDSDZrrk_Int 1851
+VADDSDZrrkz_Int 1852
+VADDSDrm 1853
+VADDSDrm_Int 1854
+VADDSDrr 1855
+VADDSDrr_Int 1856
+VADDSHZrm 1857
+VADDSHZrm_Int 1858
+VADDSHZrmk_Int 1859
+VADDSHZrmkz_Int 1860
+VADDSHZrr 1861
+VADDSHZrr_Int 1862
+VADDSHZrrb_Int 1863
+VADDSHZrrbk_Int 1864
+VADDSHZrrbkz_Int 1865
+VADDSHZrrk_Int 1866
+VADDSHZrrkz_Int 1867
+VADDSSZrm 1868
+VADDSSZrm_Int 1869
+VADDSSZrmk_Int 1870
+VADDSSZrmkz_Int 1871
+VADDSSZrr 1872
+VADDSSZrr_Int 1873
+VADDSSZrrb_Int 1874
+VADDSSZrrbk_Int 1875
+VADDSSZrrbkz_Int 1876
+VADDSSZrrk_Int 1877
+VADDSSZrrkz_Int 1878
+VADDSSrm 1879
+VADDSSrm_Int 1880
+VADDSSrr 1881
+VADDSSrr_Int 1882
+VADDSUBPDYrm 1883
+VADDSUBPDYrr 1884
+VADDSUBPDrm 1885
+VADDSUBPDrr 1886
+VADDSUBPSYrm 1887
+VADDSUBPSYrr 1888
+VADDSUBPSrm 1889
+VADDSUBPSrr 1890
+VAESDECLASTYrm 1891
+VAESDECLASTYrr 1892
+VAESDECLASTZ 1893
+VAESDECLASTZrm 1894
+VAESDECLASTZrr 1895
+VAESDECLASTrm 1896
+VAESDECLASTrr 1897
+VAESDECYrm 1898
+VAESDECYrr 1899
+VAESDECZ 1900
+VAESDECZrm 1901
+VAESDECZrr 1902
+VAESDECrm 1903
+VAESDECrr 1904
+VAESENCLASTYrm 1905
+VAESENCLASTYrr 1906
+VAESENCLASTZ 1907
+VAESENCLASTZrm 1908
+VAESENCLASTZrr 1909
+VAESENCLASTrm 1910
+VAESENCLASTrr 1911
+VAESENCYrm 1912
+VAESENCYrr 1913
+VAESENCZ 1914
+VAESENCZrm 1915
+VAESENCZrr 1916
+VAESENCrm 1917
+VAESENCrr 1918
+VAESIMCrm 1919
+VAESIMCrr 1920
+VAESKEYGENASSISTrmi 1921
+VAESKEYGENASSISTrri 1922
+VALIGNDZ 1923
+VALIGNDZrmbi 1924
+VALIGNDZrmbik 1925
+VALIGNDZrmbikz 1926
+VALIGNDZrmi 1927
+VALIGNDZrmik 1928
+VALIGNDZrmikz 1929
+VALIGNDZrri 1930
+VALIGNDZrrik 1931
+VALIGNDZrrikz 1932
+VALIGNQZ 1933
+VALIGNQZrmbi 1934
+VALIGNQZrmbik 1935
+VALIGNQZrmbikz 1936
+VALIGNQZrmi 1937
+VALIGNQZrmik 1938
+VALIGNQZrmikz 1939
+VALIGNQZrri 1940
+VALIGNQZrrik 1941
+VALIGNQZrrikz 1942
+VANDNPDYrm 1943
+VANDNPDYrr 1944
+VANDNPDZ 1945
+VANDNPDZrm 1946
+VANDNPDZrmb 1947
+VANDNPDZrmbk 1948
+VANDNPDZrmbkz 1949
+VANDNPDZrmk 1950
+VANDNPDZrmkz 1951
+VANDNPDZrr 1952
+VANDNPDZrrk 1953
+VANDNPDZrrkz 1954
+VANDNPDrm 1955
+VANDNPDrr 1956
+VANDNPSYrm 1957
+VANDNPSYrr 1958
+VANDNPSZ 1959
+VANDNPSZrm 1960
+VANDNPSZrmb 1961
+VANDNPSZrmbk 1962
+VANDNPSZrmbkz 1963
+VANDNPSZrmk 1964
+VANDNPSZrmkz 1965
+VANDNPSZrr 1966
+VANDNPSZrrk 1967
+VANDNPSZrrkz 1968
+VANDNPSrm 1969
+VANDNPSrr 1970
+VANDPDYrm 1971
+VANDPDYrr 1972
+VANDPDZ 1973
+VANDPDZrm 1974
+VANDPDZrmb 1975
+VANDPDZrmbk 1976
+VANDPDZrmbkz 1977
+VANDPDZrmk 1978
+VANDPDZrmkz 1979
+VANDPDZrr 1980
+VANDPDZrrk 1981
+VANDPDZrrkz 1982
+VANDPDrm 1983
+VANDPDrr 1984
+VANDPSYrm 1985
+VANDPSYrr 1986
+VANDPSZ 1987
+VANDPSZrm 1988
+VANDPSZrmb 1989
+VANDPSZrmbk 1990
+VANDPSZrmbkz 1991
+VANDPSZrmk 1992
+VANDPSZrmkz 1993
+VANDPSZrr 1994
+VANDPSZrrk 1995
+VANDPSZrrkz 1996
+VANDPSrm 1997
+VANDPSrr 1998
+VASTART_SAVE_XMM_REGS 1999
+VBCSTNEBF 2000
+VBCSTNESH 2001
+VBLENDMPDZ 2002
+VBLENDMPDZrm 2003
+VBLENDMPDZrmb 2004
+VBLENDMPDZrmbk 2005
+VBLENDMPDZrmbkz 2006
+VBLENDMPDZrmk 2007
+VBLENDMPDZrmkz 2008
+VBLENDMPDZrr 2009
+VBLENDMPDZrrk 2010
+VBLENDMPDZrrkz 2011
+VBLENDMPSZ 2012
+VBLENDMPSZrm 2013
+VBLENDMPSZrmb 2014
+VBLENDMPSZrmbk 2015
+VBLENDMPSZrmbkz 2016
+VBLENDMPSZrmk 2017
+VBLENDMPSZrmkz 2018
+VBLENDMPSZrr 2019
+VBLENDMPSZrrk 2020
+VBLENDMPSZrrkz 2021
+VBLENDPDYrmi 2022
+VBLENDPDYrri 2023
+VBLENDPDrmi 2024
+VBLENDPDrri 2025
+VBLENDPSYrmi 2026
+VBLENDPSYrri 2027
+VBLENDPSrmi 2028
+VBLENDPSrri 2029
+VBLENDVPDYrmr 2030
+VBLENDVPDYrrr 2031
+VBLENDVPDrmr 2032
+VBLENDVPDrrr 2033
+VBLENDVPSYrmr 2034
+VBLENDVPSYrrr 2035
+VBLENDVPSrmr 2036
+VBLENDVPSrrr 2037
+VBROADCASTF 2038
+VBROADCASTI 2039
+VBROADCASTSDYrm 2040
+VBROADCASTSDYrr 2041
+VBROADCASTSDZ 2042
+VBROADCASTSDZrm 2043
+VBROADCASTSDZrmk 2044
+VBROADCASTSDZrmkz 2045
+VBROADCASTSDZrr 2046
+VBROADCASTSDZrrk 2047
+VBROADCASTSDZrrkz 2048
+VBROADCASTSSYrm 2049
+VBROADCASTSSYrr 2050
+VBROADCASTSSZ 2051
+VBROADCASTSSZrm 2052
+VBROADCASTSSZrmk 2053
+VBROADCASTSSZrmkz 2054
+VBROADCASTSSZrr 2055
+VBROADCASTSSZrrk 2056
+VBROADCASTSSZrrkz 2057
+VBROADCASTSSrm 2058
+VBROADCASTSSrr 2059
+VCMPBF 2060
+VCMPPDYrmi 2061
+VCMPPDYrri 2062
+VCMPPDZ 2063
+VCMPPDZrmbi 2064
+VCMPPDZrmbik 2065
+VCMPPDZrmi 2066
+VCMPPDZrmik 2067
+VCMPPDZrri 2068
+VCMPPDZrrib 2069
+VCMPPDZrribk 2070
+VCMPPDZrrik 2071
+VCMPPDrmi 2072
+VCMPPDrri 2073
+VCMPPHZ 2074
+VCMPPHZrmbi 2075
+VCMPPHZrmbik 2076
+VCMPPHZrmi 2077
+VCMPPHZrmik 2078
+VCMPPHZrri 2079
+VCMPPHZrrib 2080
+VCMPPHZrribk 2081
+VCMPPHZrrik 2082
+VCMPPSYrmi 2083
+VCMPPSYrri 2084
+VCMPPSZ 2085
+VCMPPSZrmbi 2086
+VCMPPSZrmbik 2087
+VCMPPSZrmi 2088
+VCMPPSZrmik 2089
+VCMPPSZrri 2090
+VCMPPSZrrib 2091
+VCMPPSZrribk 2092
+VCMPPSZrrik 2093
+VCMPPSrmi 2094
+VCMPPSrri 2095
+VCMPSDZrmi 2096
+VCMPSDZrmi_Int 2097
+VCMPSDZrmik_Int 2098
+VCMPSDZrri 2099
+VCMPSDZrri_Int 2100
+VCMPSDZrrib_Int 2101
+VCMPSDZrribk_Int 2102
+VCMPSDZrrik_Int 2103
+VCMPSDrmi 2104
+VCMPSDrmi_Int 2105
+VCMPSDrri 2106
+VCMPSDrri_Int 2107
+VCMPSHZrmi 2108
+VCMPSHZrmi_Int 2109
+VCMPSHZrmik_Int 2110
+VCMPSHZrri 2111
+VCMPSHZrri_Int 2112
+VCMPSHZrrib_Int 2113
+VCMPSHZrribk_Int 2114
+VCMPSHZrrik_Int 2115
+VCMPSSZrmi 2116
+VCMPSSZrmi_Int 2117
+VCMPSSZrmik_Int 2118
+VCMPSSZrri 2119
+VCMPSSZrri_Int 2120
+VCMPSSZrrib_Int 2121
+VCMPSSZrribk_Int 2122
+VCMPSSZrrik_Int 2123
+VCMPSSrmi 2124
+VCMPSSrmi_Int 2125
+VCMPSSrri 2126
+VCMPSSrri_Int 2127
+VCOMISBF 2128
+VCOMISDZrm 2129
+VCOMISDZrm_Int 2130
+VCOMISDZrr 2131
+VCOMISDZrr_Int 2132
+VCOMISDZrrb 2133
+VCOMISDrm 2134
+VCOMISDrm_Int 2135
+VCOMISDrr 2136
+VCOMISDrr_Int 2137
+VCOMISHZrm 2138
+VCOMISHZrm_Int 2139
+VCOMISHZrr 2140
+VCOMISHZrr_Int 2141
+VCOMISHZrrb 2142
+VCOMISSZrm 2143
+VCOMISSZrm_Int 2144
+VCOMISSZrr 2145
+VCOMISSZrr_Int 2146
+VCOMISSZrrb 2147
+VCOMISSrm 2148
+VCOMISSrm_Int 2149
+VCOMISSrr 2150
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+VRNDSCALESDZrmik_Int 6314
+VRNDSCALESDZrmikz_Int 6315
+VRNDSCALESDZrri 6316
+VRNDSCALESDZrri_Int 6317
+VRNDSCALESDZrrib_Int 6318
+VRNDSCALESDZrribk_Int 6319
+VRNDSCALESDZrribkz_Int 6320
+VRNDSCALESDZrrik_Int 6321
+VRNDSCALESDZrrikz_Int 6322
+VRNDSCALESHZrmi 6323
+VRNDSCALESHZrmi_Int 6324
+VRNDSCALESHZrmik_Int 6325
+VRNDSCALESHZrmikz_Int 6326
+VRNDSCALESHZrri 6327
+VRNDSCALESHZrri_Int 6328
+VRNDSCALESHZrrib_Int 6329
+VRNDSCALESHZrribk_Int 6330
+VRNDSCALESHZrribkz_Int 6331
+VRNDSCALESHZrrik_Int 6332
+VRNDSCALESHZrrikz_Int 6333
+VRNDSCALESSZrmi 6334
+VRNDSCALESSZrmi_Int 6335
+VRNDSCALESSZrmik_Int 6336
+VRNDSCALESSZrmikz_Int 6337
+VRNDSCALESSZrri 6338
+VRNDSCALESSZrri_Int 6339
+VRNDSCALESSZrrib_Int 6340
+VRNDSCALESSZrribk_Int 6341
+VRNDSCALESSZrribkz_Int 6342
+VRNDSCALESSZrrik_Int 6343
+VRNDSCALESSZrrikz_Int 6344
+VROUNDPDYmi 6345
+VROUNDPDYri 6346
+VROUNDPDmi 6347
+VROUNDPDri 6348
+VROUNDPSYmi 6349
+VROUNDPSYri 6350
+VROUNDPSmi 6351
+VROUNDPSri 6352
+VROUNDSDmi 6353
+VROUNDSDmi_Int 6354
+VROUNDSDri 6355
+VROUNDSDri_Int 6356
+VROUNDSSmi 6357
+VROUNDSSmi_Int 6358
+VROUNDSSri 6359
+VROUNDSSri_Int 6360
+VRSQRT 6361
+VRSQRTBF 6362
+VRSQRTPHZ 6363
+VRSQRTPHZm 6364
+VRSQRTPHZmb 6365
+VRSQRTPHZmbk 6366
+VRSQRTPHZmbkz 6367
+VRSQRTPHZmk 6368
+VRSQRTPHZmkz 6369
+VRSQRTPHZr 6370
+VRSQRTPHZrk 6371
+VRSQRTPHZrkz 6372
+VRSQRTPSYm 6373
+VRSQRTPSYr 6374
+VRSQRTPSm 6375
+VRSQRTPSr 6376
+VRSQRTSHZrm 6377
+VRSQRTSHZrmk 6378
+VRSQRTSHZrmkz 6379
+VRSQRTSHZrr 6380
+VRSQRTSHZrrk 6381
+VRSQRTSHZrrkz 6382
+VRSQRTSSm 6383
+VRSQRTSSm_Int 6384
+VRSQRTSSr 6385
+VRSQRTSSr_Int 6386
+VSCALEFBF 6387
+VSCALEFPDZ 6388
+VSCALEFPDZrm 6389
+VSCALEFPDZrmb 6390
+VSCALEFPDZrmbk 6391
+VSCALEFPDZrmbkz 6392
+VSCALEFPDZrmk 6393
+VSCALEFPDZrmkz 6394
+VSCALEFPDZrr 6395
+VSCALEFPDZrrb 6396
+VSCALEFPDZrrbk 6397
+VSCALEFPDZrrbkz 6398
+VSCALEFPDZrrk 6399
+VSCALEFPDZrrkz 6400
+VSCALEFPHZ 6401
+VSCALEFPHZrm 6402
+VSCALEFPHZrmb 6403
+VSCALEFPHZrmbk 6404
+VSCALEFPHZrmbkz 6405
+VSCALEFPHZrmk 6406
+VSCALEFPHZrmkz 6407
+VSCALEFPHZrr 6408
+VSCALEFPHZrrb 6409
+VSCALEFPHZrrbk 6410
+VSCALEFPHZrrbkz 6411
+VSCALEFPHZrrk 6412
+VSCALEFPHZrrkz 6413
+VSCALEFPSZ 6414
+VSCALEFPSZrm 6415
+VSCALEFPSZrmb 6416
+VSCALEFPSZrmbk 6417
+VSCALEFPSZrmbkz 6418
+VSCALEFPSZrmk 6419
+VSCALEFPSZrmkz 6420
+VSCALEFPSZrr 6421
+VSCALEFPSZrrb 6422
+VSCALEFPSZrrbk 6423
+VSCALEFPSZrrbkz 6424
+VSCALEFPSZrrk 6425
+VSCALEFPSZrrkz 6426
+VSCALEFSDZrm 6427
+VSCALEFSDZrmk 6428
+VSCALEFSDZrmkz 6429
+VSCALEFSDZrr 6430
+VSCALEFSDZrrb_Int 6431
+VSCALEFSDZrrbk_Int 6432
+VSCALEFSDZrrbkz_Int 6433
+VSCALEFSDZrrk 6434
+VSCALEFSDZrrkz 6435
+VSCALEFSHZrm 6436
+VSCALEFSHZrmk 6437
+VSCALEFSHZrmkz 6438
+VSCALEFSHZrr 6439
+VSCALEFSHZrrb_Int 6440
+VSCALEFSHZrrbk_Int 6441
+VSCALEFSHZrrbkz_Int 6442
+VSCALEFSHZrrk 6443
+VSCALEFSHZrrkz 6444
+VSCALEFSSZrm 6445
+VSCALEFSSZrmk 6446
+VSCALEFSSZrmkz 6447
+VSCALEFSSZrr 6448
+VSCALEFSSZrrb_Int 6449
+VSCALEFSSZrrbk_Int 6450
+VSCALEFSSZrrbkz_Int 6451
+VSCALEFSSZrrk 6452
+VSCALEFSSZrrkz 6453
+VSCATTERDPDZ 6454
+VSCATTERDPDZmr 6455
+VSCATTERDPSZ 6456
+VSCATTERDPSZmr 6457
+VSCATTERPF 6458
+VSCATTERQPDZ 6459
+VSCATTERQPDZmr 6460
+VSCATTERQPSZ 6461
+VSCATTERQPSZmr 6462
+VSHA 6463
+VSHUFF 6464
+VSHUFI 6465
+VSHUFPDYrmi 6466
+VSHUFPDYrri 6467
+VSHUFPDZ 6468
+VSHUFPDZrmbi 6469
+VSHUFPDZrmbik 6470
+VSHUFPDZrmbikz 6471
+VSHUFPDZrmi 6472
+VSHUFPDZrmik 6473
+VSHUFPDZrmikz 6474
+VSHUFPDZrri 6475
+VSHUFPDZrrik 6476
+VSHUFPDZrrikz 6477
+VSHUFPDrmi 6478
+VSHUFPDrri 6479
+VSHUFPSYrmi 6480
+VSHUFPSYrri 6481
+VSHUFPSZ 6482
+VSHUFPSZrmbi 6483
+VSHUFPSZrmbik 6484
+VSHUFPSZrmbikz 6485
+VSHUFPSZrmi 6486
+VSHUFPSZrmik 6487
+VSHUFPSZrmikz 6488
+VSHUFPSZrri 6489
+VSHUFPSZrrik 6490
+VSHUFPSZrrikz 6491
+VSHUFPSrmi 6492
+VSHUFPSrri 6493
+VSM 6494
+VSQRTBF 6495
+VSQRTPDYm 6496
+VSQRTPDYr 6497
+VSQRTPDZ 6498
+VSQRTPDZm 6499
+VSQRTPDZmb 6500
+VSQRTPDZmbk 6501
+VSQRTPDZmbkz 6502
+VSQRTPDZmk 6503
+VSQRTPDZmkz 6504
+VSQRTPDZr 6505
+VSQRTPDZrb 6506
+VSQRTPDZrbk 6507
+VSQRTPDZrbkz 6508
+VSQRTPDZrk 6509
+VSQRTPDZrkz 6510
+VSQRTPDm 6511
+VSQRTPDr 6512
+VSQRTPHZ 6513
+VSQRTPHZm 6514
+VSQRTPHZmb 6515
+VSQRTPHZmbk 6516
+VSQRTPHZmbkz 6517
+VSQRTPHZmk 6518
+VSQRTPHZmkz 6519
+VSQRTPHZr 6520
+VSQRTPHZrb 6521
+VSQRTPHZrbk 6522
+VSQRTPHZrbkz 6523
+VSQRTPHZrk 6524
+VSQRTPHZrkz 6525
+VSQRTPSYm 6526
+VSQRTPSYr 6527
+VSQRTPSZ 6528
+VSQRTPSZm 6529
+VSQRTPSZmb 6530
+VSQRTPSZmbk 6531
+VSQRTPSZmbkz 6532
+VSQRTPSZmk 6533
+VSQRTPSZmkz 6534
+VSQRTPSZr 6535
+VSQRTPSZrb 6536
+VSQRTPSZrbk 6537
+VSQRTPSZrbkz 6538
+VSQRTPSZrk 6539
+VSQRTPSZrkz 6540
+VSQRTPSm 6541
+VSQRTPSr 6542
+VSQRTSDZm 6543
+VSQRTSDZm_Int 6544
+VSQRTSDZmk_Int 6545
+VSQRTSDZmkz_Int 6546
+VSQRTSDZr 6547
+VSQRTSDZr_Int 6548
+VSQRTSDZrb_Int 6549
+VSQRTSDZrbk_Int 6550
+VSQRTSDZrbkz_Int 6551
+VSQRTSDZrk_Int 6552
+VSQRTSDZrkz_Int 6553
+VSQRTSDm 6554
+VSQRTSDm_Int 6555
+VSQRTSDr 6556
+VSQRTSDr_Int 6557
+VSQRTSHZm 6558
+VSQRTSHZm_Int 6559
+VSQRTSHZmk_Int 6560
+VSQRTSHZmkz_Int 6561
+VSQRTSHZr 6562
+VSQRTSHZr_Int 6563
+VSQRTSHZrb_Int 6564
+VSQRTSHZrbk_Int 6565
+VSQRTSHZrbkz_Int 6566
+VSQRTSHZrk_Int 6567
+VSQRTSHZrkz_Int 6568
+VSQRTSSZm 6569
+VSQRTSSZm_Int 6570
+VSQRTSSZmk_Int 6571
+VSQRTSSZmkz_Int 6572
+VSQRTSSZr 6573
+VSQRTSSZr_Int 6574
+VSQRTSSZrb_Int 6575
+VSQRTSSZrbk_Int 6576
+VSQRTSSZrbkz_Int 6577
+VSQRTSSZrk_Int 6578
+VSQRTSSZrkz_Int 6579
+VSQRTSSm 6580
+VSQRTSSm_Int 6581
+VSQRTSSr 6582
+VSQRTSSr_Int 6583
+VSTMXCSR 6584
+VSUBBF 6585
+VSUBPDYrm 6586
+VSUBPDYrr 6587
+VSUBPDZ 6588
+VSUBPDZrm 6589
+VSUBPDZrmb 6590
+VSUBPDZrmbk 6591
+VSUBPDZrmbkz 6592
+VSUBPDZrmk 6593
+VSUBPDZrmkz 6594
+VSUBPDZrr 6595
+VSUBPDZrrb 6596
+VSUBPDZrrbk 6597
+VSUBPDZrrbkz 6598
+VSUBPDZrrk 6599
+VSUBPDZrrkz 6600
+VSUBPDrm 6601
+VSUBPDrr 6602
+VSUBPHZ 6603
+VSUBPHZrm 6604
+VSUBPHZrmb 6605
+VSUBPHZrmbk 6606
+VSUBPHZrmbkz 6607
+VSUBPHZrmk 6608
+VSUBPHZrmkz 6609
+VSUBPHZrr 6610
+VSUBPHZrrb 6611
+VSUBPHZrrbk 6612
+VSUBPHZrrbkz 6613
+VSUBPHZrrk 6614
+VSUBPHZrrkz 6615
+VSUBPSYrm 6616
+VSUBPSYrr 6617
+VSUBPSZ 6618
+VSUBPSZrm 6619
+VSUBPSZrmb 6620
+VSUBPSZrmbk 6621
+VSUBPSZrmbkz 6622
+VSUBPSZrmk 6623
+VSUBPSZrmkz 6624
+VSUBPSZrr 6625
+VSUBPSZrrb 6626
+VSUBPSZrrbk 6627
+VSUBPSZrrbkz 6628
+VSUBPSZrrk 6629
+VSUBPSZrrkz 6630
+VSUBPSrm 6631
+VSUBPSrr 6632
+VSUBSDZrm 6633
+VSUBSDZrm_Int 6634
+VSUBSDZrmk_Int 6635
+VSUBSDZrmkz_Int 6636
+VSUBSDZrr 6637
+VSUBSDZrr_Int 6638
+VSUBSDZrrb_Int 6639
+VSUBSDZrrbk_Int 6640
+VSUBSDZrrbkz_Int 6641
+VSUBSDZrrk_Int 6642
+VSUBSDZrrkz_Int 6643
+VSUBSDrm 6644
+VSUBSDrm_Int 6645
+VSUBSDrr 6646
+VSUBSDrr_Int 6647
+VSUBSHZrm 6648
+VSUBSHZrm_Int 6649
+VSUBSHZrmk_Int 6650
+VSUBSHZrmkz_Int 6651
+VSUBSHZrr 6652
+VSUBSHZrr_Int 6653
+VSUBSHZrrb_Int 6654
+VSUBSHZrrbk_Int 6655
+VSUBSHZrrbkz_Int 6656
+VSUBSHZrrk_Int 6657
+VSUBSHZrrkz_Int 6658
+VSUBSSZrm 6659
+VSUBSSZrm_Int 6660
+VSUBSSZrmk_Int 6661
+VSUBSSZrmkz_Int 6662
+VSUBSSZrr 6663
+VSUBSSZrr_Int 6664
+VSUBSSZrrb_Int 6665
+VSUBSSZrrbk_Int 6666
+VSUBSSZrrbkz_Int 6667
+VSUBSSZrrk_Int 6668
+VSUBSSZrrkz_Int 6669
+VSUBSSrm 6670
+VSUBSSrm_Int 6671
+VSUBSSrr 6672
+VSUBSSrr_Int 6673
+VTESTPDYrm 6674
+VTESTPDYrr 6675
+VTESTPDrm 6676
+VTESTPDrr 6677
+VTESTPSYrm 6678
+VTESTPSYrr 6679
+VTESTPSrm 6680
+VTESTPSrr 6681
+VUCOMISDZrm 6682
+VUCOMISDZrm_Int 6683
+VUCOMISDZrr 6684
+VUCOMISDZrr_Int 6685
+VUCOMISDZrrb 6686
+VUCOMISDrm 6687
+VUCOMISDrm_Int 6688
+VUCOMISDrr 6689
+VUCOMISDrr_Int 6690
+VUCOMISHZrm 6691
+VUCOMISHZrm_Int 6692
+VUCOMISHZrr 6693
+VUCOMISHZrr_Int 6694
+VUCOMISHZrrb 6695
+VUCOMISSZrm 6696
+VUCOMISSZrm_Int 6697
+VUCOMISSZrr 6698
+VUCOMISSZrr_Int 6699
+VUCOMISSZrrb 6700
+VUCOMISSrm 6701
+VUCOMISSrm_Int 6702
+VUCOMISSrr 6703
+VUCOMISSrr_Int 6704
+VUCOMXSDZrm 6705
+VUCOMXSDZrm_Int 6706
+VUCOMXSDZrr 6707
+VUCOMXSDZrr_Int 6708
+VUCOMXSDZrrb_Int 6709
+VUCOMXSHZrm 6710
+VUCOMXSHZrm_Int 6711
+VUCOMXSHZrr 6712
+VUCOMXSHZrr_Int 6713
+VUCOMXSHZrrb_Int 6714
+VUCOMXSSZrm 6715
+VUCOMXSSZrm_Int 6716
+VUCOMXSSZrr 6717
+VUCOMXSSZrr_Int 6718
+VUCOMXSSZrrb_Int 6719
+VUNPCKHPDYrm 6720
+VUNPCKHPDYrr 6721
+VUNPCKHPDZ 6722
+VUNPCKHPDZrm 6723
+VUNPCKHPDZrmb 6724
+VUNPCKHPDZrmbk 6725
+VUNPCKHPDZrmbkz 6726
+VUNPCKHPDZrmk 6727
+VUNPCKHPDZrmkz 6728
+VUNPCKHPDZrr 6729
+VUNPCKHPDZrrk 6730
+VUNPCKHPDZrrkz 6731
+VUNPCKHPDrm 6732
+VUNPCKHPDrr 6733
+VUNPCKHPSYrm 6734
+VUNPCKHPSYrr 6735
+VUNPCKHPSZ 6736
+VUNPCKHPSZrm 6737
+VUNPCKHPSZrmb 6738
+VUNPCKHPSZrmbk 6739
+VUNPCKHPSZrmbkz 6740
+VUNPCKHPSZrmk 6741
+VUNPCKHPSZrmkz 6742
+VUNPCKHPSZrr 6743
+VUNPCKHPSZrrk 6744
+VUNPCKHPSZrrkz 6745
+VUNPCKHPSrm 6746
+VUNPCKHPSrr 6747
+VUNPCKLPDYrm 6748
+VUNPCKLPDYrr 6749
+VUNPCKLPDZ 6750
+VUNPCKLPDZrm 6751
+VUNPCKLPDZrmb 6752
+VUNPCKLPDZrmbk 6753
+VUNPCKLPDZrmbkz 6754
+VUNPCKLPDZrmk 6755
+VUNPCKLPDZrmkz 6756
+VUNPCKLPDZrr 6757
+VUNPCKLPDZrrk 6758
+VUNPCKLPDZrrkz 6759
+VUNPCKLPDrm 6760
+VUNPCKLPDrr 6761
+VUNPCKLPSYrm 6762
+VUNPCKLPSYrr 6763
+VUNPCKLPSZ 6764
+VUNPCKLPSZrm 6765
+VUNPCKLPSZrmb 6766
+VUNPCKLPSZrmbk 6767
+VUNPCKLPSZrmbkz 6768
+VUNPCKLPSZrmk 6769
+VUNPCKLPSZrmkz 6770
+VUNPCKLPSZrr 6771
+VUNPCKLPSZrrk 6772
+VUNPCKLPSZrrkz 6773
+VUNPCKLPSrm 6774
+VUNPCKLPSrr 6775
+VXORPDYrm 6776
+VXORPDYrr 6777
+VXORPDZ 6778
+VXORPDZrm 6779
+VXORPDZrmb 6780
+VXORPDZrmbk 6781
+VXORPDZrmbkz 6782
+VXORPDZrmk 6783
+VXORPDZrmkz 6784
+VXORPDZrr 6785
+VXORPDZrrk 6786
+VXORPDZrrkz 6787
+VXORPDrm 6788
+VXORPDrr 6789
+VXORPSYrm 6790
+VXORPSYrr 6791
+VXORPSZ 6792
+VXORPSZrm 6793
+VXORPSZrmb 6794
+VXORPSZrmbk 6795
+VXORPSZrmbkz 6796
+VXORPSZrmk 6797
+VXORPSZrmkz 6798
+VXORPSZrr 6799
+VXORPSZrrk 6800
+VXORPSZrrkz 6801
+VXORPSrm 6802
+VXORPSrr 6803
+VZEROALL 6804
+VZEROUPPER 6805
+V_SET 6806
+V_SETALLONES 6807
+WAIT 6808
+WBINVD 6809
+WBNOINVD 6810
+WRFLAGS 6811
+WRFSBASE 6812
+WRGSBASE 6813
+WRMSR 6814
+WRMSRLIST 6815
+WRMSRNS 6816
+WRMSRNSir 6817
+WRMSRNSir_EVEX 6818
+WRPKRUr 6819
+WRSSD 6820
+WRSSD_EVEX 6821
+WRSSQ 6822
+WRSSQ_EVEX 6823
+WRUSSD 6824
+WRUSSD_EVEX 6825
+WRUSSQ 6826
+WRUSSQ_EVEX 6827
+XABORT 6828
+XABORT_DEF 6829
+XACQUIRE_PREFIX 6830
+XADD 6831
+XAM_F 6832
+XAM_Fp 6833
+XBEGIN 6834
+XCHG 6835
+XCH_F 6836
+XCRYPTCBC 6837
+XCRYPTCFB 6838
+XCRYPTCTR 6839
+XCRYPTECB 6840
+XCRYPTOFB 6841
+XEND 6842
+XGETBV 6843
+XLAT 6844
+XOR 6845
+XORPDrm 6846
+XORPDrr 6847
+XORPSrm 6848
+XORPSrr 6849
+XRELEASE_PREFIX 6850
+XRESLDTRK 6851
+XRSTOR 6852
+XRSTORS 6853
+XSAVE 6854
+XSAVEC 6855
+XSAVEOPT 6856
+XSAVES 6857
+XSETBV 6858
+XSHA 6859
+XSTORE 6860
+XSUSLDTRK 6861
+XTEST 6862
+Immediate 6863
+CImmediate 6864
+FPImmediate 6865
+MBB 6866
+FrameIndex 6867
+ConstantPoolIndex 6868
+TargetIndex 6869
+JumpTableIndex 6870
+ExternalSymbol 6871
+GlobalAddress 6872
+BlockAddress 6873
+RegisterMask 6874
+RegisterLiveOut 6875
+Metadata 6876
+MCSymbol 6877
+CFIIndex 6878
+IntrinsicID 6879
+Predicate 6880
+ShuffleMask 6881
+LaneMask 6882
+PhyReg_GR8 6883
+PhyReg_GRH8 6884
+PhyReg_GR8_NOREX2 6885
+PhyReg_GR8_NOREX 6886
+PhyReg_GR8_ABCD_H 6887
+PhyReg_GR8_ABCD_L 6888
+PhyReg_GRH16 6889
+PhyReg_GR16 6890
+PhyReg_GR16_NOREX2 6891
+PhyReg_GR16_NOREX 6892
+PhyReg_VK1 6893
+PhyReg_VK16 6894
+PhyReg_VK2 6895
+PhyReg_VK4 6896
+PhyReg_VK8 6897
+PhyReg_VK16WM 6898
+PhyReg_VK1WM 6899
+PhyReg_VK2WM 6900
+PhyReg_VK4WM 6901
+PhyReg_VK8WM 6902
+PhyReg_SEGMENT_REG 6903
+PhyReg_GR16_ABCD 6904
+PhyReg_FPCCR 6905
+PhyReg_FR16X 6906
+PhyReg_FR16 6907
+PhyReg_VK16PAIR 6908
+PhyReg_VK1PAIR 6909
+PhyReg_VK2PAIR 6910
+PhyReg_VK4PAIR 6911
+PhyReg_VK8PAIR 6912
+PhyReg_VK1PAIR_with_sub_mask_0_in_VK1WM 6913
+PhyReg_LOW32_ADDR_ACCESS_RBP 6914
+PhyReg_LOW32_ADDR_ACCESS 6915
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 6916
+PhyReg_FR32X 6917
+PhyReg_GR32 6918
+PhyReg_GR32_NOSP 6919
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 6920
+PhyReg_DEBUG_REG 6921
+PhyReg_FR32 6922
+PhyReg_GR32_NOREX2 6923
+PhyReg_GR32_NOREX2_NOSP 6924
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 6925
+PhyReg_GR32_NOREX 6926
+PhyReg_VK32 6927
+PhyReg_GR32_NOREX_NOSP 6928
+PhyReg_RFP32 6929
+PhyReg_VK32WM 6930
+PhyReg_GR32_ABCD 6931
+PhyReg_GR32_TC 6932
+PhyReg_GR32_ABCD_and_GR32_TC 6933
+PhyReg_GR32_AD 6934
+PhyReg_GR32_ArgRef 6935
+PhyReg_GR32_BPSP 6936
+PhyReg_GR32_BSI 6937
+PhyReg_GR32_CB 6938
+PhyReg_GR32_DC 6939
+PhyReg_GR32_DIBP 6940
+PhyReg_GR32_SIDI 6941
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 6942
+PhyReg_CCR 6943
+PhyReg_DFCCR 6944
+PhyReg_GR32_ABCD_and_GR32_BSI 6945
+PhyReg_GR32_AD_and_GR32_ArgRef 6946
+PhyReg_GR32_ArgRef_and_GR32_CB 6947
+PhyReg_GR32_BPSP_and_GR32_DIBP 6948
+PhyReg_GR32_BPSP_and_GR32_TC 6949
+PhyReg_GR32_BSI_and_GR32_SIDI 6950
+PhyReg_GR32_DIBP_and_GR32_SIDI 6951
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 6952
+PhyReg_LOW32_ADDR_ACCESS_with_sub_32bit 6953
+PhyReg_RFP64 6954
+PhyReg_GR64 6955
+PhyReg_FR64X 6956
+PhyReg_GR64_with_sub_8bit 6957
+PhyReg_GR64_NOSP 6958
+PhyReg_GR64_NOREX2 6959
+PhyReg_CONTROL_REG 6960
+PhyReg_FR64 6961
+PhyReg_GR64_with_sub_16bit_in_GR16_NOREX2 6962
+PhyReg_GR64_NOREX2_NOSP 6963
+PhyReg_GR64PLTSafe 6964
+PhyReg_GR64_TC 6965
+PhyReg_GR64_NOREX 6966
+PhyReg_GR64_TCW64 6967
+PhyReg_GR64_TC_with_sub_8bit 6968
+PhyReg_GR64_NOREX2_NOSP_and_GR64_TC 6969
+PhyReg_GR64_TCW64_with_sub_8bit 6970
+PhyReg_GR64_TC_and_GR64_TCW64 6971
+PhyReg_GR64_with_sub_16bit_in_GR16_NOREX 6972
+PhyReg_VK64 6973
+PhyReg_VR64 6974
+PhyReg_GR64PLTSafe_and_GR64_TC 6975
+PhyReg_GR64_NOREX2_NOSP_and_GR64_TCW64 6976
+PhyReg_GR64_NOREX_NOSP 6977
+PhyReg_GR64_NOREX_and_GR64_TC 6978
+PhyReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 6979
+PhyReg_VK64WM 6980
+PhyReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 6981
+PhyReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 6982
+PhyReg_GR64PLTSafe_and_GR64_TCW64 6983
+PhyReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 6984
+PhyReg_GR64_NOREX_and_GR64_TCW64 6985
+PhyReg_GR64_ABCD 6986
+PhyReg_GR64_with_sub_32bit_in_GR32_TC 6987
+PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 6988
+PhyReg_GR64_AD 6989
+PhyReg_GR64_ArgRef 6990
+PhyReg_GR64_and_LOW32_ADDR_ACCESS_RBP 6991
+PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef 6992
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP 6993
+PhyReg_GR64_with_sub_32bit_in_GR32_BSI 6994
+PhyReg_GR64_with_sub_32bit_in_GR32_CB 6995
+PhyReg_GR64_with_sub_32bit_in_GR32_DIBP 6996
+PhyReg_GR64_with_sub_32bit_in_GR32_SIDI 6997
+PhyReg_GR64_A 6998
+PhyReg_GR64_ArgRef_and_GR64_TC 6999
+PhyReg_GR64_and_LOW32_ADDR_ACCESS 7000
+PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7001
+PhyReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7002
+PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7003
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7004
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7005
+PhyReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7006
+PhyReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7007
+PhyReg_RST 7008
+PhyReg_RFP80 7009
+PhyReg_RFP80_7 7010
+PhyReg_VR128X 7011
+PhyReg_VR128 7012
+PhyReg_VR256X 7013
+PhyReg_VR256 7014
+PhyReg_VR512 7015
+PhyReg_VR512_0_15 7016
+PhyReg_TILE 7017
+VirtReg_GR8 7018
+VirtReg_GRH8 7019
+VirtReg_GR8_NOREX2 7020
+VirtReg_GR8_NOREX 7021
+VirtReg_GR8_ABCD_H 7022
+VirtReg_GR8_ABCD_L 7023
+VirtReg_GRH16 7024
+VirtReg_GR16 7025
+VirtReg_GR16_NOREX2 7026
+VirtReg_GR16_NOREX 7027
+VirtReg_VK1 7028
+VirtReg_VK16 7029
+VirtReg_VK2 7030
+VirtReg_VK4 7031
+VirtReg_VK8 7032
+VirtReg_VK16WM 7033
+VirtReg_VK1WM 7034
+VirtReg_VK2WM 7035
+VirtReg_VK4WM 7036
+VirtReg_VK8WM 7037
+VirtReg_SEGMENT_REG 7038
+VirtReg_GR16_ABCD 7039
+VirtReg_FPCCR 7040
+VirtReg_FR16X 7041
+VirtReg_FR16 7042
+VirtReg_VK16PAIR 7043
+VirtReg_VK1PAIR 7044
+VirtReg_VK2PAIR 7045
+VirtReg_VK4PAIR 7046
+VirtReg_VK8PAIR 7047
+VirtReg_VK1PAIR_with_sub_mask_0_in_VK1WM 7048
+VirtReg_LOW32_ADDR_ACCESS_RBP 7049
+VirtReg_LOW32_ADDR_ACCESS 7050
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 7051
+VirtReg_FR32X 7052
+VirtReg_GR32 7053
+VirtReg_GR32_NOSP 7054
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 7055
+VirtReg_DEBUG_REG 7056
+VirtReg_FR32 7057
+VirtReg_GR32_NOREX2 7058
+VirtReg_GR32_NOREX2_NOSP 7059
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 7060
+VirtReg_GR32_NOREX 7061
+VirtReg_VK32 7062
+VirtReg_GR32_NOREX_NOSP 7063
+VirtReg_RFP32 7064
+VirtReg_VK32WM 7065
+VirtReg_GR32_ABCD 7066
+VirtReg_GR32_TC 7067
+VirtReg_GR32_ABCD_and_GR32_TC 7068
+VirtReg_GR32_AD 7069
+VirtReg_GR32_ArgRef 7070
+VirtReg_GR32_BPSP 7071
+VirtReg_GR32_BSI 7072
+VirtReg_GR32_CB 7073
+VirtReg_GR32_DC 7074
+VirtReg_GR32_DIBP 7075
+VirtReg_GR32_SIDI 7076
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 7077
+VirtReg_CCR 7078
+VirtReg_DFCCR 7079
+VirtReg_GR32_ABCD_and_GR32_BSI 7080
+VirtReg_GR32_AD_and_GR32_ArgRef 7081
+VirtReg_GR32_ArgRef_and_GR32_CB 7082
+VirtReg_GR32_BPSP_and_GR32_DIBP 7083
+VirtReg_GR32_BPSP_and_GR32_TC 7084
+VirtReg_GR32_BSI_and_GR32_SIDI 7085
+VirtReg_GR32_DIBP_and_GR32_SIDI 7086
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 7087
+VirtReg_LOW32_ADDR_ACCESS_with_sub_32bit 7088
+VirtReg_RFP64 7089
+VirtReg_GR64 7090
+VirtReg_FR64X 7091
+VirtReg_GR64_with_sub_8bit 7092
+VirtReg_GR64_NOSP 7093
+VirtReg_GR64_NOREX2 7094
+VirtReg_CONTROL_REG 7095
+VirtReg_FR64 7096
+VirtReg_GR64_with_sub_16bit_in_GR16_NOREX2 7097
+VirtReg_GR64_NOREX2_NOSP 7098
+VirtReg_GR64PLTSafe 7099
+VirtReg_GR64_TC 7100
+VirtReg_GR64_NOREX 7101
+VirtReg_GR64_TCW64 7102
+VirtReg_GR64_TC_with_sub_8bit 7103
+VirtReg_GR64_NOREX2_NOSP_and_GR64_TC 7104
+VirtReg_GR64_TCW64_with_sub_8bit 7105
+VirtReg_GR64_TC_and_GR64_TCW64 7106
+VirtReg_GR64_with_sub_16bit_in_GR16_NOREX 7107
+VirtReg_VK64 7108
+VirtReg_VR64 7109
+VirtReg_GR64PLTSafe_and_GR64_TC 7110
+VirtReg_GR64_NOREX2_NOSP_and_GR64_TCW64 7111
+VirtReg_GR64_NOREX_NOSP 7112
+VirtReg_GR64_NOREX_and_GR64_TC 7113
+VirtReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 7114
+VirtReg_VK64WM 7115
+VirtReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 7116
+VirtReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7117
+VirtReg_GR64PLTSafe_and_GR64_TCW64 7118
+VirtReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7119
+VirtReg_GR64_NOREX_and_GR64_TCW64 7120
+VirtReg_GR64_ABCD 7121
+VirtReg_GR64_with_sub_32bit_in_GR32_TC 7122
+VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7123
+VirtReg_GR64_AD 7124
+VirtReg_GR64_ArgRef 7125
+VirtReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7126
+VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef 7127
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP 7128
+VirtReg_GR64_with_sub_32bit_in_GR32_BSI 7129
+VirtReg_GR64_with_sub_32bit_in_GR32_CB 7130
+VirtReg_GR64_with_sub_32bit_in_GR32_DIBP 7131
+VirtReg_GR64_with_sub_32bit_in_GR32_SIDI 7132
+VirtReg_GR64_A 7133
+VirtReg_GR64_ArgRef_and_GR64_TC 7134
+VirtReg_GR64_and_LOW32_ADDR_ACCESS 7135
+VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7136
+VirtReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7137
+VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7138
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7139
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7140
+VirtReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7141
+VirtReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7142
+VirtReg_RST 7143
+VirtReg_RFP80 7144
+VirtReg_RFP80_7 7145
+VirtReg_VR128X 7146
+VirtReg_VR128 7147
+VirtReg_VR256X 7148
+VirtReg_VR256 7149
+VirtReg_VR512 7150
+VirtReg_VR512_0_15 7151
+VirtReg_TILE 7152
>From 1db36337925804a6e3dc686416c968568fda1a32 Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Wed, 13 Aug 2025 10:17:49 +0000
Subject: [PATCH 4/8] Addressed reviewed changes making changes in LIT tests
mainly.
---
llvm/docs/MIRLangRef.rst | 14 ++++-
llvm/include/llvm/CodeGen/MachineInstr.h | 7 ++-
llvm/lib/CodeGen/MachineVerifier.cpp | 29 +++++-----
.../parse-lanemask-operand-invalid-0.mir | 2 +-
.../parse-lanemask-operand-invalid-1.mir | 2 +-
.../parse-lanemask-operand-invalid-2.mir | 2 +-
.../parse-lanemask-operand-invalid-3.mir | 13 +++++
.../AMDGPU/verifier-copyLanemask0.mir | 58 +++++++++++++++++++
.../AMDGPU/verifier-copyLanemask1.mir | 19 ++++++
.../verifier-copyLanemask0.mir | 24 --------
.../verifier-copyLanemask1.mir | 28 ---------
llvm/unittests/CodeGen/MachineOperandTest.cpp | 4 +-
12 files changed, 128 insertions(+), 74 deletions(-)
create mode 100644 llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-3.mir
create mode 100644 llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask0.mir
create mode 100644 llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask1.mir
delete mode 100644 llvm/test/MachineVerifier/verifier-copyLanemask0.mir
delete mode 100644 llvm/test/MachineVerifier/verifier-copyLanemask1.mir
diff --git a/llvm/docs/MIRLangRef.rst b/llvm/docs/MIRLangRef.rst
index 9596cb1e023e0..c8175b1532750 100644
--- a/llvm/docs/MIRLangRef.rst
+++ b/llvm/docs/MIRLangRef.rst
@@ -807,6 +807,19 @@ For an int eq predicate ``ICMP_EQ``, the syntax is:
%2:gpr(s32) = G_ICMP intpred(eq), %0, %1
+Lanemask Operands
+^^^^^^^^^^^^^^^^^^
+
+A Lanemask operand is 64-bit unsigned value that holds the lane information
+corrseponding to the source register operand in the instruction.
+
+For example, the COPY_LANEMASK instruction using this operand would look
+like:
+
+.. code-block:: text
+
+ $vgpr1 = COPY_LANEMASK $vgpr0, lanemask(00000000000000C0)
+
.. TODO: Describe the parsers default behaviour when optional YAML attributes
are missing.
.. TODO: Describe the syntax for virtual register YAML definitions.
@@ -819,7 +832,6 @@ For an int eq predicate ``ICMP_EQ``, the syntax is:
.. TODO: Describe the syntax of the metadata machine operands, and the
instructions debug location attribute.
.. TODO: Describe the syntax of the register live out machine operands.
-.. TODO: Describe the syntax of the lanemask machine operands.
.. TODO: Describe the syntax of the machine memory operands.
Comments
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index c2bd6abe3c719..4644ee57b876e 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -1428,9 +1428,10 @@ class MachineInstr
return getOpcode() == TargetOpcode::BUNDLE;
}
- bool isCopy() const {
- return (getOpcode() == TargetOpcode::COPY ||
- getOpcode() == TargetOpcode::COPY_LANEMASK);
+ bool isCopy() const { return getOpcode() == TargetOpcode::COPY; }
+
+ bool isCopyLanemask() const {
+ return getOpcode() == TargetOpcode::COPY_LANEMASK;
}
bool isFullCopy() const {
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index b9a45b9e567c6..7a6d39625f46d 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2435,24 +2435,27 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
const Register SrcReg = SrcOp.getReg();
const Register DstReg = DstOp.getReg();
const LaneBitmask LaneMask = LaneMaskOp.getLaneMask();
+ LaneBitmask SrcMaxLanemask = LaneBitmask::getAll();
- if (!SrcReg.isPhysical() || !DstReg.isPhysical()) {
- if (!SrcReg.isPhysical()) {
- report("Copy with lanemask Instruction uses virtual register", &SrcOp,
- 1);
- }
- if (!DstReg.isPhysical()) {
- report("Copy with lanemask Instruction uses virtual register", &DstOp,
- 0);
- }
- break;
+ if (DstOp.getSubReg())
+ report("COPY_LANEMASK must use no sub-register index.", &DstOp, 0);
+
+ if (SrcOp.getSubReg())
+ report("COPY_LANEMASK must use no sub-register index.", &SrcOp, 1);
+
+ if (SrcReg.isVirtual()) {
+ SrcMaxLanemask = MRI->getMaxLaneMaskForVReg(SrcReg);
}
if (LaneMask.none())
- report("Lanemask takes up the zero value", MI);
+ report("COPY_LANEMASK copies no lanes.", MI);
- if (LaneMask.all())
- report("Copy Instruction can be used instead of copy with lanemask", MI);
+ // In case of Src as virtual register, all lanes active implies the max
+ // lanemask bits active for that register class, else all bits would be set.
+ if (LaneMask.all() || (SrcMaxLanemask == LaneMask))
+ report(
+ "COPY should be instead of COPY_LANEMASK, as all lanes are copied.",
+ MI);
break;
}
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-0.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-0.mir
index 5bb397e8bcd08..ded2c5fca5789 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-0.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-0.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
---
name: test_missing_rparen
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-1.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-1.mir
index bb4ca36e29511..d3d3d3526261f 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-1.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-1.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
---
name: test_missing_lparen
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-2.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-2.mir
index fe520056f475c..310051b6bee52 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-2.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-2.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
---
name: test_wrong_lanemask_type
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-3.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-3.mir
new file mode 100644
index 0000000000000..0b4e4d1ef4ffa
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-3.mir
@@ -0,0 +1,13 @@
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name: test_empty_lanemask_type
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK: [[@LINE+1]]:45: expected a valid lane mask value.
+ $vgpr1 = COPY_LANEMASK $vgpr0, lanemask()
+ S_ENDPGM 0
+...
diff --git a/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask0.mir b/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask0.mir
new file mode 100644
index 0000000000000..e16deadec39fe
--- /dev/null
+++ b/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask0.mir
@@ -0,0 +1,58 @@
+# RUN: not --crash llc -o - -mtriple=amdgcn-amd-amdhsa -run-pass=none %s 2>&1 | FileCheck %s
+
+# CHECK: *** Bad machine code: COPY_LANEMASK copies no lanes. ***
+# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
+# CHECK-NEXT: - basic block: %bb.0
+# CHECK-NEXT: - instruction: $vgpr2 = COPY_LANEMASK $vgpr0, lanemask(0x0000000000000000)
+
+# CHECK: *** Bad machine code: COPY should be instead of COPY_LANEMASK, as all lanes are copied. ***
+# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
+# CHECK-NEXT: - basic block: %bb.0
+# CHECK-NEXT: - instruction: $vgpr3 = COPY_LANEMASK $vgpr1, lanemask(0xFFFFFFFFFFFFFFFF)
+
+# CHECK: *** Bad machine code: COPY should be instead of COPY_LANEMASK, as all lanes are copied. ***
+# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
+# CHECK-NEXT: - basic block: %bb.0
+# CHECK-NEXT: - instruction: %1:vgpr_32 = COPY_LANEMASK %0:vgpr_32, lanemask(0x0000000000000003)
+
+# CHECK: *** Bad machine code: COPY should be instead of COPY_LANEMASK, as all lanes are copied. ***
+# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
+# CHECK-NEXT: - basic block: %bb.0
+# CHECK-NEXT: - instruction: %2:vgpr_32 = COPY_LANEMASK %1:vgpr_32, lanemask(0xFFFFFFFFFFFFFFFF)
+
+# CHECK: *** Bad machine code: COPY should be instead of COPY_LANEMASK, as all lanes are copied. ***
+# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
+# CHECK-NEXT: - basic block: %bb.0
+# CHECK-NEXT: - instruction: %3:vreg_64 = COPY_LANEMASK $vgpr4_vgpr5, lanemask(0xFFFFFFFFFFFFFFFF)
+
+# CHECK: *** Bad machine code: COPY should be instead of COPY_LANEMASK, as all lanes are copied. ***
+# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
+# CHECK-NEXT: - basic block: %bb.0
+# CHECK-NEXT: - instruction: $vgpr6_vgpr7 = COPY_LANEMASK %3:vreg_64, lanemask(0x000000000000000F)
+
+# CHECK: *** Bad machine code: COPY_LANEMASK must use no sub-register index. ***
+# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
+# CHECK-NEXT: - basic block: %bb.0
+# CHECK-NEXT: - instruction: %4:vgpr_32 = COPY_LANEMASK %3.sub0:vreg_64, lanemask(0x0000000000000003)
+
+# NOTE: For physical register, as we don't have way to obtain their maximal lanemask directly, so
+# COPY_LANEMASK is illegal only if all lane bits are active irrespective.
+
+---
+name: test_copy_lanemask_instruction_0
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ %0:vgpr_32 = IMPLICIT_DEF
+ $vgpr2 = COPY_LANEMASK $vgpr0, lanemask(0)
+ $vgpr3 = COPY_LANEMASK $vgpr1, lanemask(0xFFFFFFFFFFFFFFFF)
+ $vgpr4_vgpr5 = COPY_LANEMASK $vgpr2_vgpr3, lanemask(0x000000000000000F)
+ %1:vgpr_32 = COPY_LANEMASK %0, lanemask(0x0000000000000003)
+ %2:vgpr_32 = COPY_LANEMASK %1, lanemask(0xFFFFFFFFFFFFFFFF)
+ %3:vreg_64 = COPY_LANEMASK $vgpr4_vgpr5, lanemask(0xFFFFFFFFFFFFFFFF)
+ $vgpr6_vgpr7 = COPY_LANEMASK %3, lanemask(0x000000000000000F)
+ %4:vgpr_32 = COPY_LANEMASK %3.sub0, lanemask(0x0000000000000003)
+ S_ENDPGM 0
+...
diff --git a/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask1.mir b/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask1.mir
new file mode 100644
index 0000000000000..d4338da717ba2
--- /dev/null
+++ b/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask1.mir
@@ -0,0 +1,19 @@
+# RUN: not --crash llc -o - -mtriple=amdgcn-amd-amdhsa -run-pass=none %s 2>&1 | FileCheck %s
+
+# CHECK: *** Bad machine code: Too few operands ***
+# CHECK-NEXT: - function: test_copy_lanemask_instruction_1
+# CHECK-NEXT: - basic block: %bb.0
+# CHECK-NEXT: - instruction: $vgpr2 = COPY_LANEMASK %0:vgpr_32
+
+---
+name: test_copy_lanemask_instruction_1
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ %0:vgpr_32 = COPY $vgpr0
+ $vgpr2 = COPY_LANEMASK %0
+ S_ENDPGM 0
+...
+
diff --git a/llvm/test/MachineVerifier/verifier-copyLanemask0.mir b/llvm/test/MachineVerifier/verifier-copyLanemask0.mir
deleted file mode 100644
index 88d368c98ba32..0000000000000
--- a/llvm/test/MachineVerifier/verifier-copyLanemask0.mir
+++ /dev/null
@@ -1,24 +0,0 @@
-# RUN: not --crash llc -o - -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
-# REQUIRES: amdgpu-registered-target
-
-# CHECK: *** Bad machine code: Lanemask takes up the zero value ***
-# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
-# CHECK-NEXT: - basic block: %bb.0
-# CHECK-NEXT: - instruction: $vgpr2 = COPY_LANEMASK $vgpr0, lanemask(0x0000000000000000)
-
-# CHECK: *** Bad machine code: Copy Instruction can be used instead of copy with lanemask ***
-# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
-# CHECK-NEXT: - basic block: %bb.0
-# CHECK-NEXT: - instruction: $vgpr3 = COPY_LANEMASK $vgpr1, lanemask(0xFFFFFFFFFFFFFFFF)
-
----
-name: test_copy_lanemask_instruction_0
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
-
- $vgpr2 = COPY_LANEMASK $vgpr0, lanemask(0)
- $vgpr3 = COPY_LANEMASK $vgpr1, lanemask(0xFFFFFFFFFFFFFFFF)
- S_ENDPGM 0
-...
diff --git a/llvm/test/MachineVerifier/verifier-copyLanemask1.mir b/llvm/test/MachineVerifier/verifier-copyLanemask1.mir
deleted file mode 100644
index b4386dcae7760..0000000000000
--- a/llvm/test/MachineVerifier/verifier-copyLanemask1.mir
+++ /dev/null
@@ -1,28 +0,0 @@
-# RUN: not --crash llc -o - -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
-# REQUIRES: amdgpu-registered-target
-
-# CHECK: *** Bad machine code: Copy with lanemask Instruction uses virtual register ***
-# CHECK-NEXT: - function: test_copy_lanemask_instruction_1
-# CHECK-NEXT: - basic block: %bb.0
-# CHECK-NEXT: - instruction: $vgpr2 = COPY_LANEMASK %0:vgpr_32, lanemask(0x0000000000000018)
-# CHECK-NEXT: - operand 1: %0:vgpr_32
-
-# CHECK: *** Bad machine code: Copy with lanemask Instruction uses virtual register ***
-# CHECK-NEXT: - function: test_copy_lanemask_instruction_1
-# CHECK-NEXT: - basic block: %bb.0
-# CHECK-NEXT: - instruction: %1:vgpr_32 = COPY_LANEMASK $vgpr1, lanemask(0x00000000000000FF)
-# CHECK-NEXT: - operand 0: %1:vgpr_32
-
----
-name: test_copy_lanemask_instruction_1
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
-
- %0:vgpr_32 = COPY $vgpr0
- $vgpr2 = COPY_LANEMASK %0, lanemask(24)
- %1:vgpr_32 = COPY_LANEMASK $vgpr1, lanemask(0x000000000000FF)
- S_ENDPGM 0
-...
-
diff --git a/llvm/unittests/CodeGen/MachineOperandTest.cpp b/llvm/unittests/CodeGen/MachineOperandTest.cpp
index 60afdad846a13..c0b2b1895975a 100644
--- a/llvm/unittests/CodeGen/MachineOperandTest.cpp
+++ b/llvm/unittests/CodeGen/MachineOperandTest.cpp
@@ -296,13 +296,13 @@ TEST(MachineOperandTest, PrintLaneMask) {
// Checking some preconditions on the newly created
// MachineOperand.
ASSERT_TRUE(MO.isLaneMask());
- ASSERT_TRUE(MO.getLaneMask() == LaneMask);
+ ASSERT_EQ(MO.getLaneMask(), LaneMask);
std::string str;
// Print a MachineOperand that is lanemask as in HEX representation.
raw_string_ostream OS(str);
MO.print(OS, /*TRI=*/nullptr);
- ASSERT_TRUE(str == "lanemask(0x000000000000000C)");
+ ASSERT_EQ(str, "lanemask(0x000000000000000C)");
}
TEST(MachineOperandTest, PrintRegisterLiveOut) {
>From 4474aa354079141c87c628ef9f3f293508df0dda Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Mon, 18 Aug 2025 10:25:55 +0000
Subject: [PATCH 5/8] Added support to find SrcLaneMask for PhysReg & updated
LIT tests.
---
llvm/docs/MIRLangRef.rst | 2 +-
llvm/include/llvm/MC/LaneBitmask.h | 1 +
llvm/lib/CodeGen/MachineVerifier.cpp | 26 ++++----
.../MIR/AMDGPU/parse-lanemask-operand.mir | 4 +-
.../AMDGPU/verifier-copyLanemask0.mir | 59 ++++++-------------
5 files changed, 37 insertions(+), 55 deletions(-)
diff --git a/llvm/docs/MIRLangRef.rst b/llvm/docs/MIRLangRef.rst
index c8175b1532750..4ae14ce39d25d 100644
--- a/llvm/docs/MIRLangRef.rst
+++ b/llvm/docs/MIRLangRef.rst
@@ -818,7 +818,7 @@ like:
.. code-block:: text
- $vgpr1 = COPY_LANEMASK $vgpr0, lanemask(00000000000000C0)
+ $vgpr1 = COPY_LANEMASK $vgpr0, lanemask(0x00000000000000C0)
.. TODO: Describe the parsers default behaviour when optional YAML attributes
are missing.
diff --git a/llvm/include/llvm/MC/LaneBitmask.h b/llvm/include/llvm/MC/LaneBitmask.h
index c06ca7dd5b8fc..b487947dcac96 100644
--- a/llvm/include/llvm/MC/LaneBitmask.h
+++ b/llvm/include/llvm/MC/LaneBitmask.h
@@ -49,6 +49,7 @@ namespace llvm {
constexpr bool operator== (LaneBitmask M) const { return Mask == M.Mask; }
constexpr bool operator!= (LaneBitmask M) const { return Mask != M.Mask; }
constexpr bool operator< (LaneBitmask M) const { return Mask < M.Mask; }
+ constexpr bool operator<=(LaneBitmask M) const { return Mask <= M.Mask; }
constexpr bool none() const { return Mask == 0; }
constexpr bool any() const { return Mask != 0; }
constexpr bool all() const { return ~Mask == 0; }
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 7a6d39625f46d..09ef0e5c3ddde 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2438,24 +2438,26 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
LaneBitmask SrcMaxLanemask = LaneBitmask::getAll();
if (DstOp.getSubReg())
- report("COPY_LANEMASK must use no sub-register index.", &DstOp, 0);
+ report("COPY_LANEMASK must not use a subregister index", &DstOp, 0);
if (SrcOp.getSubReg())
- report("COPY_LANEMASK must use no sub-register index.", &SrcOp, 1);
+ report("COPY_LANEMASK must not use a subregister index", &SrcOp, 1);
- if (SrcReg.isVirtual()) {
+ if (LaneMask.none())
+ report("COPY_LANEMASK must read at least one lane", MI);
+
+ if (SrcReg.isPhysical()) {
+ const TargetRegisterClass *SrcRC = TRI->getMinimalPhysRegClass(SrcReg);
+ if (SrcRC)
+ SrcMaxLanemask = SrcRC->getLaneMask();
+ } else {
SrcMaxLanemask = MRI->getMaxLaneMaskForVReg(SrcReg);
}
- if (LaneMask.none())
- report("COPY_LANEMASK copies no lanes.", MI);
-
- // In case of Src as virtual register, all lanes active implies the max
- // lanemask bits active for that register class, else all bits would be set.
- if (LaneMask.all() || (SrcMaxLanemask == LaneMask))
- report(
- "COPY should be instead of COPY_LANEMASK, as all lanes are copied.",
- MI);
+ // If LaneMask is equal to OR greater than the SrcMaxLanemask, it
+ // impliess COPY_LANEMASK is trying to copy all lanes.
+ if (SrcMaxLanemask <= LaneMask)
+ report("COPY_LANEMASK cannot read all lanes", MI);
break;
}
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir
index 92c58826a5031..066bc8e79a56e 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir
@@ -3,7 +3,7 @@
# This test checks for the correctness of the MIR parser for lanemask
# CHECK-LABEL: name: test_lanemask_operand
-# CHECK: COPY_LANEMASK $vgpr0, lanemask(0x0000000000000020)
+# CHECK: COPY_LANEMASK $vgpr0, lanemask(0x0000000000000002)
---
name: test_lanemask_operand
tracksRegLiveness: true
@@ -11,7 +11,7 @@ body: |
bb.0:
liveins: $vgpr0
- $vgpr1 = COPY_LANEMASK $vgpr0, lanemask(32)
+ $vgpr1 = COPY_LANEMASK $vgpr0, lanemask(2)
S_ENDPGM 0
...
diff --git a/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask0.mir b/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask0.mir
index e16deadec39fe..f976ffa24a23a 100644
--- a/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask0.mir
+++ b/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask0.mir
@@ -1,43 +1,5 @@
# RUN: not --crash llc -o - -mtriple=amdgcn-amd-amdhsa -run-pass=none %s 2>&1 | FileCheck %s
-# CHECK: *** Bad machine code: COPY_LANEMASK copies no lanes. ***
-# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
-# CHECK-NEXT: - basic block: %bb.0
-# CHECK-NEXT: - instruction: $vgpr2 = COPY_LANEMASK $vgpr0, lanemask(0x0000000000000000)
-
-# CHECK: *** Bad machine code: COPY should be instead of COPY_LANEMASK, as all lanes are copied. ***
-# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
-# CHECK-NEXT: - basic block: %bb.0
-# CHECK-NEXT: - instruction: $vgpr3 = COPY_LANEMASK $vgpr1, lanemask(0xFFFFFFFFFFFFFFFF)
-
-# CHECK: *** Bad machine code: COPY should be instead of COPY_LANEMASK, as all lanes are copied. ***
-# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
-# CHECK-NEXT: - basic block: %bb.0
-# CHECK-NEXT: - instruction: %1:vgpr_32 = COPY_LANEMASK %0:vgpr_32, lanemask(0x0000000000000003)
-
-# CHECK: *** Bad machine code: COPY should be instead of COPY_LANEMASK, as all lanes are copied. ***
-# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
-# CHECK-NEXT: - basic block: %bb.0
-# CHECK-NEXT: - instruction: %2:vgpr_32 = COPY_LANEMASK %1:vgpr_32, lanemask(0xFFFFFFFFFFFFFFFF)
-
-# CHECK: *** Bad machine code: COPY should be instead of COPY_LANEMASK, as all lanes are copied. ***
-# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
-# CHECK-NEXT: - basic block: %bb.0
-# CHECK-NEXT: - instruction: %3:vreg_64 = COPY_LANEMASK $vgpr4_vgpr5, lanemask(0xFFFFFFFFFFFFFFFF)
-
-# CHECK: *** Bad machine code: COPY should be instead of COPY_LANEMASK, as all lanes are copied. ***
-# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
-# CHECK-NEXT: - basic block: %bb.0
-# CHECK-NEXT: - instruction: $vgpr6_vgpr7 = COPY_LANEMASK %3:vreg_64, lanemask(0x000000000000000F)
-
-# CHECK: *** Bad machine code: COPY_LANEMASK must use no sub-register index. ***
-# CHECK-NEXT: - function: test_copy_lanemask_instruction_0
-# CHECK-NEXT: - basic block: %bb.0
-# CHECK-NEXT: - instruction: %4:vgpr_32 = COPY_LANEMASK %3.sub0:vreg_64, lanemask(0x0000000000000003)
-
-# NOTE: For physical register, as we don't have way to obtain their maximal lanemask directly, so
-# COPY_LANEMASK is illegal only if all lane bits are active irrespective.
-
---
name: test_copy_lanemask_instruction_0
tracksRegLiveness: true
@@ -46,13 +8,30 @@ body: |
liveins: $vgpr0, $vgpr1
%0:vgpr_32 = IMPLICIT_DEF
+
+ ; CHECK: *** Bad machine code: COPY_LANEMASK must read at least one lane ***
$vgpr2 = COPY_LANEMASK $vgpr0, lanemask(0)
+
+ ; CHECK: *** Bad machine code: COPY_LANEMASK cannot read all lanes ***
$vgpr3 = COPY_LANEMASK $vgpr1, lanemask(0xFFFFFFFFFFFFFFFF)
+
+ ; CHECK: *** Bad machine code: COPY_LANEMASK cannot read all lanes ***
$vgpr4_vgpr5 = COPY_LANEMASK $vgpr2_vgpr3, lanemask(0x000000000000000F)
+
+ ; CHECK: *** Bad machine code: COPY_LANEMASK cannot read all lanes ***
%1:vgpr_32 = COPY_LANEMASK %0, lanemask(0x0000000000000003)
- %2:vgpr_32 = COPY_LANEMASK %1, lanemask(0xFFFFFFFFFFFFFFFF)
- %3:vreg_64 = COPY_LANEMASK $vgpr4_vgpr5, lanemask(0xFFFFFFFFFFFFFFFF)
+
+ ; CHECK: *** Bad machine code: COPY_LANEMASK cannot read all lanes ***
+ %2:vgpr_32 = COPY_LANEMASK %1, lanemask(0x0000000FFFFFFFFF)
+
+ ; CHECK: *** Bad machine code: COPY_LANEMASK cannot read all lanes ***
+ %3:vreg_64 = COPY_LANEMASK $vgpr4_vgpr5, lanemask(0x00000000000000FF)
+
+ ; CHECK: *** Bad machine code: COPY_LANEMASK cannot read all lanes ***
$vgpr6_vgpr7 = COPY_LANEMASK %3, lanemask(0x000000000000000F)
+
+ ; CHECK: *** Bad machine code: COPY_LANEMASK must not use a subregister index ***
%4:vgpr_32 = COPY_LANEMASK %3.sub0, lanemask(0x0000000000000003)
+
S_ENDPGM 0
...
>From 88da3f8b13fc295f0e12dea5470602a573b37feb Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Fri, 22 Aug 2025 06:57:15 +0000
Subject: [PATCH 6/8] Updated the MIRLangRef document & COPY_LANEMASK defintion
in comments.
---
llvm/docs/MIRLangRef.rst | 10 ++++++----
llvm/include/llvm/CodeGen/MachineInstr.h | 4 +++-
llvm/include/llvm/Support/TargetOpcodes.def | 4 ++--
3 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/llvm/docs/MIRLangRef.rst b/llvm/docs/MIRLangRef.rst
index 4ae14ce39d25d..edd2bbf3f6a6b 100644
--- a/llvm/docs/MIRLangRef.rst
+++ b/llvm/docs/MIRLangRef.rst
@@ -810,11 +810,13 @@ For an int eq predicate ``ICMP_EQ``, the syntax is:
Lanemask Operands
^^^^^^^^^^^^^^^^^^
-A Lanemask operand is 64-bit unsigned value that holds the lane information
-corrseponding to the source register operand in the instruction.
+A Lanemask operand is 64-bit unsigned value that can the store lane information
+for a register operand in the instruction. It can be used as many times as needed
+in an instruction, with one (atleast) or more register operands associated with it.
-For example, the COPY_LANEMASK instruction using this operand would look
-like:
+
+For example, the COPY_LANEMASK instruction uses this operand to copy only active
+lanes(of the source register) in the mask. The syntax for it would look:
.. code-block:: text
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index 4644ee57b876e..a219f8b50b0a1 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -1428,7 +1428,9 @@ class MachineInstr
return getOpcode() == TargetOpcode::BUNDLE;
}
- bool isCopy() const { return getOpcode() == TargetOpcode::COPY; }
+ bool isCopy() const {
+ return getOpcode() == TargetOpcode::COPY;
+ }
bool isCopyLanemask() const {
return getOpcode() == TargetOpcode::COPY_LANEMASK;
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 4647b3062ef5b..3bbe46ca51d80 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -115,8 +115,8 @@ HANDLE_TARGET_OPCODE(REG_SEQUENCE)
HANDLE_TARGET_OPCODE(COPY)
/// COPY_LANEMASK - Target-independent register copy for active mask in
-/// register as represented by the lanemask. This instruction can only be
-/// used to copy between physical registers.
+/// register as represented by the lanemask. This instruction cannot be
+/// only used to copy from the subregisters of virtual registers.
HANDLE_TARGET_OPCODE(COPY_LANEMASK)
/// BUNDLE - This instruction represents an instruction bundle. Instructions
>From f838e741f564ed214193919b2b5b816a6e120311 Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Wed, 17 Sep 2025 06:54:23 +0000
Subject: [PATCH 7/8] Updated the documentation as per the review.
---
llvm/docs/MIRLangRef.rst | 8 +++++---
llvm/include/llvm/Support/TargetOpcodes.def | 4 ++--
llvm/lib/CodeGen/MachineVerifier.cpp | 1 -
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/llvm/docs/MIRLangRef.rst b/llvm/docs/MIRLangRef.rst
index edd2bbf3f6a6b..93d456ff5aa16 100644
--- a/llvm/docs/MIRLangRef.rst
+++ b/llvm/docs/MIRLangRef.rst
@@ -810,13 +810,15 @@ For an int eq predicate ``ICMP_EQ``, the syntax is:
Lanemask Operands
^^^^^^^^^^^^^^^^^^
-A Lanemask operand is 64-bit unsigned value that can the store lane information
+A Lanemask operand is a 64-bit unsigned value that can store lane information
for a register operand in the instruction. It can be used as many times as needed
-in an instruction, with one (atleast) or more register operands associated with it.
+in an instruction, with one or more register operands associated with it. While
+the active bits represent the live subregister (in virtual registers) or regUnits
+(in physical registers), the remaining bits can represent the UNDEF part of it.
For example, the COPY_LANEMASK instruction uses this operand to copy only active
-lanes(of the source register) in the mask. The syntax for it would look:
+lanes (of the source register) in the mask. The syntax for it would look like:
.. code-block:: text
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 3bbe46ca51d80..5b12c92933bfa 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -115,8 +115,8 @@ HANDLE_TARGET_OPCODE(REG_SEQUENCE)
HANDLE_TARGET_OPCODE(COPY)
/// COPY_LANEMASK - Target-independent register copy for active mask in
-/// register as represented by the lanemask. This instruction cannot be
-/// only used to copy from the subregisters of virtual registers.
+/// register as represented by the lanemask. This instruction does not
+/// support copy between subregisters of virtual registers.
HANDLE_TARGET_OPCODE(COPY_LANEMASK)
/// BUNDLE - This instruction represents an instruction bundle. Instructions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 09ef0e5c3ddde..c12666f86f88f 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2433,7 +2433,6 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
const MachineOperand &SrcOp = MI->getOperand(1);
const MachineOperand &LaneMaskOp = MI->getOperand(2);
const Register SrcReg = SrcOp.getReg();
- const Register DstReg = DstOp.getReg();
const LaneBitmask LaneMask = LaneMaskOp.getLaneMask();
LaneBitmask SrcMaxLanemask = LaneBitmask::getAll();
>From 4227ad4b5f256e95086e3665efbce0e74acfb453 Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Wed, 5 Nov 2025 08:27:52 +0000
Subject: [PATCH 8/8] Addressed the reviews related to dewscription &
documentation of the new operand.
---
llvm/docs/MIRLangRef.rst | 16 +++++++-------
llvm/include/llvm/CodeGen/MachineInstr.h | 2 +-
llvm/include/llvm/Support/TargetOpcodes.def | 5 +++--
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 8 +++----
llvm/lib/CodeGen/MachineVerifier.cpp | 22 +++++++++++++------
.../parse-lanemask-operand-invalid-0.mir | 2 +-
.../parse-lanemask-operand-invalid-1.mir | 2 +-
.../parse-lanemask-operand-invalid-2.mir | 2 +-
.../parse-lanemask-operand-invalid-3.mir | 2 +-
.../GlobalISel/legalizer-info-validation.mir | 2 +-
.../AMDGPU/verifier-copyLanemask0.mir | 12 +++++-----
.../AMDGPU/verifier-copyLanemask1.mir | 2 +-
12 files changed, 43 insertions(+), 34 deletions(-)
diff --git a/llvm/docs/MIRLangRef.rst b/llvm/docs/MIRLangRef.rst
index 93d456ff5aa16..e7c3372b6a025 100644
--- a/llvm/docs/MIRLangRef.rst
+++ b/llvm/docs/MIRLangRef.rst
@@ -807,23 +807,23 @@ For an int eq predicate ``ICMP_EQ``, the syntax is:
%2:gpr(s32) = G_ICMP intpred(eq), %0, %1
-Lanemask Operands
+LaneMask Operands
^^^^^^^^^^^^^^^^^^
-A Lanemask operand is a 64-bit unsigned value that can store lane information
-for a register operand in the instruction. It can be used as many times as needed
-in an instruction, with one or more register operands associated with it. While
-the active bits represent the live subregister (in virtual registers) or regUnits
-(in physical registers), the remaining bits can represent the UNDEF part of it.
+A LaneMask operand contains a LaneBitmask struct representing the covering of a
+register with sub-registers. [That's what it says in LaneBitmask.h!] Instructions
+typically associate a LaneMask operand with one or more Register operands, and
+use it to represent sub-register granularity information like liveness for those
+associated Register operands.
-For example, the COPY_LANEMASK instruction uses this operand to copy only active
+For example, the COPY_LANEMASK instruction uses this operand to copy only active
lanes (of the source register) in the mask. The syntax for it would look like:
.. code-block:: text
$vgpr1 = COPY_LANEMASK $vgpr0, lanemask(0x00000000000000C0)
-
+
.. TODO: Describe the parsers default behaviour when optional YAML attributes
are missing.
.. TODO: Describe the syntax for virtual register YAML definitions.
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index a219f8b50b0a1..912393b0086cf 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -1432,7 +1432,7 @@ class MachineInstr
return getOpcode() == TargetOpcode::COPY;
}
- bool isCopyLanemask() const {
+ bool isCopyLaneMask() const {
return getOpcode() == TargetOpcode::COPY_LANEMASK;
}
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 5b12c92933bfa..f99f8198805d0 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -114,8 +114,9 @@ HANDLE_TARGET_OPCODE(REG_SEQUENCE)
/// used to copy between subregisters of virtual registers.
HANDLE_TARGET_OPCODE(COPY)
-/// COPY_LANEMASK - Target-independent register copy for active mask in
-/// register as represented by the lanemask. This instruction does not
+/// COPY_LANEMASK - Target-independent partial register copy. The laneMask
+/// operand indicates which parts of the source register are copied to the
+/// destination. Other parts of the destination are undefined. It does not
/// support copy between subregisters of virtual registers.
HANDLE_TARGET_OPCODE(COPY_LANEMASK)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index c5cd09b78f0d4..e862fab40a435 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -2881,22 +2881,22 @@ bool MIParser::parseLaneMaskOperand(MachineOperand &Dest) {
lex();
if (expectAndConsume(MIToken::lparen))
- return error("lanemask should begin with '('.");
+ return true;
LaneBitmask LaneMask = LaneBitmask::getAll();
// Parse lanemask.
if (Token.isNot(MIToken::IntegerLiteral) && Token.isNot(MIToken::HexLiteral))
- return error("expected a valid lane mask value.");
+ return error("expected a valid lane mask value");
static_assert(sizeof(LaneBitmask::Type) == sizeof(uint64_t),
"Use correct get-function for lane mask.");
LaneBitmask::Type V;
if (getUint64(V))
- return error("invalid lanemask value");
+ return true;
LaneMask = LaneBitmask(V);
lex();
if (expectAndConsume(MIToken::rparen))
- return error("lanemask should be terminated by ')'.");
+ return true;
Dest = MachineOperand::CreateLaneMask(LaneMask);
return false;
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index c12666f86f88f..9adcb1b8a0e22 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2434,7 +2434,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
const MachineOperand &LaneMaskOp = MI->getOperand(2);
const Register SrcReg = SrcOp.getReg();
const LaneBitmask LaneMask = LaneMaskOp.getLaneMask();
- LaneBitmask SrcMaxLanemask = LaneBitmask::getAll();
+ LaneBitmask SrcMaxLaneMask = LaneBitmask::getAll();
if (DstOp.getSubReg())
report("COPY_LANEMASK must not use a subregister index", &DstOp, 0);
@@ -2448,15 +2448,23 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
if (SrcReg.isPhysical()) {
const TargetRegisterClass *SrcRC = TRI->getMinimalPhysRegClass(SrcReg);
if (SrcRC)
- SrcMaxLanemask = SrcRC->getLaneMask();
+ SrcMaxLaneMask = SrcRC->getLaneMask();
} else {
- SrcMaxLanemask = MRI->getMaxLaneMaskForVReg(SrcReg);
+ SrcMaxLaneMask = MRI->getMaxLaneMaskForVReg(SrcReg);
}
- // If LaneMask is equal to OR greater than the SrcMaxLanemask, it
- // impliess COPY_LANEMASK is trying to copy all lanes.
- if (SrcMaxLanemask <= LaneMask)
- report("COPY_LANEMASK cannot read all lanes", MI);
+ // COPY_LANEMASK should be used only for partial copy. For full
+ // copy, one should strictly use the COPY instruction.
+ if (SrcMaxLaneMask == LaneMask)
+ report("COPY_LANEMASK cannot be used to do full copy", MI);
+
+ // If LaneMask is equal to OR greater than the SrcMaxLaneMask, it
+ // implies COPY_LANEMASK is attempting to read from the lanes that
+ // don't exists in the source register.
+ if (SrcMaxLaneMask < LaneMask)
+ report("COPY_LANEMASK attempts to read from the lanes that "
+ "don't exist in the source register",
+ MI);
break;
}
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-0.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-0.mir
index ded2c5fca5789..052305d9f9c36 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-0.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-0.mir
@@ -7,7 +7,7 @@ body: |
bb.0:
liveins: $vgpr0
- ; CHECK: [[@LINE+1]]:47: lanemask should be terminated by ')'.
+ ; CHECK: [[@LINE+1]]:47: expected ')'
$vgpr1 = COPY_LANEMASK $vgpr0, lanemask(16
S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-1.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-1.mir
index d3d3d3526261f..3382572f67213 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-1.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-1.mir
@@ -7,7 +7,7 @@ body: |
bb.0:
liveins: $vgpr0
- ; CHECK: [[@LINE+1]]:45: lanemask should begin with '('.
+ ; CHECK: [[@LINE+1]]:45: expected '('
$vgpr1 = COPY_LANEMASK $vgpr0, lanemask 14)
S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-2.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-2.mir
index 310051b6bee52..647f6116f18f7 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-2.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-2.mir
@@ -7,7 +7,7 @@ body: |
bb.0:
liveins: $vgpr0
- ; CHECK: [[@LINE+1]]:45: expected a valid lane mask value.
+ ; CHECK: [[@LINE+1]]:45: expected a valid lane mask value
$vgpr1 = COPY_LANEMASK $vgpr0, lanemask(undef)
S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-3.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-3.mir
index 0b4e4d1ef4ffa..68324f1b2f90e 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-3.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-3.mir
@@ -7,7 +7,7 @@ body: |
bb.0:
liveins: $vgpr0
- ; CHECK: [[@LINE+1]]:45: expected a valid lane mask value.
+ ; CHECK: [[@LINE+1]]:45: expected a valid lane mask value
$vgpr1 = COPY_LANEMASK $vgpr0, lanemask()
S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
index 1f79811473579..fcef8a6a37dc3 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
@@ -77,7 +77,7 @@
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_ABDU (opcode 67): 1 type index, 0 imm indices
-# DEBUG-NEXT: .. opcode 67 is aliased to 66
+# DEBUG-NEXT: .. opcode 67 is aliased to 66
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
diff --git a/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask0.mir b/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask0.mir
index f976ffa24a23a..b7d775f7a1b35 100644
--- a/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask0.mir
+++ b/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask0.mir
@@ -12,22 +12,22 @@ body: |
; CHECK: *** Bad machine code: COPY_LANEMASK must read at least one lane ***
$vgpr2 = COPY_LANEMASK $vgpr0, lanemask(0)
- ; CHECK: *** Bad machine code: COPY_LANEMASK cannot read all lanes ***
+ ; CHECK: *** Bad machine code: COPY_LANEMASK attempts to read from the lanes that don't exist in the source register ***
$vgpr3 = COPY_LANEMASK $vgpr1, lanemask(0xFFFFFFFFFFFFFFFF)
- ; CHECK: *** Bad machine code: COPY_LANEMASK cannot read all lanes ***
+ ; CHECK: *** Bad machine code: COPY_LANEMASK cannot be used to do full copy ***
$vgpr4_vgpr5 = COPY_LANEMASK $vgpr2_vgpr3, lanemask(0x000000000000000F)
- ; CHECK: *** Bad machine code: COPY_LANEMASK cannot read all lanes ***
+ ; CHECK: *** Bad machine code: COPY_LANEMASK cannot be used to do full copy ***
%1:vgpr_32 = COPY_LANEMASK %0, lanemask(0x0000000000000003)
- ; CHECK: *** Bad machine code: COPY_LANEMASK cannot read all lanes ***
+ ; CHECK: *** Bad machine code: COPY_LANEMASK attempts to read from the lanes that don't exist in the source register ***
%2:vgpr_32 = COPY_LANEMASK %1, lanemask(0x0000000FFFFFFFFF)
- ; CHECK: *** Bad machine code: COPY_LANEMASK cannot read all lanes ***
+ ; CHECK: *** Bad machine code: COPY_LANEMASK attempts to read from the lanes that don't exist in the source register ***
%3:vreg_64 = COPY_LANEMASK $vgpr4_vgpr5, lanemask(0x00000000000000FF)
- ; CHECK: *** Bad machine code: COPY_LANEMASK cannot read all lanes ***
+ ; CHECK: *** Bad machine code: COPY_LANEMASK cannot be used to do full copy ***
$vgpr6_vgpr7 = COPY_LANEMASK %3, lanemask(0x000000000000000F)
; CHECK: *** Bad machine code: COPY_LANEMASK must not use a subregister index ***
diff --git a/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask1.mir b/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask1.mir
index d4338da717ba2..0b461107f5b5f 100644
--- a/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask1.mir
+++ b/llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask1.mir
@@ -2,7 +2,7 @@
# CHECK: *** Bad machine code: Too few operands ***
# CHECK-NEXT: - function: test_copy_lanemask_instruction_1
-# CHECK-NEXT: - basic block: %bb.0
+# CHECK-NEXT: - basic block: %bb.0
# CHECK-NEXT: - instruction: $vgpr2 = COPY_LANEMASK %0:vgpr_32
---
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