[llvm] [PowerPC][NFC] auto gen checks vec rounding tests (PR #166435)
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 4 11:46:48 PST 2025
https://github.com/lei137 created https://github.com/llvm/llvm-project/pull/166435
Update tests to contain auto generated checks.
>From 7a352b44ffcef575784c6ce5ad7d2c2bc7770d82 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Tue, 4 Nov 2025 19:51:59 +0000
Subject: [PATCH] [PowerPC][NFC] auto gen checks vec rounding tests
Update tests to contain auto generated checks.
---
llvm/test/CodeGen/PowerPC/vec_rounding.ll | 195 +++++++++++++++-------
1 file changed, 137 insertions(+), 58 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/vec_rounding.ll b/llvm/test/CodeGen/PowerPC/vec_rounding.ll
index 2f16a435440ff..438c8ebdc099e 100644
--- a/llvm/test/CodeGen/PowerPC/vec_rounding.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_rounding.ll
@@ -1,172 +1,251 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s
; Check vector round to single-precision toward -infinity (vrfim)
; instruction generation using Altivec.
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
declare <2 x double> @llvm.floor.v2f64(<2 x double> %p)
define <2 x double> @floor_v2f64(<2 x double> %p)
+; CHECK-LABEL: floor_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: frim 1, 1
+; CHECK-NEXT: frim 2, 2
+; CHECK-NEXT: blr
{
%t = call <2 x double> @llvm.floor.v2f64(<2 x double> %p)
ret <2 x double> %t
}
-; CHECK-LABEL: floor_v2f64:
-; CHECK: frim
-; CHECK: frim
declare <4 x double> @llvm.floor.v4f64(<4 x double> %p)
define <4 x double> @floor_v4f64(<4 x double> %p)
+; CHECK-LABEL: floor_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: frim 1, 1
+; CHECK-NEXT: frim 2, 2
+; CHECK-NEXT: frim 3, 3
+; CHECK-NEXT: frim 4, 4
+; CHECK-NEXT: blr
{
%t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p)
ret <4 x double> %t
}
-; CHECK-LABEL: floor_v4f64:
-; CHECK: frim
-; CHECK: frim
-; CHECK: frim
-; CHECK: frim
declare <2 x double> @llvm.ceil.v2f64(<2 x double> %p)
define <2 x double> @ceil_v2f64(<2 x double> %p)
+; CHECK-LABEL: ceil_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: frip 1, 1
+; CHECK-NEXT: frip 2, 2
+; CHECK-NEXT: blr
{
%t = call <2 x double> @llvm.ceil.v2f64(<2 x double> %p)
ret <2 x double> %t
}
-; CHECK-LABEL: ceil_v2f64:
-; CHECK: frip
-; CHECK: frip
declare <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
define <4 x double> @ceil_v4f64(<4 x double> %p)
+; CHECK-LABEL: ceil_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: frip 1, 1
+; CHECK-NEXT: frip 2, 2
+; CHECK-NEXT: frip 3, 3
+; CHECK-NEXT: frip 4, 4
+; CHECK-NEXT: blr
{
%t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
ret <4 x double> %t
}
-; CHECK-LABEL: ceil_v4f64:
-; CHECK: frip
-; CHECK: frip
-; CHECK: frip
-; CHECK: frip
declare <2 x double> @llvm.trunc.v2f64(<2 x double> %p)
define <2 x double> @trunc_v2f64(<2 x double> %p)
+; CHECK-LABEL: trunc_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: friz 1, 1
+; CHECK-NEXT: friz 2, 2
+; CHECK-NEXT: blr
{
%t = call <2 x double> @llvm.trunc.v2f64(<2 x double> %p)
ret <2 x double> %t
}
-; CHECK-LABEL: trunc_v2f64:
-; CHECK: friz
-; CHECK: friz
declare <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
define <4 x double> @trunc_v4f64(<4 x double> %p)
+; CHECK-LABEL: trunc_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: friz 1, 1
+; CHECK-NEXT: friz 2, 2
+; CHECK-NEXT: friz 3, 3
+; CHECK-NEXT: friz 4, 4
+; CHECK-NEXT: blr
{
%t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
ret <4 x double> %t
}
-; CHECK-LABEL: trunc_v4f64:
-; CHECK: friz
-; CHECK: friz
-; CHECK: friz
-; CHECK: friz
declare <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p)
-define <2 x double> @nearbyint_v2f64(<2 x double> %p)
+define <2 x double> @nearbyint_v2f64(<2 x double> %p) nounwind
+; CHECK-LABEL: nearbyint_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stdu 1, -128(1)
+; CHECK-NEXT: std 0, 144(1)
+; CHECK-NEXT: stfd 30, 112(1) # 8-byte Folded Spill
+; CHECK-NEXT: stfd 31, 120(1) # 8-byte Folded Spill
+; CHECK-NEXT: fmr 31, 2
+; CHECK-NEXT: bl nearbyint
+; CHECK-NEXT: nop
+; CHECK-NEXT: fmr 30, 1
+; CHECK-NEXT: fmr 1, 31
+; CHECK-NEXT: bl nearbyint
+; CHECK-NEXT: nop
+; CHECK-NEXT: fmr 2, 1
+; CHECK-NEXT: fmr 1, 30
+; CHECK-NEXT: lfd 31, 120(1) # 8-byte Folded Reload
+; CHECK-NEXT: lfd 30, 112(1) # 8-byte Folded Reload
+; CHECK-NEXT: addi 1, 1, 128
+; CHECK-NEXT: ld 0, 16(1)
+; CHECK-NEXT: mtlr 0
+; CHECK-NEXT: blr
{
%t = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p)
ret <2 x double> %t
}
-; CHECK-LABEL: nearbyint_v2f64:
-; CHECK: bl nearbyint
-; CHECK: bl nearbyint
declare <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
-define <4 x double> @nearbyint_v4f64(<4 x double> %p)
+define <4 x double> @nearbyint_v4f64(<4 x double> %p) nounwind
+; CHECK-LABEL: nearbyint_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stdu 1, -144(1)
+; CHECK-NEXT: std 0, 160(1)
+; CHECK-NEXT: stfd 28, 112(1) # 8-byte Folded Spill
+; CHECK-NEXT: stfd 29, 120(1) # 8-byte Folded Spill
+; CHECK-NEXT: fmr 29, 2
+; CHECK-NEXT: stfd 30, 128(1) # 8-byte Folded Spill
+; CHECK-NEXT: fmr 30, 3
+; CHECK-NEXT: stfd 31, 136(1) # 8-byte Folded Spill
+; CHECK-NEXT: fmr 31, 4
+; CHECK-NEXT: bl nearbyint
+; CHECK-NEXT: nop
+; CHECK-NEXT: fmr 28, 1
+; CHECK-NEXT: fmr 1, 29
+; CHECK-NEXT: bl nearbyint
+; CHECK-NEXT: nop
+; CHECK-NEXT: fmr 29, 1
+; CHECK-NEXT: fmr 1, 30
+; CHECK-NEXT: bl nearbyint
+; CHECK-NEXT: nop
+; CHECK-NEXT: fmr 30, 1
+; CHECK-NEXT: fmr 1, 31
+; CHECK-NEXT: bl nearbyint
+; CHECK-NEXT: nop
+; CHECK-NEXT: fmr 4, 1
+; CHECK-NEXT: fmr 1, 28
+; CHECK-NEXT: lfd 31, 136(1) # 8-byte Folded Reload
+; CHECK-NEXT: lfd 28, 112(1) # 8-byte Folded Reload
+; CHECK-NEXT: fmr 2, 29
+; CHECK-NEXT: fmr 3, 30
+; CHECK-NEXT: lfd 30, 128(1) # 8-byte Folded Reload
+; CHECK-NEXT: lfd 29, 120(1) # 8-byte Folded Reload
+; CHECK-NEXT: addi 1, 1, 144
+; CHECK-NEXT: ld 0, 16(1)
+; CHECK-NEXT: mtlr 0
+; CHECK-NEXT: blr
{
%t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
ret <4 x double> %t
}
-; CHECK-LABEL: nearbyint_v4f64:
-; CHECK: bl nearbyint
-; CHECK: bl nearbyint
-; CHECK: bl nearbyint
-; CHECK: bl nearbyint
declare <4 x float> @llvm.floor.v4f32(<4 x float> %p)
define <4 x float> @floor_v4f32(<4 x float> %p)
+; CHECK-LABEL: floor_v4f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrfim 2, 2
+; CHECK-NEXT: blr
{
%t = call <4 x float> @llvm.floor.v4f32(<4 x float> %p)
ret <4 x float> %t
}
-; CHECK-LABEL: floor_v4f32:
-; CHECK: vrfim
declare <8 x float> @llvm.floor.v8f32(<8 x float> %p)
define <8 x float> @floor_v8f32(<8 x float> %p)
+; CHECK-LABEL: floor_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrfim 2, 2
+; CHECK-NEXT: vrfim 3, 3
+; CHECK-NEXT: blr
{
%t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p)
ret <8 x float> %t
}
-; CHECK-LABEL: floor_v8f32:
-; CHECK: vrfim
-; CHECK: vrfim
declare <4 x float> @llvm.ceil.v4f32(<4 x float> %p)
define <4 x float> @ceil_v4f32(<4 x float> %p)
+; CHECK-LABEL: ceil_v4f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrfip 2, 2
+; CHECK-NEXT: blr
{
%t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %p)
ret <4 x float> %t
}
-; CHECK-LABEL: ceil_v4f32:
-; CHECK: vrfip
declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
define <8 x float> @ceil_v8f32(<8 x float> %p)
+; CHECK-LABEL: ceil_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrfip 2, 2
+; CHECK-NEXT: vrfip 3, 3
+; CHECK-NEXT: blr
{
%t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
ret <8 x float> %t
}
-; CHECK-LABEL: ceil_v8f32:
-; CHECK: vrfip
-; CHECK: vrfip
declare <4 x float> @llvm.trunc.v4f32(<4 x float> %p)
define <4 x float> @trunc_v4f32(<4 x float> %p)
+; CHECK-LABEL: trunc_v4f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrfiz 2, 2
+; CHECK-NEXT: blr
{
%t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %p)
ret <4 x float> %t
}
-; CHECK-LABEL: trunc_v4f32:
-; CHECK: vrfiz
declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
define <8 x float> @trunc_v8f32(<8 x float> %p)
+; CHECK-LABEL: trunc_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrfiz 2, 2
+; CHECK-NEXT: vrfiz 3, 3
+; CHECK-NEXT: blr
{
%t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
ret <8 x float> %t
}
-; CHECK-LABEL: trunc_v8f32:
-; CHECK: vrfiz
-; CHECK: vrfiz
declare <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p)
define <4 x float> @nearbyint_v4f32(<4 x float> %p)
+; CHECK-LABEL: nearbyint_v4f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrfin 2, 2
+; CHECK-NEXT: blr
{
%t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p)
ret <4 x float> %t
}
-; CHECK-LABEL: nearbyint_v4f32:
-; CHECK: vrfin
declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
define <8 x float> @nearbyint_v8f32(<8 x float> %p)
+; CHECK-LABEL: nearbyint_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrfin 2, 2
+; CHECK-NEXT: vrfin 3, 3
+; CHECK-NEXT: blr
{
%t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
ret <8 x float> %t
}
-; CHECK-LABEL: nearbyint_v8f32:
-; CHECK: vrfin
-; CHECK: vrfin
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