[clang] [llvm] [X86][AVX512] rematerialize smaller predicate masks (PR #166178)

[Ahmed Nour via llvm-commits]

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@@ -3173,6 +3179,23 @@ let Predicates = [HasAVX512] in {
   def : Pat<(v1i1 immAllOnesV),  (COPY_TO_REGCLASS (KSET1W), VK1)>;
 }
 
+// With AVX512DQ, use 8-bit operations for 8-bit masks to avoid setting upper
+// bits
+let Predicates = [HasDQI] in {
+  def : Pat<(v8i1 immAllZerosV), (KSET0B)>;
+  def : Pat<(v8i1 immAllOnesV), (KSET1B)>;
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ahmednoursphinx wrote:

No, primarily due to predicate specificity, not order.
`HasDQI` is more restrictive than `HasAVX512`, so the `KSET1B` pattern wins on DQI targets regardless of order. Pattern order only matters as a tie-breaker when predicate specificity is equal.

https://github.com/llvm/llvm-project/pull/166178