[llvm] [RISCV][llvm] Preliminary P extension codegen support (PR #162668)

[Brandon Wu via llvm-commits]

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@@ -1104,6 +1104,10 @@ def FeatureStdExtP
 def HasStdExtP : Predicate<"Subtarget->hasStdExtP()">,
                  AssemblerPredicate<(all_of FeatureStdExtP),
                                     "'Base P' (Packed SIMD)">;
+def FeatureEnablePExtCodeGen
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4vtomat wrote:

Oh I think thats more reasonable

https://github.com/llvm/llvm-project/pull/162668