[llvm] ca00234 - [RISCV] Correct comments in rv64-stackmap.ll to not use X86 register name. NFC (#165912)

[via llvm-commits]

Author: Craig Topper
Date: 2025-11-03T12:35:54-08:00
New Revision: ca00234c09e03bdb3471c83a24f1b8bc1fdb31f9

URL: https://github.com/llvm/llvm-project/commit/ca00234c09e03bdb3471c83a24f1b8bc1fdb31f9
DIFF: https://github.com/llvm/llvm-project/commit/ca00234c09e03bdb3471c83a24f1b8bc1fdb31f9.diff

LOG: [RISCV] Correct comments in rv64-stackmap.ll to not use X86 register name. NFC (#165912)

Note, X86 forces a frame pointer for stackmaps/patchpoint. So they use
RBP where we use SP.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv64-stackmap.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rv64-stackmap.ll b/llvm/test/CodeGen/RISCV/rv64-stackmap.ll
index c50a0fb3ffe91..320a3aa94cd7d 100644
--- a/llvm/test/CodeGen/RISCV/rv64-stackmap.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-stackmap.ll
@@ -286,8 +286,8 @@ define void @liveConstant() {
 ; CHECK-NEXT:   .half   0
 ; CHECK-NEXT:   .half   28
 ;
-; Check that at least one is a spilled entry from RBP.
-; Location: Indirect RBP + ...
+; Check that at least one is a spilled entry from SP.
+; Location: Indirect SP + ...
 ; CHECK:        .byte   3
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .half   8
@@ -307,7 +307,7 @@ entry:
 ; CHECK-NEXT:   .half   0
 ; 1 location
 ; CHECK-NEXT:   .half   1
-; Loc 0: Direct RBP - ofs
+; Loc 0: Direct SP + ofs
 ; CHECK-NEXT:   .byte   2
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .half   8
@@ -320,14 +320,14 @@ entry:
 ; CHECK-NEXT:   .half   0
 ; 2 locations
 ; CHECK-NEXT:   .half   2
-; Loc 0: Direct RBP - ofs
+; Loc 0: Direct SP + ofs
 ; CHECK-NEXT:   .byte   2
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .half   8
 ; CHECK-NEXT:   .half   2
 ; CHECK-NEXT:   .half   0
 ; CHECK-NEXT:   .word
-; Loc 1: Direct RBP - ofs
+; Loc 1: Direct SP + ofs
 ; CHECK-NEXT:   .byte   2
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .half   8