[llvm] [PowerPC] Lowering support for EVL type VP_LOAD/VP_STORE (PR #165910)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 3 11:12:16 PST 2025
https://github.com/RolandF77 updated https://github.com/llvm/llvm-project/pull/165910
>From d451b76547cda7de31a6ce9a40c22f2ff8881809 Mon Sep 17 00:00:00 2001
From: Roland Froese <froese at ca.ibm.com>
Date: Wed, 29 Oct 2025 18:46:09 +0000
Subject: [PATCH 1/4] lower vp load/store
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 88 +++++++++++++++++++
llvm/lib/Target/PowerPC/PPCISelLowering.h | 3 +
.../Target/PowerPC/PPCTargetTransformInfo.cpp | 34 +++++++
.../Target/PowerPC/PPCTargetTransformInfo.h | 3 +
4 files changed, 128 insertions(+)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 17f04d0fd05e8..cc9941f1f51c3 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -652,6 +652,15 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
+ setOperationAction(ISD::VP_STORE, MVT::v16i1, Custom);
+ setOperationAction(ISD::VP_STORE, MVT::v8i1, Custom);
+ setOperationAction(ISD::VP_STORE, MVT::v4i1, Custom);
+ setOperationAction(ISD::VP_STORE, MVT::v2i1, Custom);
+ setOperationAction(ISD::VP_LOAD, MVT::v16i1, Custom);
+ setOperationAction(ISD::VP_LOAD, MVT::v8i1, Custom);
+ setOperationAction(ISD::VP_LOAD, MVT::v4i1, Custom);
+ setOperationAction(ISD::VP_LOAD, MVT::v2i1, Custom);
+
// We want to custom lower some of our intrinsics.
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f64, Custom);
@@ -11909,6 +11918,81 @@ SDValue PPCTargetLowering::LowerIS_FPCLASS(SDValue Op,
return getDataClassTest(LHS, Category, Dl, DAG, Subtarget);
}
+static SDValue AdjustLength(SDValue Val, unsigned Bits, bool Left,
+ SelectionDAG &DAG) {
+ SDLoc dl(Val);
+ EVT VT = Val->getValueType(0);
+ unsigned LeftAdj = Left ? VT.getSizeInBits() - 8 : 0;
+ unsigned TypeAdj = llvm::countr_zero<uint32_t>(Bits / 8);
+ // unsigned Shift = llvm::countr_zero<uint64_t>(Imm);
+ // EVT ShiftAmountTy = getShiftAmountTy(VT, DAG.getDataLayout());
+ // if (Value > 0 && isPowerOf2_64(Value))
+ SDValue SHLAmt = DAG.getConstant(LeftAdj + TypeAdj, dl, VT);
+ return DAG.getNode(ISD::SHL, dl, VT, Val, SHLAmt);
+}
+
+SDValue PPCTargetLowering::LowerVP_LOAD(SDValue Op, SelectionDAG &DAG) const {
+ dbgs() << "&&& Lower VP_LOAD\n";
+ Op.dump();
+ auto VPLD = cast<VPLoadSDNode>(Op);
+ bool Future = Subtarget.isISAFuture();
+ SDLoc dl(Op);
+ assert(ISD::isConstantSplatVectorAllOnes(Op->getOperand(3).getNode(), true) &&
+ "Mask predication not supported");
+ EVT PtrVT = getPointerTy(DAG.getDataLayout());
+ SDValue Len = DAG.getNode(ISD::ANY_EXTEND, dl, PtrVT, VPLD->getOperand(4));
+ unsigned IID = Future ? Intrinsic::ppc_vsx_lxvrl : Intrinsic::ppc_vsx_lxvl;
+ unsigned EltBits = Op->getValueType(0).getScalarType().getSizeInBits();
+ Len = AdjustLength(Len, EltBits, !Future, DAG);
+ SDValue Ops[] = {
+ VPLD->getChain(), // Chain
+ // DAG.getConstant(Intrinsic::ppc_vsx_lxvl, dl, MVT::i32),
+ DAG.getConstant(IID, dl, MVT::i32),
+ VPLD->getOperand(1),
+ // VPLD->getOperand(4),
+ // DAG.getNode(ISD::ANY_EXTEND, dl, PtrVT, VPLD->getOperand(4)),
+ Len
+ };
+ SDVTList Tys = DAG.getVTList(Op->getValueType(0), MVT::Other);
+ SDValue VPL = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl, Tys,
+ Ops, VPLD->getMemoryVT(), VPLD->getMemOperand());
+ VPL.dump();
+ return VPL;
+ // return SDValue();
+}
+
+SDValue PPCTargetLowering::LowerVP_STORE(SDValue Op, SelectionDAG &DAG) const {
+ dbgs() << "&&& Lower VP_STORE\n";
+ Op.dump();
+ auto VPST = cast<VPStoreSDNode>(Op);
+ assert(ISD::isConstantSplatVectorAllOnes(Op->getOperand(4).getNode(), true) &&
+ "Mask predication not supported");
+ EVT PtrVT = getPointerTy(DAG.getDataLayout());
+ SDLoc dl(Op);
+ SDValue Len = DAG.getNode(ISD::ANY_EXTEND, dl, PtrVT, VPST->getOperand(5));
+ unsigned EltBits = Op->getOperand(1).getValueType().getScalarType().getSizeInBits();
+ bool Future = Subtarget.isISAFuture();
+ unsigned IID = Future ? Intrinsic::ppc_vsx_stxvrl : Intrinsic::ppc_vsx_stxvl;
+ Len = AdjustLength(Len, EltBits, !Future, DAG);
+ SDValue Ops[] = {
+ VPST->getChain(), // Chain
+ // DAG.getConstant(Intrinsic::ppc_vsx_stxvl, dl, MVT::i32),
+ DAG.getConstant(IID, dl, MVT::i32),
+ // DAG.getTargetConstant(Intrinsic::ppc_vsx_stxvl, dl, MVT::i64),
+ DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, VPST->getOperand(1)),
+ VPST->getOperand(2),
+ // DAG.getNode(ISD::ANY_EXTEND, dl, PtrVT, VPST->getOperand(5)),
+ Len
+ };
+ SDVTList Tys = DAG.getVTList(MVT::Other);
+ // SDValue VPS = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl, Tys,
+ SDValue VPS = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, dl, Tys,
+ Ops, VPST->getMemoryVT(), VPST->getMemOperand());
+ VPS.dump();
+ return VPS;
+ // return SDValue();
+}
+
SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
SelectionDAG &DAG) const {
SDLoc dl(Op);
@@ -12763,6 +12847,10 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
if (Op->getFlags().hasNoFPExcept())
return Op;
return SDValue();
+ case ISD::VP_LOAD:
+ return LowerVP_LOAD(Op, DAG);
+ case ISD::VP_STORE:
+ return LowerVP_STORE(Op, DAG);
}
}
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 880aca751d7d6..d967018982734 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -1345,6 +1345,9 @@ namespace llvm {
SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerVP_LOAD(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerVP_STORE(SDValue Op, SelectionDAG &DAG) const;
+
SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerDMFVectorLoad(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index 2fba090f2d501..170ca19d49670 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -1031,3 +1031,37 @@ bool PPCTTIImpl::getTgtMemIntrinsic(IntrinsicInst *Inst,
bool PPCTTIImpl::supportsTailCallFor(const CallBase *CB) const {
return TLI->supportsTailCallFor(CB);
}
+
+TargetTransformInfo::VPLegalization
+PPCTTIImpl::getVPLegalizationStrategy(const VPIntrinsic &PI) const {
+ using VPLegalization = TargetTransformInfo::VPLegalization;
+ unsigned Directive = ST->getCPUDirective();
+ VPLegalization DefaultLegalization = BaseT::getVPLegalizationStrategy(PI);
+ if (Directive != PPC::DIR_PWR10 && Directive != PPC::DIR_PWR_FUTURE)
+ return DefaultLegalization;
+
+ unsigned IID = PI.getIntrinsicID();
+ if (IID != Intrinsic::vp_load && IID != Intrinsic::vp_store)
+ return DefaultLegalization;
+
+ bool IsLoad = IID == Intrinsic::vp_load;
+ Type* VecTy = IsLoad ? PI.getType() : PI.getOperand(0)->getType();
+ EVT VT = TLI->getValueType(DL, VecTy, true);
+ dbgs() << "&&& Typecheck " << VT << "\n";
+ if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
+ VT != MVT::v16i8)
+ return DefaultLegalization;
+
+ auto IsAllTrueMask = [](Value *MaskVal) {
+ if (Value *SplattedVal = getSplatValue(MaskVal))
+ if (auto *ConstValue = dyn_cast<Constant>(SplattedVal))
+ return ConstValue->isAllOnesValue();
+ return false;
+ };
+ unsigned MaskIx = IsLoad ? 1 : 2;
+ if (!IsAllTrueMask(PI.getOperand(MaskIx)))
+ return DefaultLegalization;
+
+ return VPLegalization(VPLegalization::Legal, VPLegalization::Legal);
+}
+
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
index 475472ac3720f..385ad89876b93 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
@@ -150,6 +150,9 @@ class PPCTTIImpl final : public BasicTTIImplBase<PPCTTIImpl> {
const ArrayRef<Type *> &Types) const override;
bool supportsTailCallFor(const CallBase *CB) const override;
+ TargetTransformInfo::VPLegalization
+ getVPLegalizationStrategy(const VPIntrinsic &PI) const override;
+
private:
// The following constant is used for estimating costs on power9.
static const InstructionCost::CostType P9PipelineFlushEstimate = 80;
>From 5d3ff20400d06434c06084826fda0afd2c358d1e Mon Sep 17 00:00:00 2001
From: Roland Froese <froese at ca.ibm.com>
Date: Fri, 31 Oct 2025 14:55:57 +0000
Subject: [PATCH 2/4] allow p9 testing
---
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index 170ca19d49670..2660bc0a90a95 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -24,6 +24,9 @@ using namespace llvm;
#define DEBUG_TYPE "ppctti"
+static cl::opt<bool> Pwr9EVL("ppc-pwr9-evl",
+cl::desc("Allow vp.load and vp.store for pwr9"), cl::init(false), cl::Hidden);
+
static cl::opt<bool> VecMaskCost("ppc-vec-mask-cost",
cl::desc("add masking cost for i1 vectors"), cl::init(true), cl::Hidden);
@@ -1037,7 +1040,8 @@ PPCTTIImpl::getVPLegalizationStrategy(const VPIntrinsic &PI) const {
using VPLegalization = TargetTransformInfo::VPLegalization;
unsigned Directive = ST->getCPUDirective();
VPLegalization DefaultLegalization = BaseT::getVPLegalizationStrategy(PI);
- if (Directive != PPC::DIR_PWR10 && Directive != PPC::DIR_PWR_FUTURE)
+ if (Directive != PPC::DIR_PWR10 && Directive != PPC::DIR_PWR_FUTURE &&
+ (!Pwr9EVL || Directive != PPC::DIR_PWR9))
return DefaultLegalization;
unsigned IID = PI.getIntrinsicID();
@@ -1047,7 +1051,7 @@ PPCTTIImpl::getVPLegalizationStrategy(const VPIntrinsic &PI) const {
bool IsLoad = IID == Intrinsic::vp_load;
Type* VecTy = IsLoad ? PI.getType() : PI.getOperand(0)->getType();
EVT VT = TLI->getValueType(DL, VecTy, true);
- dbgs() << "&&& Typecheck " << VT << "\n";
+ // dbgs() << "&&& Typecheck " << VT << "\n";
if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
VT != MVT::v16i8)
return DefaultLegalization;
>From 73496b682b1b27b0949562c8f97e8c7d12b1dc35 Mon Sep 17 00:00:00 2001
From: Roland Froese <froese at ca.ibm.com>
Date: Fri, 31 Oct 2025 19:07:12 +0000
Subject: [PATCH 3/4] cleanup
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 70 +++++++------------
.../Target/PowerPC/PPCTargetTransformInfo.cpp | 7 +-
2 files changed, 29 insertions(+), 48 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index cc9941f1f51c3..f303d237e5cc2 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -652,14 +652,16 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
- setOperationAction(ISD::VP_STORE, MVT::v16i1, Custom);
- setOperationAction(ISD::VP_STORE, MVT::v8i1, Custom);
- setOperationAction(ISD::VP_STORE, MVT::v4i1, Custom);
- setOperationAction(ISD::VP_STORE, MVT::v2i1, Custom);
- setOperationAction(ISD::VP_LOAD, MVT::v16i1, Custom);
- setOperationAction(ISD::VP_LOAD, MVT::v8i1, Custom);
- setOperationAction(ISD::VP_LOAD, MVT::v4i1, Custom);
- setOperationAction(ISD::VP_LOAD, MVT::v2i1, Custom);
+ if (Subtarget.isISA3_0() && isPPC64) {
+ setOperationAction(ISD::VP_STORE, MVT::v16i1, Custom);
+ setOperationAction(ISD::VP_STORE, MVT::v8i1, Custom);
+ setOperationAction(ISD::VP_STORE, MVT::v4i1, Custom);
+ setOperationAction(ISD::VP_STORE, MVT::v2i1, Custom);
+ setOperationAction(ISD::VP_LOAD, MVT::v16i1, Custom);
+ setOperationAction(ISD::VP_LOAD, MVT::v8i1, Custom);
+ setOperationAction(ISD::VP_LOAD, MVT::v4i1, Custom);
+ setOperationAction(ISD::VP_LOAD, MVT::v2i1, Custom);
+ }
// We want to custom lower some of our intrinsics.
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
@@ -11924,16 +11926,11 @@ static SDValue AdjustLength(SDValue Val, unsigned Bits, bool Left,
EVT VT = Val->getValueType(0);
unsigned LeftAdj = Left ? VT.getSizeInBits() - 8 : 0;
unsigned TypeAdj = llvm::countr_zero<uint32_t>(Bits / 8);
- // unsigned Shift = llvm::countr_zero<uint64_t>(Imm);
- // EVT ShiftAmountTy = getShiftAmountTy(VT, DAG.getDataLayout());
- // if (Value > 0 && isPowerOf2_64(Value))
SDValue SHLAmt = DAG.getConstant(LeftAdj + TypeAdj, dl, VT);
return DAG.getNode(ISD::SHL, dl, VT, Val, SHLAmt);
}
SDValue PPCTargetLowering::LowerVP_LOAD(SDValue Op, SelectionDAG &DAG) const {
- dbgs() << "&&& Lower VP_LOAD\n";
- Op.dump();
auto VPLD = cast<VPLoadSDNode>(Op);
bool Future = Subtarget.isISAFuture();
SDLoc dl(Op);
@@ -11941,56 +11938,39 @@ SDValue PPCTargetLowering::LowerVP_LOAD(SDValue Op, SelectionDAG &DAG) const {
"Mask predication not supported");
EVT PtrVT = getPointerTy(DAG.getDataLayout());
SDValue Len = DAG.getNode(ISD::ANY_EXTEND, dl, PtrVT, VPLD->getOperand(4));
- unsigned IID = Future ? Intrinsic::ppc_vsx_lxvrl : Intrinsic::ppc_vsx_lxvl;
+ unsigned IID = Future ? Intrinsic::ppc_vsx_lxvrl : Intrinsic::ppc_vsx_lxvl;
unsigned EltBits = Op->getValueType(0).getScalarType().getSizeInBits();
Len = AdjustLength(Len, EltBits, !Future, DAG);
- SDValue Ops[] = {
- VPLD->getChain(), // Chain
- // DAG.getConstant(Intrinsic::ppc_vsx_lxvl, dl, MVT::i32),
- DAG.getConstant(IID, dl, MVT::i32),
- VPLD->getOperand(1),
- // VPLD->getOperand(4),
- // DAG.getNode(ISD::ANY_EXTEND, dl, PtrVT, VPLD->getOperand(4)),
- Len
- };
+ SDValue Ops[] = {VPLD->getChain(), DAG.getConstant(IID, dl, MVT::i32),
+ VPLD->getOperand(1), Len};
SDVTList Tys = DAG.getVTList(Op->getValueType(0), MVT::Other);
- SDValue VPL = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl, Tys,
- Ops, VPLD->getMemoryVT(), VPLD->getMemOperand());
- VPL.dump();
+ SDValue VPL =
+ DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl, Tys, Ops,
+ VPLD->getMemoryVT(), VPLD->getMemOperand());
return VPL;
- // return SDValue();
}
SDValue PPCTargetLowering::LowerVP_STORE(SDValue Op, SelectionDAG &DAG) const {
- dbgs() << "&&& Lower VP_STORE\n";
- Op.dump();
auto VPST = cast<VPStoreSDNode>(Op);
assert(ISD::isConstantSplatVectorAllOnes(Op->getOperand(4).getNode(), true) &&
"Mask predication not supported");
EVT PtrVT = getPointerTy(DAG.getDataLayout());
SDLoc dl(Op);
SDValue Len = DAG.getNode(ISD::ANY_EXTEND, dl, PtrVT, VPST->getOperand(5));
- unsigned EltBits = Op->getOperand(1).getValueType().getScalarType().getSizeInBits();
+ unsigned EltBits =
+ Op->getOperand(1).getValueType().getScalarType().getSizeInBits();
bool Future = Subtarget.isISAFuture();
- unsigned IID = Future ? Intrinsic::ppc_vsx_stxvrl : Intrinsic::ppc_vsx_stxvl;
+ unsigned IID = Future ? Intrinsic::ppc_vsx_stxvrl : Intrinsic::ppc_vsx_stxvl;
Len = AdjustLength(Len, EltBits, !Future, DAG);
SDValue Ops[] = {
- VPST->getChain(), // Chain
- // DAG.getConstant(Intrinsic::ppc_vsx_stxvl, dl, MVT::i32),
- DAG.getConstant(IID, dl, MVT::i32),
- // DAG.getTargetConstant(Intrinsic::ppc_vsx_stxvl, dl, MVT::i64),
- DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, VPST->getOperand(1)),
- VPST->getOperand(2),
- // DAG.getNode(ISD::ANY_EXTEND, dl, PtrVT, VPST->getOperand(5)),
- Len
- };
+ VPST->getChain(), DAG.getConstant(IID, dl, MVT::i32),
+ DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, VPST->getOperand(1)),
+ VPST->getOperand(2), Len};
SDVTList Tys = DAG.getVTList(MVT::Other);
- // SDValue VPS = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl, Tys,
- SDValue VPS = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, dl, Tys,
- Ops, VPST->getMemoryVT(), VPST->getMemOperand());
- VPS.dump();
+ SDValue VPS =
+ DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, dl, Tys, Ops,
+ VPST->getMemoryVT(), VPST->getMemOperand());
return VPS;
- // return SDValue();
}
SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index 2660bc0a90a95..d3deec5350e59 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -1044,14 +1044,16 @@ PPCTTIImpl::getVPLegalizationStrategy(const VPIntrinsic &PI) const {
(!Pwr9EVL || Directive != PPC::DIR_PWR9))
return DefaultLegalization;
+ if (!ST->isPPC64())
+ return DefaultLegalization;
+
unsigned IID = PI.getIntrinsicID();
if (IID != Intrinsic::vp_load && IID != Intrinsic::vp_store)
return DefaultLegalization;
bool IsLoad = IID == Intrinsic::vp_load;
- Type* VecTy = IsLoad ? PI.getType() : PI.getOperand(0)->getType();
+ Type *VecTy = IsLoad ? PI.getType() : PI.getOperand(0)->getType();
EVT VT = TLI->getValueType(DL, VecTy, true);
- // dbgs() << "&&& Typecheck " << VT << "\n";
if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
VT != MVT::v16i8)
return DefaultLegalization;
@@ -1068,4 +1070,3 @@ PPCTTIImpl::getVPLegalizationStrategy(const VPIntrinsic &PI) const {
return VPLegalization(VPLegalization::Legal, VPLegalization::Legal);
}
-
>From 7ea0aca0fece6e2e2910f2d3b6ca4f0c12420195 Mon Sep 17 00:00:00 2001
From: Roland Froese <froese at ca.ibm.com>
Date: Mon, 3 Nov 2025 19:11:48 +0000
Subject: [PATCH 4/4] formatting
---
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index d3deec5350e59..6373343f2b2e3 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -25,7 +25,8 @@ using namespace llvm;
#define DEBUG_TYPE "ppctti"
static cl::opt<bool> Pwr9EVL("ppc-pwr9-evl",
-cl::desc("Allow vp.load and vp.store for pwr9"), cl::init(false), cl::Hidden);
+ cl::desc("Allow vp.load and vp.store for pwr9"),
+ cl::init(false), cl::Hidden);
static cl::opt<bool> VecMaskCost("ppc-vec-mask-cost",
cl::desc("add masking cost for i1 vectors"), cl::init(true), cl::Hidden);
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