[llvm] [RISCV][llvm] Preliminary P extension codegen support (PR #162668)

[Craig Topper via llvm-commits]

================
@@ -18,15 +18,15 @@
 // Operand and SDNode transformation definitions.
 //===----------------------------------------------------------------------===//
 
-def simm10 : RISCVSImmOp<10>;
+def simm10 : RISCVSImmLeafOp<10>;
 
 def SImm8UnsignedAsmOperand : SImmAsmOperand<8, "Unsigned"> {
   let RenderMethod = "addSImm8UnsignedOperands";
 }
 
 // A 8-bit signed immediate allowing range [-128, 255]
 // but represented as [-128, 127].
-def simm8_unsigned : RISCVOp {
+def simm8_unsigned : RISCVSImmLeafOp<8> {
----------------
topperc wrote:

```suggestion
def simm8_unsigned : RISCVOp, ImmLeaf<XLenVT, "return isInt<" # bitsNum # ">(Imm);"> {
```

so we don't create dead code in RISCVAsmParser.cpp

https://github.com/llvm/llvm-project/pull/162668