[llvm] [X86][ISel] Improve VPTERNLOG matching for negated logic trees (PR #164863)

[Simon Pilgrim via llvm-commits]

================
@@ -4740,13 +4737,47 @@ bool X86DAGToDAGISel::tryVPTERNLOG(SDNode *N) {
     return SDValue();
   };
 
-  SDValue A, FoldableOp;
-  if ((FoldableOp = getFoldableLogicOp(N1))) {
-    A = N0;
-  } else if ((FoldableOp = getFoldableLogicOp(N0))) {
-    A = N1;
-  } else
-    return false;
+  SDValue N0, N1, A, FoldableOp;
+
+  // Identify and (optionally) peel an outer NOT that wraps a pure logic tree
+  auto tryPeelOuterNotWrappingLogic = [&](SDNode *Op) {
+    if (Op->getOpcode() == ISD::XOR && Op->hasOneUse() &&
+        ISD::isBuildVectorAllOnes(Op->getOperand(1).getNode())) {
+      SDValue InnerOp = Op->getOperand(0);
+
+      if (!getFoldableLogicOp(InnerOp))
+        return SDValue();
----------------
RKSimon wrote:

@yichi170 Should this be:
```
SDValue InnerOp = getFoldableLogicOp(Op->getOperand(0));
if (!InnerOp)
  return SDValue();
```
getFoldableLogicOp might peek through a bitcast so the original InnerOp might not be a logic binop

https://github.com/llvm/llvm-project/pull/164863