[llvm] [AArch64][GlobalISel] Improve lowering of vector fp16 fpext (PR #165554)

[Ryan Cowan via llvm-commits]

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@@ -825,6 +825,15 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .legalFor(
           {{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}})
       .libcallFor({{s128, s64}, {s128, s32}, {s128, s16}})
+      .moreElementsToNextPow2(0)
+      .lowerIf([](const LegalityQuery &Q) {
+        LLT DstTy = Q.Types[0];
+        LLT SrcTy = Q.Types[1];
+        return SrcTy.isVector() && DstTy.isVector() &&
+               SrcTy.getNumElements() > 2 &&
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HolyMolyCowMan wrote:

When there are only two elements it's legalized to 4, which is then converted to fp32 with an `fcvtn`. These values are then unmerged and each converted separately.

We can actually just go straight from fp16 -> fp64 in a single `fcvt` so it makes sense to scalarize when there are two elements.

https://github.com/llvm/llvm-project/pull/165554