[llvm] [AArch64][GlobalISel] Improve lowering of vector fp16 fpext (PR #165554)

[David Green via llvm-commits]

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@@ -4852,6 +4852,7 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
     return lowerMemcpyInline(MI);
   case G_ZEXT:
   case G_SEXT:
+  case G_FPEXT:
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davemgreen wrote:

My understanding is that providing that the larger/mid float type can represent all the values of the smaller type there is no rounding for extends. As we add more float LLT types it will likely need to be more specific with types though, so perhaps it makes sense to refactor it a little.

https://github.com/llvm/llvm-project/pull/165554