[llvm] [Xtensa] Fix S32C1I instruction encoding and copyPhysReg. (PR #165174)

[Andrei Safronov via llvm-commits]

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@@ -114,14 +114,30 @@ void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                   const DebugLoc &DL, Register DestReg,
                                   Register SrcReg, bool KillSrc,
                                   bool RenamableDest, bool RenamableSrc) const {
-  // The MOV instruction is not present in core ISA,
-  // so use OR instruction.
-  if (Xtensa::ARRegClass.contains(DestReg, SrcReg))
+  unsigned Opcode;
+
+  // when we are copying a phys reg we want the bits for fp
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andreisfr wrote:

I changed the comment.

https://github.com/llvm/llvm-project/pull/165174