[llvm] [AArch64] Optimize extending loads of small vectors (PR #163064)

[Guy David via llvm-commits]

guy-david wrote:

> 4 x i8 is custom lowered. Could we do the same thing here, or does that not work as well?

The DAGCombiner creates [zs]extload only for legal types, so I opted to do:
```
// Marked as Legal so the DAGCombiner will fold [zs]ext loads. These are
// later decomposed into scalar loads in `performSmallVectorLoadExtCombine`.
setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, MVT::v2i8, Legal);
setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i8, Legal);
...
```

I'm not sure if that's the best solution, however. I had to battle with legalization in a few other areas, but was able to keep the change inside the AArch64 backend.

https://github.com/llvm/llvm-project/pull/163064