[llvm] [AArch64] xor -1 can be mvn, so make it free (PR #166014)

[via llvm-commits]

https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/166014

>From 5ca415338c87dab4f80a961e4d257616f60f603d Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 1 Nov 2025 14:52:43 -0400
Subject: [PATCH] [AArch64] xor -1 can be mvn, so make it free

---
 .../lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index fede586cf35bc..e4a6a1ae8cfb4 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -443,6 +443,10 @@ InstructionCost AArch64TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
   case Instruction::Store:
     ImmIdx = 0;
     break;
+  case Instruction::Xor:
+    if (Imm.isAllOnes())
+      return TTI::TCC_Free; // xor a, -1 can be folded to MVN
+  [[fallthrough]];
   case Instruction::Add:
   case Instruction::Sub:
   case Instruction::Mul:
@@ -450,9 +454,7 @@ InstructionCost AArch64TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
   case Instruction::SDiv:
   case Instruction::URem:
   case Instruction::SRem:
-  case Instruction::And:
   case Instruction::Or:
-  case Instruction::Xor:
   case Instruction::ICmp:
     ImmIdx = 1;
     break;
@@ -475,6 +477,11 @@ InstructionCost AArch64TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
   case Instruction::Ret:
   case Instruction::Load:
     break;
+  case Instruction::And:
+    if (Imm == 255 || Imm == 65535)
+      return TTI::TCC_Free;
+    ImmIdx = 1;
+    break;
   }
 
   if (Idx == ImmIdx) {