[llvm] [AArch64] xor -1 can be mvn, so make it free (PR #166014)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: AZero13 (AZero13)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/166014.diff


1 Files Affected:

- (modified) llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp (+4-1) 


``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index fede586cf35bc..bd25a81f9025a 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -443,6 +443,10 @@ InstructionCost AArch64TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
   case Instruction::Store:
     ImmIdx = 0;
     break;
+  case Instruction::Xor:
+    if (Idx == 1 && (BitSize == 32 || BitSize == 64) && Imm.isAllOnes())
+      return TTI::TCC_Free; // xor a, -1 can be folded to MVN
+  [[fallthrough]];
   case Instruction::Add:
   case Instruction::Sub:
   case Instruction::Mul:
@@ -452,7 +456,6 @@ InstructionCost AArch64TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
   case Instruction::SRem:
   case Instruction::And:
   case Instruction::Or:
-  case Instruction::Xor:
   case Instruction::ICmp:
     ImmIdx = 1;
     break;

``````````

</details>


https://github.com/llvm/llvm-project/pull/166014