[llvm] [AArch64][GlobalISel] SIMD fpcvt codegen for rounding nodes (PR #165546)

[Matt Arsenault via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+;  CHECK-GI: warning: Instruction selection used fallback path for lround_i32_f16_simd
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lround_i64_f16_simd
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lround_i32_f64_simd
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lround_i32_f32_simd
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for llround_i64_f16_simd
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lround_i32_f16_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lround_i64_f16_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lround_i64_f32_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lround_i32_f64_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lround_i32_f32_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lround_i64_f64_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for llround_i64_f16_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for llround_i64_f32_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for llround_i64_f64_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_i32_f16_simd
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_i32_f64_simd
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_i32_f32_simd
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_i32_f16_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_i64_f16_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_i64_f32_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_i32_f64_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_i32_f32_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_i64_f64_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for llrint_i64_f16_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for llrint_i64_f32_simd_exp
+;  CHECK-GI-NEXT: warning: Instruction selection used fallback path for llrint_i64_f64_simd_exp
+
+;
+; (L/LL)Round
+;
+
+define float @lround_i32_f16_simd(half %x)  {
+; CHECK-LABEL: lround_i32_f16_simd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtas s0, h0
+; CHECK-NEXT:    ret
+  %val = call i32 @llvm.lround.i32.f16(half %x)
+  %sum = bitcast i32 %val to float
+  ret float %sum
+}
+
+define double @lround_i64_f16_simd(half %x)  {
+; CHECK-LABEL: lround_i64_f16_simd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtas d0, h0
+; CHECK-NEXT:    ret
+  %val = call i64 @llvm.lround.i64.f16(half %x)
+  %bc  = bitcast i64 %val to double
+  ret double %bc
+}
+
+define double @lround_i64_f32_simd(float %x)  {
+; CHECK-LABEL: lround_i64_f32_simd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtas d0, s0
+; CHECK-NEXT:    ret
+  %val = call i64 @llvm.lround.i64.f32(float %x)
+  %bc  = bitcast i64 %val to double
+  ret double %bc
+}
+
+define float @lround_i32_f64_simd(double %x)  {
+; CHECK-LABEL: lround_i32_f64_simd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtas s0, d0
+; CHECK-NEXT:    ret
+  %val = call i32 @llvm.lround.i32.f64(double %x)
+  %bc  = bitcast i32 %val to float
+  ret float %bc
+}
+
+define float @lround_i32_f32_simd(float %x)  {
+; CHECK-LABEL: lround_i32_f32_simd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtas s0, s0
+; CHECK-NEXT:    ret
+  %val = call i32 @llvm.lround.i32.f32(float %x)
+  %bc  = bitcast i32 %val to float
+  ret float %bc
+}
+
+define double @lround_i64_f64_simd(double %x)  {
+; CHECK-LABEL: lround_i64_f64_simd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtas d0, d0
+; CHECK-NEXT:    ret
+  %val = call i64 @llvm.lround.i64.f64(double %x)
+  %bc  = bitcast i64 %val to double
+  ret double %bc
+}
+
+define double @llround_i64_f16_simd(half %x)  {
+; CHECK-LABEL: llround_i64_f16_simd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtas d0, h0
+; CHECK-NEXT:    ret
+  %val = call i64 @llvm.llround.i64.f16(half %x)
+  %sum = bitcast i64 %val to double
+  ret double %sum
+}
+
+define double @llround_i64_f32_simd(float %x)  {
+; CHECK-LABEL: llround_i64_f32_simd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtas d0, s0
+; CHECK-NEXT:    ret
+  %val = call i64 @llvm.llround.i64.f32(float %x)
+  %bc  = bitcast i64 %val to double
+  ret double %bc
+}
+
+define double @llround_i64_f64_simd(double %x)  {
+; CHECK-LABEL: llround_i64_f64_simd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtas d0, d0
+; CHECK-NEXT:    ret
+  %val = call i64 @llvm.llround.i64.f64(double %x)
+  %bc  = bitcast i64 %val to double
+  ret double %bc
+}
+
+
+;
+; (L/LL)Round experimental
+;
+
+define float @lround_i32_f16_simd_exp(half %x)  {
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arsenm wrote:

I don't think the strictfp and non-strictfp cases should coexist in the same test file 

https://github.com/llvm/llvm-project/pull/165546