[llvm] [LV] Update LoopVectorizationPlanner::emitInvalidCostRemarks to handle reduction plans (PR #165913)

[Florian Hahn via llvm-commits]

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@@ -0,0 +1,159 @@
+; RUN: opt < %s -passes=loop-vectorize -S -pass-remarks=loop-vectorize 2>%t
+; RUN: cat %t | FileCheck --check-prefix=CHECK-REMARKS %s
+
+; CHECK-REMARKS: remark: repro.f90:9:5: vectorized loop (vectorization width: vscale x 2, interleaved count: 2)
+
+; ModuleID = 'FIRModule'
+source_filename = "FIRModule"
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "aarch64-unknown-linux-gnu"
+
+; Function Attrs: nofree norecurse nosync nounwind memory(argmem: readwrite) vscale_range(1,16)
+define void @repro_(ptr noalias readonly captures(none) %0, ptr noalias readonly captures(none) %1, ptr noalias captures(none) %2) local_unnamed_addr #0 !dbg !6 {
+    #dbg_declare(ptr %0, !14, !DIExpression(), !15)
+    #dbg_declare(ptr %2, !16, !DIExpression(), !15)
+    #dbg_declare(ptr %1, !17, !DIExpression(), !15)
+  %4 = load i32, ptr %0, align 4, !dbg !18, !tbaa !19
+  %5 = icmp sgt i32 %4, 0, !dbg !18
+  br i1 %5, label %.preheader.preheader, label %._crit_edge, !dbg !18
+
+.preheader.preheader:                             ; preds = %3
+  %6 = zext nneg i32 %4 to i64, !dbg !18
+  %.pre = load double, ptr %2, align 8, !dbg !25, !tbaa !26
+  %.pre5 = load double, ptr %1, align 8, !dbg !25, !tbaa !28
+  %.phi.trans.insert = getelementptr i8, ptr %2, i64 8
+  %.pre6 = load double, ptr %.phi.trans.insert, align 8, !dbg !25, !tbaa !26
+  %.phi.trans.insert7 = getelementptr i8, ptr %1, i64 8
+  %.pre8 = load double, ptr %.phi.trans.insert7, align 8, !dbg !25, !tbaa !28
+  %.phi.trans.insert9 = getelementptr i8, ptr %2, i64 16
+  %.pre10 = load double, ptr %.phi.trans.insert9, align 8, !dbg !25, !tbaa !26
+  %.phi.trans.insert11 = getelementptr i8, ptr %1, i64 16
+  %.pre12 = load double, ptr %.phi.trans.insert11, align 8, !dbg !25, !tbaa !28
+  %.phi.trans.insert13 = getelementptr i8, ptr %2, i64 24
+  %.pre14 = load double, ptr %.phi.trans.insert13, align 8, !dbg !25, !tbaa !26
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fhahn wrote:

I think most of the IR here is not needed, please could you try to reduce the input to the minimum IR needed? (llvm-reduce may help)

https://github.com/llvm/llvm-project/pull/165913