[llvm] [AArch64][GlobalISel] Improve lowering of vector fp16 fpext (PR #165554)

[Matt Arsenault via llvm-commits]

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@@ -4852,6 +4852,7 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
     return lowerMemcpyInline(MI);
   case G_ZEXT:
   case G_SEXT:
+  case G_FPEXT:
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arsenm wrote:

It's not doing trivial top bit replication. This is introducing double rounding which you can't just do 

https://github.com/llvm/llvm-project/pull/165554