[llvm] [AMDGPU] Support true16 spill restore with sram-ecc (PR #165320)

[Matt Arsenault via llvm-commits]

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@@ -1823,6 +1823,16 @@ void SIRegisterInfo::buildSpillLoadStore(
       }
     }
 
+    Register FinalValueReg = ValueReg;
+    if (LoadStoreOp == AMDGPU::SCRATCH_LOAD_USHORT_SADDR) {
+      // If we are loading 16-bit value with SRAMECC endabled we need a temp
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arsenm wrote:

Isn't this also an issue for the 8-bit cases? 

https://github.com/llvm/llvm-project/pull/165320