[llvm] AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (PR #141068)

[via llvm-commits]

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@@ -18452,6 +18462,22 @@ SITargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
   case AtomicRMWInst::Add:
     // PCIe supports add and xchg for system atomics.
     return atomicSupportedIfLegalIntType(RMW);
+  case AtomicRMWInst::USubCond:
+    if (Subtarget->hasCondSubInsts()) {
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anjenner wrote:

Fixed in https://github.com/llvm/llvm-project/pull/141068/commits/c2e8ead5ff9586c24830449cd59998882cc3e35e .

https://github.com/llvm/llvm-project/pull/141068