[llvm] [AArch64][GlobalISel] Improve lowering of vector fp16 fpext (PR #165554)

[Ryan Cowan via llvm-commits]

================
@@ -825,6 +825,15 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .legalFor(
           {{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}})
       .libcallFor({{s128, s64}, {s128, s32}, {s128, s16}})
+      .moreElementsToNextPow2(0)
+      .lowerIf([](const LegalityQuery &Q) {
+        LLT DstTy = Q.Types[0];
+        LLT SrcTy = Q.Types[1];
+        return SrcTy.isVector() && DstTy.isVector() &&
+               SrcTy.getNumElements() > 2 &&
----------------
HolyMolyCowMan wrote:

It lowers to a suboptimal sequence of instructions when the number of elements is 2 if we use the existing lowering.

https://github.com/llvm/llvm-project/pull/165554