[llvm] [AArch64] Update zero latency instructions in Neoverse scheduling tables (PR #165690)
Simon Wallis via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 30 04:30:10 PDT 2025
https://github.com/simonwallis2 updated https://github.com/llvm/llvm-project/pull/165690
>From 90fdc605033f2142f647d4aa2273210f52393d2c Mon Sep 17 00:00:00 2001
From: Simon Wallis <simon.wallis2 at arm.com>
Date: Thu, 30 Oct 2025 10:43:12 +0000
Subject: [PATCH 1/2] [AArch64] Update zero latency instructions in scheduling
tables for Neoverse cores
NeoverseZeroMove was introduced for Neoverse-V2 and was added to V3 and V3AE.
Use NeoverseZeroMove for Neoverse-V1, N2, N3 in the same way, including these instructions:
MOV Xd|Wd, #0|XZR|WZR
For all Neoverse targets, the following instructions are also decoded as not utilizing the scheduling and execution resources of the machine:
MOV Wd,Wn
MOV Xd,Xn
For Neoverse-N3 only, these instructions also have zero latency
FMOV Dd, Dn
FMOV Sd, Sn
Change-Id: I1a5f86e049798582d33d96ba99389e4b2ffb210e
---
.../Target/AArch64/AArch64SchedNeoverseN2.td | 30 ++++++++++++-
.../Target/AArch64/AArch64SchedNeoverseN3.td | 26 ++++++++++--
.../Target/AArch64/AArch64SchedNeoverseV1.td | 22 +++++++++-
.../Target/AArch64/AArch64SchedNeoverseV2.td | 5 ++-
.../Target/AArch64/AArch64SchedNeoverseV3.td | 5 ++-
.../AArch64/AArch64SchedNeoverseV3AE.td | 5 ++-
.../AArch64/Neoverse/N2-basic-instructions.s | 22 +++++-----
.../AArch64/Neoverse/N3-basic-instructions.s | 30 ++++++-------
.../AArch64/Neoverse/V1-basic-instructions.s | 22 +++++-----
.../AArch64/Neoverse/V1-zero-dependency.s | 42 +++++++++----------
.../AArch64/Neoverse/V2-basic-instructions.s | 10 ++---
.../AArch64/Neoverse/V2-zero-lat-movs.s | 24 +++++------
.../AArch64/Neoverse/V3-basic-instructions.s | 10 ++---
.../AArch64/Neoverse/V3-zero-lat-movs.s | 24 +++++------
.../Neoverse/V3AE-basic-instructions.s | 10 ++---
.../AArch64/Neoverse/V3AE-zero-lat-movs.s | 24 +++++------
16 files changed, 192 insertions(+), 119 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
index 50f10114989d0..d1ce5a13d0510 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
@@ -72,6 +72,13 @@ def : WriteRes<WriteLDHi, []> { let Latency = 4; }
// Define customized scheduler read/write types specific to the Neoverse N2.
//===----------------------------------------------------------------------===//
+
+// Define generic 0 micro-op types
+def N2Write_0c : SchedWriteRes<[]> {
+ let Latency = 0;
+ let NumMicroOps = 0;
+}
+
// Define generic 1 micro-op types
def N2Write_1c_1B : SchedWriteRes<[N2UnitB]> { let Latency = 1; }
@@ -645,6 +652,21 @@ def N2Write_11c_9L01_9S_9V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
let NumMicroOps = 27;
}
+//===----------------------------------------------------------------------===//
+// Define predicate-controlled types
+
+def N2Write_0or1c_1I : SchedWriteVariant<[
+ SchedVar<NeoverseZeroMove, [N2Write_0c]>,
+ SchedVar<NoSchedPred, [N2Write_1c_1I]>]>;
+
+def N2Write_0or2c_1V : SchedWriteVariant<[
+ SchedVar<NeoverseZeroMove, [N2Write_0c]>,
+ SchedVar<NoSchedPred, [N2Write_2c_1V]>]>;
+
+def N2Write_0or3c_1M0 : SchedWriteVariant<[
+ SchedVar<NeoverseZeroMove, [N2Write_0c]>,
+ SchedVar<NoSchedPred, [N2Write_3c_1M0]>]>;
+
//===----------------------------------------------------------------------===//
// Define types for arithmetic and logical ops with short shifts
def N2Write_Arith : SchedWriteVariant<[
@@ -680,6 +702,7 @@ def : InstRW<[N2Write_1c_1B_1S], (instrs BL, BLR)>;
// ALU, basic
// ALU, basic, flagset
def : SchedAlias<WriteI, N2Write_1c_1I>;
+def : InstRW<[N2Write_0or1c_1I], (instregex "^MOVZ[WX]i$")>;
// ALU, extend and shift
def : SchedAlias<WriteIEReg, N2Write_2c_1M>;
@@ -691,7 +714,8 @@ def : SchedAlias<WriteISReg, N2Write_Arith>;
// Logical, shift, no flagset
def : InstRW<[N2Write_1c_1I],
- (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>;
+ (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>;
+def : InstRW<[N2Write_0or1c_1I], (instregex "^ORR[WX]rs$")>;
// Logical, shift, flagset
def : InstRW<[N2Write_Logical], (instregex "^(AND|BIC)S[WX]rs$")>;
@@ -882,7 +906,7 @@ def : SchedAlias<WriteFImm, N2Write_2c_1V>;
def : InstRW<[N2Write_2c_1V], (instrs FMOVHr, FMOVSr, FMOVDr)>;
// FP transfer, from gen to low half of vec reg
-def : InstRW<[N2Write_3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr,
+def : InstRW<[N2Write_0or3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr,
FMOVHWr, FMOVHXr, FMOVSWr, FMOVDXr)>;
// FP transfer, from gen to high half of vec reg
@@ -1225,6 +1249,8 @@ def : InstRW<[N2Write_3c_1V0], (instrs BFCVT)>;
// ASIMD unzip/zip
// Handled by SchedAlias<WriteV[dq], ...>
+def : InstRW<[N2Write_0or2c_1V], (instrs MOVID, MOVIv2d_ns)>;
+
// ASIMD duplicate, gen reg
def : InstRW<[N2Write_3c_1M0], (instregex "^DUPv.+gpr")>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
index 411b372a3f533..32d48ca66ee2d 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
@@ -553,6 +553,22 @@ def N3Write_16c_16V0 : SchedWriteRes<[N3UnitV0, N3UnitV0, N3UnitV0, N3UnitV0,
let NumMicroOps = 16;
}
+
+//===----------------------------------------------------------------------===//
+// Define predicate-controlled types
+
+def N3Write_0or1c_1I : SchedWriteVariant<[
+ SchedVar<NeoverseZeroMove, [N3Write_0c]>,
+ SchedVar<NoSchedPred, [N3Write_1c_1I]>]>;
+
+def N3Write_0or2c_1V : SchedWriteVariant<[
+ SchedVar<NeoverseZeroMove, [N3Write_0c]>,
+ SchedVar<NoSchedPred, [N3Write_2c_1V]>]>;
+
+def N3Write_0or3c_1M0 : SchedWriteVariant<[
+ SchedVar<NeoverseZeroMove, [N3Write_0c]>,
+ SchedVar<NoSchedPred, [N3Write_3c_1M0]>]>;
+
// Miscellaneous
// -----------------------------------------------------------------------------
@@ -581,6 +597,7 @@ def : InstRW<[N3Write_1c_1B_1S], (instrs BL, BLR)>;
// Conditional compare
// Conditional select
def : SchedAlias<WriteI, N3Write_1c_1I>;
+def : InstRW<[N3Write_0or1c_1I], (instregex "^MOVZ[WX]i$")>;
// ALU, extend and shift
def : SchedAlias<WriteIEReg, N3Write_2c_1M>;
@@ -610,7 +627,8 @@ def : InstRW<[N3Write_1c_1I], (instrs GMI, SUBP, SUBPS)>;
// Logical, shift, no flagset
def : InstRW<[N3Write_1c_1I],
- (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>;
+ (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>;
+def : InstRW<[N3Write_0or1c_1I], (instregex "^ORR[WX]rs$")>;
// Logical, shift, flagset
def : InstRW<[N3Write_2c_1M], (instregex "^(AND|BIC)S[WX]rs$")>;
@@ -855,10 +873,11 @@ def : SchedAlias<WriteFCvt, N3Write_3c_1V0>;
def : SchedAlias<WriteFImm, N3Write_2c_1V>;
// FP move, register
-def : InstRW<[N3Write_2c_1V], (instrs FMOVHr, FMOVSr, FMOVDr)>;
+def : InstRW<[N3Write_2c_1V], (instrs FMOVHr)>;
+def : InstRW<[N3Write_0c], (instrs FMOVSr, FMOVDr)>;
// FP transfer, from gen to low half of vec reg
-def : InstRW<[N3Write_3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>;
+def : InstRW<[N3Write_0or3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>;
// FP transfer, from gen to high half of vec reg
def : InstRW<[N3Write_5c_1M0_1V], (instrs FMOVXDHighr)>;
@@ -1186,6 +1205,7 @@ def : InstRW<[N3Write_3c_1V0], (instrs BFCVT)>;
// ASIMD transpose
// ASIMD unzip/zip
// Covered by WriteV[dq]
+def : InstRW<[N3Write_0or2c_1V], (instrs MOVID, MOVIv2d_ns)>;
// ASIMD duplicate, gen reg
def : InstRW<[N3Write_3c_1M0], (instregex "^DUPv.+gpr")>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
index 3cbfc59423c9a..8d33ca22616c2 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
@@ -472,6 +472,21 @@ def V1Write_11c_9L01_9S_9V : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01,
V1UnitV, V1UnitV, V1UnitV,
V1UnitV, V1UnitV, V1UnitV]>;
+//===----------------------------------------------------------------------===//
+// Define predicate-controlled types
+
+def V1Write_0or1c_1I : SchedWriteVariant<[
+ SchedVar<NeoverseZeroMove, [V1Write_0c_0Z]>,
+ SchedVar<NoSchedPred, [V1Write_1c_1I]>]>;
+
+def V1Write_0or2c_1V : SchedWriteVariant<[
+ SchedVar<NeoverseZeroMove, [V1Write_0c_0Z]>,
+ SchedVar<NoSchedPred, [V1Write_2c_1V]>]>;
+
+def V1Write_0or3c_1M0 : SchedWriteVariant<[
+ SchedVar<NeoverseZeroMove, [V1Write_0c_0Z]>,
+ SchedVar<NoSchedPred, [V1Write_3c_1M0]>]>;
+
//===----------------------------------------------------------------------===//
// Define forwarded types
@@ -603,6 +618,7 @@ def : InstRW<[V1Write_1c_1I_1Flg],
"^(ADC|SBC)S[WX]r$",
"^ANDS[WX]ri$",
"^(AND|BIC)S[WX]rr$")>;
+def : InstRW<[V1Write_0or1c_1I], (instregex "^MOVZ[WX]i$")>;
// ALU, extend and shift
def : SchedAlias<WriteIEReg, V1Write_2c_1M>;
@@ -623,7 +639,8 @@ def : InstRW<[V1WriteISRegS],
(instregex "^(ADD|SUB)S(([WX]r[sx])|Xrx64)$")>;
// Logical, shift, no flagset
-def : InstRW<[V1Write_1c_1I], (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>;
+def : InstRW<[V1Write_1c_1I], (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>;
+def : InstRW<[V1Write_0or1c_1I], (instregex "^ORR[WX]rs$")>;
// Logical, shift, flagset
def : InstRW<[V1Write_2c_1M_1Flg], (instregex "^(AND|BIC)S[WX]rs$")>;
@@ -805,7 +822,7 @@ def : SchedAlias<WriteFImm, V1Write_2c_1V>;
def : InstRW<[V1Write_2c_1V], (instrs FMOVHr, FMOVSr, FMOVDr)>;
// FP transfer, from gen to low half of vec reg
-def : InstRW<[V1Write_3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>;
+def : InstRW<[V1Write_0or3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>;
// FP transfer, from gen to high half of vec reg
def : InstRW<[V1Write_5c_1M0_1V], (instrs FMOVXDHighr)>;
@@ -1122,6 +1139,7 @@ def : InstRW<[V1Write_3c_1V02], (instrs BFCVT)>;
// ASIMD transpose
// ASIMD unzip/zip
// Covered by "SchedAlias (WriteV[dq]...)" above
+def : InstRW<[V1Write_0or2c_1V], (instrs MOVID, MOVIv2d_ns)>;
// ASIMD duplicate, gen reg
def : InstRW<[V1Write_3c_1M0],
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index 2387f176f3051..1ef087f07022d 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -94,7 +94,10 @@ def : WriteRes<WriteLDHi, []> { let Latency = 4; }
//===----------------------------------------------------------------------===//
// Define generic 0 micro-op types
-def V2Write_0c : SchedWriteRes<[]> { let Latency = 0; }
+def V2Write_0c : SchedWriteRes<[]> {
+ let Latency = 0;
+ let NumMicroOps = 0;
+}
// Define generic 1 micro-op types
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td
index e23576a20d277..3dd2988088f0b 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td
@@ -94,7 +94,10 @@ def : WriteRes<WriteLDHi, []> { let Latency = 4; }
//===----------------------------------------------------------------------===//
// Define generic 0 micro-op types
-def V3Write_0c : SchedWriteRes<[]> { let Latency = 0; }
+def V3Write_0c : SchedWriteRes<[]> {
+ let Latency = 0;
+ let NumMicroOps = 0;
+}
// Define generic 1 micro-op types
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td
index 0f1ec669a4e5e..19b56260387e1 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td
@@ -89,7 +89,10 @@ def : WriteRes<WriteLDHi, []> { let Latency = 4; }
//===----------------------------------------------------------------------===//
// Define generic 0 micro-op types
-def V3AEWrite_0c : SchedWriteRes<[]> { let Latency = 0; }
+def V3AEWrite_0c : SchedWriteRes<[]> {
+ let Latency = 0;
+ let NumMicroOps = 0;
+}
// Define generic 1 micro-op types
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
index cf1cf0e98c801..d3343ab055887 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
@@ -2508,14 +2508,14 @@ drps
# CHECK-NEXT: 1 2 0.50 bics x3, xzr, x3, lsl #1
# CHECK-NEXT: 1 2 0.50 tst w3, w7, lsl #31
# CHECK-NEXT: 1 2 0.50 tst x2, x20, asr #2
-# CHECK-NEXT: 1 1 0.25 mov x3, x6
-# CHECK-NEXT: 1 1 0.25 mov x3, xzr
-# CHECK-NEXT: 1 1 0.25 mov wzr, w2
-# CHECK-NEXT: 1 1 0.25 mov w3, w5
+# CHECK-NEXT: 0 0 0.00 mov x3, x6
+# CHECK-NEXT: 0 0 0.00 mov x3, xzr
+# CHECK-NEXT: 0 0 0.00 mov wzr, w2
+# CHECK-NEXT: 0 0 0.00 mov w3, w5
# CHECK-NEXT: 1 1 0.25 movz w2, #0, lsl #16
# CHECK-NEXT: 1 1 0.25 mov w2, #-1235
# CHECK-NEXT: 1 1 0.25 mov x2, #5299989643264
-# CHECK-NEXT: 1 1 0.25 mov x2, #0
+# CHECK-NEXT: 0 0 0.00 mov x2, #0
# CHECK-NEXT: 1 1 0.25 movk w3, #0
# CHECK-NEXT: 1 1 0.25 movz x4, #0, lsl #16
# CHECK-NEXT: 1 1 0.25 movk w5, #0, lsl #16
@@ -2557,7 +2557,7 @@ drps
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8]
-# CHECK-NEXT: 11.00 11.00 33.00 33.00 87.33 151.33 151.33 517.00 251.00 162.50 162.50 215.50 85.50
+# CHECK-NEXT: 11.00 11.00 33.00 33.00 87.33 151.33 151.33 515.75 249.75 161.25 161.25 215.50 85.50
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] Instructions:
@@ -3692,14 +3692,14 @@ drps
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - bics x3, xzr, x3, lsl #1
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - tst w3, w7, lsl #31
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - tst x2, x20, asr #2
-# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x3, x6
-# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x3, xzr
-# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov wzr, w2
-# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov w3, w5
+# CHECK-NEXT: - - - - - - - - - - - - - mov x3, x6
+# CHECK-NEXT: - - - - - - - - - - - - - mov x3, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - mov wzr, w2
+# CHECK-NEXT: - - - - - - - - - - - - - mov w3, w5
# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movz w2, #0, lsl #16
# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov w2, #-1235
# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x2, #5299989643264
-# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x2, #0
+# CHECK-NEXT: - - - - - - - - - - - - - mov x2, #0
# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movk w3, #0
# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movz x4, #0, lsl #16
# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movk w5, #0, lsl #16
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s
index b9758280e2491..f7311b5e41b2e 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s
@@ -1888,7 +1888,7 @@ drps
# CHECK-NEXT: 1 2 0.50 fccmpe d31, d5, #7, ne
# CHECK-NEXT: 1 2 0.50 fcsel s3, s20, s9, pl
# CHECK-NEXT: 1 2 0.50 fcsel d9, d10, d11, mi
-# CHECK-NEXT: 1 2 0.50 fmov s0, s1
+# CHECK-NEXT: 0 0 0.00 fmov s0, s1
# CHECK-NEXT: 1 2 0.50 fabs s2, s3
# CHECK-NEXT: 1 2 0.50 fneg s4, s5
# CHECK-NEXT: 1 7 1.00 fsqrt s6, s7
@@ -1901,7 +1901,7 @@ drps
# CHECK-NEXT: 1 3 1.00 frinta s20, s21
# CHECK-NEXT: 1 3 1.00 frintx s22, s23
# CHECK-NEXT: 1 3 1.00 frinti s24, s25
-# CHECK-NEXT: 1 2 0.50 fmov d0, d1
+# CHECK-NEXT: 0 0 0.00 fmov d0, d1
# CHECK-NEXT: 1 2 0.50 fabs d2, d3
# CHECK-NEXT: 1 2 0.50 fneg d4, d5
# CHECK-NEXT: 1 12 1.00 fsqrt d6, d7
@@ -2508,14 +2508,14 @@ drps
# CHECK-NEXT: 1 2 0.50 bics x3, xzr, x3, lsl #1
# CHECK-NEXT: 1 2 0.50 tst w3, w7, lsl #31
# CHECK-NEXT: 1 2 0.50 tst x2, x20, asr #2
-# CHECK-NEXT: 1 1 0.25 mov x3, x6
-# CHECK-NEXT: 1 1 0.25 mov x3, xzr
-# CHECK-NEXT: 1 1 0.25 mov wzr, w2
-# CHECK-NEXT: 1 1 0.25 mov w3, w5
+# CHECK-NEXT: 0 0 0.00 mov x3, x6
+# CHECK-NEXT: 0 0 0.00 mov x3, xzr
+# CHECK-NEXT: 0 0 0.00 mov wzr, w2
+# CHECK-NEXT: 0 0 0.00 mov w3, w5
# CHECK-NEXT: 1 1 0.25 movz w2, #0, lsl #16
# CHECK-NEXT: 1 1 0.25 mov w2, #-1235
# CHECK-NEXT: 1 1 0.25 mov x2, #5299989643264
-# CHECK-NEXT: 1 1 0.25 mov x2, #0
+# CHECK-NEXT: 0 0 0.00 mov x2, #0
# CHECK-NEXT: 1 1 0.25 movk w3, #0
# CHECK-NEXT: 1 1 0.25 movz x4, #0, lsl #16
# CHECK-NEXT: 1 1 0.25 movk w5, #0, lsl #16
@@ -2557,7 +2557,7 @@ drps
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8]
-# CHECK-NEXT: 11.00 11.00 33.00 33.00 99.33 163.33 163.33 357.75 212.75 156.25 156.25 184.50 64.50
+# CHECK-NEXT: 11.00 11.00 33.00 33.00 99.33 163.33 163.33 356.50 211.50 155.00 155.00 183.50 63.50
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] Instructions:
@@ -3072,7 +3072,7 @@ drps
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fccmpe d31, d5, #7, ne
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fcsel s3, s20, s9, pl
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fcsel d9, d10, d11, mi
-# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fmov s0, s1
+# CHECK-NEXT: - - - - - - - - - - - - - fmov s0, s1
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fabs s2, s3
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fneg s4, s5
# CHECK-NEXT: - - - - - - - - - - - 1.00 - fsqrt s6, s7
@@ -3085,7 +3085,7 @@ drps
# CHECK-NEXT: - - - - - - - - - - - 1.00 - frinta s20, s21
# CHECK-NEXT: - - - - - - - - - - - 1.00 - frintx s22, s23
# CHECK-NEXT: - - - - - - - - - - - 1.00 - frinti s24, s25
-# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fmov d0, d1
+# CHECK-NEXT: - - - - - - - - - - - - - fmov d0, d1
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fabs d2, d3
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fneg d4, d5
# CHECK-NEXT: - - - - - - - - - - - 1.00 - fsqrt d6, d7
@@ -3692,14 +3692,14 @@ drps
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - bics x3, xzr, x3, lsl #1
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - tst w3, w7, lsl #31
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - tst x2, x20, asr #2
-# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x3, x6
-# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x3, xzr
-# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov wzr, w2
-# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov w3, w5
+# CHECK-NEXT: - - - - - - - - - - - - - mov x3, x6
+# CHECK-NEXT: - - - - - - - - - - - - - mov x3, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - mov wzr, w2
+# CHECK-NEXT: - - - - - - - - - - - - - mov w3, w5
# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movz w2, #0, lsl #16
# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov w2, #-1235
# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x2, #5299989643264
-# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x2, #0
+# CHECK-NEXT: - - - - - - - - - - - - - mov x2, #0
# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movk w3, #0
# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movz x4, #0, lsl #16
# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movk w5, #0, lsl #16
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s
index eddc3e565c353..f75222f27a94a 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s
@@ -2673,14 +2673,14 @@ drps
# CHECK-NEXT: 1 2 0.50 bics x3, xzr, x3, lsl #1
# CHECK-NEXT: 1 2 0.50 tst w3, w7, lsl #31
# CHECK-NEXT: 1 2 0.50 tst x2, x20, asr #2
-# CHECK-NEXT: 1 1 0.25 mov x3, x6
-# CHECK-NEXT: 1 1 0.25 mov x3, xzr
-# CHECK-NEXT: 1 1 0.25 mov wzr, w2
-# CHECK-NEXT: 1 1 0.25 mov w3, w5
+# CHECK-NEXT: 0 0 0.00 mov x3, x6
+# CHECK-NEXT: 0 0 0.00 mov x3, xzr
+# CHECK-NEXT: 0 0 0.00 mov wzr, w2
+# CHECK-NEXT: 0 0 0.00 mov w3, w5
# CHECK-NEXT: 1 1 0.25 movz w2, #0, lsl #16
# CHECK-NEXT: 1 1 0.25 mov w2, #-1235
# CHECK-NEXT: 1 1 0.25 mov x2, #5299989643264
-# CHECK-NEXT: 1 1 0.25 mov x2, #0
+# CHECK-NEXT: 0 0 0.00 mov x2, #0
# CHECK-NEXT: 1 1 0.25 movk w3, #0
# CHECK-NEXT: 1 1 0.25 movz x4, #0, lsl #16
# CHECK-NEXT: 1 1 0.25 movk w5, #0, lsl #16
@@ -2731,7 +2731,7 @@ drps
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11]
-# CHECK-NEXT: 13.00 13.00 40.50 40.50 48.00 48.00 48.00 96.67 175.17 175.17 322.50 209.50 142.00 142.00 189.00 55.50 65.50 13.00
+# CHECK-NEXT: 13.00 13.00 40.50 40.50 48.00 48.00 48.00 96.67 175.17 175.17 321.25 208.25 140.75 140.75 189.00 55.50 65.50 13.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions:
@@ -3944,14 +3944,14 @@ drps
# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - 0.50 0.50 - - - - - - bics x3, xzr, x3, lsl #1
# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - 0.50 0.50 - - - - - - tst w3, w7, lsl #31
# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - 0.50 0.50 - - - - - - tst x2, x20, asr #2
-# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - mov x3, x6
-# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - mov x3, xzr
-# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - mov wzr, w2
-# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - mov w3, w5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - mov x3, x6
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - mov x3, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - mov wzr, w2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - mov w3, w5
# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - movz w2, #0, lsl #16
# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - mov w2, #-1235
# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - mov x2, #5299989643264
-# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - mov x2, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - mov x2, #0
# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - movk w3, #0
# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - movz x4, #0, lsl #16
# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - movk w5, #0, lsl #16
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-zero-dependency.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-zero-dependency.s
index 3954cbd8c5490..7767b95ff98ea 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-zero-dependency.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-zero-dependency.s
@@ -6,13 +6,13 @@ cmp x0, #4
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 54
-# CHECK-NEXT: Total uOps: 200
+# CHECK-NEXT: Total Cycles: 37
+# CHECK-NEXT: Total uOps: 100
# CHECK: Dispatch Width: 8
-# CHECK-NEXT: uOps Per Cycle: 3.70
-# CHECK-NEXT: IPC: 3.70
-# CHECK-NEXT: Block RThroughput: 0.5
+# CHECK-NEXT: uOps Per Cycle: 2.70
+# CHECK-NEXT: IPC: 5.41
+# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -23,7 +23,7 @@ cmp x0, #4
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 0.25 mov x0, x1
+# CHECK-NEXT: 0 0 0.00 mov x0, x1
# CHECK-NEXT: 1 1 0.33 cmp x0, #4
# CHECK: Resources:
@@ -48,24 +48,24 @@ cmp x0, #4
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11]
-# CHECK-NEXT: - - - - 0.33 0.33 0.34 - - - 0.50 0.50 0.50 0.50 - - - -
+# CHECK-NEXT: - - - - 0.33 0.33 0.34 - - - 0.22 0.22 0.28 0.28 - - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions:
-# CHECK-NEXT: - - - - - - - - - - 0.49 0.49 0.01 0.01 - - - - mov x0, x1
-# CHECK-NEXT: - - - - 0.33 0.33 0.34 - - - 0.01 0.01 0.49 0.49 - - - - cmp x0, #4
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - mov x0, x1
+# CHECK-NEXT: - - - - 0.33 0.33 0.34 - - - 0.22 0.22 0.28 0.28 - - - - cmp x0, #4
# CHECK: Timeline view:
-# CHECK-NEXT: Index 012345
+# CHECK-NEXT: Index 01234
-# CHECK: [0,0] DeER . mov x0, x1
-# CHECK-NEXT: [0,1] D=eER. cmp x0, #4
-# CHECK-NEXT: [1,0] DeE-R. mov x0, x1
-# CHECK-NEXT: [1,1] D=eER. cmp x0, #4
-# CHECK-NEXT: [2,0] DeE-R. mov x0, x1
-# CHECK-NEXT: [2,1] D=eER. cmp x0, #4
-# CHECK-NEXT: [3,0] DeE-R. mov x0, x1
-# CHECK-NEXT: [3,1] D==eER cmp x0, #4
+# CHECK: [0,0] DR . mov x0, x1
+# CHECK-NEXT: [0,1] DeER. cmp x0, #4
+# CHECK-NEXT: [1,0] D--R. mov x0, x1
+# CHECK-NEXT: [1,1] DeER. cmp x0, #4
+# CHECK-NEXT: [2,0] D--R. mov x0, x1
+# CHECK-NEXT: [2,1] DeER. cmp x0, #4
+# CHECK-NEXT: [3,0] D--R. mov x0, x1
+# CHECK-NEXT: [3,1] D=eER cmp x0, #4
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -74,6 +74,6 @@ cmp x0, #4
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.0 1.0 0.8 mov x0, x1
-# CHECK-NEXT: 1. 4 2.3 0.3 0.0 cmp x0, #4
-# CHECK-NEXT: 4 1.6 0.6 0.4 <total>
+# CHECK-NEXT: 0. 4 0.0 0.0 1.5 mov x0, x1
+# CHECK-NEXT: 1. 4 1.3 1.3 0.0 cmp x0, #4
+# CHECK-NEXT: 4 0.6 0.6 0.8 <total>
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s
index 54b5f1644be48..9c987d54d2350 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s
@@ -2536,14 +2536,14 @@ drps
# CHECK-NEXT: 1 2 0.50 bics x3, xzr, x3, lsl #1
# CHECK-NEXT: 1 2 0.50 tst w3, w7, lsl #31
# CHECK-NEXT: 1 2 0.50 tst x2, x20, asr #2
-# CHECK-NEXT: 1 0 0.17 mov x3, x6
-# CHECK-NEXT: 1 0 0.17 mov x3, xzr
-# CHECK-NEXT: 1 0 0.17 mov wzr, w2
-# CHECK-NEXT: 1 0 0.17 mov w3, w5
+# CHECK-NEXT: 0 0 0.00 mov x3, x6
+# CHECK-NEXT: 0 0 0.00 mov x3, xzr
+# CHECK-NEXT: 0 0 0.00 mov wzr, w2
+# CHECK-NEXT: 0 0 0.00 mov w3, w5
# CHECK-NEXT: 1 1 0.17 movz w2, #0, lsl #16
# CHECK-NEXT: 1 1 0.17 mov w2, #-1235
# CHECK-NEXT: 1 1 0.17 mov x2, #5299989643264
-# CHECK-NEXT: 1 0 0.17 mov x2, #0
+# CHECK-NEXT: 0 0 0.00 mov x2, #0
# CHECK-NEXT: 1 1 0.17 movk w3, #0
# CHECK-NEXT: 1 1 0.17 movz x4, #0, lsl #16
# CHECK-NEXT: 1 1 0.17 movk w5, #0, lsl #16
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-zero-lat-movs.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-zero-lat-movs.s
index 3ddb525327015..1cec5897db425 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-zero-lat-movs.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-zero-lat-movs.s
@@ -23,18 +23,18 @@ mov x1, x2
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 0 0.17 mov x1, #0
-# CHECK-NEXT: 1 0 0.17 mov x1, xzr
-# CHECK-NEXT: 1 0 0.17 mov w1, #0
-# CHECK-NEXT: 1 0 0.17 mov w1, wzr
-# CHECK-NEXT: 1 0 0.17 fmov h1, wzr
-# CHECK-NEXT: 1 0 0.17 fmov h1, xzr
-# CHECK-NEXT: 1 0 0.17 fmov s1, wzr
-# CHECK-NEXT: 1 0 0.17 fmov d1, xzr
-# CHECK-NEXT: 1 0 0.17 movi d1, #0000000000000000
-# CHECK-NEXT: 1 0 0.17 movi v1.2d, #0000000000000000
-# CHECK-NEXT: 1 0 0.17 mov w1, w2
-# CHECK-NEXT: 1 0 0.17 mov x1, x2
+# CHECK-NEXT: 0 0 0.00 mov x1, #0
+# CHECK-NEXT: 0 0 0.00 mov x1, xzr
+# CHECK-NEXT: 0 0 0.00 mov w1, #0
+# CHECK-NEXT: 0 0 0.00 mov w1, wzr
+# CHECK-NEXT: 0 0 0.00 fmov h1, wzr
+# CHECK-NEXT: 0 0 0.00 fmov h1, xzr
+# CHECK-NEXT: 0 0 0.00 fmov s1, wzr
+# CHECK-NEXT: 0 0 0.00 fmov d1, xzr
+# CHECK-NEXT: 0 0 0.00 movi d1, #0000000000000000
+# CHECK-NEXT: 0 0 0.00 movi v1.2d, #0000000000000000
+# CHECK-NEXT: 0 0 0.00 mov w1, w2
+# CHECK-NEXT: 0 0 0.00 mov x1, x2
# CHECK: Resources:
# CHECK-NEXT: [0.0] - V2UnitB
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s
index 73fd95d6e4a5b..67af391e52863 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s
@@ -2536,14 +2536,14 @@ drps
# CHECK-NEXT: 1 2 0.50 bics x3, xzr, x3, lsl #1
# CHECK-NEXT: 1 2 0.50 tst w3, w7, lsl #31
# CHECK-NEXT: 1 2 0.50 tst x2, x20, asr #2
-# CHECK-NEXT: 1 0 0.10 mov x3, x6
-# CHECK-NEXT: 1 0 0.10 mov x3, xzr
-# CHECK-NEXT: 1 0 0.10 mov wzr, w2
-# CHECK-NEXT: 1 0 0.10 mov w3, w5
+# CHECK-NEXT: 0 0 0.00 mov x3, x6
+# CHECK-NEXT: 0 0 0.00 mov x3, xzr
+# CHECK-NEXT: 0 0 0.00 mov wzr, w2
+# CHECK-NEXT: 0 0 0.00 mov w3, w5
# CHECK-NEXT: 1 1 0.13 movz w2, #0, lsl #16
# CHECK-NEXT: 1 1 0.13 mov w2, #-1235
# CHECK-NEXT: 1 1 0.13 mov x2, #5299989643264
-# CHECK-NEXT: 1 0 0.10 mov x2, #0
+# CHECK-NEXT: 0 0 0.00 mov x2, #0
# CHECK-NEXT: 1 1 0.13 movk w3, #0
# CHECK-NEXT: 1 1 0.13 movz x4, #0, lsl #16
# CHECK-NEXT: 1 1 0.13 movk w5, #0, lsl #16
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-zero-lat-movs.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-zero-lat-movs.s
index 1eef230b8174e..9b4834b12a79b 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-zero-lat-movs.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-zero-lat-movs.s
@@ -23,18 +23,18 @@ mov x1, x2
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 0 0.10 mov x1, #0
-# CHECK-NEXT: 1 0 0.10 mov x1, xzr
-# CHECK-NEXT: 1 0 0.10 mov w1, #0
-# CHECK-NEXT: 1 0 0.10 mov w1, wzr
-# CHECK-NEXT: 1 0 0.10 fmov h1, wzr
-# CHECK-NEXT: 1 0 0.10 fmov h1, xzr
-# CHECK-NEXT: 1 0 0.10 fmov s1, wzr
-# CHECK-NEXT: 1 0 0.10 fmov d1, xzr
-# CHECK-NEXT: 1 0 0.10 movi d1, #0000000000000000
-# CHECK-NEXT: 1 0 0.10 movi v1.2d, #0000000000000000
-# CHECK-NEXT: 1 0 0.10 mov w1, w2
-# CHECK-NEXT: 1 0 0.10 mov x1, x2
+# CHECK-NEXT: 0 0 0.00 mov x1, #0
+# CHECK-NEXT: 0 0 0.00 mov x1, xzr
+# CHECK-NEXT: 0 0 0.00 mov w1, #0
+# CHECK-NEXT: 0 0 0.00 mov w1, wzr
+# CHECK-NEXT: 0 0 0.00 fmov h1, wzr
+# CHECK-NEXT: 0 0 0.00 fmov h1, xzr
+# CHECK-NEXT: 0 0 0.00 fmov s1, wzr
+# CHECK-NEXT: 0 0 0.00 fmov d1, xzr
+# CHECK-NEXT: 0 0 0.00 movi d1, #0000000000000000
+# CHECK-NEXT: 0 0 0.00 movi v1.2d, #0000000000000000
+# CHECK-NEXT: 0 0 0.00 mov w1, w2
+# CHECK-NEXT: 0 0 0.00 mov x1, x2
# CHECK: Resources:
# CHECK-NEXT: [0.0] - V3UnitB
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s
index 7ab2be5eaa365..5009ce1d54a86 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s
@@ -2536,14 +2536,14 @@ drps
# CHECK-NEXT: 1 2 0.50 bics x3, xzr, x3, lsl #1
# CHECK-NEXT: 1 2 0.50 tst w3, w7, lsl #31
# CHECK-NEXT: 1 2 0.50 tst x2, x20, asr #2
-# CHECK-NEXT: 1 0 0.10 mov x3, x6
-# CHECK-NEXT: 1 0 0.10 mov x3, xzr
-# CHECK-NEXT: 1 0 0.10 mov wzr, w2
-# CHECK-NEXT: 1 0 0.10 mov w3, w5
+# CHECK-NEXT: 0 0 0.00 mov x3, x6
+# CHECK-NEXT: 0 0 0.00 mov x3, xzr
+# CHECK-NEXT: 0 0 0.00 mov wzr, w2
+# CHECK-NEXT: 0 0 0.00 mov w3, w5
# CHECK-NEXT: 1 1 0.13 movz w2, #0, lsl #16
# CHECK-NEXT: 1 1 0.13 mov w2, #-1235
# CHECK-NEXT: 1 1 0.13 mov x2, #5299989643264
-# CHECK-NEXT: 1 0 0.10 mov x2, #0
+# CHECK-NEXT: 0 0 0.00 mov x2, #0
# CHECK-NEXT: 1 1 0.13 movk w3, #0
# CHECK-NEXT: 1 1 0.13 movz x4, #0, lsl #16
# CHECK-NEXT: 1 1 0.13 movk w5, #0, lsl #16
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-zero-lat-movs.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-zero-lat-movs.s
index a0840dcddcbab..783bea288b121 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-zero-lat-movs.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-zero-lat-movs.s
@@ -23,18 +23,18 @@ mov x1, x2
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 0 0.10 mov x1, #0
-# CHECK-NEXT: 1 0 0.10 mov x1, xzr
-# CHECK-NEXT: 1 0 0.10 mov w1, #0
-# CHECK-NEXT: 1 0 0.10 mov w1, wzr
-# CHECK-NEXT: 1 0 0.10 fmov h1, wzr
-# CHECK-NEXT: 1 0 0.10 fmov h1, xzr
-# CHECK-NEXT: 1 0 0.10 fmov s1, wzr
-# CHECK-NEXT: 1 0 0.10 fmov d1, xzr
-# CHECK-NEXT: 1 0 0.10 movi d1, #0000000000000000
-# CHECK-NEXT: 1 0 0.10 movi v1.2d, #0000000000000000
-# CHECK-NEXT: 1 0 0.10 mov w1, w2
-# CHECK-NEXT: 1 0 0.10 mov x1, x2
+# CHECK-NEXT: 0 0 0.00 mov x1, #0
+# CHECK-NEXT: 0 0 0.00 mov x1, xzr
+# CHECK-NEXT: 0 0 0.00 mov w1, #0
+# CHECK-NEXT: 0 0 0.00 mov w1, wzr
+# CHECK-NEXT: 0 0 0.00 fmov h1, wzr
+# CHECK-NEXT: 0 0 0.00 fmov h1, xzr
+# CHECK-NEXT: 0 0 0.00 fmov s1, wzr
+# CHECK-NEXT: 0 0 0.00 fmov d1, xzr
+# CHECK-NEXT: 0 0 0.00 movi d1, #0000000000000000
+# CHECK-NEXT: 0 0 0.00 movi v1.2d, #0000000000000000
+# CHECK-NEXT: 0 0 0.00 mov w1, w2
+# CHECK-NEXT: 0 0 0.00 mov x1, x2
# CHECK: Resources:
# CHECK-NEXT: [0.0] - V3AEUnitB
>From 695b27d6540de00f9feb943744715758607380ff Mon Sep 17 00:00:00 2001
From: Simon Wallis <simon.wallis2 at arm.com>
Date: Thu, 30 Oct 2025 11:29:34 +0000
Subject: [PATCH 2/2] [AArch64] Update zero latency instructions in scheduling
tables for Neoverse cores
NeoverseZeroMove was introduced for Neoverse-V2 and was added to V3 and V3AE.
Use NeoverseZeroMove for Neoverse-V1, N2, N3 in the same way, including these instructions:
MOV Xd|Wd, #0|XZR|WZR
For all Neoverse targets, the following instructions are also decoded as not utilizing the scheduling and execution resources of the machine:
MOV Wd,Wn
MOV Xd,Xn
For Neoverse-N3 only, these instructions also have zero latency
FMOV Dd, Dn
FMOV Sd, Sn
Change-Id: I955cfe3efc689bea305a708eb6d7259dced6fe04
---
llvm/test/CodeGen/AArch64/pr164181.ll | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/pr164181.ll b/llvm/test/CodeGen/AArch64/pr164181.ll
index 4ec63ecb2eeb4..987c92b084001 100644
--- a/llvm/test/CodeGen/AArch64/pr164181.ll
+++ b/llvm/test/CodeGen/AArch64/pr164181.ll
@@ -52,11 +52,11 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: mov x10, xzr
; CHECK-NEXT: mov w23, wzr
; CHECK-NEXT: mov w30, wzr
-; CHECK-NEXT: ldrb w19, [sp, #240]
; CHECK-NEXT: mov w25, wzr
; CHECK-NEXT: mov x24, xzr
-; CHECK-NEXT: str w8, [sp, #108] // 4-byte Folded Spill
; CHECK-NEXT: mov x3, x26
+; CHECK-NEXT: str w8, [sp, #108] // 4-byte Folded Spill
+; CHECK-NEXT: ldrb w19, [sp, #240]
; CHECK-NEXT: ldp x9, x8, [sp, #344]
; CHECK-NEXT: str w12, [sp, #92] // 4-byte Folded Spill
; CHECK-NEXT: mov w12, #1 // =0x1
@@ -123,8 +123,8 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: mov x12, #-30 // =0xffffffffffffffe2
; CHECK-NEXT: add x19, x4, w8, sxtw #2
; CHECK-NEXT: mov x9, xzr
-; CHECK-NEXT: csel x12, x24, x12, lo
; CHECK-NEXT: mov w4, w30
+; CHECK-NEXT: csel x12, x24, x12, lo
; CHECK-NEXT: str x12, [sp, #56] // 8-byte Folded Spill
; CHECK-NEXT: b .LBB0_8
; CHECK-NEXT: .p2align 5, , 16
@@ -341,8 +341,8 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: mov x24, x27
; CHECK-NEXT: lsl x23, x14, #1
; CHECK-NEXT: mov x27, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: madd x14, x14, x3, x11
; CHECK-NEXT: mov w28, w30
+; CHECK-NEXT: madd x14, x14, x3, x11
; CHECK-NEXT: mov w3, #-7680 // =0xffffe200
; CHECK-NEXT: b .LBB0_39
; CHECK-NEXT: .p2align 5, , 16
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