[llvm] Improved AMDGPU Lowering of abs(i16) and -abs(i16) (PR #165626)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/lib/Target/AMDGPU/SISAbs16Fixup.cpp llvm/lib/Target/AMDGPU/AMDGPU.h llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SISAbs16Fixup.cpp b/llvm/lib/Target/AMDGPU/SISAbs16Fixup.cpp
index fd305b6ff..ca9d314c0 100644
--- a/llvm/lib/Target/AMDGPU/SISAbs16Fixup.cpp
+++ b/llvm/lib/Target/AMDGPU/SISAbs16Fixup.cpp
@@ -24,7 +24,7 @@
 
 using namespace llvm;
 
-static Register pierceCopies(Register R, MachineRegisterInfo& MRI) {
+static Register pierceCopies(Register R, MachineRegisterInfo &MRI) {
   MachineInstr *CopyMI = MRI.getVRegDef(R);
   while (CopyMI && CopyMI->getOpcode() == AMDGPU::COPY) {
     Register T = CopyMI->getOperand(1).getReg();
@@ -41,25 +41,24 @@ static Register pierceCopies(Register R, MachineRegisterInfo& MRI) {
 static MachineInstr *matchExpandAbsPattern(MachineInstr &MI,
                                            MachineRegisterInfo &MRI) {
   std::array<MachineInstr *, 2> SextInstructions;
-  for (unsigned I = 0; I < SextInstructions.size(); I++)
-  {
+  for (unsigned I = 0; I < SextInstructions.size(); I++) {
     SextInstructions[I] = MRI.getVRegDef(MI.getOperand(I + 1).getReg());
     if (SextInstructions[I]->getOpcode() != AMDGPU::S_SEXT_I32_I16)
       return nullptr;
   }
 
   Register AbsSource;
-  MachineInstr* SubIns = nullptr;
+  MachineInstr *SubIns = nullptr;
   for (MachineInstr *SextMI : SextInstructions) {
     Register SextReg = SextMI->getOperand(1).getReg();
-    MachineInstr* OperandMI = MRI.getVRegDef(SextReg);
+    MachineInstr *OperandMI = MRI.getVRegDef(SextReg);
     if (OperandMI->getOpcode() == AMDGPU::S_SUB_I32)
-      if(!SubIns)
+      if (!SubIns)
         SubIns = OperandMI;
       else
         return nullptr;
     else
-      AbsSource = pierceCopies(SextReg,MRI);
+      AbsSource = pierceCopies(SextReg, MRI);
   }
 
   if (!SubIns)
@@ -85,12 +84,12 @@ static bool runSAbs16Fixup(MachineFunction &MF) {
   const SIInstrInfo &TII = *MF.getSubtarget<GCNSubtarget>().getInstrInfo();
 
   bool Changed = false;
-  
+
   for (MachineBasicBlock &MBB : MF)
     for (MachineInstr &MI : make_early_inc_range(MBB)) {
       bool IsPositive = MI.getOpcode() == AMDGPU::S_MAX_I32;
       bool IsNegative = MI.getOpcode() == AMDGPU::S_MIN_I32;
-      MachineInstr* AbsSourceMI;
+      MachineInstr *AbsSourceMI;
       if ((!IsPositive && !IsNegative) ||
           !(AbsSourceMI = matchExpandAbsPattern(MI, MRI)))
         continue;
@@ -107,7 +106,7 @@ static bool runSAbs16Fixup(MachineFunction &MF) {
       BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_ABS_I32), AbsDestReg)
           .addReg(SextDestReg);
 
-      if(IsNegative)
+      if (IsNegative)
         BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_SUB_I32),
                 MI.getOperand(0).getReg())
             .addImm(0)
@@ -154,10 +153,10 @@ bool SISAbs16FixupLegacy::runOnMachineFunction(MachineFunction &MF) {
   return runSAbs16Fixup(MF);
 }
 
-INITIALIZE_PASS_BEGIN(SISAbs16FixupLegacy, DEBUG_TYPE, "SI SAbs16 Fixup",
-                      false, false)
-INITIALIZE_PASS_END(SISAbs16FixupLegacy, DEBUG_TYPE, "SI SAbs16 Fixup",
-                    false, false)
+INITIALIZE_PASS_BEGIN(SISAbs16FixupLegacy, DEBUG_TYPE, "SI SAbs16 Fixup", false,
+                      false)
+INITIALIZE_PASS_END(SISAbs16FixupLegacy, DEBUG_TYPE, "SI SAbs16 Fixup", false,
+                    false)
 
 char SISAbs16FixupLegacy::ID = 0;
 

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https://github.com/llvm/llvm-project/pull/165626