[llvm] [CodeGen] Register-coalescer remat fix subreg liveness (PR #165662)

[Vigneshwar Jayakumar via llvm-commits]

https://github.com/VigneshwarJ created https://github.com/llvm/llvm-project/pull/165662

This is a bugfix in rematerialization where the liveness of subreg mask was incorrectly updated causing crash in scheduler.

>From 64bbd4b298187c375abb518761b7e25080eedf2d Mon Sep 17 00:00:00 2001
From: vigneshwar jayakumar <vigneshwar.jayakumar at amd.com>
Date: Thu, 30 Oct 2025 01:59:23 -0500
Subject: [PATCH] [CodeGen] Register-coalescer remat fix subreg liveness

This is a bugfix in rematerialization where the liveness of subreg mask
was incorrectly updated causing crash in scheduler.
---
 llvm/lib/CodeGen/RegisterCoalescer.cpp        |  1 +
 .../AMDGPU/reg-coalescer-subreg-liveness.mir  | 55 +++++++++++++++++++
 2 files changed, 56 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir

diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index e17a214b9a27d..acd189e4b1a8d 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1625,6 +1625,7 @@ bool RegisterCoalescer::reMaterializeDef(const CoalescerPair &CP,
           // dead def so that the interferences are properly modeled.
           if (!SR.liveAt(DefIndex))
             SR.createDeadDef(DefIndex, Alloc);
+          SR.LaneMask = DstMask & SR.LaneMask;
         }
       }
       if (UpdatedSubRanges)
diff --git a/llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir b/llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
new file mode 100644
index 0000000000000..3afc1d343a728
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -run-pass=register-coalescer -verify-coalescing -o - %s | FileCheck %s
+
+# This test is to check fix for failure with "Bad machine code: Defining instruction does not modify register" due to corrupt lane mask.
+
+---
+name:            reg_coalescer_subreg_liveness
+tracksRegLiveness: true
+liveins:
+body:             |
+  ; CHECK-LABEL: name: reg_coalescer_subreg_liveness
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $sgpr4_sgpr5
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
+  ; CHECK-NEXT:   undef [[S_LOAD_DWORD_IMM:%[0-9]+]].sub2:sgpr_128 = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)
+  ; CHECK-NEXT:   [[S_LOAD_DWORD_IMM:%[0-9]+]].sub1:sgpr_128 = S_LOAD_DWORD_IMM [[COPY]](p4), 24, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
+  ; CHECK-NEXT:   [[S_LOAD_DWORD_IMM:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 1
+  ; CHECK-NEXT:   undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   S_NOP 0, implicit [[S_LOAD_DWORD_IMM]], implicit [[S_MOV_B32_]]
+  ; CHECK-NEXT:   S_BRANCH %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   S_ENDPGM 0
+  bb.0:
+    liveins: $sgpr4_sgpr5
+
+    %5:sgpr_64(p4) = COPY killed $sgpr4_sgpr5
+    %8:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %5(p4), 0, 0 :: (dereferenceable invariant load (s32) , align 16, addrspace 4)
+    %10:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed %5(p4), 24, 0 :: (dereferenceable invariant load (s32) , align 8, addrspace 4)
+    %7:sreg_32 = S_MOV_B32 1
+    undef %20.sub0:sgpr_128 = COPY %7
+    %0:sgpr_128 = COPY %20
+    %0.sub1:sgpr_128 = COPY killed %10
+    %27:sgpr_128 = COPY %0
+    %27.sub2:sgpr_128 = COPY killed %8
+    %29:sreg_32 = S_MOV_B32 0
+    undef %30.sub0:sgpr_256 = COPY %29
+    %37:sreg_32 = COPY %7
+  bb.1:
+
+    %1:sreg_32 = COPY killed %37
+    undef %33.sub0:sgpr_128 = COPY %7
+    %33.sub1:sgpr_128 = COPY killed %1
+    S_NOP 0, implicit %0, implicit %30
+    S_BRANCH %bb.2
+
+  bb.2:
+    S_ENDPGM 0
+...