[llvm] [DAG] Use known-bits when creating umulh/smulh. (PR #160916)

[Simon Pilgrim via llvm-commits]

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@@ -10821,18 +10825,17 @@ static SDValue combineShiftToMULH(SDNode *N, const SDLoc &DL, SelectionDAG &DAG,
   }
 
   SDValue MulhRightOp;
-  if (ConstantSDNode *Constant = isConstOrConstSplat(RightOp)) {
-    unsigned ActiveBits = IsSignExt
-                              ? Constant->getAPIntValue().getSignificantBits()
-                              : Constant->getAPIntValue().getActiveBits();
-    if (ActiveBits > NarrowVTSize)
+  if (LeftOp.getOpcode() != RightOp.getOpcode()) {
+    if (IsZeroExt && ShiftOperand.hasOneUse() &&
+        DAG.computeKnownBits(RightOp).countMinLeadingZeros() >= NarrowVTSize) {
+      MulhRightOp = DAG.getNode(ISD::TRUNCATE, DL, NarrowVT, RightOp);
+    } else if (IsSignExt && ShiftOperand.hasOneUse() &&
+               DAG.ComputeNumSignBits(RightOp) > NarrowVTSize) {
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RKSimon wrote:

Is this correct? We've gone from a getSignificantBits/getActiveBits check to a leading zero/sign bits check for the same NarrowVTSize bounds

https://github.com/llvm/llvm-project/pull/160916