[llvm] fca1e46 - [X86] Remove a redundant cast (NFC) (#165509)

via llvm-commits llvm-commits at lists.llvm.org
Wed Oct 29 07:36:02 PDT 2025


Author: Kazu Hirata
Date: 2025-10-29T07:35:57-07:00
New Revision: fca1e460652b91fafbaeed9b298e058e41041e96

URL: https://github.com/llvm/llvm-project/commit/fca1e460652b91fafbaeed9b298e058e41041e96
DIFF: https://github.com/llvm/llvm-project/commit/fca1e460652b91fafbaeed9b298e058e41041e96.diff

LOG: [X86] Remove a redundant cast (NFC) (#165509)

ShiftAmt is already of type int.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 5785440a20e43..89b42da9a40f0 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -12213,7 +12213,7 @@ static int matchShuffleAsShift(MVT &ShiftVT, unsigned &Opcode,
     MVT ShiftSVT = MVT::getIntegerVT(ScalarSizeInBits * Scale);
     ShiftVT = ByteShift ? MVT::getVectorVT(MVT::i8, SizeInBits / 8)
                         : MVT::getVectorVT(ShiftSVT, Size / Scale);
-    return (int)ShiftAmt;
+    return ShiftAmt;
   };
 
   // SSE/AVX supports logical shifts up to 64-bit integers - so we can just


        


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