[llvm] [AArch64][GlobalISel] Improve lowering of vector fp16 fptrunc (PR #163398)
Ryan Cowan via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 29 07:09:00 PDT 2025
https://github.com/HolyMolyCowMan updated https://github.com/llvm/llvm-project/pull/163398
>From 737470ec3a70bca31c44fad5948899fb79832be7 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 13 Oct 2025 12:14:00 +0000
Subject: [PATCH 01/13] [AArch64][GlobalISel] Improve lowering of vector fp16
fptrunc and fpext
---
llvm/lib/Target/AArch64/AArch64Combine.td | 9 +-
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 62 +++-
.../AArch64/GISel/AArch64LegalizerInfo.h | 2 +
.../GISel/AArch64PostLegalizerLowering.cpp | 194 ++++++++++++
.../GlobalISel/legalizer-info-validation.mir | 8 +-
llvm/test/CodeGen/AArch64/arm64-fp128.ll | 24 +-
llvm/test/CodeGen/AArch64/fmla.ll | 48 +--
.../CodeGen/AArch64/fp16-v4-instructions.ll | 73 +----
.../CodeGen/AArch64/fp16-v8-instructions.ll | 100 ++-----
llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll | 186 +++++-------
llvm/test/CodeGen/AArch64/fpext.ll | 49 ++-
llvm/test/CodeGen/AArch64/fptoi.ll | 278 ++++++------------
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 85 ++----
.../test/CodeGen/AArch64/fptoui-sat-vector.ll | 85 ++----
llvm/test/CodeGen/AArch64/fptrunc.ll | 101 +++----
15 files changed, 592 insertions(+), 712 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index 278314792bfb9..e70bf43a842b4 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -332,6 +332,13 @@ def combine_mul_cmlt : GICombineRule<
(apply [{ applyCombineMulCMLT(*${root}, MRI, B, ${matchinfo}); }])
>;
+def lower_fptrunc_fptrunc: GICombineRule<
+ (defs root:$root),
+ (match (wip_match_opcode G_FPTRUNC):$root,
+ [{ return matchFpTruncFpTrunc(*${root}, MRI); }]),
+ (apply [{ applyFpTruncFpTrunc(*${root}, MRI, B); }])
+>;
+
// Post-legalization combines which should happen at all optimization levels.
// (E.g. ones that facilitate matching for the selector) For example, matching
// pseudos.
@@ -340,7 +347,7 @@ def AArch64PostLegalizerLowering
[shuffle_vector_lowering, vashr_vlshr_imm,
icmp_lowering, build_vector_lowering,
lower_vector_fcmp, form_truncstore, fconstant_to_constant,
- vector_sext_inreg_to_shift,
+ vector_sext_inreg_to_shift, lower_fptrunc_fptrunc,
unmerge_ext_to_unmerge, lower_mulv2s64,
vector_unmerge_lowering, insertelt_nonconst,
unmerge_duplanes]> {
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 5f93847bc680e..9153694817676 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/IR/DerivedTypes.h"
@@ -817,14 +818,31 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.legalFor(
{{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}})
.libcallFor({{s16, s128}, {s32, s128}, {s64, s128}})
- .clampNumElements(0, v4s16, v4s16)
- .clampNumElements(0, v2s32, v2s32)
+ .moreElementsToNextPow2(1)
+ .customIf([](const LegalityQuery &Q) {
+ LLT DstTy = Q.Types[0];
+ LLT SrcTy = Q.Types[1];
+ return SrcTy.isFixedVector() && DstTy.isFixedVector() &&
+ SrcTy.getScalarSizeInBits() == 64 &&
+ DstTy.getScalarSizeInBits() == 16;
+ })
+ // Clamp based on input
+ .clampNumElements(1, v4s32, v4s32)
+ .clampNumElements(1, v2s64, v2s64)
.scalarize(0);
getActionDefinitionsBuilder(G_FPEXT)
.legalFor(
{{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}})
.libcallFor({{s128, s64}, {s128, s32}, {s128, s16}})
+ .moreElementsToNextPow2(0)
+ .customIf([](const LegalityQuery &Q) {
+ LLT DstTy = Q.Types[0];
+ LLT SrcTy = Q.Types[1];
+ return SrcTy.isVector() && DstTy.isVector() &&
+ SrcTy.getScalarSizeInBits() == 16 &&
+ DstTy.getScalarSizeInBits() == 64;
+ })
.clampNumElements(0, v4s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
.scalarize(0);
@@ -1464,6 +1482,12 @@ bool AArch64LegalizerInfo::legalizeCustom(
return legalizeICMP(MI, MRI, MIRBuilder);
case TargetOpcode::G_BITCAST:
return legalizeBitcast(MI, Helper);
+ case TargetOpcode::G_FPEXT:
+ // In order to vectorise f16 to f64 properly, we need to use f32 as an
+ // intermediary
+ return legalizeViaF32(MI, MIRBuilder, MRI, TargetOpcode::G_FPEXT);
+ case TargetOpcode::G_FPTRUNC:
+ return legalizeViaF32(MI, MIRBuilder, MRI, TargetOpcode::G_FPTRUNC);
}
llvm_unreachable("expected switch to return");
@@ -2390,3 +2414,37 @@ bool AArch64LegalizerInfo::legalizePrefetch(MachineInstr &MI,
MI.eraseFromParent();
return true;
}
+
+bool AArch64LegalizerInfo::legalizeViaF32(MachineInstr &MI,
+ MachineIRBuilder &MIRBuilder,
+ MachineRegisterInfo &MRI,
+ unsigned Opcode) const {
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src = MI.getOperand(1).getReg();
+ LLT DstTy = MRI.getType(Dst);
+ LLT SrcTy = MRI.getType(Src);
+
+ LLT MidTy = LLT::fixed_vector(SrcTy.getNumElements(), LLT::scalar(32));
+
+ MachineInstrBuilder Mid;
+ MachineInstrBuilder Fin;
+ MIRBuilder.setInstrAndDebugLoc(MI);
+ switch (Opcode) {
+ default:
+ return false;
+ case TargetOpcode::G_FPEXT: {
+ Mid = MIRBuilder.buildFPExt(MidTy, Src);
+ Fin = MIRBuilder.buildFPExt(DstTy, Mid.getReg(0));
+ break;
+ }
+ case TargetOpcode::G_FPTRUNC: {
+ Mid = MIRBuilder.buildFPTrunc(MidTy, Src);
+ Fin = MIRBuilder.buildFPTrunc(DstTy, Mid.getReg(0));
+ break;
+ }
+ }
+
+ MRI.replaceRegWith(Dst, Fin.getReg(0));
+ MI.eraseFromParent();
+ return true;
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
index bcb294326fa92..049808d66f983 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
@@ -67,6 +67,8 @@ class AArch64LegalizerInfo : public LegalizerInfo {
bool legalizeDynStackAlloc(MachineInstr &MI, LegalizerHelper &Helper) const;
bool legalizePrefetch(MachineInstr &MI, LegalizerHelper &Helper) const;
bool legalizeBitcast(MachineInstr &MI, LegalizerHelper &Helper) const;
+ bool legalizeViaF32(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
+ MachineRegisterInfo &MRI, unsigned Opcode) const;
const AArch64Subtarget *ST;
};
} // End llvm namespace.
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 23dcaea2ac1a4..e675fac0f13ac 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -901,6 +901,200 @@ unsigned getCmpOperandFoldingProfit(Register CmpOp, MachineRegisterInfo &MRI) {
return 0;
}
+// Helper function for matchFpTruncFpTrunc.
+// Checks that the given definition belongs to an FPTRUNC and that the source is
+// not an integer, as no rounding is necessary due to the range of values
+bool checkTruncSrc(MachineRegisterInfo &MRI, MachineInstr *MaybeFpTrunc) {
+ if (!MaybeFpTrunc || MaybeFpTrunc->getOpcode() != TargetOpcode::G_FPTRUNC)
+ return false;
+
+ // Check the source is 64 bits as we only want to match a very specific
+ // pattern
+ Register FpTruncSrc = MaybeFpTrunc->getOperand(1).getReg();
+ LLT SrcTy = MRI.getType(FpTruncSrc);
+ if (SrcTy.getScalarSizeInBits() != 64)
+ return false;
+
+ // Need to check the float didn't come from an int as no rounding is
+ // neccessary
+ MachineInstr *FpTruncSrcDef = getDefIgnoringCopies(FpTruncSrc, MRI);
+ if (FpTruncSrcDef->getOpcode() == TargetOpcode::G_SITOFP ||
+ FpTruncSrcDef->getOpcode() == TargetOpcode::G_UITOFP)
+ return false;
+
+ return true;
+}
+
+// To avoid double rounding issues we need to lower FPTRUNC(FPTRUNC) to an odd
+// rounding truncate and a normal truncate. When
+// truncating an FP that came from an integer this is not a problem as the range
+// of values is lower in the int
+bool matchFpTruncFpTrunc(MachineInstr &MI, MachineRegisterInfo &MRI) {
+ if (MI.getOpcode() != TargetOpcode::G_FPTRUNC)
+ return false;
+
+ // Check the destination is 16 bits as we only want to match a very specific
+ // pattern
+ Register Dst = MI.getOperand(0).getReg();
+ LLT DstTy = MRI.getType(Dst);
+ if (DstTy.getScalarSizeInBits() != 16)
+ return false;
+
+ Register Src = MI.getOperand(1).getReg();
+
+ MachineInstr *ParentDef = getDefIgnoringCopies(Src, MRI);
+ if (!ParentDef)
+ return false;
+
+ MachineInstr *FpTruncDef;
+ switch (ParentDef->getOpcode()) {
+ default:
+ return false;
+ case TargetOpcode::G_CONCAT_VECTORS: {
+ // Expecting exactly two FPTRUNCs
+ if (ParentDef->getNumOperands() != 3)
+ return false;
+
+ // All operands need to be FPTRUNC
+ for (unsigned OpIdx = 1, NumOperands = ParentDef->getNumOperands();
+ OpIdx != NumOperands; ++OpIdx) {
+ Register FpTruncDst = ParentDef->getOperand(OpIdx).getReg();
+
+ FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
+
+ if (!checkTruncSrc(MRI, FpTruncDef))
+ return false;
+ }
+
+ return true;
+ }
+ // This is to match cases in which vectors are widened to a larger size
+ case TargetOpcode::G_INSERT_VECTOR_ELT: {
+ Register VecExtractDst = ParentDef->getOperand(2).getReg();
+ MachineInstr *VecExtractDef = getDefIgnoringCopies(VecExtractDst, MRI);
+
+ Register FpTruncDst = VecExtractDef->getOperand(1).getReg();
+ FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
+
+ if (!checkTruncSrc(MRI, FpTruncDef))
+ return false;
+ break;
+ }
+ case TargetOpcode::G_FPTRUNC: {
+ Register FpTruncDst = ParentDef->getOperand(1).getReg();
+ FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
+
+ if (!checkTruncSrc(MRI, FpTruncDef))
+ return false;
+ break;
+ }
+ }
+
+ return true;
+}
+
+void applyFpTruncFpTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
+ MachineIRBuilder &B) {
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src = MI.getOperand(1).getReg();
+
+ LLT V2F32 = LLT::fixed_vector(2, LLT::scalar(32));
+ LLT V4F32 = LLT::fixed_vector(4, LLT::scalar(32));
+ LLT V4F16 = LLT::fixed_vector(4, LLT::scalar(16));
+
+ B.setInstrAndDebugLoc(MI);
+
+ MachineInstr *ParentDef = getDefIgnoringCopies(Src, MRI);
+ if (!ParentDef)
+ return;
+
+ switch (ParentDef->getOpcode()) {
+ default:
+ return;
+ case TargetOpcode::G_INSERT_VECTOR_ELT: {
+ Register VecExtractDst = ParentDef->getOperand(2).getReg();
+ MachineInstr *VecExtractDef = getDefIgnoringCopies(VecExtractDst, MRI);
+
+ Register FpTruncDst = VecExtractDef->getOperand(1).getReg();
+ MachineInstr *FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
+
+ Register FpTruncSrc = FpTruncDef->getOperand(1).getReg();
+ MRI.setRegClass(FpTruncSrc, &AArch64::FPR128RegClass);
+
+ Register Fp32 = MRI.createGenericVirtualRegister(V2F32);
+ MRI.setRegClass(Fp32, &AArch64::FPR64RegClass);
+
+ B.buildInstr(AArch64::FCVTXNv2f32, {Fp32}, {FpTruncSrc});
+
+ // Only 4f32 -> 4f16 is legal so we need to mimic that situation
+ Register Fp32Padding = B.buildUndef(V2F32).getReg(0);
+ MRI.setRegClass(Fp32Padding, &AArch64::FPR64RegClass);
+
+ Register Fp32Full = MRI.createGenericVirtualRegister(V4F32);
+ MRI.setRegClass(Fp32Full, &AArch64::FPR128RegClass);
+ B.buildConcatVectors(Fp32Full, {Fp32, Fp32Padding});
+
+ Register Fp16 = MRI.createGenericVirtualRegister(V4F16);
+ MRI.setRegClass(Fp16, &AArch64::FPR64RegClass);
+ B.buildFPTrunc(Fp16, Fp32Full);
+
+ MRI.replaceRegWith(Dst, Fp16);
+ MI.eraseFromParent();
+ break;
+ }
+ case TargetOpcode::G_CONCAT_VECTORS: {
+ // Get the two FP Truncs that are being concatenated
+ Register FpTrunc1Dst = ParentDef->getOperand(1).getReg();
+ Register FpTrunc2Dst = ParentDef->getOperand(2).getReg();
+
+ MachineInstr *FpTrunc1Def = getDefIgnoringCopies(FpTrunc1Dst, MRI);
+ MachineInstr *FpTrunc2Def = getDefIgnoringCopies(FpTrunc2Dst, MRI);
+
+ // Make the registers 128bit to store the 2 doubles
+ Register LoFp64 = FpTrunc1Def->getOperand(1).getReg();
+ MRI.setRegClass(LoFp64, &AArch64::FPR128RegClass);
+ Register HiFp64 = FpTrunc2Def->getOperand(1).getReg();
+ MRI.setRegClass(HiFp64, &AArch64::FPR128RegClass);
+
+ B.setInstrAndDebugLoc(MI);
+
+ // Convert the lower half
+ Register LoFp32 = MRI.createGenericVirtualRegister(V2F32);
+ MRI.setRegClass(LoFp32, &AArch64::FPR64RegClass);
+ B.buildInstr(AArch64::FCVTXNv2f32, {LoFp32}, {LoFp64});
+
+ // Create a register for the high half to use
+ Register AccUndef = MRI.createGenericVirtualRegister(V4F32);
+ MRI.setRegClass(AccUndef, &AArch64::FPR128RegClass);
+ B.buildUndef(AccUndef);
+
+ Register Acc = MRI.createGenericVirtualRegister(V4F32);
+ MRI.setRegClass(Acc, &AArch64::FPR128RegClass);
+ B.buildInstr(TargetOpcode::INSERT_SUBREG)
+ .addDef(Acc)
+ .addUse(AccUndef)
+ .addUse(LoFp32)
+ .addImm(AArch64::dsub);
+
+ // Convert the high half
+ Register AccOut = MRI.createGenericVirtualRegister(V4F32);
+ MRI.setRegClass(AccOut, &AArch64::FPR128RegClass);
+ B.buildInstr(AArch64::FCVTXNv4f32)
+ .addDef(AccOut)
+ .addUse(Acc)
+ .addUse(HiFp64);
+
+ Register Fp16 = MRI.createGenericVirtualRegister(V4F16);
+ MRI.setRegClass(Fp16, &AArch64::FPR64RegClass);
+ B.buildFPTrunc(Fp16, AccOut);
+
+ MRI.replaceRegWith(Dst, Fp16);
+ MI.eraseFromParent();
+ break;
+ }
+ }
+}
+
/// \returns true if it would be profitable to swap the LHS and RHS of a G_ICMP
/// instruction \p MI.
bool trySwapICmpOperands(MachineInstr &MI, MachineRegisterInfo &MRI) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 896603d6eb20d..0561f91b6e015 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -555,11 +555,11 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_FPEXT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. the first uncovered type index: 2, OK
-# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_FPTRUNC (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. the first uncovered type index: 2, OK
-# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_FPTOSI (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/CodeGen/AArch64/arm64-fp128.ll b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
index 3e4b887fed55d..b8b8d20b9a17b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fp128.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
@@ -1197,30 +1197,22 @@ define <2 x half> @vec_round_f16(<2 x fp128> %val) {
;
; CHECK-GI-LABEL: vec_round_f16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #64
-; CHECK-GI-NEXT: str x30, [sp, #48] // 8-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
+; CHECK-GI-NEXT: sub sp, sp, #48
+; CHECK-GI-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
; CHECK-GI-NEXT: .cfi_offset w30, -16
-; CHECK-GI-NEXT: mov v2.d[0], x8
; CHECK-GI-NEXT: str q1, [sp] // 16-byte Folded Spill
-; CHECK-GI-NEXT: mov v2.d[1], x8
-; CHECK-GI-NEXT: str q2, [sp, #32] // 16-byte Folded Spill
; CHECK-GI-NEXT: bl __trunctfhf2
; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-GI-NEXT: bl __trunctfhf2
+; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $q0
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
-; CHECK-GI-NEXT: bl __trunctfhf2
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
-; CHECK-GI-NEXT: bl __trunctfhf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload
-; CHECK-GI-NEXT: ldr x30, [sp, #48] // 8-byte Folded Reload
-; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: add sp, sp, #64
+; CHECK-GI-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
+; CHECK-GI-NEXT: mov v1.h[1], v0.h[0]
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: ret
%dst = fptrunc <2 x fp128> %val to <2 x half>
ret <2 x half> %dst
diff --git a/llvm/test/CodeGen/AArch64/fmla.ll b/llvm/test/CodeGen/AArch64/fmla.ll
index a37aabb0b5384..12b6562b5cf0c 100644
--- a/llvm/test/CodeGen/AArch64/fmla.ll
+++ b/llvm/test/CodeGen/AArch64/fmla.ll
@@ -865,22 +865,22 @@ define <7 x half> @fmuladd_v7f16(<7 x half> %a, <7 x half> %b, <7 x half> %c) {
; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v3.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v5.4h
-; CHECK-GI-NOFP16-NEXT: mov v5.h[0], v2.h[4]
; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v4.4h
; CHECK-GI-NOFP16-NEXT: fadd v0.4s, v0.4s, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v5.h[1], v2.h[5]
-; CHECK-GI-NOFP16-NEXT: fmul v1.4s, v3.4s, v4.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn v3.4h, v0.4s
-; CHECK-GI-NOFP16-NEXT: mov v5.h[2], v2.h[6]
-; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v0.h[0], v3.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v5.4h
+; CHECK-GI-NOFP16-NEXT: mov v1.h[0], v2.h[4]
+; CHECK-GI-NOFP16-NEXT: fmul v3.4s, v3.4s, v4.4s
+; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[5]
+; CHECK-GI-NOFP16-NEXT: fcvtn v4.4h, v0.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn v3.4h, v3.4s
+; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v2.h[6]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[0], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v3.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v3.h[1]
-; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v1.4s, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v3.h[2]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v4.h[1]
+; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v2.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v4.h[2]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v3.h[3]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v4.h[3]
; CHECK-GI-NOFP16-NEXT: mov v0.h[4], v1.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v1.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[2]
@@ -1350,22 +1350,22 @@ define <7 x half> @fmul_v7f16(<7 x half> %a, <7 x half> %b, <7 x half> %c) {
; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v3.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v5.4h
-; CHECK-GI-NOFP16-NEXT: mov v5.h[0], v2.h[4]
; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v4.4h
; CHECK-GI-NOFP16-NEXT: fadd v0.4s, v0.4s, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v5.h[1], v2.h[5]
-; CHECK-GI-NOFP16-NEXT: fmul v1.4s, v3.4s, v4.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn v3.4h, v0.4s
-; CHECK-GI-NOFP16-NEXT: mov v5.h[2], v2.h[6]
-; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v0.h[0], v3.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v5.4h
+; CHECK-GI-NOFP16-NEXT: mov v1.h[0], v2.h[4]
+; CHECK-GI-NOFP16-NEXT: fmul v3.4s, v3.4s, v4.4s
+; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[5]
+; CHECK-GI-NOFP16-NEXT: fcvtn v4.4h, v0.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn v3.4h, v3.4s
+; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v2.h[6]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[0], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v3.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v3.h[1]
-; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v1.4s, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v3.h[2]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v4.h[1]
+; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v2.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v4.h[2]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v3.h[3]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v4.h[3]
; CHECK-GI-NOFP16-NEXT: mov v0.h[4], v1.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v1.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[2]
diff --git a/llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll b/llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
index 6233ce743b706..760742a4efad7 100644
--- a/llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
@@ -170,47 +170,12 @@ define <4 x half> @s_to_h(<4 x float> %a) {
}
define <4 x half> @d_to_h(<4 x double> %a) {
-; CHECK-CVT-SD-LABEL: d_to_h:
-; CHECK-CVT-SD: // %bb.0:
-; CHECK-CVT-SD-NEXT: fcvtxn v0.2s, v0.2d
-; CHECK-CVT-SD-NEXT: fcvtxn2 v0.4s, v1.2d
-; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v0.4s
-; CHECK-CVT-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: d_to_h:
-; CHECK-FP16-SD: // %bb.0:
-; CHECK-FP16-SD-NEXT: fcvtxn v0.2s, v0.2d
-; CHECK-FP16-SD-NEXT: fcvtxn2 v0.4s, v1.2d
-; CHECK-FP16-SD-NEXT: fcvtn v0.4h, v0.4s
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-CVT-GI-LABEL: d_to_h:
-; CHECK-CVT-GI: // %bb.0:
-; CHECK-CVT-GI-NEXT: mov d2, v0.d[1]
-; CHECK-CVT-GI-NEXT: fcvt h0, d0
-; CHECK-CVT-GI-NEXT: mov d3, v1.d[1]
-; CHECK-CVT-GI-NEXT: fcvt h1, d1
-; CHECK-CVT-GI-NEXT: fcvt h2, d2
-; CHECK-CVT-GI-NEXT: mov v0.h[1], v2.h[0]
-; CHECK-CVT-GI-NEXT: fcvt h2, d3
-; CHECK-CVT-GI-NEXT: mov v0.h[2], v1.h[0]
-; CHECK-CVT-GI-NEXT: mov v0.h[3], v2.h[0]
-; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-CVT-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: d_to_h:
-; CHECK-FP16-GI: // %bb.0:
-; CHECK-FP16-GI-NEXT: mov d2, v0.d[1]
-; CHECK-FP16-GI-NEXT: fcvt h0, d0
-; CHECK-FP16-GI-NEXT: mov d3, v1.d[1]
-; CHECK-FP16-GI-NEXT: fcvt h1, d1
-; CHECK-FP16-GI-NEXT: fcvt h2, d2
-; CHECK-FP16-GI-NEXT: mov v0.h[1], v2.h[0]
-; CHECK-FP16-GI-NEXT: fcvt h2, d3
-; CHECK-FP16-GI-NEXT: mov v0.h[2], v1.h[0]
-; CHECK-FP16-GI-NEXT: mov v0.h[3], v2.h[0]
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: d_to_h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtxn v0.2s, v0.2d
+; CHECK-NEXT: fcvtxn2 v0.4s, v1.2d
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%1 = fptrunc <4 x double> %a to <4 x half>
ret <4 x half> %1
}
@@ -241,30 +206,16 @@ define <4 x double> @h_to_d(<4 x half> %a) {
;
; CHECK-CVT-GI-LABEL: h_to_d:
; CHECK-CVT-GI: // %bb.0:
-; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
-; CHECK-CVT-GI-NEXT: mov h2, v0.h[2]
-; CHECK-CVT-GI-NEXT: mov h3, v0.h[3]
-; CHECK-CVT-GI-NEXT: fcvt d0, h0
-; CHECK-CVT-GI-NEXT: fcvt d4, h1
-; CHECK-CVT-GI-NEXT: fcvt d1, h2
-; CHECK-CVT-GI-NEXT: fcvt d2, h3
-; CHECK-CVT-GI-NEXT: mov v0.d[1], v4.d[0]
-; CHECK-CVT-GI-NEXT: mov v1.d[1], v2.d[0]
+; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-GI-NEXT: fcvtl v0.2d, v1.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v1.2d, v1.4s
; CHECK-CVT-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: h_to_d:
; CHECK-FP16-GI: // %bb.0:
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
-; CHECK-FP16-GI-NEXT: fcvt d4, h1
-; CHECK-FP16-GI-NEXT: fcvt d1, h2
-; CHECK-FP16-GI-NEXT: fcvt d2, h3
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v4.d[0]
-; CHECK-FP16-GI-NEXT: mov v1.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl v0.2d, v1.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v1.2d, v1.4s
; CHECK-FP16-GI-NEXT: ret
%1 = fpext <4 x half> %a to <4 x double>
ret <4 x double> %1
diff --git a/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll b/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
index 86763eb5f9e3b..4d8505679c71c 100644
--- a/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
@@ -198,48 +198,22 @@ define <8 x half> @d_to_h(<8 x double> %a) {
;
; CHECK-CVT-GI-LABEL: d_to_h:
; CHECK-CVT-GI: // %bb.0:
-; CHECK-CVT-GI-NEXT: mov d4, v0.d[1]
-; CHECK-CVT-GI-NEXT: fcvt h0, d0
-; CHECK-CVT-GI-NEXT: mov d5, v1.d[1]
-; CHECK-CVT-GI-NEXT: fcvt h1, d1
-; CHECK-CVT-GI-NEXT: fcvt h4, d4
-; CHECK-CVT-GI-NEXT: mov v0.h[1], v4.h[0]
-; CHECK-CVT-GI-NEXT: fcvt h4, d5
-; CHECK-CVT-GI-NEXT: mov v0.h[2], v1.h[0]
-; CHECK-CVT-GI-NEXT: mov d1, v2.d[1]
-; CHECK-CVT-GI-NEXT: fcvt h2, d2
-; CHECK-CVT-GI-NEXT: mov v0.h[3], v4.h[0]
-; CHECK-CVT-GI-NEXT: fcvt h1, d1
-; CHECK-CVT-GI-NEXT: mov v0.h[4], v2.h[0]
-; CHECK-CVT-GI-NEXT: mov d2, v3.d[1]
-; CHECK-CVT-GI-NEXT: fcvt h3, d3
-; CHECK-CVT-GI-NEXT: mov v0.h[5], v1.h[0]
-; CHECK-CVT-GI-NEXT: fcvt h1, d2
-; CHECK-CVT-GI-NEXT: mov v0.h[6], v3.h[0]
-; CHECK-CVT-GI-NEXT: mov v0.h[7], v1.h[0]
+; CHECK-CVT-GI-NEXT: fcvtxn v0.2s, v0.2d
+; CHECK-CVT-GI-NEXT: fcvtxn2 v0.4s, v1.2d
+; CHECK-CVT-GI-NEXT: fcvtxn v1.2s, v2.2d
+; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-CVT-GI-NEXT: fcvtxn2 v1.4s, v3.2d
+; CHECK-CVT-GI-NEXT: fcvtn2 v0.8h, v1.4s
; CHECK-CVT-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: d_to_h:
; CHECK-FP16-GI: // %bb.0:
-; CHECK-FP16-GI-NEXT: mov d4, v0.d[1]
-; CHECK-FP16-GI-NEXT: fcvt h0, d0
-; CHECK-FP16-GI-NEXT: mov d5, v1.d[1]
-; CHECK-FP16-GI-NEXT: fcvt h1, d1
-; CHECK-FP16-GI-NEXT: fcvt h4, d4
-; CHECK-FP16-GI-NEXT: mov v0.h[1], v4.h[0]
-; CHECK-FP16-GI-NEXT: fcvt h4, d5
-; CHECK-FP16-GI-NEXT: mov v0.h[2], v1.h[0]
-; CHECK-FP16-GI-NEXT: mov d1, v2.d[1]
-; CHECK-FP16-GI-NEXT: fcvt h2, d2
-; CHECK-FP16-GI-NEXT: mov v0.h[3], v4.h[0]
-; CHECK-FP16-GI-NEXT: fcvt h1, d1
-; CHECK-FP16-GI-NEXT: mov v0.h[4], v2.h[0]
-; CHECK-FP16-GI-NEXT: mov d2, v3.d[1]
-; CHECK-FP16-GI-NEXT: fcvt h3, d3
-; CHECK-FP16-GI-NEXT: mov v0.h[5], v1.h[0]
-; CHECK-FP16-GI-NEXT: fcvt h1, d2
-; CHECK-FP16-GI-NEXT: mov v0.h[6], v3.h[0]
-; CHECK-FP16-GI-NEXT: mov v0.h[7], v1.h[0]
+; CHECK-FP16-GI-NEXT: fcvtxn v0.2s, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtxn2 v0.4s, v1.2d
+; CHECK-FP16-GI-NEXT: fcvtxn v1.2s, v2.2d
+; CHECK-FP16-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtxn2 v1.4s, v3.2d
+; CHECK-FP16-GI-NEXT: fcvtn2 v0.8h, v1.4s
; CHECK-FP16-GI-NEXT: ret
%1 = fptrunc <8 x double> %a to <8 x half>
ret <8 x half> %1
@@ -298,48 +272,22 @@ define <8 x double> @h_to_d(<8 x half> %a) {
;
; CHECK-CVT-GI-LABEL: h_to_d:
; CHECK-CVT-GI: // %bb.0:
-; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
-; CHECK-CVT-GI-NEXT: mov h2, v0.h[2]
-; CHECK-CVT-GI-NEXT: mov h3, v0.h[3]
-; CHECK-CVT-GI-NEXT: mov h4, v0.h[4]
-; CHECK-CVT-GI-NEXT: mov h5, v0.h[5]
-; CHECK-CVT-GI-NEXT: mov h6, v0.h[6]
-; CHECK-CVT-GI-NEXT: mov h7, v0.h[7]
-; CHECK-CVT-GI-NEXT: fcvt d0, h0
-; CHECK-CVT-GI-NEXT: fcvt d16, h1
-; CHECK-CVT-GI-NEXT: fcvt d1, h2
-; CHECK-CVT-GI-NEXT: fcvt d17, h3
-; CHECK-CVT-GI-NEXT: fcvt d2, h4
-; CHECK-CVT-GI-NEXT: fcvt d4, h5
-; CHECK-CVT-GI-NEXT: fcvt d3, h6
-; CHECK-CVT-GI-NEXT: fcvt d5, h7
-; CHECK-CVT-GI-NEXT: mov v0.d[1], v16.d[0]
-; CHECK-CVT-GI-NEXT: mov v1.d[1], v17.d[0]
-; CHECK-CVT-GI-NEXT: mov v2.d[1], v4.d[0]
-; CHECK-CVT-GI-NEXT: mov v3.d[1], v5.d[0]
+; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-GI-NEXT: fcvtl2 v3.4s, v0.8h
+; CHECK-CVT-GI-NEXT: fcvtl v0.2d, v1.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v3.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v3.2d, v3.4s
; CHECK-CVT-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: h_to_d:
; CHECK-FP16-GI: // %bb.0:
-; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
-; CHECK-FP16-GI-NEXT: mov h4, v0.h[4]
-; CHECK-FP16-GI-NEXT: mov h5, v0.h[5]
-; CHECK-FP16-GI-NEXT: mov h6, v0.h[6]
-; CHECK-FP16-GI-NEXT: mov h7, v0.h[7]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
-; CHECK-FP16-GI-NEXT: fcvt d16, h1
-; CHECK-FP16-GI-NEXT: fcvt d1, h2
-; CHECK-FP16-GI-NEXT: fcvt d17, h3
-; CHECK-FP16-GI-NEXT: fcvt d2, h4
-; CHECK-FP16-GI-NEXT: fcvt d4, h5
-; CHECK-FP16-GI-NEXT: fcvt d3, h6
-; CHECK-FP16-GI-NEXT: fcvt d5, h7
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v16.d[0]
-; CHECK-FP16-GI-NEXT: mov v1.d[1], v17.d[0]
-; CHECK-FP16-GI-NEXT: mov v2.d[1], v4.d[0]
-; CHECK-FP16-GI-NEXT: mov v3.d[1], v5.d[0]
+; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl2 v3.4s, v0.8h
+; CHECK-FP16-GI-NEXT: fcvtl v0.2d, v1.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v3.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v3.2d, v3.4s
; CHECK-FP16-GI-NEXT: ret
%1 = fpext <8 x half> %a to <8 x double>
ret <8 x double> %1
diff --git a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
index 637c02875b84e..b075a8b6f70ee 100644
--- a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
@@ -285,31 +285,24 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) {
;
; CHECK-FP16-GI-LABEL: stest_f16i32:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
; CHECK-FP16-GI-NEXT: adrp x8, .LCPI6_1
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
-; CHECK-FP16-GI-NEXT: fcvt d1, h1
-; CHECK-FP16-GI-NEXT: fcvt d2, h2
-; CHECK-FP16-GI-NEXT: fcvt d3, h3
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v2.2d
; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI6_1]
; CHECK-FP16-GI-NEXT: adrp x8, .LCPI6_0
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v2.2d, v0.2d
-; CHECK-FP16-GI-NEXT: cmgt v4.2d, v2.2d, v1.2d
-; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v4.16b
; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI6_0]
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v0.2d, v2.2d
-; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
-; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
@@ -351,24 +344,17 @@ define <4 x i32> @utest_f16i32(<4 x half> %x) {
;
; CHECK-FP16-GI-LABEL: utest_f16i32:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
-; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
-; CHECK-FP16-GI-NEXT: fcvt d2, h2
-; CHECK-FP16-GI-NEXT: fcvt d3, h3
-; CHECK-FP16-GI-NEXT: fcvt d4, h4
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
-; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v2.2d
; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v3.2d
-; CHECK-FP16-GI-NEXT: cmhi v3.2d, v1.2d, v0.2d
-; CHECK-FP16-GI-NEXT: cmhi v4.2d, v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
-; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: cmhi v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <4 x half> %x to <4 x i64>
@@ -412,28 +398,21 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
;
; CHECK-FP16-GI-LABEL: ustest_f16i32:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
-; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
-; CHECK-FP16-GI-NEXT: fcvt d2, h2
-; CHECK-FP16-GI-NEXT: fcvt d3, h3
-; CHECK-FP16-GI-NEXT: fcvt d4, h4
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
-; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v2.2d
; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v3.2d
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v0.2d
-; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
-; CHECK-FP16-GI-NEXT: cmgt v2.2d, v0.2d, #0
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, #0
-; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-FP16-GI-NEXT: and v1.16b, v1.16b, v3.16b
-; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-FP16-GI-NEXT: cmgt v1.2d, v2.2d, #0
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v0.2d, #0
+; CHECK-FP16-GI-NEXT: and v1.16b, v2.16b, v1.16b
+; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
@@ -2273,31 +2252,24 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
;
; CHECK-FP16-GI-LABEL: stest_f16i32_mm:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
; CHECK-FP16-GI-NEXT: adrp x8, .LCPI33_1
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
-; CHECK-FP16-GI-NEXT: fcvt d1, h1
-; CHECK-FP16-GI-NEXT: fcvt d2, h2
-; CHECK-FP16-GI-NEXT: fcvt d3, h3
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v2.2d
; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI33_1]
; CHECK-FP16-GI-NEXT: adrp x8, .LCPI33_0
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v2.2d, v0.2d
-; CHECK-FP16-GI-NEXT: cmgt v4.2d, v2.2d, v1.2d
-; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v4.16b
; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI33_0]
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v0.2d, v2.2d
-; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
-; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
@@ -2337,24 +2309,17 @@ define <4 x i32> @utest_f16i32_mm(<4 x half> %x) {
;
; CHECK-FP16-GI-LABEL: utest_f16i32_mm:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
-; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
-; CHECK-FP16-GI-NEXT: fcvt d2, h2
-; CHECK-FP16-GI-NEXT: fcvt d3, h3
-; CHECK-FP16-GI-NEXT: fcvt d4, h4
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
-; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v2.2d
; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v3.2d
-; CHECK-FP16-GI-NEXT: cmhi v3.2d, v1.2d, v0.2d
-; CHECK-FP16-GI-NEXT: cmhi v4.2d, v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
-; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: cmhi v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <4 x half> %x to <4 x i64>
@@ -2397,28 +2362,21 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
;
; CHECK-FP16-GI-LABEL: ustest_f16i32_mm:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
-; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
-; CHECK-FP16-GI-NEXT: fcvt d2, h2
-; CHECK-FP16-GI-NEXT: fcvt d3, h3
-; CHECK-FP16-GI-NEXT: fcvt d4, h4
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
-; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v2.2d
; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v3.2d
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v0.2d
-; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
-; CHECK-FP16-GI-NEXT: cmgt v2.2d, v0.2d, #0
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, #0
-; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-FP16-GI-NEXT: and v1.16b, v1.16b, v3.16b
-; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-FP16-GI-NEXT: cmgt v1.2d, v2.2d, #0
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v0.2d, #0
+; CHECK-FP16-GI-NEXT: and v1.16b, v2.16b, v1.16b
+; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
diff --git a/llvm/test/CodeGen/AArch64/fpext.ll b/llvm/test/CodeGen/AArch64/fpext.ll
index df90f9d5f0910..8980340a447de 100644
--- a/llvm/test/CodeGen/AArch64/fpext.ll
+++ b/llvm/test/CodeGen/AArch64/fpext.ll
@@ -82,11 +82,12 @@ define <3 x double> @fpext_v3f32_v3f64(<3 x float> %a) {
;
; CHECK-GI-LABEL: fpext_v3f32_v3f64:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov s1, v0.s[2]
+; CHECK-GI-NEXT: mov v1.s[0], v0.s[2]
; CHECK-GI-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-GI-NEXT: fcvt d2, s1
+; CHECK-GI-NEXT: fcvtl v2.2d, v1.2s
; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-GI-NEXT: ret
entry:
%c = fpext <3 x float> %a to <3 x double>
@@ -320,20 +321,11 @@ entry:
}
define <2 x double> @fpext_v2f16_v2f64(<2 x half> %a) {
-; CHECK-SD-LABEL: fpext_v2f16_v2f64:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fpext_v2f16_v2f64:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: mov h1, v0.h[1]
-; CHECK-GI-NEXT: fcvt d0, h0
-; CHECK-GI-NEXT: fcvt d1, h1
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fpext_v2f16_v2f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-NEXT: ret
entry:
%c = fpext <2 x half> %a to <2 x double>
ret <2 x double> %c
@@ -353,12 +345,12 @@ define <3 x double> @fpext_v3f16_v3f64(<3 x half> %a) {
;
; CHECK-GI-LABEL: fpext_v3f16_v3f64:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: mov h1, v0.h[1]
-; CHECK-GI-NEXT: mov h2, v0.h[2]
-; CHECK-GI-NEXT: fcvt d0, h0
-; CHECK-GI-NEXT: fcvt d1, h1
-; CHECK-GI-NEXT: fcvt d2, h2
+; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl v0.2d, v1.2s
+; CHECK-GI-NEXT: fcvtl2 v2.2d, v1.4s
+; CHECK-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
%c = fpext <3 x half> %a to <3 x double>
@@ -375,16 +367,9 @@ define <4 x double> @fpext_v4f16_v4f64(<4 x half> %a) {
;
; CHECK-GI-LABEL: fpext_v4f16_v4f64:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: mov h1, v0.h[1]
-; CHECK-GI-NEXT: mov h2, v0.h[2]
-; CHECK-GI-NEXT: mov h3, v0.h[3]
-; CHECK-GI-NEXT: fcvt d0, h0
-; CHECK-GI-NEXT: fcvt d4, h1
-; CHECK-GI-NEXT: fcvt d1, h2
-; CHECK-GI-NEXT: fcvt d2, h3
-; CHECK-GI-NEXT: mov v0.d[1], v4.d[0]
-; CHECK-GI-NEXT: mov v1.d[1], v2.d[0]
+; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl v0.2d, v1.2s
+; CHECK-GI-NEXT: fcvtl2 v1.2d, v1.4s
; CHECK-GI-NEXT: ret
entry:
%c = fpext <4 x half> %a to <4 x double>
diff --git a/llvm/test/CodeGen/AArch64/fptoi.ll b/llvm/test/CodeGen/AArch64/fptoi.ll
index f6053cee50dae..3dafabe0b69d7 100644
--- a/llvm/test/CodeGen/AArch64/fptoi.ll
+++ b/llvm/test/CodeGen/AArch64/fptoi.ll
@@ -4610,11 +4610,8 @@ define <2 x i64> @fptos_v2f16_v2i64(<2 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptos_v2f16_v2i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
-; CHECK-FP16-GI-NEXT: fcvt d1, h1
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl v0.2d, v0.2s
; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
; CHECK-FP16-GI-NEXT: ret
entry:
@@ -4654,11 +4651,8 @@ define <2 x i64> @fptou_v2f16_v2i64(<2 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptou_v2f16_v2i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
-; CHECK-FP16-GI-NEXT: fcvt d1, h1
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl v0.2d, v0.2s
; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
; CHECK-FP16-GI-NEXT: ret
entry:
@@ -4710,20 +4704,14 @@ define <3 x i64> @fptos_v3f16_v3i64(<3 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptos_v3f16_v3i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
-; CHECK-FP16-GI-NEXT: fcvt d1, h0
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
-; CHECK-FP16-GI-NEXT: fcvt d2, h2
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
-; CHECK-FP16-GI-NEXT: fcvt d2, h3
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: mov v2.d[1], v1.d[0]
-; CHECK-FP16-GI-NEXT: mov d1, v0.d[1]
+; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v2.2d, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v1.2d
; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v2.2d
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-FP16-GI-NEXT: mov d1, v0.d[1]
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptosi <3 x half> %a to <3 x i64>
@@ -4774,20 +4762,14 @@ define <3 x i64> @fptou_v3f16_v3i64(<3 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptou_v3f16_v3i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
-; CHECK-FP16-GI-NEXT: fcvt d1, h0
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
-; CHECK-FP16-GI-NEXT: fcvt d2, h2
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
-; CHECK-FP16-GI-NEXT: fcvt d2, h3
-; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: mov v2.d[1], v1.d[0]
-; CHECK-FP16-GI-NEXT: mov d1, v0.d[1]
+; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v2.2d, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v1.2d
; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v2.2d
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-FP16-GI-NEXT: mov d1, v0.d[1]
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptoui <3 x half> %a to <3 x i64>
@@ -4842,17 +4824,10 @@ define <4 x i64> @fptos_v4f16_v4i64(<4 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptos_v4f16_v4i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
-; CHECK-FP16-GI-NEXT: fcvt d1, h1
-; CHECK-FP16-GI-NEXT: fcvt d2, h2
-; CHECK-FP16-GI-NEXT: fcvt d3, h3
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v2.2d, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v1.2d
; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v2.2d
; CHECK-FP16-GI-NEXT: ret
entry:
@@ -4908,17 +4883,10 @@ define <4 x i64> @fptou_v4f16_v4i64(<4 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptou_v4f16_v4i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
-; CHECK-FP16-GI-NEXT: fcvt d1, h1
-; CHECK-FP16-GI-NEXT: fcvt d2, h2
-; CHECK-FP16-GI-NEXT: fcvt d3, h3
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
-; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v2.2d, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v1.2d
; CHECK-FP16-GI-NEXT: fcvtzu v1.2d, v2.2d
; CHECK-FP16-GI-NEXT: ret
entry:
@@ -5005,29 +4973,16 @@ define <8 x i64> @fptos_v8f16_v8i64(<8 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptos_v8f16_v8i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
-; CHECK-FP16-GI-NEXT: mov h4, v0.h[4]
-; CHECK-FP16-GI-NEXT: mov h5, v0.h[5]
-; CHECK-FP16-GI-NEXT: mov h6, v0.h[6]
-; CHECK-FP16-GI-NEXT: mov h7, v0.h[7]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
-; CHECK-FP16-GI-NEXT: fcvt d1, h1
-; CHECK-FP16-GI-NEXT: fcvt d2, h2
-; CHECK-FP16-GI-NEXT: fcvt d3, h3
-; CHECK-FP16-GI-NEXT: fcvt d4, h4
-; CHECK-FP16-GI-NEXT: fcvt d5, h5
-; CHECK-FP16-GI-NEXT: fcvt d6, h6
-; CHECK-FP16-GI-NEXT: fcvt d7, h7
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
-; CHECK-FP16-GI-NEXT: mov v4.d[1], v5.d[0]
-; CHECK-FP16-GI-NEXT: mov v6.d[1], v7.d[0]
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v4.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v3.2d, v6.2d
+; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v1.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-FP16-GI-NEXT: fcvtl v3.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v4.2d, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v3.2d, v4.2d
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptosi <8 x half> %a to <8 x i64>
@@ -5113,29 +5068,16 @@ define <8 x i64> @fptou_v8f16_v8i64(<8 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptou_v8f16_v8i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
-; CHECK-FP16-GI-NEXT: mov h4, v0.h[4]
-; CHECK-FP16-GI-NEXT: mov h5, v0.h[5]
-; CHECK-FP16-GI-NEXT: mov h6, v0.h[6]
-; CHECK-FP16-GI-NEXT: mov h7, v0.h[7]
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
-; CHECK-FP16-GI-NEXT: fcvt d1, h1
-; CHECK-FP16-GI-NEXT: fcvt d2, h2
-; CHECK-FP16-GI-NEXT: fcvt d3, h3
-; CHECK-FP16-GI-NEXT: fcvt d4, h4
-; CHECK-FP16-GI-NEXT: fcvt d5, h5
-; CHECK-FP16-GI-NEXT: fcvt d6, h6
-; CHECK-FP16-GI-NEXT: fcvt d7, h7
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
-; CHECK-FP16-GI-NEXT: mov v4.d[1], v5.d[0]
-; CHECK-FP16-GI-NEXT: mov v6.d[1], v7.d[0]
-; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v4.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v3.2d, v6.2d
+; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v1.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-FP16-GI-NEXT: fcvtl v3.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v4.2d, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v1.2d, v1.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v3.2d, v4.2d
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptoui <8 x half> %a to <8 x i64>
@@ -5285,52 +5227,26 @@ define <16 x i64> @fptos_v16f16_v16i64(<16 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptos_v16f16_v16i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[1]
-; CHECK-FP16-GI-NEXT: mov h4, v0.h[2]
-; CHECK-FP16-GI-NEXT: mov h5, v0.h[3]
-; CHECK-FP16-GI-NEXT: fcvt d2, h0
-; CHECK-FP16-GI-NEXT: mov h6, v0.h[4]
-; CHECK-FP16-GI-NEXT: mov h7, v0.h[5]
-; CHECK-FP16-GI-NEXT: mov h16, v0.h[6]
-; CHECK-FP16-GI-NEXT: mov h0, v0.h[7]
-; CHECK-FP16-GI-NEXT: mov h17, v1.h[1]
-; CHECK-FP16-GI-NEXT: mov h18, v1.h[2]
-; CHECK-FP16-GI-NEXT: mov h19, v1.h[3]
-; CHECK-FP16-GI-NEXT: mov h20, v1.h[4]
-; CHECK-FP16-GI-NEXT: mov h21, v1.h[5]
-; CHECK-FP16-GI-NEXT: mov h22, v1.h[6]
-; CHECK-FP16-GI-NEXT: mov h23, v1.h[7]
-; CHECK-FP16-GI-NEXT: fcvt d3, h3
-; CHECK-FP16-GI-NEXT: fcvt d4, h4
-; CHECK-FP16-GI-NEXT: fcvt d5, h5
-; CHECK-FP16-GI-NEXT: fcvt d6, h6
-; CHECK-FP16-GI-NEXT: fcvt d7, h7
-; CHECK-FP16-GI-NEXT: fcvt d16, h16
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
-; CHECK-FP16-GI-NEXT: fcvt d24, h1
-; CHECK-FP16-GI-NEXT: fcvt d1, h17
-; CHECK-FP16-GI-NEXT: fcvt d17, h18
-; CHECK-FP16-GI-NEXT: fcvt d18, h19
-; CHECK-FP16-GI-NEXT: fcvt d19, h20
-; CHECK-FP16-GI-NEXT: fcvt d20, h21
-; CHECK-FP16-GI-NEXT: fcvt d21, h22
-; CHECK-FP16-GI-NEXT: fcvt d22, h23
-; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
-; CHECK-FP16-GI-NEXT: mov v4.d[1], v5.d[0]
-; CHECK-FP16-GI-NEXT: mov v6.d[1], v7.d[0]
-; CHECK-FP16-GI-NEXT: mov v16.d[1], v0.d[0]
-; CHECK-FP16-GI-NEXT: mov v24.d[1], v1.d[0]
-; CHECK-FP16-GI-NEXT: mov v17.d[1], v18.d[0]
-; CHECK-FP16-GI-NEXT: mov v19.d[1], v20.d[0]
-; CHECK-FP16-GI-NEXT: mov v21.d[1], v22.d[0]
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v2.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v4.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v6.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v3.2d, v16.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v4.2d, v24.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v5.2d, v17.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v6.2d, v19.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v7.2d, v21.2d
+; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-FP16-GI-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-FP16-GI-NEXT: fcvtl2 v1.4s, v1.8h
+; CHECK-FP16-GI-NEXT: fcvtl v4.2d, v2.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v2.2d, v2.4s
+; CHECK-FP16-GI-NEXT: fcvtl v5.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v6.2d, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtl v7.2d, v3.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v16.2d, v3.4s
+; CHECK-FP16-GI-NEXT: fcvtl v17.2d, v1.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v18.2d, v1.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v4.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v5.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v3.2d, v6.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v4.2d, v7.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v5.2d, v16.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v6.2d, v17.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v7.2d, v18.2d
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptosi <16 x half> %a to <16 x i64>
@@ -5480,52 +5396,26 @@ define <16 x i64> @fptou_v16f16_v16i64(<16 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptou_v16f16_v16i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: mov h3, v0.h[1]
-; CHECK-FP16-GI-NEXT: mov h4, v0.h[2]
-; CHECK-FP16-GI-NEXT: mov h5, v0.h[3]
-; CHECK-FP16-GI-NEXT: fcvt d2, h0
-; CHECK-FP16-GI-NEXT: mov h6, v0.h[4]
-; CHECK-FP16-GI-NEXT: mov h7, v0.h[5]
-; CHECK-FP16-GI-NEXT: mov h16, v0.h[6]
-; CHECK-FP16-GI-NEXT: mov h0, v0.h[7]
-; CHECK-FP16-GI-NEXT: mov h17, v1.h[1]
-; CHECK-FP16-GI-NEXT: mov h18, v1.h[2]
-; CHECK-FP16-GI-NEXT: mov h19, v1.h[3]
-; CHECK-FP16-GI-NEXT: mov h20, v1.h[4]
-; CHECK-FP16-GI-NEXT: mov h21, v1.h[5]
-; CHECK-FP16-GI-NEXT: mov h22, v1.h[6]
-; CHECK-FP16-GI-NEXT: mov h23, v1.h[7]
-; CHECK-FP16-GI-NEXT: fcvt d3, h3
-; CHECK-FP16-GI-NEXT: fcvt d4, h4
-; CHECK-FP16-GI-NEXT: fcvt d5, h5
-; CHECK-FP16-GI-NEXT: fcvt d6, h6
-; CHECK-FP16-GI-NEXT: fcvt d7, h7
-; CHECK-FP16-GI-NEXT: fcvt d16, h16
-; CHECK-FP16-GI-NEXT: fcvt d0, h0
-; CHECK-FP16-GI-NEXT: fcvt d24, h1
-; CHECK-FP16-GI-NEXT: fcvt d1, h17
-; CHECK-FP16-GI-NEXT: fcvt d17, h18
-; CHECK-FP16-GI-NEXT: fcvt d18, h19
-; CHECK-FP16-GI-NEXT: fcvt d19, h20
-; CHECK-FP16-GI-NEXT: fcvt d20, h21
-; CHECK-FP16-GI-NEXT: fcvt d21, h22
-; CHECK-FP16-GI-NEXT: fcvt d22, h23
-; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
-; CHECK-FP16-GI-NEXT: mov v4.d[1], v5.d[0]
-; CHECK-FP16-GI-NEXT: mov v6.d[1], v7.d[0]
-; CHECK-FP16-GI-NEXT: mov v16.d[1], v0.d[0]
-; CHECK-FP16-GI-NEXT: mov v24.d[1], v1.d[0]
-; CHECK-FP16-GI-NEXT: mov v17.d[1], v18.d[0]
-; CHECK-FP16-GI-NEXT: mov v19.d[1], v20.d[0]
-; CHECK-FP16-GI-NEXT: mov v21.d[1], v22.d[0]
-; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v2.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v1.2d, v4.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v6.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v3.2d, v16.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v4.2d, v24.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v5.2d, v17.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v6.2d, v19.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v7.2d, v21.2d
+; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-FP16-GI-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-FP16-GI-NEXT: fcvtl2 v1.4s, v1.8h
+; CHECK-FP16-GI-NEXT: fcvtl v4.2d, v2.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v2.2d, v2.4s
+; CHECK-FP16-GI-NEXT: fcvtl v5.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v6.2d, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtl v7.2d, v3.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v16.2d, v3.4s
+; CHECK-FP16-GI-NEXT: fcvtl v17.2d, v1.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v18.2d, v1.4s
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v4.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v5.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v3.2d, v6.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v4.2d, v7.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v5.2d, v16.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v6.2d, v17.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v7.2d, v18.2d
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptoui <16 x half> %a to <16 x i64>
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index b963acd8cb2a1..dbcfaff8aee05 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -3088,30 +3088,14 @@ define <4 x i64> @test_signed_v4f16_v4i64(<4 x half> %f) {
; CHECK-SD-FP16-NEXT: mov v1.d[1], x11
; CHECK-SD-FP16-NEXT: ret
;
-; CHECK-GI-CVT-LABEL: test_signed_v4f16_v4i64:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-CVT-NEXT: fcvtl v1.2d, v0.2s
-; CHECK-GI-CVT-NEXT: fcvtl2 v2.2d, v0.4s
-; CHECK-GI-CVT-NEXT: fcvtzs v0.2d, v1.2d
-; CHECK-GI-CVT-NEXT: fcvtzs v1.2d, v2.2d
-; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_signed_v4f16_v4i64:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
-; CHECK-GI-FP16-NEXT: fcvt d0, h0
-; CHECK-GI-FP16-NEXT: fcvt d1, h1
-; CHECK-GI-FP16-NEXT: fcvt d2, h2
-; CHECK-GI-FP16-NEXT: fcvt d3, h3
-; CHECK-GI-FP16-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-FP16-NEXT: mov v2.d[1], v3.d[0]
-; CHECK-GI-FP16-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-GI-FP16-NEXT: fcvtzs v1.2d, v2.2d
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-GI-LABEL: test_signed_v4f16_v4i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v2.2d, v0.4s
+; CHECK-GI-NEXT: fcvtzs v0.2d, v1.2d
+; CHECK-GI-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-GI-NEXT: ret
%x = call <4 x i64> @llvm.fptosi.sat.v4f16.v4i64(<4 x half> %f)
ret <4 x i64> %x
}
@@ -3797,46 +3781,19 @@ define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
; CHECK-SD-FP16-NEXT: mov v3.d[1], x14
; CHECK-SD-FP16-NEXT: ret
;
-; CHECK-GI-CVT-LABEL: test_signed_v8f16_v8i64:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-GI-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-CVT-NEXT: fcvtl v2.2d, v1.2s
-; CHECK-GI-CVT-NEXT: fcvtl2 v1.2d, v1.4s
-; CHECK-GI-CVT-NEXT: fcvtl v3.2d, v0.2s
-; CHECK-GI-CVT-NEXT: fcvtl2 v4.2d, v0.4s
-; CHECK-GI-CVT-NEXT: fcvtzs v0.2d, v2.2d
-; CHECK-GI-CVT-NEXT: fcvtzs v1.2d, v1.2d
-; CHECK-GI-CVT-NEXT: fcvtzs v2.2d, v3.2d
-; CHECK-GI-CVT-NEXT: fcvtzs v3.2d, v4.2d
-; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_signed_v8f16_v8i64:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
-; CHECK-GI-FP16-NEXT: mov h4, v0.h[4]
-; CHECK-GI-FP16-NEXT: mov h5, v0.h[5]
-; CHECK-GI-FP16-NEXT: mov h6, v0.h[6]
-; CHECK-GI-FP16-NEXT: mov h7, v0.h[7]
-; CHECK-GI-FP16-NEXT: fcvt d0, h0
-; CHECK-GI-FP16-NEXT: fcvt d1, h1
-; CHECK-GI-FP16-NEXT: fcvt d2, h2
-; CHECK-GI-FP16-NEXT: fcvt d3, h3
-; CHECK-GI-FP16-NEXT: fcvt d4, h4
-; CHECK-GI-FP16-NEXT: fcvt d5, h5
-; CHECK-GI-FP16-NEXT: fcvt d6, h6
-; CHECK-GI-FP16-NEXT: fcvt d7, h7
-; CHECK-GI-FP16-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-FP16-NEXT: mov v2.d[1], v3.d[0]
-; CHECK-GI-FP16-NEXT: mov v4.d[1], v5.d[0]
-; CHECK-GI-FP16-NEXT: mov v6.d[1], v7.d[0]
-; CHECK-GI-FP16-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-GI-FP16-NEXT: fcvtzs v1.2d, v2.2d
-; CHECK-GI-FP16-NEXT: fcvtzs v2.2d, v4.2d
-; CHECK-GI-FP16-NEXT: fcvtzs v3.2d, v6.2d
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-GI-LABEL: test_signed_v8f16_v8i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NEXT: fcvtl v2.2d, v1.2s
+; CHECK-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-GI-NEXT: fcvtl v3.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v4.2d, v0.4s
+; CHECK-GI-NEXT: fcvtzs v0.2d, v2.2d
+; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-GI-NEXT: fcvtzs v2.2d, v3.2d
+; CHECK-GI-NEXT: fcvtzs v3.2d, v4.2d
+; CHECK-GI-NEXT: ret
%x = call <8 x i64> @llvm.fptosi.sat.v8f16.v8i64(<8 x half> %f)
ret <8 x i64> %x
}
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index 5a66b68af8e96..44e6e9415263b 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -2506,30 +2506,14 @@ define <4 x i64> @test_unsigned_v4f16_v4i64(<4 x half> %f) {
; CHECK-SD-FP16-NEXT: mov v1.d[1], x11
; CHECK-SD-FP16-NEXT: ret
;
-; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i64:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-CVT-NEXT: fcvtl v1.2d, v0.2s
-; CHECK-GI-CVT-NEXT: fcvtl2 v2.2d, v0.4s
-; CHECK-GI-CVT-NEXT: fcvtzu v0.2d, v1.2d
-; CHECK-GI-CVT-NEXT: fcvtzu v1.2d, v2.2d
-; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i64:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
-; CHECK-GI-FP16-NEXT: fcvt d0, h0
-; CHECK-GI-FP16-NEXT: fcvt d1, h1
-; CHECK-GI-FP16-NEXT: fcvt d2, h2
-; CHECK-GI-FP16-NEXT: fcvt d3, h3
-; CHECK-GI-FP16-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-FP16-NEXT: mov v2.d[1], v3.d[0]
-; CHECK-GI-FP16-NEXT: fcvtzu v0.2d, v0.2d
-; CHECK-GI-FP16-NEXT: fcvtzu v1.2d, v2.2d
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-GI-LABEL: test_unsigned_v4f16_v4i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v2.2d, v0.4s
+; CHECK-GI-NEXT: fcvtzu v0.2d, v1.2d
+; CHECK-GI-NEXT: fcvtzu v1.2d, v2.2d
+; CHECK-GI-NEXT: ret
%x = call <4 x i64> @llvm.fptoui.sat.v4f16.v4i64(<4 x half> %f)
ret <4 x i64> %x
}
@@ -3114,46 +3098,19 @@ define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; CHECK-SD-FP16-NEXT: mov v3.d[1], x14
; CHECK-SD-FP16-NEXT: ret
;
-; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i64:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-GI-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-CVT-NEXT: fcvtl v2.2d, v1.2s
-; CHECK-GI-CVT-NEXT: fcvtl2 v1.2d, v1.4s
-; CHECK-GI-CVT-NEXT: fcvtl v3.2d, v0.2s
-; CHECK-GI-CVT-NEXT: fcvtl2 v4.2d, v0.4s
-; CHECK-GI-CVT-NEXT: fcvtzu v0.2d, v2.2d
-; CHECK-GI-CVT-NEXT: fcvtzu v1.2d, v1.2d
-; CHECK-GI-CVT-NEXT: fcvtzu v2.2d, v3.2d
-; CHECK-GI-CVT-NEXT: fcvtzu v3.2d, v4.2d
-; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i64:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
-; CHECK-GI-FP16-NEXT: mov h4, v0.h[4]
-; CHECK-GI-FP16-NEXT: mov h5, v0.h[5]
-; CHECK-GI-FP16-NEXT: mov h6, v0.h[6]
-; CHECK-GI-FP16-NEXT: mov h7, v0.h[7]
-; CHECK-GI-FP16-NEXT: fcvt d0, h0
-; CHECK-GI-FP16-NEXT: fcvt d1, h1
-; CHECK-GI-FP16-NEXT: fcvt d2, h2
-; CHECK-GI-FP16-NEXT: fcvt d3, h3
-; CHECK-GI-FP16-NEXT: fcvt d4, h4
-; CHECK-GI-FP16-NEXT: fcvt d5, h5
-; CHECK-GI-FP16-NEXT: fcvt d6, h6
-; CHECK-GI-FP16-NEXT: fcvt d7, h7
-; CHECK-GI-FP16-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-FP16-NEXT: mov v2.d[1], v3.d[0]
-; CHECK-GI-FP16-NEXT: mov v4.d[1], v5.d[0]
-; CHECK-GI-FP16-NEXT: mov v6.d[1], v7.d[0]
-; CHECK-GI-FP16-NEXT: fcvtzu v0.2d, v0.2d
-; CHECK-GI-FP16-NEXT: fcvtzu v1.2d, v2.2d
-; CHECK-GI-FP16-NEXT: fcvtzu v2.2d, v4.2d
-; CHECK-GI-FP16-NEXT: fcvtzu v3.2d, v6.2d
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-GI-LABEL: test_unsigned_v8f16_v8i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NEXT: fcvtl v2.2d, v1.2s
+; CHECK-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-GI-NEXT: fcvtl v3.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v4.2d, v0.4s
+; CHECK-GI-NEXT: fcvtzu v0.2d, v2.2d
+; CHECK-GI-NEXT: fcvtzu v1.2d, v1.2d
+; CHECK-GI-NEXT: fcvtzu v2.2d, v3.2d
+; CHECK-GI-NEXT: fcvtzu v3.2d, v4.2d
+; CHECK-GI-NEXT: ret
%x = call <8 x i64> @llvm.fptoui.sat.v8f16.v8i64(<8 x half> %f)
ret <8 x i64> %x
}
diff --git a/llvm/test/CodeGen/AArch64/fptrunc.ll b/llvm/test/CodeGen/AArch64/fptrunc.ll
index 1f84c944d7c16..de780bf475138 100644
--- a/llvm/test/CodeGen/AArch64/fptrunc.ll
+++ b/llvm/test/CodeGen/AArch64/fptrunc.ll
@@ -112,30 +112,22 @@ define <2 x half> @fptrunc_v2f128_v2f16(<2 x fp128> %a) {
;
; CHECK-GI-LABEL: fptrunc_v2f128_v2f16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: sub sp, sp, #64
-; CHECK-GI-NEXT: str x30, [sp, #48] // 8-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
+; CHECK-GI-NEXT: sub sp, sp, #48
+; CHECK-GI-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
; CHECK-GI-NEXT: .cfi_offset w30, -16
-; CHECK-GI-NEXT: mov v2.d[0], x8
; CHECK-GI-NEXT: str q1, [sp] // 16-byte Folded Spill
-; CHECK-GI-NEXT: mov v2.d[1], x8
-; CHECK-GI-NEXT: str q2, [sp, #32] // 16-byte Folded Spill
; CHECK-GI-NEXT: bl __trunctfhf2
; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-GI-NEXT: bl __trunctfhf2
+; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $q0
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
-; CHECK-GI-NEXT: bl __trunctfhf2
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
-; CHECK-GI-NEXT: bl __trunctfhf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload
-; CHECK-GI-NEXT: ldr x30, [sp, #48] // 8-byte Folded Reload
-; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: add sp, sp, #64
+; CHECK-GI-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
+; CHECK-GI-NEXT: mov v1.h[1], v0.h[0]
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: ret
entry:
%c = fptrunc <2 x fp128> %a to <2 x half>
@@ -260,8 +252,9 @@ define <3 x float> @fptrunc_v3f64_v3f32(<3 x double> %a) {
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-GI-NEXT: fcvt s2, d2
+; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: fcvtn v2.2s, v2.2d
; CHECK-GI-NEXT: fcvtn v1.2s, v0.2d
; CHECK-GI-NEXT: mov v0.s[0], v1.s[0]
; CHECK-GI-NEXT: mov v0.s[1], v1.s[1]
@@ -284,61 +277,49 @@ entry:
}
define <2 x half> @fptrunc_v2f64_v2f16(<2 x double> %a) {
-; CHECK-SD-LABEL: fptrunc_v2f64_v2f16:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: fcvtxn v0.2s, v0.2d
-; CHECK-SD-NEXT: fcvtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fptrunc_v2f64_v2f16:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcvt h0, d0
-; CHECK-GI-NEXT: fcvt h1, d1
-; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fptrunc_v2f64_v2f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtxn v0.2s, v0.2d
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: ret
entry:
%c = fptrunc <2 x double> %a to <2 x half>
ret <2 x half> %c
}
define <3 x half> @fptrunc_v3f64_v3f16(<3 x double> %a) {
-; CHECK-LABEL: fptrunc_v3f64_v3f16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvt h0, d0
-; CHECK-NEXT: fcvt h1, d1
-; CHECK-NEXT: fcvt h2, d2
-; CHECK-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-NEXT: mov v0.h[2], v2.h[0]
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: fptrunc_v3f64_v3f16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvt h0, d0
+; CHECK-SD-NEXT: fcvt h1, d1
+; CHECK-SD-NEXT: fcvt h2, d2
+; CHECK-SD-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-SD-NEXT: mov v0.h[2], v2.h[0]
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fptrunc_v3f64_v3f16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: fcvtxn v0.2s, v0.2d
+; CHECK-GI-NEXT: fcvtxn2 v0.4s, v2.2d
+; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = fptrunc <3 x double> %a to <3 x half>
ret <3 x half> %c
}
define <4 x half> @fptrunc_v4f64_v4f16(<4 x double> %a) {
-; CHECK-SD-LABEL: fptrunc_v4f64_v4f16:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: fcvtxn v0.2s, v0.2d
-; CHECK-SD-NEXT: fcvtxn2 v0.4s, v1.2d
-; CHECK-SD-NEXT: fcvtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fptrunc_v4f64_v4f16:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: fcvt h0, d0
-; CHECK-GI-NEXT: mov d3, v1.d[1]
-; CHECK-GI-NEXT: fcvt h1, d1
-; CHECK-GI-NEXT: fcvt h2, d2
-; CHECK-GI-NEXT: mov v0.h[1], v2.h[0]
-; CHECK-GI-NEXT: fcvt h2, d3
-; CHECK-GI-NEXT: mov v0.h[2], v1.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v2.h[0]
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fptrunc_v4f64_v4f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtxn v0.2s, v0.2d
+; CHECK-NEXT: fcvtxn2 v0.4s, v1.2d
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: ret
entry:
%c = fptrunc <4 x double> %a to <4 x half>
ret <4 x half> %c
>From ae3ef1e266a9bf22f7e1624f2fb8e0d82e1204ce Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Fri, 17 Oct 2025 13:04:54 +0000
Subject: [PATCH 02/13] Address review comments
---
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 14 ++++----
.../AArch64/GISel/AArch64LegalizerInfo.h | 4 +--
.../GISel/AArch64PostLegalizerLowering.cpp | 32 +++++++++----------
3 files changed, 23 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 9153694817676..e188e32b87e04 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1483,11 +1483,10 @@ bool AArch64LegalizerInfo::legalizeCustom(
case TargetOpcode::G_BITCAST:
return legalizeBitcast(MI, Helper);
case TargetOpcode::G_FPEXT:
+ case TargetOpcode::G_FPTRUNC:
// In order to vectorise f16 to f64 properly, we need to use f32 as an
// intermediary
- return legalizeViaF32(MI, MIRBuilder, MRI, TargetOpcode::G_FPEXT);
- case TargetOpcode::G_FPTRUNC:
- return legalizeViaF32(MI, MIRBuilder, MRI, TargetOpcode::G_FPTRUNC);
+ return legalizeFpextFptrunc(MI, MIRBuilder, MRI);
}
llvm_unreachable("expected switch to return");
@@ -2415,10 +2414,9 @@ bool AArch64LegalizerInfo::legalizePrefetch(MachineInstr &MI,
return true;
}
-bool AArch64LegalizerInfo::legalizeViaF32(MachineInstr &MI,
- MachineIRBuilder &MIRBuilder,
- MachineRegisterInfo &MRI,
- unsigned Opcode) const {
+bool AArch64LegalizerInfo::legalizeFpextFptrunc(
+ MachineInstr &MI, MachineIRBuilder &MIRBuilder,
+ MachineRegisterInfo &MRI) const {
Register Dst = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg();
LLT DstTy = MRI.getType(Dst);
@@ -2429,7 +2427,7 @@ bool AArch64LegalizerInfo::legalizeViaF32(MachineInstr &MI,
MachineInstrBuilder Mid;
MachineInstrBuilder Fin;
MIRBuilder.setInstrAndDebugLoc(MI);
- switch (Opcode) {
+ switch (MI.getOpcode()) {
default:
return false;
case TargetOpcode::G_FPEXT: {
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
index 049808d66f983..15999a44174d3 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
@@ -67,8 +67,8 @@ class AArch64LegalizerInfo : public LegalizerInfo {
bool legalizeDynStackAlloc(MachineInstr &MI, LegalizerHelper &Helper) const;
bool legalizePrefetch(MachineInstr &MI, LegalizerHelper &Helper) const;
bool legalizeBitcast(MachineInstr &MI, LegalizerHelper &Helper) const;
- bool legalizeViaF32(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
- MachineRegisterInfo &MRI, unsigned Opcode) const;
+ bool legalizeFpextFptrunc(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
+ MachineRegisterInfo &MRI) const;
const AArch64Subtarget *ST;
};
} // End llvm namespace.
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index e675fac0f13ac..2fa1b86a8a9c6 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -904,7 +904,7 @@ unsigned getCmpOperandFoldingProfit(Register CmpOp, MachineRegisterInfo &MRI) {
// Helper function for matchFpTruncFpTrunc.
// Checks that the given definition belongs to an FPTRUNC and that the source is
// not an integer, as no rounding is necessary due to the range of values
-bool checkTruncSrc(MachineRegisterInfo &MRI, MachineInstr *MaybeFpTrunc) {
+bool isFPTruncFromDouble(MachineRegisterInfo &MRI, MachineInstr *MaybeFpTrunc) {
if (!MaybeFpTrunc || MaybeFpTrunc->getOpcode() != TargetOpcode::G_FPTRUNC)
return false;
@@ -930,8 +930,7 @@ bool checkTruncSrc(MachineRegisterInfo &MRI, MachineInstr *MaybeFpTrunc) {
// truncating an FP that came from an integer this is not a problem as the range
// of values is lower in the int
bool matchFpTruncFpTrunc(MachineInstr &MI, MachineRegisterInfo &MRI) {
- if (MI.getOpcode() != TargetOpcode::G_FPTRUNC)
- return false;
+ assert(MI.getOpcode() == TargetOpcode::G_FPTRUNC && "Expected G_FPTRUNC");
// Check the destination is 16 bits as we only want to match a very specific
// pattern
@@ -959,10 +958,9 @@ bool matchFpTruncFpTrunc(MachineInstr &MI, MachineRegisterInfo &MRI) {
for (unsigned OpIdx = 1, NumOperands = ParentDef->getNumOperands();
OpIdx != NumOperands; ++OpIdx) {
Register FpTruncDst = ParentDef->getOperand(OpIdx).getReg();
-
FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
- if (!checkTruncSrc(MRI, FpTruncDef))
+ if (!isFPTruncFromDouble(MRI, FpTruncDef))
return false;
}
@@ -973,41 +971,43 @@ bool matchFpTruncFpTrunc(MachineInstr &MI, MachineRegisterInfo &MRI) {
Register VecExtractDst = ParentDef->getOperand(2).getReg();
MachineInstr *VecExtractDef = getDefIgnoringCopies(VecExtractDst, MRI);
+ if (!VecExtractDef ||
+ VecExtractDef->getOpcode() != TargetOpcode::G_EXTRACT_VECTOR_ELT)
+ return false;
+
Register FpTruncDst = VecExtractDef->getOperand(1).getReg();
FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
-
- if (!checkTruncSrc(MRI, FpTruncDef))
- return false;
break;
}
case TargetOpcode::G_FPTRUNC: {
Register FpTruncDst = ParentDef->getOperand(1).getReg();
FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
-
- if (!checkTruncSrc(MRI, FpTruncDef))
- return false;
break;
}
}
+ if (!isFPTruncFromDouble(MRI, FpTruncDef))
+ return false;
+
return true;
}
void applyFpTruncFpTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) {
+ assert(MI.getOpcode() == TargetOpcode::G_FPTRUNC && "Expected G_FPTRUNC");
Register Dst = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg();
+ MachineInstr *ParentDef = getDefIgnoringCopies(Src, MRI);
+ if (!ParentDef)
+ return;
+
LLT V2F32 = LLT::fixed_vector(2, LLT::scalar(32));
LLT V4F32 = LLT::fixed_vector(4, LLT::scalar(32));
LLT V4F16 = LLT::fixed_vector(4, LLT::scalar(16));
B.setInstrAndDebugLoc(MI);
- MachineInstr *ParentDef = getDefIgnoringCopies(Src, MRI);
- if (!ParentDef)
- return;
-
switch (ParentDef->getOpcode()) {
default:
return;
@@ -1056,8 +1056,6 @@ void applyFpTruncFpTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
Register HiFp64 = FpTrunc2Def->getOperand(1).getReg();
MRI.setRegClass(HiFp64, &AArch64::FPR128RegClass);
- B.setInstrAndDebugLoc(MI);
-
// Convert the lower half
Register LoFp32 = MRI.createGenericVirtualRegister(V2F32);
MRI.setRegClass(LoFp32, &AArch64::FPR64RegClass);
>From 43b150983defafe2a1f9f7091cae61bca75de4b3 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 20 Oct 2025 09:35:46 +0000
Subject: [PATCH 03/13] Separate FPEXT & FPTRUNC changes
---
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 18 +-
.../AArch64/GISel/AArch64LegalizerInfo.h | 2 +-
llvm/test/CodeGen/AArch64/fmla.ll | 48 +--
.../CodeGen/AArch64/fp16-v4-instructions.ll | 26 +-
.../CodeGen/AArch64/fp16-v8-instructions.ll | 50 +++-
llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll | 186 +++++++-----
llvm/test/CodeGen/AArch64/fpext.ll | 49 +--
llvm/test/CodeGen/AArch64/fptoi.ll | 278 ++++++++++++------
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 85 ++++--
.../test/CodeGen/AArch64/fptoui-sat-vector.ll | 85 ++++--
10 files changed, 553 insertions(+), 274 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index e188e32b87e04..4f3c8ab2e62e6 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -835,14 +835,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.legalFor(
{{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}})
.libcallFor({{s128, s64}, {s128, s32}, {s128, s16}})
- .moreElementsToNextPow2(0)
- .customIf([](const LegalityQuery &Q) {
- LLT DstTy = Q.Types[0];
- LLT SrcTy = Q.Types[1];
- return SrcTy.isVector() && DstTy.isVector() &&
- SrcTy.getScalarSizeInBits() == 16 &&
- DstTy.getScalarSizeInBits() == 64;
- })
.clampNumElements(0, v4s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
.scalarize(0);
@@ -1482,11 +1474,10 @@ bool AArch64LegalizerInfo::legalizeCustom(
return legalizeICMP(MI, MRI, MIRBuilder);
case TargetOpcode::G_BITCAST:
return legalizeBitcast(MI, Helper);
- case TargetOpcode::G_FPEXT:
case TargetOpcode::G_FPTRUNC:
// In order to vectorise f16 to f64 properly, we need to use f32 as an
// intermediary
- return legalizeFpextFptrunc(MI, MIRBuilder, MRI);
+ return legalizeFptrunc(MI, MIRBuilder, MRI);
}
llvm_unreachable("expected switch to return");
@@ -2414,7 +2405,7 @@ bool AArch64LegalizerInfo::legalizePrefetch(MachineInstr &MI,
return true;
}
-bool AArch64LegalizerInfo::legalizeFpextFptrunc(
+bool AArch64LegalizerInfo::legalizeFptrunc(
MachineInstr &MI, MachineIRBuilder &MIRBuilder,
MachineRegisterInfo &MRI) const {
Register Dst = MI.getOperand(0).getReg();
@@ -2430,11 +2421,6 @@ bool AArch64LegalizerInfo::legalizeFpextFptrunc(
switch (MI.getOpcode()) {
default:
return false;
- case TargetOpcode::G_FPEXT: {
- Mid = MIRBuilder.buildFPExt(MidTy, Src);
- Fin = MIRBuilder.buildFPExt(DstTy, Mid.getReg(0));
- break;
- }
case TargetOpcode::G_FPTRUNC: {
Mid = MIRBuilder.buildFPTrunc(MidTy, Src);
Fin = MIRBuilder.buildFPTrunc(DstTy, Mid.getReg(0));
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
index 15999a44174d3..630f31fd24f28 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
@@ -67,7 +67,7 @@ class AArch64LegalizerInfo : public LegalizerInfo {
bool legalizeDynStackAlloc(MachineInstr &MI, LegalizerHelper &Helper) const;
bool legalizePrefetch(MachineInstr &MI, LegalizerHelper &Helper) const;
bool legalizeBitcast(MachineInstr &MI, LegalizerHelper &Helper) const;
- bool legalizeFpextFptrunc(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
+ bool legalizeFptrunc(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
MachineRegisterInfo &MRI) const;
const AArch64Subtarget *ST;
};
diff --git a/llvm/test/CodeGen/AArch64/fmla.ll b/llvm/test/CodeGen/AArch64/fmla.ll
index 12b6562b5cf0c..a37aabb0b5384 100644
--- a/llvm/test/CodeGen/AArch64/fmla.ll
+++ b/llvm/test/CodeGen/AArch64/fmla.ll
@@ -865,22 +865,22 @@ define <7 x half> @fmuladd_v7f16(<7 x half> %a, <7 x half> %b, <7 x half> %c) {
; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v3.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v5.4h
+; CHECK-GI-NOFP16-NEXT: mov v5.h[0], v2.h[4]
; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v4.4h
; CHECK-GI-NOFP16-NEXT: fadd v0.4s, v0.4s, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[0], v2.h[4]
-; CHECK-GI-NOFP16-NEXT: fmul v3.4s, v3.4s, v4.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtn v4.4h, v0.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn v3.4h, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v2.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[0], v4.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v3.4h
+; CHECK-GI-NOFP16-NEXT: mov v5.h[1], v2.h[5]
+; CHECK-GI-NOFP16-NEXT: fmul v1.4s, v3.4s, v4.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn v3.4h, v0.4s
+; CHECK-GI-NOFP16-NEXT: mov v5.h[2], v2.h[6]
+; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[0], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v5.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v4.h[1]
-; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v2.4s, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v4.h[2]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v3.h[1]
+; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v1.4s, v2.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v3.h[2]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v4.h[3]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v3.h[3]
; CHECK-GI-NOFP16-NEXT: mov v0.h[4], v1.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v1.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[2]
@@ -1350,22 +1350,22 @@ define <7 x half> @fmul_v7f16(<7 x half> %a, <7 x half> %b, <7 x half> %c) {
; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v3.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v5.4h
+; CHECK-GI-NOFP16-NEXT: mov v5.h[0], v2.h[4]
; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v4.4h
; CHECK-GI-NOFP16-NEXT: fadd v0.4s, v0.4s, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[0], v2.h[4]
-; CHECK-GI-NOFP16-NEXT: fmul v3.4s, v3.4s, v4.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtn v4.4h, v0.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn v3.4h, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v2.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[0], v4.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v3.4h
+; CHECK-GI-NOFP16-NEXT: mov v5.h[1], v2.h[5]
+; CHECK-GI-NOFP16-NEXT: fmul v1.4s, v3.4s, v4.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn v3.4h, v0.4s
+; CHECK-GI-NOFP16-NEXT: mov v5.h[2], v2.h[6]
+; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[0], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v5.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v4.h[1]
-; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v2.4s, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v4.h[2]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v3.h[1]
+; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v1.4s, v2.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v3.h[2]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v4.h[3]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v3.h[3]
; CHECK-GI-NOFP16-NEXT: mov v0.h[4], v1.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v1.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[2]
diff --git a/llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll b/llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
index 760742a4efad7..104fca4ef3989 100644
--- a/llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
@@ -206,16 +206,30 @@ define <4 x double> @h_to_d(<4 x half> %a) {
;
; CHECK-CVT-GI-LABEL: h_to_d:
; CHECK-CVT-GI: // %bb.0:
-; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-GI-NEXT: fcvtl v0.2d, v1.2s
-; CHECK-CVT-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-GI-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-GI-NEXT: mov h3, v0.h[3]
+; CHECK-CVT-GI-NEXT: fcvt d0, h0
+; CHECK-CVT-GI-NEXT: fcvt d4, h1
+; CHECK-CVT-GI-NEXT: fcvt d1, h2
+; CHECK-CVT-GI-NEXT: fcvt d2, h3
+; CHECK-CVT-GI-NEXT: mov v0.d[1], v4.d[0]
+; CHECK-CVT-GI-NEXT: mov v1.d[1], v2.d[0]
; CHECK-CVT-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: h_to_d:
; CHECK-FP16-GI: // %bb.0:
-; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-FP16-GI-NEXT: fcvtl v0.2d, v1.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d4, h1
+; CHECK-FP16-GI-NEXT: fcvt d1, h2
+; CHECK-FP16-GI-NEXT: fcvt d2, h3
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT: mov v1.d[1], v2.d[0]
; CHECK-FP16-GI-NEXT: ret
%1 = fpext <4 x half> %a to <4 x double>
ret <4 x double> %1
diff --git a/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll b/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
index 4d8505679c71c..78db49613f1e6 100644
--- a/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
@@ -272,22 +272,48 @@ define <8 x double> @h_to_d(<8 x half> %a) {
;
; CHECK-CVT-GI-LABEL: h_to_d:
; CHECK-CVT-GI: // %bb.0:
-; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-GI-NEXT: fcvtl2 v3.4s, v0.8h
-; CHECK-CVT-GI-NEXT: fcvtl v0.2d, v1.2s
-; CHECK-CVT-GI-NEXT: fcvtl2 v1.2d, v1.4s
-; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v3.2s
-; CHECK-CVT-GI-NEXT: fcvtl2 v3.2d, v3.4s
+; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-GI-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-GI-NEXT: mov h3, v0.h[3]
+; CHECK-CVT-GI-NEXT: mov h4, v0.h[4]
+; CHECK-CVT-GI-NEXT: mov h5, v0.h[5]
+; CHECK-CVT-GI-NEXT: mov h6, v0.h[6]
+; CHECK-CVT-GI-NEXT: mov h7, v0.h[7]
+; CHECK-CVT-GI-NEXT: fcvt d0, h0
+; CHECK-CVT-GI-NEXT: fcvt d16, h1
+; CHECK-CVT-GI-NEXT: fcvt d1, h2
+; CHECK-CVT-GI-NEXT: fcvt d17, h3
+; CHECK-CVT-GI-NEXT: fcvt d2, h4
+; CHECK-CVT-GI-NEXT: fcvt d4, h5
+; CHECK-CVT-GI-NEXT: fcvt d3, h6
+; CHECK-CVT-GI-NEXT: fcvt d5, h7
+; CHECK-CVT-GI-NEXT: mov v0.d[1], v16.d[0]
+; CHECK-CVT-GI-NEXT: mov v1.d[1], v17.d[0]
+; CHECK-CVT-GI-NEXT: mov v2.d[1], v4.d[0]
+; CHECK-CVT-GI-NEXT: mov v3.d[1], v5.d[0]
; CHECK-CVT-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: h_to_d:
; CHECK-FP16-GI: // %bb.0:
-; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-FP16-GI-NEXT: fcvtl2 v3.4s, v0.8h
-; CHECK-FP16-GI-NEXT: fcvtl v0.2d, v1.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v1.2d, v1.4s
-; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v3.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v3.2d, v3.4s
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[4]
+; CHECK-FP16-GI-NEXT: mov h5, v0.h[5]
+; CHECK-FP16-GI-NEXT: mov h6, v0.h[6]
+; CHECK-FP16-GI-NEXT: mov h7, v0.h[7]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d16, h1
+; CHECK-FP16-GI-NEXT: fcvt d1, h2
+; CHECK-FP16-GI-NEXT: fcvt d17, h3
+; CHECK-FP16-GI-NEXT: fcvt d2, h4
+; CHECK-FP16-GI-NEXT: fcvt d4, h5
+; CHECK-FP16-GI-NEXT: fcvt d3, h6
+; CHECK-FP16-GI-NEXT: fcvt d5, h7
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v16.d[0]
+; CHECK-FP16-GI-NEXT: mov v1.d[1], v17.d[0]
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT: mov v3.d[1], v5.d[0]
; CHECK-FP16-GI-NEXT: ret
%1 = fpext <8 x half> %a to <8 x double>
ret <8 x double> %1
diff --git a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
index b075a8b6f70ee..637c02875b84e 100644
--- a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
@@ -285,24 +285,31 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) {
;
; CHECK-FP16-GI-LABEL: stest_f16i32:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
; CHECK-FP16-GI-NEXT: adrp x8, .LCPI6_1
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d1, h1
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v2.2d
; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI6_1]
; CHECK-FP16-GI-NEXT: adrp x8, .LCPI6_0
-; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
-; CHECK-FP16-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
-; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v2.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v2.2d, v1.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI6_0]
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
-; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v4.16b
-; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
@@ -344,17 +351,24 @@ define <4 x i32> @utest_f16i32(<4 x half> %x) {
;
; CHECK-FP16-GI-LABEL: utest_f16i32:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
-; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v0.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: cmhi v3.2d, v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
-; CHECK-FP16-GI-NEXT: bif v2.16b, v1.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v4.16b
-; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: cmhi v3.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmhi v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <4 x half> %x to <4 x i64>
@@ -398,21 +412,28 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
;
; CHECK-FP16-GI-LABEL: ustest_f16i32:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
-; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v0.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v0.2d
-; CHECK-FP16-GI-NEXT: bif v2.16b, v1.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v4.16b
-; CHECK-FP16-GI-NEXT: cmgt v1.2d, v2.2d, #0
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v0.2d, #0
-; CHECK-FP16-GI-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v3.16b
-; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: cmgt v2.2d, v0.2d, #0
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, #0
+; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-FP16-GI-NEXT: and v1.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
@@ -2252,24 +2273,31 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
;
; CHECK-FP16-GI-LABEL: stest_f16i32_mm:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
; CHECK-FP16-GI-NEXT: adrp x8, .LCPI33_1
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d1, h1
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v2.2d
; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI33_1]
; CHECK-FP16-GI-NEXT: adrp x8, .LCPI33_0
-; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
-; CHECK-FP16-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
-; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v2.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v2.2d, v1.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI33_0]
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
-; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v4.16b
-; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
@@ -2309,17 +2337,24 @@ define <4 x i32> @utest_f16i32_mm(<4 x half> %x) {
;
; CHECK-FP16-GI-LABEL: utest_f16i32_mm:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
-; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v0.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: cmhi v3.2d, v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
-; CHECK-FP16-GI-NEXT: bif v2.16b, v1.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v4.16b
-; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: cmhi v3.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmhi v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <4 x half> %x to <4 x i64>
@@ -2362,21 +2397,28 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
;
; CHECK-FP16-GI-LABEL: ustest_f16i32_mm:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
-; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v0.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v0.2d
-; CHECK-FP16-GI-NEXT: bif v2.16b, v1.16b, v3.16b
-; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v4.16b
-; CHECK-FP16-GI-NEXT: cmgt v1.2d, v2.2d, #0
-; CHECK-FP16-GI-NEXT: cmgt v3.2d, v0.2d, #0
-; CHECK-FP16-GI-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v3.16b
-; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: cmgt v2.2d, v0.2d, #0
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, #0
+; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-FP16-GI-NEXT: and v1.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
diff --git a/llvm/test/CodeGen/AArch64/fpext.ll b/llvm/test/CodeGen/AArch64/fpext.ll
index 8980340a447de..df90f9d5f0910 100644
--- a/llvm/test/CodeGen/AArch64/fpext.ll
+++ b/llvm/test/CodeGen/AArch64/fpext.ll
@@ -82,12 +82,11 @@ define <3 x double> @fpext_v3f32_v3f64(<3 x float> %a) {
;
; CHECK-GI-LABEL: fpext_v3f32_v3f64:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov v1.s[0], v0.s[2]
+; CHECK-GI-NEXT: mov s1, v0.s[2]
; CHECK-GI-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-GI-NEXT: fcvtl v2.2d, v1.2s
+; CHECK-GI-NEXT: fcvt d2, s1
; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-GI-NEXT: ret
entry:
%c = fpext <3 x float> %a to <3 x double>
@@ -321,11 +320,20 @@ entry:
}
define <2 x double> @fpext_v2f16_v2f64(<2 x half> %a) {
-; CHECK-LABEL: fpext_v2f16_v2f64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: fpext_v2f16_v2f64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fpext_v2f16_v2f64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NEXT: fcvt d0, h0
+; CHECK-GI-NEXT: fcvt d1, h1
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: ret
entry:
%c = fpext <2 x half> %a to <2 x double>
ret <2 x double> %c
@@ -345,12 +353,12 @@ define <3 x double> @fpext_v3f16_v3f64(<3 x half> %a) {
;
; CHECK-GI-LABEL: fpext_v3f16_v3f64:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-GI-NEXT: fcvtl v0.2d, v1.2s
-; CHECK-GI-NEXT: fcvtl2 v2.2d, v1.4s
-; CHECK-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NEXT: mov h2, v0.h[2]
+; CHECK-GI-NEXT: fcvt d0, h0
+; CHECK-GI-NEXT: fcvt d1, h1
+; CHECK-GI-NEXT: fcvt d2, h2
; CHECK-GI-NEXT: ret
entry:
%c = fpext <3 x half> %a to <3 x double>
@@ -367,9 +375,16 @@ define <4 x double> @fpext_v4f16_v4f64(<4 x half> %a) {
;
; CHECK-GI-LABEL: fpext_v4f16_v4f64:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-GI-NEXT: fcvtl v0.2d, v1.2s
-; CHECK-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NEXT: mov h2, v0.h[2]
+; CHECK-GI-NEXT: mov h3, v0.h[3]
+; CHECK-GI-NEXT: fcvt d0, h0
+; CHECK-GI-NEXT: fcvt d4, h1
+; CHECK-GI-NEXT: fcvt d1, h2
+; CHECK-GI-NEXT: fcvt d2, h3
+; CHECK-GI-NEXT: mov v0.d[1], v4.d[0]
+; CHECK-GI-NEXT: mov v1.d[1], v2.d[0]
; CHECK-GI-NEXT: ret
entry:
%c = fpext <4 x half> %a to <4 x double>
diff --git a/llvm/test/CodeGen/AArch64/fptoi.ll b/llvm/test/CodeGen/AArch64/fptoi.ll
index 3dafabe0b69d7..f6053cee50dae 100644
--- a/llvm/test/CodeGen/AArch64/fptoi.ll
+++ b/llvm/test/CodeGen/AArch64/fptoi.ll
@@ -4610,8 +4610,11 @@ define <2 x i64> @fptos_v2f16_v2i64(<2 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptos_v2f16_v2i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-FP16-GI-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d1, h1
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
; CHECK-FP16-GI-NEXT: ret
entry:
@@ -4651,8 +4654,11 @@ define <2 x i64> @fptou_v2f16_v2i64(<2 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptou_v2f16_v2i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-FP16-GI-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d1, h1
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
; CHECK-FP16-GI-NEXT: ret
entry:
@@ -4704,14 +4710,20 @@ define <3 x i64> @fptos_v3f16_v3i64(<3 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptos_v3f16_v3i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v2.2d, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v1.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v2.2d
-; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvt d1, h0
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: fcvt d2, h3
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v1.d[0]
; CHECK-FP16-GI-NEXT: mov d1, v0.d[1]
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v2.2d
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptosi <3 x half> %a to <3 x i64>
@@ -4762,14 +4774,20 @@ define <3 x i64> @fptou_v3f16_v3i64(<3 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptou_v3f16_v3i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v2.2d, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v1.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v2.2d
-; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvt d1, h0
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: fcvt d2, h3
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v1.d[0]
; CHECK-FP16-GI-NEXT: mov d1, v0.d[1]
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v2.2d
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptoui <3 x half> %a to <3 x i64>
@@ -4824,10 +4842,17 @@ define <4 x i64> @fptos_v4f16_v4i64(<4 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptos_v4f16_v4i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v2.2d, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v1.2d
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d1, h1
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v2.2d
; CHECK-FP16-GI-NEXT: ret
entry:
@@ -4883,10 +4908,17 @@ define <4 x i64> @fptou_v4f16_v4i64(<4 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptou_v4f16_v4i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v2.2d, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v1.2d
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d1, h1
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
; CHECK-FP16-GI-NEXT: fcvtzu v1.2d, v2.2d
; CHECK-FP16-GI-NEXT: ret
entry:
@@ -4973,16 +5005,29 @@ define <8 x i64> @fptos_v8f16_v8i64(<8 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptos_v8f16_v8i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v1.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v1.2d, v1.4s
-; CHECK-FP16-GI-NEXT: fcvtl v3.2d, v0.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v4.2d, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v2.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v3.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v3.2d, v4.2d
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[4]
+; CHECK-FP16-GI-NEXT: mov h5, v0.h[5]
+; CHECK-FP16-GI-NEXT: mov h6, v0.h[6]
+; CHECK-FP16-GI-NEXT: mov h7, v0.h[7]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d1, h1
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: fcvt d5, h5
+; CHECK-FP16-GI-NEXT: fcvt d6, h6
+; CHECK-FP16-GI-NEXT: fcvt d7, h7
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-FP16-GI-NEXT: mov v4.d[1], v5.d[0]
+; CHECK-FP16-GI-NEXT: mov v6.d[1], v7.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v4.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v3.2d, v6.2d
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptosi <8 x half> %a to <8 x i64>
@@ -5068,16 +5113,29 @@ define <8 x i64> @fptou_v8f16_v8i64(<8 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptou_v8f16_v8i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v1.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v1.2d, v1.4s
-; CHECK-FP16-GI-NEXT: fcvtl v3.2d, v0.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v4.2d, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v2.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v1.2d, v1.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v3.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v3.2d, v4.2d
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[4]
+; CHECK-FP16-GI-NEXT: mov h5, v0.h[5]
+; CHECK-FP16-GI-NEXT: mov h6, v0.h[6]
+; CHECK-FP16-GI-NEXT: mov h7, v0.h[7]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d1, h1
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: fcvt d5, h5
+; CHECK-FP16-GI-NEXT: fcvt d6, h6
+; CHECK-FP16-GI-NEXT: fcvt d7, h7
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-FP16-GI-NEXT: mov v4.d[1], v5.d[0]
+; CHECK-FP16-GI-NEXT: mov v6.d[1], v7.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v4.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v3.2d, v6.2d
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptoui <8 x half> %a to <8 x i64>
@@ -5227,26 +5285,52 @@ define <16 x i64> @fptos_v16f16_v16i64(<16 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptos_v16f16_v16i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
-; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-FP16-GI-NEXT: fcvtl v3.4s, v1.4h
-; CHECK-FP16-GI-NEXT: fcvtl2 v1.4s, v1.8h
-; CHECK-FP16-GI-NEXT: fcvtl v4.2d, v2.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v2.2d, v2.4s
-; CHECK-FP16-GI-NEXT: fcvtl v5.2d, v0.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v6.2d, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtl v7.2d, v3.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v16.2d, v3.4s
-; CHECK-FP16-GI-NEXT: fcvtl v17.2d, v1.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v18.2d, v1.4s
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v4.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v5.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v3.2d, v6.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v4.2d, v7.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v5.2d, v16.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v6.2d, v17.2d
-; CHECK-FP16-GI-NEXT: fcvtzs v7.2d, v18.2d
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h5, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d2, h0
+; CHECK-FP16-GI-NEXT: mov h6, v0.h[4]
+; CHECK-FP16-GI-NEXT: mov h7, v0.h[5]
+; CHECK-FP16-GI-NEXT: mov h16, v0.h[6]
+; CHECK-FP16-GI-NEXT: mov h0, v0.h[7]
+; CHECK-FP16-GI-NEXT: mov h17, v1.h[1]
+; CHECK-FP16-GI-NEXT: mov h18, v1.h[2]
+; CHECK-FP16-GI-NEXT: mov h19, v1.h[3]
+; CHECK-FP16-GI-NEXT: mov h20, v1.h[4]
+; CHECK-FP16-GI-NEXT: mov h21, v1.h[5]
+; CHECK-FP16-GI-NEXT: mov h22, v1.h[6]
+; CHECK-FP16-GI-NEXT: mov h23, v1.h[7]
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: fcvt d5, h5
+; CHECK-FP16-GI-NEXT: fcvt d6, h6
+; CHECK-FP16-GI-NEXT: fcvt d7, h7
+; CHECK-FP16-GI-NEXT: fcvt d16, h16
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d24, h1
+; CHECK-FP16-GI-NEXT: fcvt d1, h17
+; CHECK-FP16-GI-NEXT: fcvt d17, h18
+; CHECK-FP16-GI-NEXT: fcvt d18, h19
+; CHECK-FP16-GI-NEXT: fcvt d19, h20
+; CHECK-FP16-GI-NEXT: fcvt d20, h21
+; CHECK-FP16-GI-NEXT: fcvt d21, h22
+; CHECK-FP16-GI-NEXT: fcvt d22, h23
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-FP16-GI-NEXT: mov v4.d[1], v5.d[0]
+; CHECK-FP16-GI-NEXT: mov v6.d[1], v7.d[0]
+; CHECK-FP16-GI-NEXT: mov v16.d[1], v0.d[0]
+; CHECK-FP16-GI-NEXT: mov v24.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT: mov v17.d[1], v18.d[0]
+; CHECK-FP16-GI-NEXT: mov v19.d[1], v20.d[0]
+; CHECK-FP16-GI-NEXT: mov v21.d[1], v22.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v4.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v6.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v3.2d, v16.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v4.2d, v24.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v5.2d, v17.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v6.2d, v19.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v7.2d, v21.2d
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptosi <16 x half> %a to <16 x i64>
@@ -5396,26 +5480,52 @@ define <16 x i64> @fptou_v16f16_v16i64(<16 x half> %a) {
;
; CHECK-FP16-GI-LABEL: fptou_v16f16_v16i64:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
-; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-FP16-GI-NEXT: fcvtl v3.4s, v1.4h
-; CHECK-FP16-GI-NEXT: fcvtl2 v1.4s, v1.8h
-; CHECK-FP16-GI-NEXT: fcvtl v4.2d, v2.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v2.2d, v2.4s
-; CHECK-FP16-GI-NEXT: fcvtl v5.2d, v0.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v6.2d, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtl v7.2d, v3.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v16.2d, v3.4s
-; CHECK-FP16-GI-NEXT: fcvtl v17.2d, v1.2s
-; CHECK-FP16-GI-NEXT: fcvtl2 v18.2d, v1.4s
-; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v4.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v1.2d, v2.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v5.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v3.2d, v6.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v4.2d, v7.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v5.2d, v16.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v6.2d, v17.2d
-; CHECK-FP16-GI-NEXT: fcvtzu v7.2d, v18.2d
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h5, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d2, h0
+; CHECK-FP16-GI-NEXT: mov h6, v0.h[4]
+; CHECK-FP16-GI-NEXT: mov h7, v0.h[5]
+; CHECK-FP16-GI-NEXT: mov h16, v0.h[6]
+; CHECK-FP16-GI-NEXT: mov h0, v0.h[7]
+; CHECK-FP16-GI-NEXT: mov h17, v1.h[1]
+; CHECK-FP16-GI-NEXT: mov h18, v1.h[2]
+; CHECK-FP16-GI-NEXT: mov h19, v1.h[3]
+; CHECK-FP16-GI-NEXT: mov h20, v1.h[4]
+; CHECK-FP16-GI-NEXT: mov h21, v1.h[5]
+; CHECK-FP16-GI-NEXT: mov h22, v1.h[6]
+; CHECK-FP16-GI-NEXT: mov h23, v1.h[7]
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: fcvt d5, h5
+; CHECK-FP16-GI-NEXT: fcvt d6, h6
+; CHECK-FP16-GI-NEXT: fcvt d7, h7
+; CHECK-FP16-GI-NEXT: fcvt d16, h16
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d24, h1
+; CHECK-FP16-GI-NEXT: fcvt d1, h17
+; CHECK-FP16-GI-NEXT: fcvt d17, h18
+; CHECK-FP16-GI-NEXT: fcvt d18, h19
+; CHECK-FP16-GI-NEXT: fcvt d19, h20
+; CHECK-FP16-GI-NEXT: fcvt d20, h21
+; CHECK-FP16-GI-NEXT: fcvt d21, h22
+; CHECK-FP16-GI-NEXT: fcvt d22, h23
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-FP16-GI-NEXT: mov v4.d[1], v5.d[0]
+; CHECK-FP16-GI-NEXT: mov v6.d[1], v7.d[0]
+; CHECK-FP16-GI-NEXT: mov v16.d[1], v0.d[0]
+; CHECK-FP16-GI-NEXT: mov v24.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT: mov v17.d[1], v18.d[0]
+; CHECK-FP16-GI-NEXT: mov v19.d[1], v20.d[0]
+; CHECK-FP16-GI-NEXT: mov v21.d[1], v22.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v1.2d, v4.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v6.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v3.2d, v16.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v4.2d, v24.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v5.2d, v17.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v6.2d, v19.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v7.2d, v21.2d
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptoui <16 x half> %a to <16 x i64>
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index dbcfaff8aee05..b963acd8cb2a1 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -3088,14 +3088,30 @@ define <4 x i64> @test_signed_v4f16_v4i64(<4 x half> %f) {
; CHECK-SD-FP16-NEXT: mov v1.d[1], x11
; CHECK-SD-FP16-NEXT: ret
;
-; CHECK-GI-LABEL: test_signed_v4f16_v4i64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-NEXT: fcvtl v1.2d, v0.2s
-; CHECK-GI-NEXT: fcvtl2 v2.2d, v0.4s
-; CHECK-GI-NEXT: fcvtzs v0.2d, v1.2d
-; CHECK-GI-NEXT: fcvtzs v1.2d, v2.2d
-; CHECK-GI-NEXT: ret
+; CHECK-GI-CVT-LABEL: test_signed_v4f16_v4i64:
+; CHECK-GI-CVT: // %bb.0:
+; CHECK-GI-CVT-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-GI-CVT-NEXT: fcvtl2 v2.2d, v0.4s
+; CHECK-GI-CVT-NEXT: fcvtzs v0.2d, v1.2d
+; CHECK-GI-CVT-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-GI-CVT-NEXT: ret
+;
+; CHECK-GI-FP16-LABEL: test_signed_v4f16_v4i64:
+; CHECK-GI-FP16: // %bb.0:
+; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
+; CHECK-GI-FP16-NEXT: fcvt d0, h0
+; CHECK-GI-FP16-NEXT: fcvt d1, h1
+; CHECK-GI-FP16-NEXT: fcvt d2, h2
+; CHECK-GI-FP16-NEXT: fcvt d3, h3
+; CHECK-GI-FP16-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-FP16-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-GI-FP16-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-FP16-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-GI-FP16-NEXT: ret
%x = call <4 x i64> @llvm.fptosi.sat.v4f16.v4i64(<4 x half> %f)
ret <4 x i64> %x
}
@@ -3781,19 +3797,46 @@ define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
; CHECK-SD-FP16-NEXT: mov v3.d[1], x14
; CHECK-SD-FP16-NEXT: ret
;
-; CHECK-GI-LABEL: test_signed_v8f16_v8i64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-NEXT: fcvtl v2.2d, v1.2s
-; CHECK-GI-NEXT: fcvtl2 v1.2d, v1.4s
-; CHECK-GI-NEXT: fcvtl v3.2d, v0.2s
-; CHECK-GI-NEXT: fcvtl2 v4.2d, v0.4s
-; CHECK-GI-NEXT: fcvtzs v0.2d, v2.2d
-; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d
-; CHECK-GI-NEXT: fcvtzs v2.2d, v3.2d
-; CHECK-GI-NEXT: fcvtzs v3.2d, v4.2d
-; CHECK-GI-NEXT: ret
+; CHECK-GI-CVT-LABEL: test_signed_v8f16_v8i64:
+; CHECK-GI-CVT: // %bb.0:
+; CHECK-GI-CVT-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-CVT-NEXT: fcvtl v2.2d, v1.2s
+; CHECK-GI-CVT-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-GI-CVT-NEXT: fcvtl v3.2d, v0.2s
+; CHECK-GI-CVT-NEXT: fcvtl2 v4.2d, v0.4s
+; CHECK-GI-CVT-NEXT: fcvtzs v0.2d, v2.2d
+; CHECK-GI-CVT-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-GI-CVT-NEXT: fcvtzs v2.2d, v3.2d
+; CHECK-GI-CVT-NEXT: fcvtzs v3.2d, v4.2d
+; CHECK-GI-CVT-NEXT: ret
+;
+; CHECK-GI-FP16-LABEL: test_signed_v8f16_v8i64:
+; CHECK-GI-FP16: // %bb.0:
+; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
+; CHECK-GI-FP16-NEXT: mov h4, v0.h[4]
+; CHECK-GI-FP16-NEXT: mov h5, v0.h[5]
+; CHECK-GI-FP16-NEXT: mov h6, v0.h[6]
+; CHECK-GI-FP16-NEXT: mov h7, v0.h[7]
+; CHECK-GI-FP16-NEXT: fcvt d0, h0
+; CHECK-GI-FP16-NEXT: fcvt d1, h1
+; CHECK-GI-FP16-NEXT: fcvt d2, h2
+; CHECK-GI-FP16-NEXT: fcvt d3, h3
+; CHECK-GI-FP16-NEXT: fcvt d4, h4
+; CHECK-GI-FP16-NEXT: fcvt d5, h5
+; CHECK-GI-FP16-NEXT: fcvt d6, h6
+; CHECK-GI-FP16-NEXT: fcvt d7, h7
+; CHECK-GI-FP16-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-FP16-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-GI-FP16-NEXT: mov v4.d[1], v5.d[0]
+; CHECK-GI-FP16-NEXT: mov v6.d[1], v7.d[0]
+; CHECK-GI-FP16-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-FP16-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-GI-FP16-NEXT: fcvtzs v2.2d, v4.2d
+; CHECK-GI-FP16-NEXT: fcvtzs v3.2d, v6.2d
+; CHECK-GI-FP16-NEXT: ret
%x = call <8 x i64> @llvm.fptosi.sat.v8f16.v8i64(<8 x half> %f)
ret <8 x i64> %x
}
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index 44e6e9415263b..5a66b68af8e96 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -2506,14 +2506,30 @@ define <4 x i64> @test_unsigned_v4f16_v4i64(<4 x half> %f) {
; CHECK-SD-FP16-NEXT: mov v1.d[1], x11
; CHECK-SD-FP16-NEXT: ret
;
-; CHECK-GI-LABEL: test_unsigned_v4f16_v4i64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-NEXT: fcvtl v1.2d, v0.2s
-; CHECK-GI-NEXT: fcvtl2 v2.2d, v0.4s
-; CHECK-GI-NEXT: fcvtzu v0.2d, v1.2d
-; CHECK-GI-NEXT: fcvtzu v1.2d, v2.2d
-; CHECK-GI-NEXT: ret
+; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i64:
+; CHECK-GI-CVT: // %bb.0:
+; CHECK-GI-CVT-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-GI-CVT-NEXT: fcvtl2 v2.2d, v0.4s
+; CHECK-GI-CVT-NEXT: fcvtzu v0.2d, v1.2d
+; CHECK-GI-CVT-NEXT: fcvtzu v1.2d, v2.2d
+; CHECK-GI-CVT-NEXT: ret
+;
+; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i64:
+; CHECK-GI-FP16: // %bb.0:
+; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
+; CHECK-GI-FP16-NEXT: fcvt d0, h0
+; CHECK-GI-FP16-NEXT: fcvt d1, h1
+; CHECK-GI-FP16-NEXT: fcvt d2, h2
+; CHECK-GI-FP16-NEXT: fcvt d3, h3
+; CHECK-GI-FP16-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-FP16-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-GI-FP16-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-GI-FP16-NEXT: fcvtzu v1.2d, v2.2d
+; CHECK-GI-FP16-NEXT: ret
%x = call <4 x i64> @llvm.fptoui.sat.v4f16.v4i64(<4 x half> %f)
ret <4 x i64> %x
}
@@ -3098,19 +3114,46 @@ define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; CHECK-SD-FP16-NEXT: mov v3.d[1], x14
; CHECK-SD-FP16-NEXT: ret
;
-; CHECK-GI-LABEL: test_unsigned_v8f16_v8i64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-NEXT: fcvtl v2.2d, v1.2s
-; CHECK-GI-NEXT: fcvtl2 v1.2d, v1.4s
-; CHECK-GI-NEXT: fcvtl v3.2d, v0.2s
-; CHECK-GI-NEXT: fcvtl2 v4.2d, v0.4s
-; CHECK-GI-NEXT: fcvtzu v0.2d, v2.2d
-; CHECK-GI-NEXT: fcvtzu v1.2d, v1.2d
-; CHECK-GI-NEXT: fcvtzu v2.2d, v3.2d
-; CHECK-GI-NEXT: fcvtzu v3.2d, v4.2d
-; CHECK-GI-NEXT: ret
+; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i64:
+; CHECK-GI-CVT: // %bb.0:
+; CHECK-GI-CVT-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-CVT-NEXT: fcvtl v2.2d, v1.2s
+; CHECK-GI-CVT-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-GI-CVT-NEXT: fcvtl v3.2d, v0.2s
+; CHECK-GI-CVT-NEXT: fcvtl2 v4.2d, v0.4s
+; CHECK-GI-CVT-NEXT: fcvtzu v0.2d, v2.2d
+; CHECK-GI-CVT-NEXT: fcvtzu v1.2d, v1.2d
+; CHECK-GI-CVT-NEXT: fcvtzu v2.2d, v3.2d
+; CHECK-GI-CVT-NEXT: fcvtzu v3.2d, v4.2d
+; CHECK-GI-CVT-NEXT: ret
+;
+; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i64:
+; CHECK-GI-FP16: // %bb.0:
+; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
+; CHECK-GI-FP16-NEXT: mov h4, v0.h[4]
+; CHECK-GI-FP16-NEXT: mov h5, v0.h[5]
+; CHECK-GI-FP16-NEXT: mov h6, v0.h[6]
+; CHECK-GI-FP16-NEXT: mov h7, v0.h[7]
+; CHECK-GI-FP16-NEXT: fcvt d0, h0
+; CHECK-GI-FP16-NEXT: fcvt d1, h1
+; CHECK-GI-FP16-NEXT: fcvt d2, h2
+; CHECK-GI-FP16-NEXT: fcvt d3, h3
+; CHECK-GI-FP16-NEXT: fcvt d4, h4
+; CHECK-GI-FP16-NEXT: fcvt d5, h5
+; CHECK-GI-FP16-NEXT: fcvt d6, h6
+; CHECK-GI-FP16-NEXT: fcvt d7, h7
+; CHECK-GI-FP16-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-FP16-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-GI-FP16-NEXT: mov v4.d[1], v5.d[0]
+; CHECK-GI-FP16-NEXT: mov v6.d[1], v7.d[0]
+; CHECK-GI-FP16-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-GI-FP16-NEXT: fcvtzu v1.2d, v2.2d
+; CHECK-GI-FP16-NEXT: fcvtzu v2.2d, v4.2d
+; CHECK-GI-FP16-NEXT: fcvtzu v3.2d, v6.2d
+; CHECK-GI-FP16-NEXT: ret
%x = call <8 x i64> @llvm.fptoui.sat.v8f16.v8i64(<8 x half> %f)
ret <8 x i64> %x
}
>From 437caa32c29e85fd54c844c02b0d38203d3a8b06 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Tue, 21 Oct 2025 08:13:04 +0000
Subject: [PATCH 04/13] Add new opcode for rounding to odd
---
.../llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 14 ++++++++++++++
llvm/include/llvm/Support/TargetOpcodes.def | 3 +++
llvm/include/llvm/Target/GenericOpcodes.td | 6 ++++++
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 1 +
llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 6 ++++++
.../Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 7 ++++++-
6 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 40c7792f7e8a2..1e39b1f4452c6 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1332,6 +1332,20 @@ class LLVM_ABI MachineIRBuilder {
buildFPTrunc(const DstOp &Res, const SrcOp &Op,
std::optional<unsigned> Flags = std::nullopt);
+ /// Build and insert \p Res = G_FPTRUNC_ODD \p Op
+ ///
+ /// G_FPTRUNC_ODD converts a floating-point value into one with a smaller type using round to odd.
+ ///
+ /// \pre setBasicBlock or setMI must have been called.
+ /// \pre \p Res must be a generic virtual register with scalar or vector type.
+ /// \pre \p Op must be a generic virtual register with scalar or vector type.
+ /// \pre \p Res must be smaller than \p Op
+ ///
+ /// \return The newly created instruction.
+ MachineInstrBuilder
+ buildFPTruncOdd(const DstOp &Res, const SrcOp &Op,
+ std::optional<unsigned> Flags = std::nullopt);
+
/// Build and insert \p Res = G_TRUNC \p Op
///
/// G_TRUNC extracts the low bits of a type. For a vector type each element is
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index e55314568d683..198499b7f4b30 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -692,6 +692,9 @@ HANDLE_TARGET_OPCODE(G_FPEXT)
/// Generic float to signed-int conversion
HANDLE_TARGET_OPCODE(G_FPTRUNC)
+/// Generic float to signed-int conversion using round to odd
+HANDLE_TARGET_OPCODE(G_FPTRUNC_ODD)
+
/// Generic float to signed-int conversion
HANDLE_TARGET_OPCODE(G_FPTOSI)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index e3f995d53484f..f083bd9312983 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -782,6 +782,12 @@ def G_FPTRUNC : GenericInstruction {
let hasSideEffects = false;
}
+def G_FPTRUNC_ODD : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type1:$src);
+ let hasSideEffects = false;
+}
+
def G_FPTOSI : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 52c43a4ac4a04..450fe3220e1c2 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -5595,6 +5595,7 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
case G_ANYEXT:
case G_FPEXT:
case G_FPTRUNC:
+ case G_FPTRUNC_ODD:
case G_SITOFP:
case G_UITOFP:
case G_FPTOSI:
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 4b4df98024f4a..b96bb442f3e63 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -936,6 +936,12 @@ MachineIRBuilder::buildFPTrunc(const DstOp &Res, const SrcOp &Op,
return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op, Flags);
}
+MachineInstrBuilder
+MachineIRBuilder::buildFPTruncOdd(const DstOp &Res, const SrcOp &Op,
+ std::optional<unsigned> Flags) {
+ return buildInstr(TargetOpcode::G_FPTRUNC_ODD, Res, Op, Flags);
+}
+
MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
const DstOp &Res,
const SrcOp &Op0,
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 4f3c8ab2e62e6..576a9b090a4ca 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -831,6 +831,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampNumElements(1, v2s64, v2s64)
.scalarize(0);
+ getActionDefinitionsBuilder(G_FPTRUNC_ODD)
+ .legalFor({{s16, s32}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}})
+ .clampMaxNumElements(1, s32, 4)
+ .clampMaxNumElements(1, s64, 2);
+
getActionDefinitionsBuilder(G_FPEXT)
.legalFor(
{{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}})
@@ -2422,7 +2427,7 @@ bool AArch64LegalizerInfo::legalizeFptrunc(
default:
return false;
case TargetOpcode::G_FPTRUNC: {
- Mid = MIRBuilder.buildFPTrunc(MidTy, Src);
+ Mid = MIRBuilder.buildFPTruncOdd(MidTy, Src);
Fin = MIRBuilder.buildFPTrunc(DstTy, Mid.getReg(0));
break;
}
>From 6abe127fce38bfed4c54b5353f2d686417ea9b5f Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Tue, 21 Oct 2025 08:49:29 +0000
Subject: [PATCH 05/13] Disable combiner
---
llvm/lib/Target/AArch64/AArch64Combine.td | 14 +++++++-------
.../AArch64/GISel/AArch64PostLegalizerLowering.cpp | 2 +-
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index e70bf43a842b4..45a10d16bcd87 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -332,12 +332,12 @@ def combine_mul_cmlt : GICombineRule<
(apply [{ applyCombineMulCMLT(*${root}, MRI, B, ${matchinfo}); }])
>;
-def lower_fptrunc_fptrunc: GICombineRule<
- (defs root:$root),
- (match (wip_match_opcode G_FPTRUNC):$root,
- [{ return matchFpTruncFpTrunc(*${root}, MRI); }]),
- (apply [{ applyFpTruncFpTrunc(*${root}, MRI, B); }])
->;
+// def lower_fptrunc_fptrunc: GICombineRule<
+// (defs root:$root),
+// (match (wip_match_opcode G_FPTRUNC):$root,
+// [{ return matchFpTruncFpTrunc(*${root}, MRI); }]),
+// (apply [{ applyFpTruncFpTrunc(*${root}, MRI, B); }])
+// >;
// Post-legalization combines which should happen at all optimization levels.
// (E.g. ones that facilitate matching for the selector) For example, matching
@@ -347,7 +347,7 @@ def AArch64PostLegalizerLowering
[shuffle_vector_lowering, vashr_vlshr_imm,
icmp_lowering, build_vector_lowering,
lower_vector_fcmp, form_truncstore, fconstant_to_constant,
- vector_sext_inreg_to_shift, lower_fptrunc_fptrunc,
+ vector_sext_inreg_to_shift,
unmerge_ext_to_unmerge, lower_mulv2s64,
vector_unmerge_lowering, insertelt_nonconst,
unmerge_duplanes]> {
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 2fa1b86a8a9c6..8e84a8e472eca 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -905,7 +905,7 @@ unsigned getCmpOperandFoldingProfit(Register CmpOp, MachineRegisterInfo &MRI) {
// Checks that the given definition belongs to an FPTRUNC and that the source is
// not an integer, as no rounding is necessary due to the range of values
bool isFPTruncFromDouble(MachineRegisterInfo &MRI, MachineInstr *MaybeFpTrunc) {
- if (!MaybeFpTrunc || MaybeFpTrunc->getOpcode() != TargetOpcode::G_FPTRUNC)
+ if (!MaybeFpTrunc || MaybeFpTrunc->getOpcode() != TargetOpcode::G_FPTRUNC_ODD)
return false;
// Check the source is 64 bits as we only want to match a very specific
>From 13fc5dc3c31d38e29001167df64ead77cff475ac Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Tue, 21 Oct 2025 08:49:38 +0000
Subject: [PATCH 06/13] Use tablegen for matching
---
llvm/lib/Target/AArch64/AArch64InstrGISel.td | 2 +
.../CodeGen/AArch64/fp16-v8-instructions.ll | 48 ++++---------------
llvm/test/CodeGen/AArch64/fptrunc.ll | 18 +++++--
3 files changed, 24 insertions(+), 44 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index 30b7b03f7a69a..576db35b88c14 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -290,6 +290,8 @@ def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
def : GINodeEquiv<G_AARCH64_PREFETCH, AArch64Prefetch>;
+def : GINodeEquiv<G_FPTRUNC_ODD, AArch64fcvtxn_n>;
+
// These are patterns that we only use for GlobalISel via the importer.
def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
(vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
diff --git a/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll b/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
index 78db49613f1e6..0d138e59089c0 100644
--- a/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
@@ -176,45 +176,15 @@ define <8 x half> @s_to_h(<8 x float> %a) {
}
define <8 x half> @d_to_h(<8 x double> %a) {
-; CHECK-CVT-SD-LABEL: d_to_h:
-; CHECK-CVT-SD: // %bb.0:
-; CHECK-CVT-SD-NEXT: fcvtxn v0.2s, v0.2d
-; CHECK-CVT-SD-NEXT: fcvtxn v2.2s, v2.2d
-; CHECK-CVT-SD-NEXT: fcvtxn2 v0.4s, v1.2d
-; CHECK-CVT-SD-NEXT: fcvtxn2 v2.4s, v3.2d
-; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v0.4s
-; CHECK-CVT-SD-NEXT: fcvtn2 v0.8h, v2.4s
-; CHECK-CVT-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: d_to_h:
-; CHECK-FP16-SD: // %bb.0:
-; CHECK-FP16-SD-NEXT: fcvtxn v0.2s, v0.2d
-; CHECK-FP16-SD-NEXT: fcvtxn v2.2s, v2.2d
-; CHECK-FP16-SD-NEXT: fcvtxn2 v0.4s, v1.2d
-; CHECK-FP16-SD-NEXT: fcvtxn2 v2.4s, v3.2d
-; CHECK-FP16-SD-NEXT: fcvtn v0.4h, v0.4s
-; CHECK-FP16-SD-NEXT: fcvtn2 v0.8h, v2.4s
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-CVT-GI-LABEL: d_to_h:
-; CHECK-CVT-GI: // %bb.0:
-; CHECK-CVT-GI-NEXT: fcvtxn v0.2s, v0.2d
-; CHECK-CVT-GI-NEXT: fcvtxn2 v0.4s, v1.2d
-; CHECK-CVT-GI-NEXT: fcvtxn v1.2s, v2.2d
-; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v0.4s
-; CHECK-CVT-GI-NEXT: fcvtxn2 v1.4s, v3.2d
-; CHECK-CVT-GI-NEXT: fcvtn2 v0.8h, v1.4s
-; CHECK-CVT-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: d_to_h:
-; CHECK-FP16-GI: // %bb.0:
-; CHECK-FP16-GI-NEXT: fcvtxn v0.2s, v0.2d
-; CHECK-FP16-GI-NEXT: fcvtxn2 v0.4s, v1.2d
-; CHECK-FP16-GI-NEXT: fcvtxn v1.2s, v2.2d
-; CHECK-FP16-GI-NEXT: fcvtn v0.4h, v0.4s
-; CHECK-FP16-GI-NEXT: fcvtxn2 v1.4s, v3.2d
-; CHECK-FP16-GI-NEXT: fcvtn2 v0.8h, v1.4s
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: d_to_h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtxn v0.2s, v0.2d
+; CHECK-NEXT: fcvtxn v2.2s, v2.2d
+; CHECK-NEXT: fcvtxn2 v0.4s, v1.2d
+; CHECK-NEXT: fcvtxn2 v2.4s, v3.2d
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: fcvtn2 v0.8h, v2.4s
+; CHECK-NEXT: ret
%1 = fptrunc <8 x double> %a to <8 x half>
ret <8 x half> %1
}
diff --git a/llvm/test/CodeGen/AArch64/fptrunc.ll b/llvm/test/CodeGen/AArch64/fptrunc.ll
index de780bf475138..aaaa7e2c599fa 100644
--- a/llvm/test/CodeGen/AArch64/fptrunc.ll
+++ b/llvm/test/CodeGen/AArch64/fptrunc.ll
@@ -277,11 +277,19 @@ entry:
}
define <2 x half> @fptrunc_v2f64_v2f16(<2 x double> %a) {
-; CHECK-LABEL: fptrunc_v2f64_v2f16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtxn v0.2s, v0.2d
-; CHECK-NEXT: fcvtn v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: fptrunc_v2f64_v2f16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtxn v0.2s, v0.2d
+; CHECK-SD-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fptrunc_v2f64_v2f16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtxn v0.2s, v0.2d
+; CHECK-GI-NEXT: mov v1.s[0], v0.s[0]
+; CHECK-GI-NEXT: mov v1.s[1], v0.s[1]
+; CHECK-GI-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-GI-NEXT: ret
entry:
%c = fptrunc <2 x double> %a to <2 x half>
ret <2 x half> %c
>From 0ceacd7c7f62d5922fa6bcf56850225719556f0f Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Tue, 21 Oct 2025 09:02:31 +0000
Subject: [PATCH 07/13] Remove unused code
---
llvm/lib/Target/AArch64/AArch64Combine.td | 7 -
.../GISel/AArch64PostLegalizerLowering.cpp | 192 ------------------
2 files changed, 199 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index 45a10d16bcd87..278314792bfb9 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -332,13 +332,6 @@ def combine_mul_cmlt : GICombineRule<
(apply [{ applyCombineMulCMLT(*${root}, MRI, B, ${matchinfo}); }])
>;
-// def lower_fptrunc_fptrunc: GICombineRule<
-// (defs root:$root),
-// (match (wip_match_opcode G_FPTRUNC):$root,
-// [{ return matchFpTruncFpTrunc(*${root}, MRI); }]),
-// (apply [{ applyFpTruncFpTrunc(*${root}, MRI, B); }])
-// >;
-
// Post-legalization combines which should happen at all optimization levels.
// (E.g. ones that facilitate matching for the selector) For example, matching
// pseudos.
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 8e84a8e472eca..23dcaea2ac1a4 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -901,198 +901,6 @@ unsigned getCmpOperandFoldingProfit(Register CmpOp, MachineRegisterInfo &MRI) {
return 0;
}
-// Helper function for matchFpTruncFpTrunc.
-// Checks that the given definition belongs to an FPTRUNC and that the source is
-// not an integer, as no rounding is necessary due to the range of values
-bool isFPTruncFromDouble(MachineRegisterInfo &MRI, MachineInstr *MaybeFpTrunc) {
- if (!MaybeFpTrunc || MaybeFpTrunc->getOpcode() != TargetOpcode::G_FPTRUNC_ODD)
- return false;
-
- // Check the source is 64 bits as we only want to match a very specific
- // pattern
- Register FpTruncSrc = MaybeFpTrunc->getOperand(1).getReg();
- LLT SrcTy = MRI.getType(FpTruncSrc);
- if (SrcTy.getScalarSizeInBits() != 64)
- return false;
-
- // Need to check the float didn't come from an int as no rounding is
- // neccessary
- MachineInstr *FpTruncSrcDef = getDefIgnoringCopies(FpTruncSrc, MRI);
- if (FpTruncSrcDef->getOpcode() == TargetOpcode::G_SITOFP ||
- FpTruncSrcDef->getOpcode() == TargetOpcode::G_UITOFP)
- return false;
-
- return true;
-}
-
-// To avoid double rounding issues we need to lower FPTRUNC(FPTRUNC) to an odd
-// rounding truncate and a normal truncate. When
-// truncating an FP that came from an integer this is not a problem as the range
-// of values is lower in the int
-bool matchFpTruncFpTrunc(MachineInstr &MI, MachineRegisterInfo &MRI) {
- assert(MI.getOpcode() == TargetOpcode::G_FPTRUNC && "Expected G_FPTRUNC");
-
- // Check the destination is 16 bits as we only want to match a very specific
- // pattern
- Register Dst = MI.getOperand(0).getReg();
- LLT DstTy = MRI.getType(Dst);
- if (DstTy.getScalarSizeInBits() != 16)
- return false;
-
- Register Src = MI.getOperand(1).getReg();
-
- MachineInstr *ParentDef = getDefIgnoringCopies(Src, MRI);
- if (!ParentDef)
- return false;
-
- MachineInstr *FpTruncDef;
- switch (ParentDef->getOpcode()) {
- default:
- return false;
- case TargetOpcode::G_CONCAT_VECTORS: {
- // Expecting exactly two FPTRUNCs
- if (ParentDef->getNumOperands() != 3)
- return false;
-
- // All operands need to be FPTRUNC
- for (unsigned OpIdx = 1, NumOperands = ParentDef->getNumOperands();
- OpIdx != NumOperands; ++OpIdx) {
- Register FpTruncDst = ParentDef->getOperand(OpIdx).getReg();
- FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
-
- if (!isFPTruncFromDouble(MRI, FpTruncDef))
- return false;
- }
-
- return true;
- }
- // This is to match cases in which vectors are widened to a larger size
- case TargetOpcode::G_INSERT_VECTOR_ELT: {
- Register VecExtractDst = ParentDef->getOperand(2).getReg();
- MachineInstr *VecExtractDef = getDefIgnoringCopies(VecExtractDst, MRI);
-
- if (!VecExtractDef ||
- VecExtractDef->getOpcode() != TargetOpcode::G_EXTRACT_VECTOR_ELT)
- return false;
-
- Register FpTruncDst = VecExtractDef->getOperand(1).getReg();
- FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
- break;
- }
- case TargetOpcode::G_FPTRUNC: {
- Register FpTruncDst = ParentDef->getOperand(1).getReg();
- FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
- break;
- }
- }
-
- if (!isFPTruncFromDouble(MRI, FpTruncDef))
- return false;
-
- return true;
-}
-
-void applyFpTruncFpTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &B) {
- assert(MI.getOpcode() == TargetOpcode::G_FPTRUNC && "Expected G_FPTRUNC");
- Register Dst = MI.getOperand(0).getReg();
- Register Src = MI.getOperand(1).getReg();
-
- MachineInstr *ParentDef = getDefIgnoringCopies(Src, MRI);
- if (!ParentDef)
- return;
-
- LLT V2F32 = LLT::fixed_vector(2, LLT::scalar(32));
- LLT V4F32 = LLT::fixed_vector(4, LLT::scalar(32));
- LLT V4F16 = LLT::fixed_vector(4, LLT::scalar(16));
-
- B.setInstrAndDebugLoc(MI);
-
- switch (ParentDef->getOpcode()) {
- default:
- return;
- case TargetOpcode::G_INSERT_VECTOR_ELT: {
- Register VecExtractDst = ParentDef->getOperand(2).getReg();
- MachineInstr *VecExtractDef = getDefIgnoringCopies(VecExtractDst, MRI);
-
- Register FpTruncDst = VecExtractDef->getOperand(1).getReg();
- MachineInstr *FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
-
- Register FpTruncSrc = FpTruncDef->getOperand(1).getReg();
- MRI.setRegClass(FpTruncSrc, &AArch64::FPR128RegClass);
-
- Register Fp32 = MRI.createGenericVirtualRegister(V2F32);
- MRI.setRegClass(Fp32, &AArch64::FPR64RegClass);
-
- B.buildInstr(AArch64::FCVTXNv2f32, {Fp32}, {FpTruncSrc});
-
- // Only 4f32 -> 4f16 is legal so we need to mimic that situation
- Register Fp32Padding = B.buildUndef(V2F32).getReg(0);
- MRI.setRegClass(Fp32Padding, &AArch64::FPR64RegClass);
-
- Register Fp32Full = MRI.createGenericVirtualRegister(V4F32);
- MRI.setRegClass(Fp32Full, &AArch64::FPR128RegClass);
- B.buildConcatVectors(Fp32Full, {Fp32, Fp32Padding});
-
- Register Fp16 = MRI.createGenericVirtualRegister(V4F16);
- MRI.setRegClass(Fp16, &AArch64::FPR64RegClass);
- B.buildFPTrunc(Fp16, Fp32Full);
-
- MRI.replaceRegWith(Dst, Fp16);
- MI.eraseFromParent();
- break;
- }
- case TargetOpcode::G_CONCAT_VECTORS: {
- // Get the two FP Truncs that are being concatenated
- Register FpTrunc1Dst = ParentDef->getOperand(1).getReg();
- Register FpTrunc2Dst = ParentDef->getOperand(2).getReg();
-
- MachineInstr *FpTrunc1Def = getDefIgnoringCopies(FpTrunc1Dst, MRI);
- MachineInstr *FpTrunc2Def = getDefIgnoringCopies(FpTrunc2Dst, MRI);
-
- // Make the registers 128bit to store the 2 doubles
- Register LoFp64 = FpTrunc1Def->getOperand(1).getReg();
- MRI.setRegClass(LoFp64, &AArch64::FPR128RegClass);
- Register HiFp64 = FpTrunc2Def->getOperand(1).getReg();
- MRI.setRegClass(HiFp64, &AArch64::FPR128RegClass);
-
- // Convert the lower half
- Register LoFp32 = MRI.createGenericVirtualRegister(V2F32);
- MRI.setRegClass(LoFp32, &AArch64::FPR64RegClass);
- B.buildInstr(AArch64::FCVTXNv2f32, {LoFp32}, {LoFp64});
-
- // Create a register for the high half to use
- Register AccUndef = MRI.createGenericVirtualRegister(V4F32);
- MRI.setRegClass(AccUndef, &AArch64::FPR128RegClass);
- B.buildUndef(AccUndef);
-
- Register Acc = MRI.createGenericVirtualRegister(V4F32);
- MRI.setRegClass(Acc, &AArch64::FPR128RegClass);
- B.buildInstr(TargetOpcode::INSERT_SUBREG)
- .addDef(Acc)
- .addUse(AccUndef)
- .addUse(LoFp32)
- .addImm(AArch64::dsub);
-
- // Convert the high half
- Register AccOut = MRI.createGenericVirtualRegister(V4F32);
- MRI.setRegClass(AccOut, &AArch64::FPR128RegClass);
- B.buildInstr(AArch64::FCVTXNv4f32)
- .addDef(AccOut)
- .addUse(Acc)
- .addUse(HiFp64);
-
- Register Fp16 = MRI.createGenericVirtualRegister(V4F16);
- MRI.setRegClass(Fp16, &AArch64::FPR64RegClass);
- B.buildFPTrunc(Fp16, AccOut);
-
- MRI.replaceRegWith(Dst, Fp16);
- MI.eraseFromParent();
- break;
- }
- }
-}
-
/// \returns true if it would be profitable to swap the LHS and RHS of a G_ICMP
/// instruction \p MI.
bool trySwapICmpOperands(MachineInstr &MI, MachineRegisterInfo &MRI) {
>From 8b857442b31a138a25a7c92079201c0d905393ab Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Tue, 28 Oct 2025 11:29:06 +0000
Subject: [PATCH 08/13] Update tests
---
.../GlobalISel/legalizer-info-validation.mir | 7 +-
.../GlobalISel/legalizer-info-validation.mir | 3 +
.../match-table-cxx.td | 132 +++++++++---------
.../GlobalISelEmitter/GlobalISelEmitter.td | 2 +-
llvm/test/TableGen/get-named-operand-idx.td | 3 +-
5 files changed, 77 insertions(+), 70 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 0561f91b6e015..5207921a79e47 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -555,11 +555,14 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_FPEXT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. the first uncovered type index: 2, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_FPTRUNC (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: G_FPTRUNC_ODD (opcode 204): 2 type indices, 0 imm indices
+# DEBUG-NEXT: .. the first uncovered type index: 2, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_FPTOSI (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
index da7546e12e58b..d3694c02bab78 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
@@ -556,6 +556,9 @@
# DEBUG-NEXT: G_FPTRUNC (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: G_FPTRUNC_ODD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_FPTOSI (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
index 18960b43ab97d..bf19f479b6104 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
@@ -96,71 +96,71 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const {
// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = {
-// CHECK-NEXT: /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(99), GIMT_Encode2(211), /*)*//*default:*//*Label 5*/ GIMT_Encode4(524),
-// CHECK-NEXT: /* 10 */ /*TargetOpcode::G_STORE*//*Label 0*/ GIMT_Encode4(458), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
-// CHECK-NEXT: /* 182 */ /*TargetOpcode::G_SEXT*//*Label 1*/ GIMT_Encode4(476), GIMT_Encode4(0),
-// CHECK-NEXT: /* 190 */ /*TargetOpcode::G_ZEXT*//*Label 2*/ GIMT_Encode4(488), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
-// CHECK-NEXT: /* 418 */ /*TargetOpcode::G_FNEG*//*Label 3*/ GIMT_Encode4(500), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
-// CHECK-NEXT: /* 454 */ /*TargetOpcode::G_FABS*//*Label 4*/ GIMT_Encode4(512),
-// CHECK-NEXT: /* 458 */ // Label 0: @458
-// CHECK-NEXT: /* 458 */ GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(475), // Rule ID 2 //
-// CHECK-NEXT: /* 463 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule2Enabled),
-// CHECK-NEXT: /* 466 */ // MIs[0] x
-// CHECK-NEXT: /* 466 */ // No operand predicates
-// CHECK-NEXT: /* 466 */ // MIs[0] y
-// CHECK-NEXT: /* 466 */ // No operand predicates
-// CHECK-NEXT: /* 466 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner0),
-// CHECK-NEXT: /* 470 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner1),
-// CHECK-NEXT: /* 474 */ // Combiner Rule #2: TwoMatchNoApply
-// CHECK-NEXT: /* 474 */ GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: /* 475 */ // Label 6: @475
-// CHECK-NEXT: /* 475 */ GIM_Reject,
-// CHECK-NEXT: /* 476 */ // Label 1: @476
-// CHECK-NEXT: /* 476 */ GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(487), // Rule ID 3 //
-// CHECK-NEXT: /* 481 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule3Enabled),
-// CHECK-NEXT: /* 484 */ // MIs[0] a
-// CHECK-NEXT: /* 484 */ // No operand predicates
-// CHECK-NEXT: /* 484 */ // MIs[0] y
-// CHECK-NEXT: /* 484 */ // No operand predicates
-// CHECK-NEXT: /* 484 */ // Combiner Rule #3: NoMatchTwoApply
-// CHECK-NEXT: /* 484 */ GIR_DoneWithCustomAction, /*Fn*/GIMT_Encode2(GICXXCustomAction_GICombiner2),
-// CHECK-NEXT: /* 487 */ // Label 7: @487
-// CHECK-NEXT: /* 487 */ GIM_Reject,
-// CHECK-NEXT: /* 488 */ // Label 2: @488
-// CHECK-NEXT: /* 488 */ GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(499), // Rule ID 4 //
-// CHECK-NEXT: /* 493 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule4Enabled),
-// CHECK-NEXT: /* 496 */ // MIs[0] a
-// CHECK-NEXT: /* 496 */ // No operand predicates
-// CHECK-NEXT: /* 496 */ // MIs[0] y
-// CHECK-NEXT: /* 496 */ // No operand predicates
-// CHECK-NEXT: /* 496 */ // Combiner Rule #4: CombineCXXOrder
-// CHECK-NEXT: /* 496 */ GIR_DoneWithCustomAction, /*Fn*/GIMT_Encode2(GICXXCustomAction_GICombiner3),
-// CHECK-NEXT: /* 499 */ // Label 8: @499
-// CHECK-NEXT: /* 499 */ GIM_Reject,
-// CHECK-NEXT: /* 500 */ // Label 3: @500
-// CHECK-NEXT: /* 500 */ GIM_Try, /*On fail goto*//*Label 9*/ GIMT_Encode4(511), // Rule ID 1 //
-// CHECK-NEXT: /* 505 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule1Enabled),
-// CHECK-NEXT: /* 508 */ // MIs[0] a
-// CHECK-NEXT: /* 508 */ // No operand predicates
-// CHECK-NEXT: /* 508 */ // MIs[0] b
-// CHECK-NEXT: /* 508 */ // No operand predicates
-// CHECK-NEXT: /* 508 */ // Combiner Rule #1: TwoMatchTwoApply
-// CHECK-NEXT: /* 508 */ GIR_DoneWithCustomAction, /*Fn*/GIMT_Encode2(GICXXCustomAction_GICombiner1),
-// CHECK-NEXT: /* 511 */ // Label 9: @511
-// CHECK-NEXT: /* 511 */ GIM_Reject,
-// CHECK-NEXT: /* 512 */ // Label 4: @512
-// CHECK-NEXT: /* 512 */ GIM_Try, /*On fail goto*//*Label 10*/ GIMT_Encode4(523), // Rule ID 0 //
-// CHECK-NEXT: /* 517 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled),
-// CHECK-NEXT: /* 520 */ // MIs[0] a
-// CHECK-NEXT: /* 520 */ // No operand predicates
-// CHECK-NEXT: /* 520 */ // MIs[0] b
-// CHECK-NEXT: /* 520 */ // No operand predicates
-// CHECK-NEXT: /* 520 */ // Combiner Rule #0: OneMatchOneApply
-// CHECK-NEXT: /* 520 */ GIR_DoneWithCustomAction, /*Fn*/GIMT_Encode2(GICXXCustomAction_GICombiner0),
-// CHECK-NEXT: /* 523 */ // Label 10: @523
-// CHECK-NEXT: /* 523 */ GIM_Reject,
-// CHECK-NEXT: /* 524 */ // Label 5: @524
-// CHECK-NEXT: /* 524 */ GIM_Reject,
-// CHECK-NEXT: /* 525 */ }; // Size: 525 bytes
+// CHECK-NEXT: /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(99), GIMT_Encode2(212), /*)*//*default:*//*Label 5*/ GIMT_Encode4(528),
+// CHECK-NEXT: /* 10 */ /*TargetOpcode::G_STORE*//*Label 0*/ GIMT_Encode4(462), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
+// CHECK-NEXT: /* 182 */ /*TargetOpcode::G_SEXT*//*Label 1*/ GIMT_Encode4(480), GIMT_Encode4(0),
+// CHECK-NEXT: /* 190 */ /*TargetOpcode::G_ZEXT*//*Label 2*/ GIMT_Encode4(492), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
+// CHECK-NEXT: /* 418 */ /*TargetOpcode::G_FNEG*//*Label 3*/ GIMT_Encode4(504), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
+// CHECK-NEXT: /* 458 */ /*TargetOpcode::G_FABS*//*Label 4*/ GIMT_Encode4(516),
+// CHECK-NEXT: /* 462 */ // Label 0: @462
+// CHECK-NEXT: /* 462 */ GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(479), // Rule ID 2 //
+// CHECK-NEXT: /* 467 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule2Enabled),
+// CHECK-NEXT: /* 470 */ // MIs[0] x
+// CHECK-NEXT: /* 470 */ // No operand predicates
+// CHECK-NEXT: /* 470 */ // MIs[0] y
+// CHECK-NEXT: /* 470 */ // No operand predicates
+// CHECK-NEXT: /* 470 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner0),
+// CHECK-NEXT: /* 474 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner1),
+// CHECK-NEXT: /* 478 */ // Combiner Rule #2: TwoMatchNoApply
+// CHECK-NEXT: /* 478 */ GIR_EraseRootFromParent_Done,
+// CHECK-NEXT: /* 479 */ // Label 6: @479
+// CHECK-NEXT: /* 479 */ GIM_Reject,
+// CHECK-NEXT: /* 480 */ // Label 1: @480
+// CHECK-NEXT: /* 480 */ GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(491), // Rule ID 3 //
+// CHECK-NEXT: /* 485 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule3Enabled),
+// CHECK-NEXT: /* 488 */ // MIs[0] a
+// CHECK-NEXT: /* 488 */ // No operand predicates
+// CHECK-NEXT: /* 488 */ // MIs[0] y
+// CHECK-NEXT: /* 488 */ // No operand predicates
+// CHECK-NEXT: /* 488 */ // Combiner Rule #3: NoMatchTwoApply
+// CHECK-NEXT: /* 488 */ GIR_DoneWithCustomAction, /*Fn*/GIMT_Encode2(GICXXCustomAction_GICombiner2),
+// CHECK-NEXT: /* 491 */ // Label 7: @491
+// CHECK-NEXT: /* 491 */ GIM_Reject,
+// CHECK-NEXT: /* 492 */ // Label 2: @492
+// CHECK-NEXT: /* 492 */ GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(503), // Rule ID 4 //
+// CHECK-NEXT: /* 497 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule4Enabled),
+// CHECK-NEXT: /* 500 */ // MIs[0] a
+// CHECK-NEXT: /* 500 */ // No operand predicates
+// CHECK-NEXT: /* 500 */ // MIs[0] y
+// CHECK-NEXT: /* 500 */ // No operand predicates
+// CHECK-NEXT: /* 500 */ // Combiner Rule #4: CombineCXXOrder
+// CHECK-NEXT: /* 500 */ GIR_DoneWithCustomAction, /*Fn*/GIMT_Encode2(GICXXCustomAction_GICombiner3),
+// CHECK-NEXT: /* 503 */ // Label 8: @503
+// CHECK-NEXT: /* 503 */ GIM_Reject,
+// CHECK-NEXT: /* 504 */ // Label 3: @504
+// CHECK-NEXT: /* 504 */ GIM_Try, /*On fail goto*//*Label 9*/ GIMT_Encode4(515), // Rule ID 1 //
+// CHECK-NEXT: /* 509 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule1Enabled),
+// CHECK-NEXT: /* 512 */ // MIs[0] a
+// CHECK-NEXT: /* 512 */ // No operand predicates
+// CHECK-NEXT: /* 512 */ // MIs[0] b
+// CHECK-NEXT: /* 512 */ // No operand predicates
+// CHECK-NEXT: /* 512 */ // Combiner Rule #1: TwoMatchTwoApply
+// CHECK-NEXT: /* 512 */ GIR_DoneWithCustomAction, /*Fn*/GIMT_Encode2(GICXXCustomAction_GICombiner1),
+// CHECK-NEXT: /* 515 */ // Label 9: @515
+// CHECK-NEXT: /* 515 */ GIM_Reject,
+// CHECK-NEXT: /* 516 */ // Label 4: @516
+// CHECK-NEXT: /* 516 */ GIM_Try, /*On fail goto*//*Label 10*/ GIMT_Encode4(527), // Rule ID 0 //
+// CHECK-NEXT: /* 521 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled),
+// CHECK-NEXT: /* 524 */ // MIs[0] a
+// CHECK-NEXT: /* 524 */ // No operand predicates
+// CHECK-NEXT: /* 524 */ // MIs[0] b
+// CHECK-NEXT: /* 524 */ // No operand predicates
+// CHECK-NEXT: /* 524 */ // Combiner Rule #0: OneMatchOneApply
+// CHECK-NEXT: /* 524 */ GIR_DoneWithCustomAction, /*Fn*/GIMT_Encode2(GICXXCustomAction_GICombiner0),
+// CHECK-NEXT: /* 527 */ // Label 10: @527
+// CHECK-NEXT: /* 527 */ GIM_Reject,
+// CHECK-NEXT: /* 528 */ // Label 5: @528
+// CHECK-NEXT: /* 528 */ GIM_Reject,
+// CHECK-NEXT: /* 529 */ }; // Size: 529 bytes
// CHECK-NEXT: return MatchTable0;
// CHECK-NEXT: }
diff --git a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
index fdabc53a3ff3b..905e16f504048 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
@@ -535,7 +535,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
// R00O-NEXT: GIM_Reject,
// R00O: // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
// R00O-NEXT: GIM_Reject,
-// R00O-NEXT: }; // Size: 1902 bytes
+// R00O-NEXT: }; // Size: 1906 bytes
def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4),
[(set GPR32:$dst,
diff --git a/llvm/test/TableGen/get-named-operand-idx.td b/llvm/test/TableGen/get-named-operand-idx.td
index e6f6331cd9c48..a10cdd9696a4e 100644
--- a/llvm/test/TableGen/get-named-operand-idx.td
+++ b/llvm/test/TableGen/get-named-operand-idx.td
@@ -89,7 +89,8 @@ def InstD : InstBase {
// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 2, 0,
+// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 2,
+// CHECK-NEXT: 0,
// CHECK-NEXT: };
// CHECK-NEXT: return InstructionIndex[Opcode];
// CHECK-NEXT: }
>From ec102fc3f4415b4b3f098a4accd2b19ebd9f7c2c Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 29 Oct 2025 11:03:13 +0000
Subject: [PATCH 09/13] Move from a custom legalize function to lowering
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 30 ++++++++++++++--
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 34 +------------------
2 files changed, 28 insertions(+), 36 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 450fe3220e1c2..f3fb23246538a 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -8477,7 +8477,8 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
return Legalized;
}
-// f64 -> f16 conversion using round-to-nearest-even rounding mode.
+// f64 -> f16 conversion using round-to-nearest-even rounding mode for scalars
+// and round-to-odd for vectors.
LegalizerHelper::LegalizeResult
LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
const LLT S1 = LLT::scalar(1);
@@ -8487,8 +8488,31 @@ LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
assert(MRI.getType(Dst).getScalarType() == LLT::scalar(16) &&
MRI.getType(Src).getScalarType() == LLT::scalar(64));
- if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly.
- return UnableToLegalize;
+ if (MRI.getType(Src).isVector()) {
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src = MI.getOperand(1).getReg();
+ LLT DstTy = MRI.getType(Dst);
+ LLT SrcTy = MRI.getType(Src);
+
+ LLT MidTy = LLT::fixed_vector(SrcTy.getNumElements(), LLT::scalar(32));
+
+ MachineInstrBuilder Mid;
+ MachineInstrBuilder Fin;
+ MIRBuilder.setInstrAndDebugLoc(MI);
+ switch (MI.getOpcode()) {
+ default:
+ return UnableToLegalize;
+ case TargetOpcode::G_FPTRUNC: {
+ Mid = MIRBuilder.buildFPTruncOdd(MidTy, Src);
+ Fin = MIRBuilder.buildFPTrunc(DstTy, Mid.getReg(0));
+ break;
+ }
+ }
+
+ MRI.replaceRegWith(Dst, Fin.getReg(0));
+ MI.eraseFromParent();
+ return Legalized;
+ }
if (MI.getFlag(MachineInstr::FmAfn)) {
unsigned Flags = MI.getFlags();
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 576a9b090a4ca..7927c834b9507 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -819,7 +819,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}})
.libcallFor({{s16, s128}, {s32, s128}, {s64, s128}})
.moreElementsToNextPow2(1)
- .customIf([](const LegalityQuery &Q) {
+ .lowerIf([](const LegalityQuery &Q) {
LLT DstTy = Q.Types[0];
LLT SrcTy = Q.Types[1];
return SrcTy.isFixedVector() && DstTy.isFixedVector() &&
@@ -1479,10 +1479,6 @@ bool AArch64LegalizerInfo::legalizeCustom(
return legalizeICMP(MI, MRI, MIRBuilder);
case TargetOpcode::G_BITCAST:
return legalizeBitcast(MI, Helper);
- case TargetOpcode::G_FPTRUNC:
- // In order to vectorise f16 to f64 properly, we need to use f32 as an
- // intermediary
- return legalizeFptrunc(MI, MIRBuilder, MRI);
}
llvm_unreachable("expected switch to return");
@@ -2408,32 +2404,4 @@ bool AArch64LegalizerInfo::legalizePrefetch(MachineInstr &MI,
MIB.buildInstr(AArch64::G_AARCH64_PREFETCH).addImm(PrfOp).add(AddrVal);
MI.eraseFromParent();
return true;
-}
-
-bool AArch64LegalizerInfo::legalizeFptrunc(
- MachineInstr &MI, MachineIRBuilder &MIRBuilder,
- MachineRegisterInfo &MRI) const {
- Register Dst = MI.getOperand(0).getReg();
- Register Src = MI.getOperand(1).getReg();
- LLT DstTy = MRI.getType(Dst);
- LLT SrcTy = MRI.getType(Src);
-
- LLT MidTy = LLT::fixed_vector(SrcTy.getNumElements(), LLT::scalar(32));
-
- MachineInstrBuilder Mid;
- MachineInstrBuilder Fin;
- MIRBuilder.setInstrAndDebugLoc(MI);
- switch (MI.getOpcode()) {
- default:
- return false;
- case TargetOpcode::G_FPTRUNC: {
- Mid = MIRBuilder.buildFPTruncOdd(MidTy, Src);
- Fin = MIRBuilder.buildFPTrunc(DstTy, Mid.getReg(0));
- break;
- }
- }
-
- MRI.replaceRegWith(Dst, Fin.getReg(0));
- MI.eraseFromParent();
- return true;
}
\ No newline at end of file
>From 411afc09ac6f746b503c232638a155ad3359bcf6 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 29 Oct 2025 11:04:05 +0000
Subject: [PATCH 10/13] Linting
---
llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 5 +++--
llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 2 +-
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 6 +++---
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h | 2 +-
4 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 1e39b1f4452c6..7a1475907df53 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1334,7 +1334,8 @@ class LLVM_ABI MachineIRBuilder {
/// Build and insert \p Res = G_FPTRUNC_ODD \p Op
///
- /// G_FPTRUNC_ODD converts a floating-point value into one with a smaller type using round to odd.
+ /// G_FPTRUNC_ODD converts a floating-point value into one with a smaller type
+ /// using round to odd.
///
/// \pre setBasicBlock or setMI must have been called.
/// \pre \p Res must be a generic virtual register with scalar or vector type.
@@ -1344,7 +1345,7 @@ class LLVM_ABI MachineIRBuilder {
/// \return The newly created instruction.
MachineInstrBuilder
buildFPTruncOdd(const DstOp &Res, const SrcOp &Op,
- std::optional<unsigned> Flags = std::nullopt);
+ std::optional<unsigned> Flags = std::nullopt);
/// Build and insert \p Res = G_TRUNC \p Op
///
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index b96bb442f3e63..2be733589c1ed 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -938,7 +938,7 @@ MachineIRBuilder::buildFPTrunc(const DstOp &Res, const SrcOp &Op,
MachineInstrBuilder
MachineIRBuilder::buildFPTruncOdd(const DstOp &Res, const SrcOp &Op,
- std::optional<unsigned> Flags) {
+ std::optional<unsigned> Flags) {
return buildInstr(TargetOpcode::G_FPTRUNC_ODD, Res, Op, Flags);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 7927c834b9507..5a9d7f094584d 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -832,9 +832,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.scalarize(0);
getActionDefinitionsBuilder(G_FPTRUNC_ODD)
- .legalFor({{s16, s32}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}})
- .clampMaxNumElements(1, s32, 4)
- .clampMaxNumElements(1, s64, 2);
+ .legalFor({{s16, s32}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}})
+ .clampMaxNumElements(1, s32, 4)
+ .clampMaxNumElements(1, s64, 2);
getActionDefinitionsBuilder(G_FPEXT)
.legalFor(
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
index 630f31fd24f28..12b6a6fa395a8 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
@@ -68,7 +68,7 @@ class AArch64LegalizerInfo : public LegalizerInfo {
bool legalizePrefetch(MachineInstr &MI, LegalizerHelper &Helper) const;
bool legalizeBitcast(MachineInstr &MI, LegalizerHelper &Helper) const;
bool legalizeFptrunc(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
- MachineRegisterInfo &MRI) const;
+ MachineRegisterInfo &MRI) const;
const AArch64Subtarget *ST;
};
} // End llvm namespace.
>From 60b6da7dc583f13ab97e8d3b0e7896ce711c6502 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 29 Oct 2025 13:24:58 +0000
Subject: [PATCH 11/13] Update vocab & entities lists
---
.../Inputs/reference_x86_vocab_print.txt | 1 +
.../reference_x86_vocab_wo=0.5_print.txt | 1 +
.../output/reference_x86_entities.txt | 13499 ++++++++--------
3 files changed, 6752 insertions(+), 6749 deletions(-)
diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
index d3c0da9862245..0139518eb9306 100644
--- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
+++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
@@ -423,6 +423,7 @@ Key: G_FPTOSI_SAT: [ 0.00 0.00 ]
Key: G_FPTOUI: [ 0.00 0.00 ]
Key: G_FPTOUI_SAT: [ 0.00 0.00 ]
Key: G_FPTRUNC: [ 0.00 0.00 ]
+Key: G_FPTRUNC_ODD: [ 0.00 0.00 ]
Key: G_FRAME_INDEX: [ 0.00 0.00 ]
Key: G_FREEZE: [ 0.00 0.00 ]
Key: G_FREM: [ 0.00 0.00 ]
diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
index c6e5508248b9b..f18ab6c2900b6 100644
--- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
+++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
@@ -423,6 +423,7 @@ Key: G_FPTOSI_SAT: [ 0.00 0.00 ]
Key: G_FPTOUI: [ 0.00 0.00 ]
Key: G_FPTOUI_SAT: [ 0.00 0.00 ]
Key: G_FPTRUNC: [ 0.00 0.00 ]
+Key: G_FPTRUNC_ODD: [ 0.00 0.00 ]
Key: G_FRAME_INDEX: [ 0.00 0.00 ]
Key: G_FREEZE: [ 0.00 0.00 ]
Key: G_FREM: [ 0.00 0.00 ]
diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
index dc436d123fd35..f50fefc089176 100644
--- a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
+++ b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
@@ -1,4 +1,4 @@
-7173
+7174
AAA 0
AAD 1
AADD 2
@@ -424,6751 +424,6752 @@ G_FPTOSI_SAT 421
G_FPTOUI 422
G_FPTOUI_SAT 423
G_FPTRUNC 424
-G_FRAME_INDEX 425
-G_FREEZE 426
-G_FREM 427
-G_FRINT 428
-G_FSHL 429
-G_FSHR 430
-G_FSIN 431
-G_FSINCOS 432
-G_FSINH 433
-G_FSQRT 434
-G_FSUB 435
-G_FTAN 436
-G_FTANH 437
-G_GET_FPENV 438
-G_GET_FPMODE 439
-G_GET_ROUNDING 440
-G_GLOBAL_VALUE 441
-G_ICMP 442
-G_IMPLICIT_DEF 443
-G_INDEXED_LOAD 444
-G_INDEXED_SEXTLOAD 445
-G_INDEXED_STORE 446
-G_INDEXED_ZEXTLOAD 447
-G_INSERT 448
-G_INSERT_SUBVECTOR 449
-G_INSERT_VECTOR_ELT 450
-G_INTRINSIC 451
-G_INTRINSIC_CONVERGENT 452
-G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS 453
-G_INTRINSIC_FPTRUNC_ROUND 454
-G_INTRINSIC_LLRINT 455
-G_INTRINSIC_LRINT 456
-G_INTRINSIC_ROUND 457
-G_INTRINSIC_ROUNDEVEN 458
-G_INTRINSIC_TRUNC 459
-G_INTRINSIC_W_SIDE_EFFECTS 460
-G_INTTOPTR 461
-G_INVOKE_REGION_START 462
-G_IS_FPCLASS 463
-G_JUMP_TABLE 464
-G_LLROUND 465
-G_LOAD 466
-G_LROUND 467
-G_LSHR 468
-G_MEMCPY 469
-G_MEMCPY_INLINE 470
-G_MEMMOVE 471
-G_MEMSET 472
-G_MERGE_VALUES 473
-G_MUL 474
-G_OR 475
-G_PHI 476
-G_PREFETCH 477
-G_PTRAUTH_GLOBAL_VALUE 478
-G_PTRMASK 479
-G_PTRTOINT 480
-G_PTR_ADD 481
-G_READCYCLECOUNTER 482
-G_READSTEADYCOUNTER 483
-G_READ_REGISTER 484
-G_RESET_FPENV 485
-G_RESET_FPMODE 486
-G_ROTL 487
-G_ROTR 488
-G_SADDE 489
-G_SADDO 490
-G_SADDSAT 491
-G_SBFX 492
-G_SCMP 493
-G_SDIV 494
-G_SDIVFIX 495
-G_SDIVFIXSAT 496
-G_SDIVREM 497
-G_SELECT 498
-G_SET_FPENV 499
-G_SET_FPMODE 500
-G_SET_ROUNDING 501
-G_SEXT 502
-G_SEXTLOAD 503
-G_SEXT_INREG 504
-G_SHL 505
-G_SHUFFLE_VECTOR 506
-G_SITOFP 507
-G_SMAX 508
-G_SMIN 509
-G_SMULFIX 510
-G_SMULFIXSAT 511
-G_SMULH 512
-G_SMULO 513
-G_SPLAT_VECTOR 514
-G_SREM 515
-G_SSHLSAT 516
-G_SSUBE 517
-G_SSUBO 518
-G_SSUBSAT 519
-G_STACKRESTORE 520
-G_STACKSAVE 521
-G_STEP_VECTOR 522
-G_STORE 523
-G_STRICT_FADD 524
-G_STRICT_FDIV 525
-G_STRICT_FLDEXP 526
-G_STRICT_FMA 527
-G_STRICT_FMUL 528
-G_STRICT_FREM 529
-G_STRICT_FSQRT 530
-G_STRICT_FSUB 531
-G_SUB 532
-G_TRAP 533
-G_TRUNC 534
-G_TRUNC_SSAT_S 535
-G_TRUNC_SSAT_U 536
-G_TRUNC_USAT_U 537
-G_UADDE 538
-G_UADDO 539
-G_UADDSAT 540
-G_UBFX 541
-G_UBSANTRAP 542
-G_UCMP 543
-G_UDIV 544
-G_UDIVFIX 545
-G_UDIVFIXSAT 546
-G_UDIVREM 547
-G_UITOFP 548
-G_UMAX 549
-G_UMIN 550
-G_UMULFIX 551
-G_UMULFIXSAT 552
-G_UMULH 553
-G_UMULO 554
-G_UNMERGE_VALUES 555
-G_UREM 556
-G_USHLSAT 557
-G_USUBE 558
-G_USUBO 559
-G_USUBSAT 560
-G_VAARG 561
-G_VASTART 562
-G_VECREDUCE_ADD 563
-G_VECREDUCE_AND 564
-G_VECREDUCE_FADD 565
-G_VECREDUCE_FMAX 566
-G_VECREDUCE_FMAXIMUM 567
-G_VECREDUCE_FMIN 568
-G_VECREDUCE_FMINIMUM 569
-G_VECREDUCE_FMUL 570
-G_VECREDUCE_MUL 571
-G_VECREDUCE_OR 572
-G_VECREDUCE_SEQ_FADD 573
-G_VECREDUCE_SEQ_FMUL 574
-G_VECREDUCE_SMAX 575
-G_VECREDUCE_SMIN 576
-G_VECREDUCE_UMAX 577
-G_VECREDUCE_UMIN 578
-G_VECREDUCE_XOR 579
-G_VECTOR_COMPRESS 580
-G_VSCALE 581
-G_WRITE_REGISTER 582
-G_XOR 583
-G_ZEXT 584
-G_ZEXTLOAD 585
-HADDPDrm 586
-HADDPDrr 587
-HADDPSrm 588
-HADDPSrr 589
-HLT 590
-HRESET 591
-HSUBPDrm 592
-HSUBPDrr 593
-HSUBPSrm 594
-HSUBPSrr 595
-ICALL_BRANCH_FUNNEL 596
-IDIV 597
-ILD_F 598
-ILD_Fp 599
-IMPLICIT_DEF 600
-IMUL 601
-IMULZU 602
-IN 603
-INC 604
-INCSSPD 605
-INCSSPQ 606
-INDIRECT_THUNK_CALL 607
-INDIRECT_THUNK_TCRETURN 608
-INIT_UNDEF 609
-INLINEASM 610
-INLINEASM_BR 611
-INSB 612
-INSERTPSrmi 613
-INSERTPSrri 614
-INSERTQ 615
-INSERTQI 616
-INSERT_SUBREG 617
-INSL 618
-INSW 619
-INT 620
-INTO 621
-INVD 622
-INVEPT 623
-INVLPG 624
-INVLPGA 625
-INVLPGB 626
-INVPCID 627
-INVVPID 628
-IRET 629
-ISTT_FP 630
-ISTT_Fp 631
-IST_F 632
-IST_FP 633
-IST_Fp 634
-Int_eh_sjlj_setup_dispatch 635
-JCC 636
-JCXZ 637
-JECXZ 638
-JMP 639
-JMPABS 640
-JRCXZ 641
-JUMP_TABLE_DEBUG_INFO 642
-KADDBkk 643
-KADDDkk 644
-KADDQkk 645
-KADDWkk 646
-KANDBkk 647
-KANDDkk 648
-KANDNBkk 649
-KANDNDkk 650
-KANDNQkk 651
-KANDNWkk 652
-KANDQkk 653
-KANDWkk 654
-KCFI_CHECK 655
-KILL 656
-KMOVBkk 657
-KMOVBkk_EVEX 658
-KMOVBkm 659
-KMOVBkm_EVEX 660
-KMOVBkr 661
-KMOVBkr_EVEX 662
-KMOVBmk 663
-KMOVBmk_EVEX 664
-KMOVBrk 665
-KMOVBrk_EVEX 666
-KMOVDkk 667
-KMOVDkk_EVEX 668
-KMOVDkm 669
-KMOVDkm_EVEX 670
-KMOVDkr 671
-KMOVDkr_EVEX 672
-KMOVDmk 673
-KMOVDmk_EVEX 674
-KMOVDrk 675
-KMOVDrk_EVEX 676
-KMOVQkk 677
-KMOVQkk_EVEX 678
-KMOVQkm 679
-KMOVQkm_EVEX 680
-KMOVQkr 681
-KMOVQkr_EVEX 682
-KMOVQmk 683
-KMOVQmk_EVEX 684
-KMOVQrk 685
-KMOVQrk_EVEX 686
-KMOVWkk 687
-KMOVWkk_EVEX 688
-KMOVWkm 689
-KMOVWkm_EVEX 690
-KMOVWkr 691
-KMOVWkr_EVEX 692
-KMOVWmk 693
-KMOVWmk_EVEX 694
-KMOVWrk 695
-KMOVWrk_EVEX 696
-KNOTBkk 697
-KNOTDkk 698
-KNOTQkk 699
-KNOTWkk 700
-KORBkk 701
-KORDkk 702
-KORQkk 703
-KORTESTBkk 704
-KORTESTDkk 705
-KORTESTQkk 706
-KORTESTWkk 707
-KORWkk 708
-KSET 709
-KSHIFTLBki 710
-KSHIFTLDki 711
-KSHIFTLQki 712
-KSHIFTLWki 713
-KSHIFTRBki 714
-KSHIFTRDki 715
-KSHIFTRQki 716
-KSHIFTRWki 717
-KTESTBkk 718
-KTESTDkk 719
-KTESTQkk 720
-KTESTWkk 721
-KUNPCKBWkk 722
-KUNPCKDQkk 723
-KUNPCKWDkk 724
-KXNORBkk 725
-KXNORDkk 726
-KXNORQkk 727
-KXNORWkk 728
-KXORBkk 729
-KXORDkk 730
-KXORQkk 731
-KXORWkk 732
-LAHF 733
-LAR 734
-LCMPXCHG 735
-LDDQUrm 736
-LDMXCSR 737
-LDS 738
-LDTILECFG 739
-LDTILECFG_EVEX 740
-LD_F 741
-LD_Fp 742
-LD_Frr 743
-LEA 744
-LEAVE 745
-LES 746
-LFENCE 747
-LFS 748
-LGDT 749
-LGS 750
-LIDT 751
-LIFETIME_END 752
-LIFETIME_START 753
-LKGS 754
-LLDT 755
-LLWPCB 756
-LMSW 757
-LOADIWKEY 758
-LOAD_STACK_GUARD 759
-LOCAL_ESCAPE 760
-LOCK_ADD 761
-LOCK_AND 762
-LOCK_BTC 763
-LOCK_BTC_RM 764
-LOCK_BTR 765
-LOCK_BTR_RM 766
-LOCK_BTS 767
-LOCK_BTS_RM 768
-LOCK_DEC 769
-LOCK_INC 770
-LOCK_OR 771
-LOCK_PREFIX 772
-LOCK_SUB 773
-LOCK_XOR 774
-LODSB 775
-LODSL 776
-LODSQ 777
-LODSW 778
-LOOP 779
-LOOPE 780
-LOOPNE 781
-LRET 782
-LRETI 783
-LSL 784
-LSS 785
-LTRm 786
-LTRr 787
-LWPINS 788
-LWPVAL 789
-LXADD 790
-LZCNT 791
-MASKMOVDQU 792
-MASKPAIR 793
-MAXCPDrm 794
-MAXCPDrr 795
-MAXCPSrm 796
-MAXCPSrr 797
-MAXCSDrm 798
-MAXCSDrr 799
-MAXCSSrm 800
-MAXCSSrr 801
-MAXPDrm 802
-MAXPDrr 803
-MAXPSrm 804
-MAXPSrr 805
-MAXSDrm 806
-MAXSDrm_Int 807
-MAXSDrr 808
-MAXSDrr_Int 809
-MAXSSrm 810
-MAXSSrm_Int 811
-MAXSSrr 812
-MAXSSrr_Int 813
-MEMBARRIER 814
-MFENCE 815
-MINCPDrm 816
-MINCPDrr 817
-MINCPSrm 818
-MINCPSrr 819
-MINCSDrm 820
-MINCSDrr 821
-MINCSSrm 822
-MINCSSrr 823
-MINPDrm 824
-MINPDrr 825
-MINPSrm 826
-MINPSrr 827
-MINSDrm 828
-MINSDrm_Int 829
-MINSDrr 830
-MINSDrr_Int 831
-MINSSrm 832
-MINSSrm_Int 833
-MINSSrr 834
-MINSSrr_Int 835
-MMX_CVTPD 836
-MMX_CVTPI 837
-MMX_CVTPS 838
-MMX_CVTTPD 839
-MMX_CVTTPS 840
-MMX_EMMS 841
-MMX_MASKMOVQ 842
-MMX_MOVD 843
-MMX_MOVDQ 844
-MMX_MOVFR 845
-MMX_MOVNTQmr 846
-MMX_MOVQ 847
-MMX_PABSBrm 848
-MMX_PABSBrr 849
-MMX_PABSDrm 850
-MMX_PABSDrr 851
-MMX_PABSWrm 852
-MMX_PABSWrr 853
-MMX_PACKSSDWrm 854
-MMX_PACKSSDWrr 855
-MMX_PACKSSWBrm 856
-MMX_PACKSSWBrr 857
-MMX_PACKUSWBrm 858
-MMX_PACKUSWBrr 859
-MMX_PADDBrm 860
-MMX_PADDBrr 861
-MMX_PADDDrm 862
-MMX_PADDDrr 863
-MMX_PADDQrm 864
-MMX_PADDQrr 865
-MMX_PADDSBrm 866
-MMX_PADDSBrr 867
-MMX_PADDSWrm 868
-MMX_PADDSWrr 869
-MMX_PADDUSBrm 870
-MMX_PADDUSBrr 871
-MMX_PADDUSWrm 872
-MMX_PADDUSWrr 873
-MMX_PADDWrm 874
-MMX_PADDWrr 875
-MMX_PALIGNRrmi 876
-MMX_PALIGNRrri 877
-MMX_PANDNrm 878
-MMX_PANDNrr 879
-MMX_PANDrm 880
-MMX_PANDrr 881
-MMX_PAVGBrm 882
-MMX_PAVGBrr 883
-MMX_PAVGWrm 884
-MMX_PAVGWrr 885
-MMX_PCMPEQBrm 886
-MMX_PCMPEQBrr 887
-MMX_PCMPEQDrm 888
-MMX_PCMPEQDrr 889
-MMX_PCMPEQWrm 890
-MMX_PCMPEQWrr 891
-MMX_PCMPGTBrm 892
-MMX_PCMPGTBrr 893
-MMX_PCMPGTDrm 894
-MMX_PCMPGTDrr 895
-MMX_PCMPGTWrm 896
-MMX_PCMPGTWrr 897
-MMX_PEXTRWrri 898
-MMX_PHADDDrm 899
-MMX_PHADDDrr 900
-MMX_PHADDSWrm 901
-MMX_PHADDSWrr 902
-MMX_PHADDWrm 903
-MMX_PHADDWrr 904
-MMX_PHSUBDrm 905
-MMX_PHSUBDrr 906
-MMX_PHSUBSWrm 907
-MMX_PHSUBSWrr 908
-MMX_PHSUBWrm 909
-MMX_PHSUBWrr 910
-MMX_PINSRWrmi 911
-MMX_PINSRWrri 912
-MMX_PMADDUBSWrm 913
-MMX_PMADDUBSWrr 914
-MMX_PMADDWDrm 915
-MMX_PMADDWDrr 916
-MMX_PMAXSWrm 917
-MMX_PMAXSWrr 918
-MMX_PMAXUBrm 919
-MMX_PMAXUBrr 920
-MMX_PMINSWrm 921
-MMX_PMINSWrr 922
-MMX_PMINUBrm 923
-MMX_PMINUBrr 924
-MMX_PMOVMSKBrr 925
-MMX_PMULHRSWrm 926
-MMX_PMULHRSWrr 927
-MMX_PMULHUWrm 928
-MMX_PMULHUWrr 929
-MMX_PMULHWrm 930
-MMX_PMULHWrr 931
-MMX_PMULLWrm 932
-MMX_PMULLWrr 933
-MMX_PMULUDQrm 934
-MMX_PMULUDQrr 935
-MMX_PORrm 936
-MMX_PORrr 937
-MMX_PSADBWrm 938
-MMX_PSADBWrr 939
-MMX_PSHUFBrm 940
-MMX_PSHUFBrr 941
-MMX_PSHUFWmi 942
-MMX_PSHUFWri 943
-MMX_PSIGNBrm 944
-MMX_PSIGNBrr 945
-MMX_PSIGNDrm 946
-MMX_PSIGNDrr 947
-MMX_PSIGNWrm 948
-MMX_PSIGNWrr 949
-MMX_PSLLDri 950
-MMX_PSLLDrm 951
-MMX_PSLLDrr 952
-MMX_PSLLQri 953
-MMX_PSLLQrm 954
-MMX_PSLLQrr 955
-MMX_PSLLWri 956
-MMX_PSLLWrm 957
-MMX_PSLLWrr 958
-MMX_PSRADri 959
-MMX_PSRADrm 960
-MMX_PSRADrr 961
-MMX_PSRAWri 962
-MMX_PSRAWrm 963
-MMX_PSRAWrr 964
-MMX_PSRLDri 965
-MMX_PSRLDrm 966
-MMX_PSRLDrr 967
-MMX_PSRLQri 968
-MMX_PSRLQrm 969
-MMX_PSRLQrr 970
-MMX_PSRLWri 971
-MMX_PSRLWrm 972
-MMX_PSRLWrr 973
-MMX_PSUBBrm 974
-MMX_PSUBBrr 975
-MMX_PSUBDrm 976
-MMX_PSUBDrr 977
-MMX_PSUBQrm 978
-MMX_PSUBQrr 979
-MMX_PSUBSBrm 980
-MMX_PSUBSBrr 981
-MMX_PSUBSWrm 982
-MMX_PSUBSWrr 983
-MMX_PSUBUSBrm 984
-MMX_PSUBUSBrr 985
-MMX_PSUBUSWrm 986
-MMX_PSUBUSWrr 987
-MMX_PSUBWrm 988
-MMX_PSUBWrr 989
-MMX_PUNPCKHBWrm 990
-MMX_PUNPCKHBWrr 991
-MMX_PUNPCKHDQrm 992
-MMX_PUNPCKHDQrr 993
-MMX_PUNPCKHWDrm 994
-MMX_PUNPCKHWDrr 995
-MMX_PUNPCKLBWrm 996
-MMX_PUNPCKLBWrr 997
-MMX_PUNPCKLDQrm 998
-MMX_PUNPCKLDQrr 999
-MMX_PUNPCKLWDrm 1000
-MMX_PUNPCKLWDrr 1001
-MMX_PXORrm 1002
-MMX_PXORrr 1003
-MMX_SET 1004
-MONITOR 1005
-MONITORX 1006
-MONTMUL 1007
-MORESTACK_RET 1008
-MORESTACK_RET_RESTORE_R 1009
-MOV 1010
-MOVAPDmr 1011
-MOVAPDrm 1012
-MOVAPDrr 1013
-MOVAPDrr_REV 1014
-MOVAPSmr 1015
-MOVAPSrm 1016
-MOVAPSrr 1017
-MOVAPSrr_REV 1018
-MOVBE 1019
-MOVDDUPrm 1020
-MOVDDUPrr 1021
-MOVDI 1022
-MOVDIR 1023
-MOVDIRI 1024
-MOVDQAmr 1025
-MOVDQArm 1026
-MOVDQArr 1027
-MOVDQArr_REV 1028
-MOVDQUmr 1029
-MOVDQUrm 1030
-MOVDQUrr 1031
-MOVDQUrr_REV 1032
-MOVHLPSrr 1033
-MOVHPDmr 1034
-MOVHPDrm 1035
-MOVHPSmr 1036
-MOVHPSrm 1037
-MOVLHPSrr 1038
-MOVLPDmr 1039
-MOVLPDrm 1040
-MOVLPSmr 1041
-MOVLPSrm 1042
-MOVMSKPDrr 1043
-MOVMSKPSrr 1044
-MOVNTDQArm 1045
-MOVNTDQmr 1046
-MOVNTI 1047
-MOVNTImr 1048
-MOVNTPDmr 1049
-MOVNTPSmr 1050
-MOVNTSD 1051
-MOVNTSS 1052
-MOVPC 1053
-MOVPDI 1054
-MOVPQI 1055
-MOVPQIto 1056
-MOVQI 1057
-MOVRS 1058
-MOVSB 1059
-MOVSDmr 1060
-MOVSDrm 1061
-MOVSDrm_alt 1062
-MOVSDrr 1063
-MOVSDrr_REV 1064
-MOVSDto 1065
-MOVSHDUPrm 1066
-MOVSHDUPrr 1067
-MOVSHPmr 1068
-MOVSHPrm 1069
-MOVSL 1070
-MOVSLDUPrm 1071
-MOVSLDUPrr 1072
-MOVSQ 1073
-MOVSS 1074
-MOVSSmr 1075
-MOVSSrm 1076
-MOVSSrm_alt 1077
-MOVSSrr 1078
-MOVSSrr_REV 1079
-MOVSW 1080
-MOVSX 1081
-MOVUPDmr 1082
-MOVUPDrm 1083
-MOVUPDrr 1084
-MOVUPDrr_REV 1085
-MOVUPSmr 1086
-MOVUPSrm 1087
-MOVUPSrr 1088
-MOVUPSrr_REV 1089
-MOVZPQILo 1090
-MOVZX 1091
-MPSADBWrmi 1092
-MPSADBWrri 1093
-MUL 1094
-MULPDrm 1095
-MULPDrr 1096
-MULPSrm 1097
-MULPSrr 1098
-MULSDrm 1099
-MULSDrm_Int 1100
-MULSDrr 1101
-MULSDrr_Int 1102
-MULSSrm 1103
-MULSSrm_Int 1104
-MULSSrr 1105
-MULSSrr_Int 1106
-MULX 1107
-MUL_F 1108
-MUL_FI 1109
-MUL_FPrST 1110
-MUL_FST 1111
-MUL_Fp 1112
-MUL_FpI 1113
-MUL_FrST 1114
-MWAITX 1115
-MWAITX_SAVE_RBX 1116
-MWAITXrrr 1117
-MWAITrr 1118
-NEG 1119
-NOOP 1120
-NOOPL 1121
-NOOPLr 1122
-NOOPQ 1123
-NOOPQr 1124
-NOOPW 1125
-NOOPWr 1126
-NOT 1127
-OR 1128
-ORPDrm 1129
-ORPDrr 1130
-ORPSrm 1131
-ORPSrr 1132
-OUT 1133
-OUTSB 1134
-OUTSL 1135
-OUTSW 1136
-PABSBrm 1137
-PABSBrr 1138
-PABSDrm 1139
-PABSDrr 1140
-PABSWrm 1141
-PABSWrr 1142
-PACKSSDWrm 1143
-PACKSSDWrr 1144
-PACKSSWBrm 1145
-PACKSSWBrr 1146
-PACKUSDWrm 1147
-PACKUSDWrr 1148
-PACKUSWBrm 1149
-PACKUSWBrr 1150
-PADDBrm 1151
-PADDBrr 1152
-PADDDrm 1153
-PADDDrr 1154
-PADDQrm 1155
-PADDQrr 1156
-PADDSBrm 1157
-PADDSBrr 1158
-PADDSWrm 1159
-PADDSWrr 1160
-PADDUSBrm 1161
-PADDUSBrr 1162
-PADDUSWrm 1163
-PADDUSWrr 1164
-PADDWrm 1165
-PADDWrr 1166
-PALIGNRrmi 1167
-PALIGNRrri 1168
-PANDNrm 1169
-PANDNrr 1170
-PANDrm 1171
-PANDrr 1172
-PATCHABLE_EVENT_CALL 1173
-PATCHABLE_FUNCTION_ENTER 1174
-PATCHABLE_FUNCTION_EXIT 1175
-PATCHABLE_OP 1176
-PATCHABLE_RET 1177
-PATCHABLE_TAIL_CALL 1178
-PATCHABLE_TYPED_EVENT_CALL 1179
-PATCHPOINT 1180
-PAUSE 1181
-PAVGBrm 1182
-PAVGBrr 1183
-PAVGUSBrm 1184
-PAVGUSBrr 1185
-PAVGWrm 1186
-PAVGWrr 1187
-PBLENDVBrm 1188
-PBLENDVBrr 1189
-PBLENDWrmi 1190
-PBLENDWrri 1191
-PBNDKB 1192
-PCLMULQDQrmi 1193
-PCLMULQDQrri 1194
-PCMPEQBrm 1195
-PCMPEQBrr 1196
-PCMPEQDrm 1197
-PCMPEQDrr 1198
-PCMPEQQrm 1199
-PCMPEQQrr 1200
-PCMPEQWrm 1201
-PCMPEQWrr 1202
-PCMPESTRIrmi 1203
-PCMPESTRIrri 1204
-PCMPESTRMrmi 1205
-PCMPESTRMrri 1206
-PCMPGTBrm 1207
-PCMPGTBrr 1208
-PCMPGTDrm 1209
-PCMPGTDrr 1210
-PCMPGTQrm 1211
-PCMPGTQrr 1212
-PCMPGTWrm 1213
-PCMPGTWrr 1214
-PCMPISTRIrmi 1215
-PCMPISTRIrri 1216
-PCMPISTRMrmi 1217
-PCMPISTRMrri 1218
-PCONFIG 1219
-PDEP 1220
-PEXT 1221
-PEXTRBmri 1222
-PEXTRBrri 1223
-PEXTRDmri 1224
-PEXTRDrri 1225
-PEXTRQmri 1226
-PEXTRQrri 1227
-PEXTRWmri 1228
-PEXTRWrri 1229
-PEXTRWrri_REV 1230
-PF 1231
-PFACCrm 1232
-PFACCrr 1233
-PFADDrm 1234
-PFADDrr 1235
-PFCMPEQrm 1236
-PFCMPEQrr 1237
-PFCMPGErm 1238
-PFCMPGErr 1239
-PFCMPGTrm 1240
-PFCMPGTrr 1241
-PFMAXrm 1242
-PFMAXrr 1243
-PFMINrm 1244
-PFMINrr 1245
-PFMULrm 1246
-PFMULrr 1247
-PFNACCrm 1248
-PFNACCrr 1249
-PFPNACCrm 1250
-PFPNACCrr 1251
-PFRCPIT 1252
-PFRCPrm 1253
-PFRCPrr 1254
-PFRSQIT 1255
-PFRSQRTrm 1256
-PFRSQRTrr 1257
-PFSUBRrm 1258
-PFSUBRrr 1259
-PFSUBrm 1260
-PFSUBrr 1261
-PHADDDrm 1262
-PHADDDrr 1263
-PHADDSWrm 1264
-PHADDSWrr 1265
-PHADDWrm 1266
-PHADDWrr 1267
-PHI 1268
-PHMINPOSUWrm 1269
-PHMINPOSUWrr 1270
-PHSUBDrm 1271
-PHSUBDrr 1272
-PHSUBSWrm 1273
-PHSUBSWrr 1274
-PHSUBWrm 1275
-PHSUBWrr 1276
-PI 1277
-PINSRBrmi 1278
-PINSRBrri 1279
-PINSRDrmi 1280
-PINSRDrri 1281
-PINSRQrmi 1282
-PINSRQrri 1283
-PINSRWrmi 1284
-PINSRWrri 1285
-PLDTILECFGV 1286
-PLEA 1287
-PMADDUBSWrm 1288
-PMADDUBSWrr 1289
-PMADDWDrm 1290
-PMADDWDrr 1291
-PMAXSBrm 1292
-PMAXSBrr 1293
-PMAXSDrm 1294
-PMAXSDrr 1295
-PMAXSWrm 1296
-PMAXSWrr 1297
-PMAXUBrm 1298
-PMAXUBrr 1299
-PMAXUDrm 1300
-PMAXUDrr 1301
-PMAXUWrm 1302
-PMAXUWrr 1303
-PMINSBrm 1304
-PMINSBrr 1305
-PMINSDrm 1306
-PMINSDrr 1307
-PMINSWrm 1308
-PMINSWrr 1309
-PMINUBrm 1310
-PMINUBrr 1311
-PMINUDrm 1312
-PMINUDrr 1313
-PMINUWrm 1314
-PMINUWrr 1315
-PMOVMSKBrr 1316
-PMOVSXBDrm 1317
-PMOVSXBDrr 1318
-PMOVSXBQrm 1319
-PMOVSXBQrr 1320
-PMOVSXBWrm 1321
-PMOVSXBWrr 1322
-PMOVSXDQrm 1323
-PMOVSXDQrr 1324
-PMOVSXWDrm 1325
-PMOVSXWDrr 1326
-PMOVSXWQrm 1327
-PMOVSXWQrr 1328
-PMOVZXBDrm 1329
-PMOVZXBDrr 1330
-PMOVZXBQrm 1331
-PMOVZXBQrr 1332
-PMOVZXBWrm 1333
-PMOVZXBWrr 1334
-PMOVZXDQrm 1335
-PMOVZXDQrr 1336
-PMOVZXWDrm 1337
-PMOVZXWDrr 1338
-PMOVZXWQrm 1339
-PMOVZXWQrr 1340
-PMULDQrm 1341
-PMULDQrr 1342
-PMULHRSWrm 1343
-PMULHRSWrr 1344
-PMULHRWrm 1345
-PMULHRWrr 1346
-PMULHUWrm 1347
-PMULHUWrr 1348
-PMULHWrm 1349
-PMULHWrr 1350
-PMULLDrm 1351
-PMULLDrr 1352
-PMULLWrm 1353
-PMULLWrr 1354
-PMULUDQrm 1355
-PMULUDQrr 1356
-POP 1357
-POPA 1358
-POPCNT 1359
-POPDS 1360
-POPES 1361
-POPF 1362
-POPFS 1363
-POPGS 1364
-POPP 1365
-POPSS 1366
-PORrm 1367
-PORrr 1368
-PREALLOCATED_ARG 1369
-PREALLOCATED_SETUP 1370
-PREFETCH 1371
-PREFETCHIT 1372
-PREFETCHNTA 1373
-PREFETCHRST 1374
-PREFETCHT 1375
-PREFETCHW 1376
-PREFETCHWT 1377
-PROBED_ALLOCA 1378
-PSADBWrm 1379
-PSADBWrr 1380
-PSEUDO_PROBE 1381
-PSHUFBrm 1382
-PSHUFBrr 1383
-PSHUFDmi 1384
-PSHUFDri 1385
-PSHUFHWmi 1386
-PSHUFHWri 1387
-PSHUFLWmi 1388
-PSHUFLWri 1389
-PSIGNBrm 1390
-PSIGNBrr 1391
-PSIGNDrm 1392
-PSIGNDrr 1393
-PSIGNWrm 1394
-PSIGNWrr 1395
-PSLLDQri 1396
-PSLLDri 1397
-PSLLDrm 1398
-PSLLDrr 1399
-PSLLQri 1400
-PSLLQrm 1401
-PSLLQrr 1402
-PSLLWri 1403
-PSLLWrm 1404
-PSLLWrr 1405
-PSMASH 1406
-PSRADri 1407
-PSRADrm 1408
-PSRADrr 1409
-PSRAWri 1410
-PSRAWrm 1411
-PSRAWrr 1412
-PSRLDQri 1413
-PSRLDri 1414
-PSRLDrm 1415
-PSRLDrr 1416
-PSRLQri 1417
-PSRLQrm 1418
-PSRLQrr 1419
-PSRLWri 1420
-PSRLWrm 1421
-PSRLWrr 1422
-PSUBBrm 1423
-PSUBBrr 1424
-PSUBDrm 1425
-PSUBDrr 1426
-PSUBQrm 1427
-PSUBQrr 1428
-PSUBSBrm 1429
-PSUBSBrr 1430
-PSUBSWrm 1431
-PSUBSWrr 1432
-PSUBUSBrm 1433
-PSUBUSBrr 1434
-PSUBUSWrm 1435
-PSUBUSWrr 1436
-PSUBWrm 1437
-PSUBWrr 1438
-PSWAPDrm 1439
-PSWAPDrr 1440
-PT 1441
-PTCMMIMFP 1442
-PTCMMRLFP 1443
-PTCONJTCMMIMFP 1444
-PTCONJTFP 1445
-PTCVTROWD 1446
-PTCVTROWPS 1447
-PTDPBF 1448
-PTDPBHF 1449
-PTDPBSSD 1450
-PTDPBSSDV 1451
-PTDPBSUD 1452
-PTDPBSUDV 1453
-PTDPBUSD 1454
-PTDPBUSDV 1455
-PTDPBUUD 1456
-PTDPBUUDV 1457
-PTDPFP 1458
-PTDPHBF 1459
-PTDPHF 1460
-PTESTrm 1461
-PTESTrr 1462
-PTILELOADD 1463
-PTILELOADDRS 1464
-PTILELOADDRST 1465
-PTILELOADDRSV 1466
-PTILELOADDT 1467
-PTILELOADDV 1468
-PTILEMOVROWrre 1469
-PTILEMOVROWrreV 1470
-PTILEMOVROWrri 1471
-PTILEMOVROWrriV 1472
-PTILEPAIRLOAD 1473
-PTILEPAIRSTORE 1474
-PTILESTORED 1475
-PTILESTOREDV 1476
-PTILEZERO 1477
-PTILEZEROV 1478
-PTMMULTF 1479
-PTTCMMIMFP 1480
-PTTCMMRLFP 1481
-PTTDPBF 1482
-PTTDPFP 1483
-PTTMMULTF 1484
-PTTRANSPOSED 1485
-PTTRANSPOSEDV 1486
-PTWRITE 1487
-PTWRITEm 1488
-PTWRITEr 1489
-PUNPCKHBWrm 1490
-PUNPCKHBWrr 1491
-PUNPCKHDQrm 1492
-PUNPCKHDQrr 1493
-PUNPCKHQDQrm 1494
-PUNPCKHQDQrr 1495
-PUNPCKHWDrm 1496
-PUNPCKHWDrr 1497
-PUNPCKLBWrm 1498
-PUNPCKLBWrr 1499
-PUNPCKLDQrm 1500
-PUNPCKLDQrr 1501
-PUNPCKLQDQrm 1502
-PUNPCKLQDQrr 1503
-PUNPCKLWDrm 1504
-PUNPCKLWDrr 1505
-PUSH 1506
-PUSHA 1507
-PUSHCS 1508
-PUSHDS 1509
-PUSHES 1510
-PUSHF 1511
-PUSHFS 1512
-PUSHGS 1513
-PUSHP 1514
-PUSHSS 1515
-PVALIDATE 1516
-PXORrm 1517
-PXORrr 1518
-RCL 1519
-RCPPSm 1520
-RCPPSr 1521
-RCPSSm 1522
-RCPSSm_Int 1523
-RCPSSr 1524
-RCPSSr_Int 1525
-RCR 1526
-RDFLAGS 1527
-RDFSBASE 1528
-RDGSBASE 1529
-RDMSR 1530
-RDMSRLIST 1531
-RDMSRri 1532
-RDMSRri_EVEX 1533
-RDPID 1534
-RDPKRUr 1535
-RDPMC 1536
-RDPRU 1537
-RDRAND 1538
-RDSEED 1539
-RDSSPD 1540
-RDSSPQ 1541
-RDTSC 1542
-RDTSCP 1543
-REG_SEQUENCE 1544
-REPNE_PREFIX 1545
-REP_MOVSB 1546
-REP_MOVSD 1547
-REP_MOVSQ 1548
-REP_MOVSW 1549
-REP_PREFIX 1550
-REP_STOSB 1551
-REP_STOSD 1552
-REP_STOSQ 1553
-REP_STOSW 1554
-RET 1555
-RETI 1556
-REX 1557
-RMPADJUST 1558
-RMPQUERY 1559
-RMPUPDATE 1560
-ROL 1561
-ROR 1562
-RORX 1563
-ROUNDPDmi 1564
-ROUNDPDri 1565
-ROUNDPSmi 1566
-ROUNDPSri 1567
-ROUNDSDmi 1568
-ROUNDSDmi_Int 1569
-ROUNDSDri 1570
-ROUNDSDri_Int 1571
-ROUNDSSmi 1572
-ROUNDSSmi_Int 1573
-ROUNDSSri 1574
-ROUNDSSri_Int 1575
-RSM 1576
-RSQRTPSm 1577
-RSQRTPSr 1578
-RSQRTSSm 1579
-RSQRTSSm_Int 1580
-RSQRTSSr 1581
-RSQRTSSr_Int 1582
-RSTORSSP 1583
-SAHF 1584
-SALC 1585
-SAR 1586
-SARX 1587
-SAVEPREVSSP 1588
-SBB 1589
-SCASB 1590
-SCASL 1591
-SCASQ 1592
-SCASW 1593
-SEAMCALL 1594
-SEAMOPS 1595
-SEAMRET 1596
-SEG_ALLOCA 1597
-SEH_BeginEpilogue 1598
-SEH_EndEpilogue 1599
-SEH_EndPrologue 1600
-SEH_PushFrame 1601
-SEH_PushReg 1602
-SEH_SaveReg 1603
-SEH_SaveXMM 1604
-SEH_SetFrame 1605
-SEH_StackAlign 1606
-SEH_StackAlloc 1607
-SEH_UnwindV 1608
-SEH_UnwindVersion 1609
-SENDUIPI 1610
-SERIALIZE 1611
-SETB_C 1612
-SETCCm 1613
-SETCCm_EVEX 1614
-SETCCr 1615
-SETCCr_EVEX 1616
-SETSSBSY 1617
-SETZUCCm 1618
-SETZUCCr 1619
-SFENCE 1620
-SGDT 1621
-SHA 1622
-SHL 1623
-SHLD 1624
-SHLDROT 1625
-SHLX 1626
-SHR 1627
-SHRD 1628
-SHRDROT 1629
-SHRX 1630
-SHUFPDrmi 1631
-SHUFPDrri 1632
-SHUFPSrmi 1633
-SHUFPSrri 1634
-SIDT 1635
-SKINIT 1636
-SLDT 1637
-SLWPCB 1638
-SMSW 1639
-SQRTPDm 1640
-SQRTPDr 1641
-SQRTPSm 1642
-SQRTPSr 1643
-SQRTSDm 1644
-SQRTSDm_Int 1645
-SQRTSDr 1646
-SQRTSDr_Int 1647
-SQRTSSm 1648
-SQRTSSm_Int 1649
-SQRTSSr 1650
-SQRTSSr_Int 1651
-SQRT_F 1652
-SQRT_Fp 1653
-SS_PREFIX 1654
-STAC 1655
-STACKALLOC_W_PROBING 1656
-STACKMAP 1657
-STATEPOINT 1658
-STC 1659
-STD 1660
-STGI 1661
-STI 1662
-STMXCSR 1663
-STOSB 1664
-STOSL 1665
-STOSQ 1666
-STOSW 1667
-STR 1668
-STRm 1669
-STTILECFG 1670
-STTILECFG_EVEX 1671
-STUI 1672
-ST_F 1673
-ST_FP 1674
-ST_FPrr 1675
-ST_Fp 1676
-ST_FpP 1677
-ST_Frr 1678
-SUB 1679
-SUBPDrm 1680
-SUBPDrr 1681
-SUBPSrm 1682
-SUBPSrr 1683
-SUBREG_TO_REG 1684
-SUBR_F 1685
-SUBR_FI 1686
-SUBR_FPrST 1687
-SUBR_FST 1688
-SUBR_Fp 1689
-SUBR_FpI 1690
-SUBR_FrST 1691
-SUBSDrm 1692
-SUBSDrm_Int 1693
-SUBSDrr 1694
-SUBSDrr_Int 1695
-SUBSSrm 1696
-SUBSSrm_Int 1697
-SUBSSrr 1698
-SUBSSrr_Int 1699
-SUB_F 1700
-SUB_FI 1701
-SUB_FPrST 1702
-SUB_FST 1703
-SUB_Fp 1704
-SUB_FpI 1705
-SUB_FrST 1706
-SWAPGS 1707
-SYSCALL 1708
-SYSENTER 1709
-SYSEXIT 1710
-SYSRET 1711
-T 1712
-TAILJMPd 1713
-TAILJMPd_CC 1714
-TAILJMPm 1715
-TAILJMPr 1716
-TCMMIMFP 1717
-TCMMRLFP 1718
-TCONJTCMMIMFP 1719
-TCONJTFP 1720
-TCRETURN_HIPE 1721
-TCRETURN_WIN 1722
-TCRETURN_WINmi 1723
-TCRETURNdi 1724
-TCRETURNdicc 1725
-TCRETURNmi 1726
-TCRETURNri 1727
-TCVTROWD 1728
-TCVTROWPS 1729
-TDCALL 1730
-TDPBF 1731
-TDPBHF 1732
-TDPBSSD 1733
-TDPBSUD 1734
-TDPBUSD 1735
-TDPBUUD 1736
-TDPFP 1737
-TDPHBF 1738
-TDPHF 1739
-TEST 1740
-TESTUI 1741
-TILELOADD 1742
-TILELOADDRS 1743
-TILELOADDRST 1744
-TILELOADDRS_EVEX 1745
-TILELOADDT 1746
-TILELOADD_EVEX 1747
-TILEMOVROWrre 1748
-TILEMOVROWrri 1749
-TILERELEASE 1750
-TILESTORED 1751
-TILESTORED_EVEX 1752
-TILEZERO 1753
-TLBSYNC 1754
-TLSCall 1755
-TLS_addr 1756
-TLS_addrX 1757
-TLS_base_addr 1758
-TLS_base_addrX 1759
-TLS_desc 1760
-TMMULTF 1761
-TPAUSE 1762
-TRAP 1763
-TST_F 1764
-TST_Fp 1765
-TTCMMIMFP 1766
-TTCMMRLFP 1767
-TTDPBF 1768
-TTDPFP 1769
-TTMMULTF 1770
-TTRANSPOSED 1771
-TZCNT 1772
-TZMSK 1773
-UBSAN_UD 1774
-UCOMISDrm 1775
-UCOMISDrm_Int 1776
-UCOMISDrr 1777
-UCOMISDrr_Int 1778
-UCOMISSrm 1779
-UCOMISSrm_Int 1780
-UCOMISSrr 1781
-UCOMISSrr_Int 1782
-UCOM_FIPr 1783
-UCOM_FIr 1784
-UCOM_FPPr 1785
-UCOM_FPr 1786
-UCOM_FpIr 1787
-UCOM_Fpr 1788
-UCOM_Fr 1789
-UD 1790
-UIRET 1791
-UMONITOR 1792
-UMWAIT 1793
-UNPCKHPDrm 1794
-UNPCKHPDrr 1795
-UNPCKHPSrm 1796
-UNPCKHPSrr 1797
-UNPCKLPDrm 1798
-UNPCKLPDrr 1799
-UNPCKLPSrm 1800
-UNPCKLPSrr 1801
-URDMSRri 1802
-URDMSRri_EVEX 1803
-URDMSRrr 1804
-URDMSRrr_EVEX 1805
-UWRMSRir 1806
-UWRMSRir_EVEX 1807
-UWRMSRrr 1808
-UWRMSRrr_EVEX 1809
-V 1810
-VAARG 1811
-VAARG_X 1812
-VADDBF 1813
-VADDPDYrm 1814
-VADDPDYrr 1815
-VADDPDZ 1816
-VADDPDZrm 1817
-VADDPDZrmb 1818
-VADDPDZrmbk 1819
-VADDPDZrmbkz 1820
-VADDPDZrmk 1821
-VADDPDZrmkz 1822
-VADDPDZrr 1823
-VADDPDZrrb 1824
-VADDPDZrrbk 1825
-VADDPDZrrbkz 1826
-VADDPDZrrk 1827
-VADDPDZrrkz 1828
-VADDPDrm 1829
-VADDPDrr 1830
-VADDPHZ 1831
-VADDPHZrm 1832
-VADDPHZrmb 1833
-VADDPHZrmbk 1834
-VADDPHZrmbkz 1835
-VADDPHZrmk 1836
-VADDPHZrmkz 1837
-VADDPHZrr 1838
-VADDPHZrrb 1839
-VADDPHZrrbk 1840
-VADDPHZrrbkz 1841
-VADDPHZrrk 1842
-VADDPHZrrkz 1843
-VADDPSYrm 1844
-VADDPSYrr 1845
-VADDPSZ 1846
-VADDPSZrm 1847
-VADDPSZrmb 1848
-VADDPSZrmbk 1849
-VADDPSZrmbkz 1850
-VADDPSZrmk 1851
-VADDPSZrmkz 1852
-VADDPSZrr 1853
-VADDPSZrrb 1854
-VADDPSZrrbk 1855
-VADDPSZrrbkz 1856
-VADDPSZrrk 1857
-VADDPSZrrkz 1858
-VADDPSrm 1859
-VADDPSrr 1860
-VADDSDZrm 1861
-VADDSDZrm_Int 1862
-VADDSDZrmk_Int 1863
-VADDSDZrmkz_Int 1864
-VADDSDZrr 1865
-VADDSDZrr_Int 1866
-VADDSDZrrb_Int 1867
-VADDSDZrrbk_Int 1868
-VADDSDZrrbkz_Int 1869
-VADDSDZrrk_Int 1870
-VADDSDZrrkz_Int 1871
-VADDSDrm 1872
-VADDSDrm_Int 1873
-VADDSDrr 1874
-VADDSDrr_Int 1875
-VADDSHZrm 1876
-VADDSHZrm_Int 1877
-VADDSHZrmk_Int 1878
-VADDSHZrmkz_Int 1879
-VADDSHZrr 1880
-VADDSHZrr_Int 1881
-VADDSHZrrb_Int 1882
-VADDSHZrrbk_Int 1883
-VADDSHZrrbkz_Int 1884
-VADDSHZrrk_Int 1885
-VADDSHZrrkz_Int 1886
-VADDSSZrm 1887
-VADDSSZrm_Int 1888
-VADDSSZrmk_Int 1889
-VADDSSZrmkz_Int 1890
-VADDSSZrr 1891
-VADDSSZrr_Int 1892
-VADDSSZrrb_Int 1893
-VADDSSZrrbk_Int 1894
-VADDSSZrrbkz_Int 1895
-VADDSSZrrk_Int 1896
-VADDSSZrrkz_Int 1897
-VADDSSrm 1898
-VADDSSrm_Int 1899
-VADDSSrr 1900
-VADDSSrr_Int 1901
-VADDSUBPDYrm 1902
-VADDSUBPDYrr 1903
-VADDSUBPDrm 1904
-VADDSUBPDrr 1905
-VADDSUBPSYrm 1906
-VADDSUBPSYrr 1907
-VADDSUBPSrm 1908
-VADDSUBPSrr 1909
-VAESDECLASTYrm 1910
-VAESDECLASTYrr 1911
-VAESDECLASTZ 1912
-VAESDECLASTZrm 1913
-VAESDECLASTZrr 1914
-VAESDECLASTrm 1915
-VAESDECLASTrr 1916
-VAESDECYrm 1917
-VAESDECYrr 1918
-VAESDECZ 1919
-VAESDECZrm 1920
-VAESDECZrr 1921
-VAESDECrm 1922
-VAESDECrr 1923
-VAESENCLASTYrm 1924
-VAESENCLASTYrr 1925
-VAESENCLASTZ 1926
-VAESENCLASTZrm 1927
-VAESENCLASTZrr 1928
-VAESENCLASTrm 1929
-VAESENCLASTrr 1930
-VAESENCYrm 1931
-VAESENCYrr 1932
-VAESENCZ 1933
-VAESENCZrm 1934
-VAESENCZrr 1935
-VAESENCrm 1936
-VAESENCrr 1937
-VAESIMCrm 1938
-VAESIMCrr 1939
-VAESKEYGENASSISTrmi 1940
-VAESKEYGENASSISTrri 1941
-VALIGNDZ 1942
-VALIGNDZrmbi 1943
-VALIGNDZrmbik 1944
-VALIGNDZrmbikz 1945
-VALIGNDZrmi 1946
-VALIGNDZrmik 1947
-VALIGNDZrmikz 1948
-VALIGNDZrri 1949
-VALIGNDZrrik 1950
-VALIGNDZrrikz 1951
-VALIGNQZ 1952
-VALIGNQZrmbi 1953
-VALIGNQZrmbik 1954
-VALIGNQZrmbikz 1955
-VALIGNQZrmi 1956
-VALIGNQZrmik 1957
-VALIGNQZrmikz 1958
-VALIGNQZrri 1959
-VALIGNQZrrik 1960
-VALIGNQZrrikz 1961
-VANDNPDYrm 1962
-VANDNPDYrr 1963
-VANDNPDZ 1964
-VANDNPDZrm 1965
-VANDNPDZrmb 1966
-VANDNPDZrmbk 1967
-VANDNPDZrmbkz 1968
-VANDNPDZrmk 1969
-VANDNPDZrmkz 1970
-VANDNPDZrr 1971
-VANDNPDZrrk 1972
-VANDNPDZrrkz 1973
-VANDNPDrm 1974
-VANDNPDrr 1975
-VANDNPSYrm 1976
-VANDNPSYrr 1977
-VANDNPSZ 1978
-VANDNPSZrm 1979
-VANDNPSZrmb 1980
-VANDNPSZrmbk 1981
-VANDNPSZrmbkz 1982
-VANDNPSZrmk 1983
-VANDNPSZrmkz 1984
-VANDNPSZrr 1985
-VANDNPSZrrk 1986
-VANDNPSZrrkz 1987
-VANDNPSrm 1988
-VANDNPSrr 1989
-VANDPDYrm 1990
-VANDPDYrr 1991
-VANDPDZ 1992
-VANDPDZrm 1993
-VANDPDZrmb 1994
-VANDPDZrmbk 1995
-VANDPDZrmbkz 1996
-VANDPDZrmk 1997
-VANDPDZrmkz 1998
-VANDPDZrr 1999
-VANDPDZrrk 2000
-VANDPDZrrkz 2001
-VANDPDrm 2002
-VANDPDrr 2003
-VANDPSYrm 2004
-VANDPSYrr 2005
-VANDPSZ 2006
-VANDPSZrm 2007
-VANDPSZrmb 2008
-VANDPSZrmbk 2009
-VANDPSZrmbkz 2010
-VANDPSZrmk 2011
-VANDPSZrmkz 2012
-VANDPSZrr 2013
-VANDPSZrrk 2014
-VANDPSZrrkz 2015
-VANDPSrm 2016
-VANDPSrr 2017
-VASTART_SAVE_XMM_REGS 2018
-VBCSTNEBF 2019
-VBCSTNESH 2020
-VBLENDMPDZ 2021
-VBLENDMPDZrm 2022
-VBLENDMPDZrmb 2023
-VBLENDMPDZrmbk 2024
-VBLENDMPDZrmbkz 2025
-VBLENDMPDZrmk 2026
-VBLENDMPDZrmkz 2027
-VBLENDMPDZrr 2028
-VBLENDMPDZrrk 2029
-VBLENDMPDZrrkz 2030
-VBLENDMPSZ 2031
-VBLENDMPSZrm 2032
-VBLENDMPSZrmb 2033
-VBLENDMPSZrmbk 2034
-VBLENDMPSZrmbkz 2035
-VBLENDMPSZrmk 2036
-VBLENDMPSZrmkz 2037
-VBLENDMPSZrr 2038
-VBLENDMPSZrrk 2039
-VBLENDMPSZrrkz 2040
-VBLENDPDYrmi 2041
-VBLENDPDYrri 2042
-VBLENDPDrmi 2043
-VBLENDPDrri 2044
-VBLENDPSYrmi 2045
-VBLENDPSYrri 2046
-VBLENDPSrmi 2047
-VBLENDPSrri 2048
-VBLENDVPDYrmr 2049
-VBLENDVPDYrrr 2050
-VBLENDVPDrmr 2051
-VBLENDVPDrrr 2052
-VBLENDVPSYrmr 2053
-VBLENDVPSYrrr 2054
-VBLENDVPSrmr 2055
-VBLENDVPSrrr 2056
-VBROADCASTF 2057
-VBROADCASTI 2058
-VBROADCASTSDYrm 2059
-VBROADCASTSDYrr 2060
-VBROADCASTSDZ 2061
-VBROADCASTSDZrm 2062
-VBROADCASTSDZrmk 2063
-VBROADCASTSDZrmkz 2064
-VBROADCASTSDZrr 2065
-VBROADCASTSDZrrk 2066
-VBROADCASTSDZrrkz 2067
-VBROADCASTSSYrm 2068
-VBROADCASTSSYrr 2069
-VBROADCASTSSZ 2070
-VBROADCASTSSZrm 2071
-VBROADCASTSSZrmk 2072
-VBROADCASTSSZrmkz 2073
-VBROADCASTSSZrr 2074
-VBROADCASTSSZrrk 2075
-VBROADCASTSSZrrkz 2076
-VBROADCASTSSrm 2077
-VBROADCASTSSrr 2078
-VCMPBF 2079
-VCMPPDYrmi 2080
-VCMPPDYrri 2081
-VCMPPDZ 2082
-VCMPPDZrmbi 2083
-VCMPPDZrmbik 2084
-VCMPPDZrmi 2085
-VCMPPDZrmik 2086
-VCMPPDZrri 2087
-VCMPPDZrrib 2088
-VCMPPDZrribk 2089
-VCMPPDZrrik 2090
-VCMPPDrmi 2091
-VCMPPDrri 2092
-VCMPPHZ 2093
-VCMPPHZrmbi 2094
-VCMPPHZrmbik 2095
-VCMPPHZrmi 2096
-VCMPPHZrmik 2097
-VCMPPHZrri 2098
-VCMPPHZrrib 2099
-VCMPPHZrribk 2100
-VCMPPHZrrik 2101
-VCMPPSYrmi 2102
-VCMPPSYrri 2103
-VCMPPSZ 2104
-VCMPPSZrmbi 2105
-VCMPPSZrmbik 2106
-VCMPPSZrmi 2107
-VCMPPSZrmik 2108
-VCMPPSZrri 2109
-VCMPPSZrrib 2110
-VCMPPSZrribk 2111
-VCMPPSZrrik 2112
-VCMPPSrmi 2113
-VCMPPSrri 2114
-VCMPSDZrmi 2115
-VCMPSDZrmi_Int 2116
-VCMPSDZrmik_Int 2117
-VCMPSDZrri 2118
-VCMPSDZrri_Int 2119
-VCMPSDZrrib_Int 2120
-VCMPSDZrribk_Int 2121
-VCMPSDZrrik_Int 2122
-VCMPSDrmi 2123
-VCMPSDrmi_Int 2124
-VCMPSDrri 2125
-VCMPSDrri_Int 2126
-VCMPSHZrmi 2127
-VCMPSHZrmi_Int 2128
-VCMPSHZrmik_Int 2129
-VCMPSHZrri 2130
-VCMPSHZrri_Int 2131
-VCMPSHZrrib_Int 2132
-VCMPSHZrribk_Int 2133
-VCMPSHZrrik_Int 2134
-VCMPSSZrmi 2135
-VCMPSSZrmi_Int 2136
-VCMPSSZrmik_Int 2137
-VCMPSSZrri 2138
-VCMPSSZrri_Int 2139
-VCMPSSZrrib_Int 2140
-VCMPSSZrribk_Int 2141
-VCMPSSZrrik_Int 2142
-VCMPSSrmi 2143
-VCMPSSrmi_Int 2144
-VCMPSSrri 2145
-VCMPSSrri_Int 2146
-VCOMISBF 2147
-VCOMISDZrm 2148
-VCOMISDZrm_Int 2149
-VCOMISDZrr 2150
-VCOMISDZrr_Int 2151
-VCOMISDZrrb 2152
-VCOMISDrm 2153
-VCOMISDrm_Int 2154
-VCOMISDrr 2155
-VCOMISDrr_Int 2156
-VCOMISHZrm 2157
-VCOMISHZrm_Int 2158
-VCOMISHZrr 2159
-VCOMISHZrr_Int 2160
-VCOMISHZrrb 2161
-VCOMISSZrm 2162
-VCOMISSZrm_Int 2163
-VCOMISSZrr 2164
-VCOMISSZrr_Int 2165
-VCOMISSZrrb 2166
-VCOMISSrm 2167
-VCOMISSrm_Int 2168
-VCOMISSrr 2169
-VCOMISSrr_Int 2170
-VCOMPRESSPDZ 2171
-VCOMPRESSPDZmr 2172
-VCOMPRESSPDZmrk 2173
-VCOMPRESSPDZrr 2174
-VCOMPRESSPDZrrk 2175
-VCOMPRESSPDZrrkz 2176
-VCOMPRESSPSZ 2177
-VCOMPRESSPSZmr 2178
-VCOMPRESSPSZmrk 2179
-VCOMPRESSPSZrr 2180
-VCOMPRESSPSZrrk 2181
-VCOMPRESSPSZrrkz 2182
-VCOMXSDZrm_Int 2183
-VCOMXSDZrr_Int 2184
-VCOMXSDZrrb_Int 2185
-VCOMXSHZrm_Int 2186
-VCOMXSHZrr_Int 2187
-VCOMXSHZrrb_Int 2188
-VCOMXSSZrm_Int 2189
-VCOMXSSZrr_Int 2190
-VCOMXSSZrrb_Int 2191
-VCVT 2192
-VCVTBF 2193
-VCVTBIASPH 2194
-VCVTDQ 2195
-VCVTHF 2196
-VCVTNE 2197
-VCVTNEEBF 2198
-VCVTNEEPH 2199
-VCVTNEOBF 2200
-VCVTNEOPH 2201
-VCVTNEPS 2202
-VCVTPD 2203
-VCVTPH 2204
-VCVTPS 2205
-VCVTQQ 2206
-VCVTSD 2207
-VCVTSH 2208
-VCVTSI 2209
-VCVTSS 2210
-VCVTTBF 2211
-VCVTTPD 2212
-VCVTTPH 2213
-VCVTTPS 2214
-VCVTTSD 2215
-VCVTTSH 2216
-VCVTTSS 2217
-VCVTUDQ 2218
-VCVTUQQ 2219
-VCVTUSI 2220
-VCVTUW 2221
-VCVTW 2222
-VDBPSADBWZ 2223
-VDBPSADBWZrmi 2224
-VDBPSADBWZrmik 2225
-VDBPSADBWZrmikz 2226
-VDBPSADBWZrri 2227
-VDBPSADBWZrrik 2228
-VDBPSADBWZrrikz 2229
-VDIVBF 2230
-VDIVPDYrm 2231
-VDIVPDYrr 2232
-VDIVPDZ 2233
-VDIVPDZrm 2234
-VDIVPDZrmb 2235
-VDIVPDZrmbk 2236
-VDIVPDZrmbkz 2237
-VDIVPDZrmk 2238
-VDIVPDZrmkz 2239
-VDIVPDZrr 2240
-VDIVPDZrrb 2241
-VDIVPDZrrbk 2242
-VDIVPDZrrbkz 2243
-VDIVPDZrrk 2244
-VDIVPDZrrkz 2245
-VDIVPDrm 2246
-VDIVPDrr 2247
-VDIVPHZ 2248
-VDIVPHZrm 2249
-VDIVPHZrmb 2250
-VDIVPHZrmbk 2251
-VDIVPHZrmbkz 2252
-VDIVPHZrmk 2253
-VDIVPHZrmkz 2254
-VDIVPHZrr 2255
-VDIVPHZrrb 2256
-VDIVPHZrrbk 2257
-VDIVPHZrrbkz 2258
-VDIVPHZrrk 2259
-VDIVPHZrrkz 2260
-VDIVPSYrm 2261
-VDIVPSYrr 2262
-VDIVPSZ 2263
-VDIVPSZrm 2264
-VDIVPSZrmb 2265
-VDIVPSZrmbk 2266
-VDIVPSZrmbkz 2267
-VDIVPSZrmk 2268
-VDIVPSZrmkz 2269
-VDIVPSZrr 2270
-VDIVPSZrrb 2271
-VDIVPSZrrbk 2272
-VDIVPSZrrbkz 2273
-VDIVPSZrrk 2274
-VDIVPSZrrkz 2275
-VDIVPSrm 2276
-VDIVPSrr 2277
-VDIVSDZrm 2278
-VDIVSDZrm_Int 2279
-VDIVSDZrmk_Int 2280
-VDIVSDZrmkz_Int 2281
-VDIVSDZrr 2282
-VDIVSDZrr_Int 2283
-VDIVSDZrrb_Int 2284
-VDIVSDZrrbk_Int 2285
-VDIVSDZrrbkz_Int 2286
-VDIVSDZrrk_Int 2287
-VDIVSDZrrkz_Int 2288
-VDIVSDrm 2289
-VDIVSDrm_Int 2290
-VDIVSDrr 2291
-VDIVSDrr_Int 2292
-VDIVSHZrm 2293
-VDIVSHZrm_Int 2294
-VDIVSHZrmk_Int 2295
-VDIVSHZrmkz_Int 2296
-VDIVSHZrr 2297
-VDIVSHZrr_Int 2298
-VDIVSHZrrb_Int 2299
-VDIVSHZrrbk_Int 2300
-VDIVSHZrrbkz_Int 2301
-VDIVSHZrrk_Int 2302
-VDIVSHZrrkz_Int 2303
-VDIVSSZrm 2304
-VDIVSSZrm_Int 2305
-VDIVSSZrmk_Int 2306
-VDIVSSZrmkz_Int 2307
-VDIVSSZrr 2308
-VDIVSSZrr_Int 2309
-VDIVSSZrrb_Int 2310
-VDIVSSZrrbk_Int 2311
-VDIVSSZrrbkz_Int 2312
-VDIVSSZrrk_Int 2313
-VDIVSSZrrkz_Int 2314
-VDIVSSrm 2315
-VDIVSSrm_Int 2316
-VDIVSSrr 2317
-VDIVSSrr_Int 2318
-VDPBF 2319
-VDPPDrmi 2320
-VDPPDrri 2321
-VDPPHPSZ 2322
-VDPPHPSZm 2323
-VDPPHPSZmb 2324
-VDPPHPSZmbk 2325
-VDPPHPSZmbkz 2326
-VDPPHPSZmk 2327
-VDPPHPSZmkz 2328
-VDPPHPSZr 2329
-VDPPHPSZrk 2330
-VDPPHPSZrkz 2331
-VDPPSYrmi 2332
-VDPPSYrri 2333
-VDPPSrmi 2334
-VDPPSrri 2335
-VERRm 2336
-VERRr 2337
-VERWm 2338
-VERWr 2339
-VEXP 2340
-VEXPANDPDZ 2341
-VEXPANDPDZrm 2342
-VEXPANDPDZrmk 2343
-VEXPANDPDZrmkz 2344
-VEXPANDPDZrr 2345
-VEXPANDPDZrrk 2346
-VEXPANDPDZrrkz 2347
-VEXPANDPSZ 2348
-VEXPANDPSZrm 2349
-VEXPANDPSZrmk 2350
-VEXPANDPSZrmkz 2351
-VEXPANDPSZrr 2352
-VEXPANDPSZrrk 2353
-VEXPANDPSZrrkz 2354
-VEXTRACTF 2355
-VEXTRACTI 2356
-VEXTRACTPSZmri 2357
-VEXTRACTPSZrri 2358
-VEXTRACTPSmri 2359
-VEXTRACTPSrri 2360
-VFCMADDCPHZ 2361
-VFCMADDCPHZm 2362
-VFCMADDCPHZmb 2363
-VFCMADDCPHZmbk 2364
-VFCMADDCPHZmbkz 2365
-VFCMADDCPHZmk 2366
-VFCMADDCPHZmkz 2367
-VFCMADDCPHZr 2368
-VFCMADDCPHZrb 2369
-VFCMADDCPHZrbk 2370
-VFCMADDCPHZrbkz 2371
-VFCMADDCPHZrk 2372
-VFCMADDCPHZrkz 2373
-VFCMADDCSHZm 2374
-VFCMADDCSHZmk 2375
-VFCMADDCSHZmkz 2376
-VFCMADDCSHZr 2377
-VFCMADDCSHZrb 2378
-VFCMADDCSHZrbk 2379
-VFCMADDCSHZrbkz 2380
-VFCMADDCSHZrk 2381
-VFCMADDCSHZrkz 2382
-VFCMULCPHZ 2383
-VFCMULCPHZrm 2384
-VFCMULCPHZrmb 2385
-VFCMULCPHZrmbk 2386
-VFCMULCPHZrmbkz 2387
-VFCMULCPHZrmk 2388
-VFCMULCPHZrmkz 2389
-VFCMULCPHZrr 2390
-VFCMULCPHZrrb 2391
-VFCMULCPHZrrbk 2392
-VFCMULCPHZrrbkz 2393
-VFCMULCPHZrrk 2394
-VFCMULCPHZrrkz 2395
-VFCMULCSHZrm 2396
-VFCMULCSHZrmk 2397
-VFCMULCSHZrmkz 2398
-VFCMULCSHZrr 2399
-VFCMULCSHZrrb 2400
-VFCMULCSHZrrbk 2401
-VFCMULCSHZrrbkz 2402
-VFCMULCSHZrrk 2403
-VFCMULCSHZrrkz 2404
-VFIXUPIMMPDZ 2405
-VFIXUPIMMPDZrmbi 2406
-VFIXUPIMMPDZrmbik 2407
-VFIXUPIMMPDZrmbikz 2408
-VFIXUPIMMPDZrmi 2409
-VFIXUPIMMPDZrmik 2410
-VFIXUPIMMPDZrmikz 2411
-VFIXUPIMMPDZrri 2412
-VFIXUPIMMPDZrrib 2413
-VFIXUPIMMPDZrribk 2414
-VFIXUPIMMPDZrribkz 2415
-VFIXUPIMMPDZrrik 2416
-VFIXUPIMMPDZrrikz 2417
-VFIXUPIMMPSZ 2418
-VFIXUPIMMPSZrmbi 2419
-VFIXUPIMMPSZrmbik 2420
-VFIXUPIMMPSZrmbikz 2421
-VFIXUPIMMPSZrmi 2422
-VFIXUPIMMPSZrmik 2423
-VFIXUPIMMPSZrmikz 2424
-VFIXUPIMMPSZrri 2425
-VFIXUPIMMPSZrrib 2426
-VFIXUPIMMPSZrribk 2427
-VFIXUPIMMPSZrribkz 2428
-VFIXUPIMMPSZrrik 2429
-VFIXUPIMMPSZrrikz 2430
-VFIXUPIMMSDZrmi 2431
-VFIXUPIMMSDZrmik 2432
-VFIXUPIMMSDZrmikz 2433
-VFIXUPIMMSDZrri 2434
-VFIXUPIMMSDZrrib 2435
-VFIXUPIMMSDZrribk 2436
-VFIXUPIMMSDZrribkz 2437
-VFIXUPIMMSDZrrik 2438
-VFIXUPIMMSDZrrikz 2439
-VFIXUPIMMSSZrmi 2440
-VFIXUPIMMSSZrmik 2441
-VFIXUPIMMSSZrmikz 2442
-VFIXUPIMMSSZrri 2443
-VFIXUPIMMSSZrrib 2444
-VFIXUPIMMSSZrribk 2445
-VFIXUPIMMSSZrribkz 2446
-VFIXUPIMMSSZrrik 2447
-VFIXUPIMMSSZrrikz 2448
-VFMADD 2449
-VFMADDCPHZ 2450
-VFMADDCPHZm 2451
-VFMADDCPHZmb 2452
-VFMADDCPHZmbk 2453
-VFMADDCPHZmbkz 2454
-VFMADDCPHZmk 2455
-VFMADDCPHZmkz 2456
-VFMADDCPHZr 2457
-VFMADDCPHZrb 2458
-VFMADDCPHZrbk 2459
-VFMADDCPHZrbkz 2460
-VFMADDCPHZrk 2461
-VFMADDCPHZrkz 2462
-VFMADDCSHZm 2463
-VFMADDCSHZmk 2464
-VFMADDCSHZmkz 2465
-VFMADDCSHZr 2466
-VFMADDCSHZrb 2467
-VFMADDCSHZrbk 2468
-VFMADDCSHZrbkz 2469
-VFMADDCSHZrk 2470
-VFMADDCSHZrkz 2471
-VFMADDPD 2472
-VFMADDPS 2473
-VFMADDSD 2474
-VFMADDSS 2475
-VFMADDSUB 2476
-VFMADDSUBPD 2477
-VFMADDSUBPS 2478
-VFMSUB 2479
-VFMSUBADD 2480
-VFMSUBADDPD 2481
-VFMSUBADDPS 2482
-VFMSUBPD 2483
-VFMSUBPS 2484
-VFMSUBSD 2485
-VFMSUBSS 2486
-VFMULCPHZ 2487
-VFMULCPHZrm 2488
-VFMULCPHZrmb 2489
-VFMULCPHZrmbk 2490
-VFMULCPHZrmbkz 2491
-VFMULCPHZrmk 2492
-VFMULCPHZrmkz 2493
-VFMULCPHZrr 2494
-VFMULCPHZrrb 2495
-VFMULCPHZrrbk 2496
-VFMULCPHZrrbkz 2497
-VFMULCPHZrrk 2498
-VFMULCPHZrrkz 2499
-VFMULCSHZrm 2500
-VFMULCSHZrmk 2501
-VFMULCSHZrmkz 2502
-VFMULCSHZrr 2503
-VFMULCSHZrrb 2504
-VFMULCSHZrrbk 2505
-VFMULCSHZrrbkz 2506
-VFMULCSHZrrk 2507
-VFMULCSHZrrkz 2508
-VFNMADD 2509
-VFNMADDPD 2510
-VFNMADDPS 2511
-VFNMADDSD 2512
-VFNMADDSS 2513
-VFNMSUB 2514
-VFNMSUBPD 2515
-VFNMSUBPS 2516
-VFNMSUBSD 2517
-VFNMSUBSS 2518
-VFPCLASSBF 2519
-VFPCLASSPDZ 2520
-VFPCLASSPDZmbi 2521
-VFPCLASSPDZmbik 2522
-VFPCLASSPDZmi 2523
-VFPCLASSPDZmik 2524
-VFPCLASSPDZri 2525
-VFPCLASSPDZrik 2526
-VFPCLASSPHZ 2527
-VFPCLASSPHZmbi 2528
-VFPCLASSPHZmbik 2529
-VFPCLASSPHZmi 2530
-VFPCLASSPHZmik 2531
-VFPCLASSPHZri 2532
-VFPCLASSPHZrik 2533
-VFPCLASSPSZ 2534
-VFPCLASSPSZmbi 2535
-VFPCLASSPSZmbik 2536
-VFPCLASSPSZmi 2537
-VFPCLASSPSZmik 2538
-VFPCLASSPSZri 2539
-VFPCLASSPSZrik 2540
-VFPCLASSSDZmi 2541
-VFPCLASSSDZmik 2542
-VFPCLASSSDZri 2543
-VFPCLASSSDZrik 2544
-VFPCLASSSHZmi 2545
-VFPCLASSSHZmik 2546
-VFPCLASSSHZri 2547
-VFPCLASSSHZrik 2548
-VFPCLASSSSZmi 2549
-VFPCLASSSSZmik 2550
-VFPCLASSSSZri 2551
-VFPCLASSSSZrik 2552
-VFRCZPDYrm 2553
-VFRCZPDYrr 2554
-VFRCZPDrm 2555
-VFRCZPDrr 2556
-VFRCZPSYrm 2557
-VFRCZPSYrr 2558
-VFRCZPSrm 2559
-VFRCZPSrr 2560
-VFRCZSDrm 2561
-VFRCZSDrr 2562
-VFRCZSSrm 2563
-VFRCZSSrr 2564
-VGATHERDPDYrm 2565
-VGATHERDPDZ 2566
-VGATHERDPDZrm 2567
-VGATHERDPDrm 2568
-VGATHERDPSYrm 2569
-VGATHERDPSZ 2570
-VGATHERDPSZrm 2571
-VGATHERDPSrm 2572
-VGATHERPF 2573
-VGATHERQPDYrm 2574
-VGATHERQPDZ 2575
-VGATHERQPDZrm 2576
-VGATHERQPDrm 2577
-VGATHERQPSYrm 2578
-VGATHERQPSZ 2579
-VGATHERQPSZrm 2580
-VGATHERQPSrm 2581
-VGETEXPBF 2582
-VGETEXPPDZ 2583
-VGETEXPPDZm 2584
-VGETEXPPDZmb 2585
-VGETEXPPDZmbk 2586
-VGETEXPPDZmbkz 2587
-VGETEXPPDZmk 2588
-VGETEXPPDZmkz 2589
-VGETEXPPDZr 2590
-VGETEXPPDZrb 2591
-VGETEXPPDZrbk 2592
-VGETEXPPDZrbkz 2593
-VGETEXPPDZrk 2594
-VGETEXPPDZrkz 2595
-VGETEXPPHZ 2596
-VGETEXPPHZm 2597
-VGETEXPPHZmb 2598
-VGETEXPPHZmbk 2599
-VGETEXPPHZmbkz 2600
-VGETEXPPHZmk 2601
-VGETEXPPHZmkz 2602
-VGETEXPPHZr 2603
-VGETEXPPHZrb 2604
-VGETEXPPHZrbk 2605
-VGETEXPPHZrbkz 2606
-VGETEXPPHZrk 2607
-VGETEXPPHZrkz 2608
-VGETEXPPSZ 2609
-VGETEXPPSZm 2610
-VGETEXPPSZmb 2611
-VGETEXPPSZmbk 2612
-VGETEXPPSZmbkz 2613
-VGETEXPPSZmk 2614
-VGETEXPPSZmkz 2615
-VGETEXPPSZr 2616
-VGETEXPPSZrb 2617
-VGETEXPPSZrbk 2618
-VGETEXPPSZrbkz 2619
-VGETEXPPSZrk 2620
-VGETEXPPSZrkz 2621
-VGETEXPSDZm 2622
-VGETEXPSDZmk 2623
-VGETEXPSDZmkz 2624
-VGETEXPSDZr 2625
-VGETEXPSDZrb 2626
-VGETEXPSDZrbk 2627
-VGETEXPSDZrbkz 2628
-VGETEXPSDZrk 2629
-VGETEXPSDZrkz 2630
-VGETEXPSHZm 2631
-VGETEXPSHZmk 2632
-VGETEXPSHZmkz 2633
-VGETEXPSHZr 2634
-VGETEXPSHZrb 2635
-VGETEXPSHZrbk 2636
-VGETEXPSHZrbkz 2637
-VGETEXPSHZrk 2638
-VGETEXPSHZrkz 2639
-VGETEXPSSZm 2640
-VGETEXPSSZmk 2641
-VGETEXPSSZmkz 2642
-VGETEXPSSZr 2643
-VGETEXPSSZrb 2644
-VGETEXPSSZrbk 2645
-VGETEXPSSZrbkz 2646
-VGETEXPSSZrk 2647
-VGETEXPSSZrkz 2648
-VGETMANTBF 2649
-VGETMANTPDZ 2650
-VGETMANTPDZrmbi 2651
-VGETMANTPDZrmbik 2652
-VGETMANTPDZrmbikz 2653
-VGETMANTPDZrmi 2654
-VGETMANTPDZrmik 2655
-VGETMANTPDZrmikz 2656
-VGETMANTPDZrri 2657
-VGETMANTPDZrrib 2658
-VGETMANTPDZrribk 2659
-VGETMANTPDZrribkz 2660
-VGETMANTPDZrrik 2661
-VGETMANTPDZrrikz 2662
-VGETMANTPHZ 2663
-VGETMANTPHZrmbi 2664
-VGETMANTPHZrmbik 2665
-VGETMANTPHZrmbikz 2666
-VGETMANTPHZrmi 2667
-VGETMANTPHZrmik 2668
-VGETMANTPHZrmikz 2669
-VGETMANTPHZrri 2670
-VGETMANTPHZrrib 2671
-VGETMANTPHZrribk 2672
-VGETMANTPHZrribkz 2673
-VGETMANTPHZrrik 2674
-VGETMANTPHZrrikz 2675
-VGETMANTPSZ 2676
-VGETMANTPSZrmbi 2677
-VGETMANTPSZrmbik 2678
-VGETMANTPSZrmbikz 2679
-VGETMANTPSZrmi 2680
-VGETMANTPSZrmik 2681
-VGETMANTPSZrmikz 2682
-VGETMANTPSZrri 2683
-VGETMANTPSZrrib 2684
-VGETMANTPSZrribk 2685
-VGETMANTPSZrribkz 2686
-VGETMANTPSZrrik 2687
-VGETMANTPSZrrikz 2688
-VGETMANTSDZrmi 2689
-VGETMANTSDZrmik 2690
-VGETMANTSDZrmikz 2691
-VGETMANTSDZrri 2692
-VGETMANTSDZrrib 2693
-VGETMANTSDZrribk 2694
-VGETMANTSDZrribkz 2695
-VGETMANTSDZrrik 2696
-VGETMANTSDZrrikz 2697
-VGETMANTSHZrmi 2698
-VGETMANTSHZrmik 2699
-VGETMANTSHZrmikz 2700
-VGETMANTSHZrri 2701
-VGETMANTSHZrrib 2702
-VGETMANTSHZrribk 2703
-VGETMANTSHZrribkz 2704
-VGETMANTSHZrrik 2705
-VGETMANTSHZrrikz 2706
-VGETMANTSSZrmi 2707
-VGETMANTSSZrmik 2708
-VGETMANTSSZrmikz 2709
-VGETMANTSSZrri 2710
-VGETMANTSSZrrib 2711
-VGETMANTSSZrribk 2712
-VGETMANTSSZrribkz 2713
-VGETMANTSSZrrik 2714
-VGETMANTSSZrrikz 2715
-VGF 2716
-VHADDPDYrm 2717
-VHADDPDYrr 2718
-VHADDPDrm 2719
-VHADDPDrr 2720
-VHADDPSYrm 2721
-VHADDPSYrr 2722
-VHADDPSrm 2723
-VHADDPSrr 2724
-VHSUBPDYrm 2725
-VHSUBPDYrr 2726
-VHSUBPDrm 2727
-VHSUBPDrr 2728
-VHSUBPSYrm 2729
-VHSUBPSYrr 2730
-VHSUBPSrm 2731
-VHSUBPSrr 2732
-VINSERTF 2733
-VINSERTI 2734
-VINSERTPSZrmi 2735
-VINSERTPSZrri 2736
-VINSERTPSrmi 2737
-VINSERTPSrri 2738
-VLDDQUYrm 2739
-VLDDQUrm 2740
-VLDMXCSR 2741
-VMASKMOVDQU 2742
-VMASKMOVPDYmr 2743
-VMASKMOVPDYrm 2744
-VMASKMOVPDmr 2745
-VMASKMOVPDrm 2746
-VMASKMOVPSYmr 2747
-VMASKMOVPSYrm 2748
-VMASKMOVPSmr 2749
-VMASKMOVPSrm 2750
-VMAXBF 2751
-VMAXCPDYrm 2752
-VMAXCPDYrr 2753
-VMAXCPDZ 2754
-VMAXCPDZrm 2755
-VMAXCPDZrmb 2756
-VMAXCPDZrmbk 2757
-VMAXCPDZrmbkz 2758
-VMAXCPDZrmk 2759
-VMAXCPDZrmkz 2760
-VMAXCPDZrr 2761
-VMAXCPDZrrk 2762
-VMAXCPDZrrkz 2763
-VMAXCPDrm 2764
-VMAXCPDrr 2765
-VMAXCPHZ 2766
-VMAXCPHZrm 2767
-VMAXCPHZrmb 2768
-VMAXCPHZrmbk 2769
-VMAXCPHZrmbkz 2770
-VMAXCPHZrmk 2771
-VMAXCPHZrmkz 2772
-VMAXCPHZrr 2773
-VMAXCPHZrrk 2774
-VMAXCPHZrrkz 2775
-VMAXCPSYrm 2776
-VMAXCPSYrr 2777
-VMAXCPSZ 2778
-VMAXCPSZrm 2779
-VMAXCPSZrmb 2780
-VMAXCPSZrmbk 2781
-VMAXCPSZrmbkz 2782
-VMAXCPSZrmk 2783
-VMAXCPSZrmkz 2784
-VMAXCPSZrr 2785
-VMAXCPSZrrk 2786
-VMAXCPSZrrkz 2787
-VMAXCPSrm 2788
-VMAXCPSrr 2789
-VMAXCSDZrm 2790
-VMAXCSDZrr 2791
-VMAXCSDrm 2792
-VMAXCSDrr 2793
-VMAXCSHZrm 2794
-VMAXCSHZrr 2795
-VMAXCSSZrm 2796
-VMAXCSSZrr 2797
-VMAXCSSrm 2798
-VMAXCSSrr 2799
-VMAXPDYrm 2800
-VMAXPDYrr 2801
-VMAXPDZ 2802
-VMAXPDZrm 2803
-VMAXPDZrmb 2804
-VMAXPDZrmbk 2805
-VMAXPDZrmbkz 2806
-VMAXPDZrmk 2807
-VMAXPDZrmkz 2808
-VMAXPDZrr 2809
-VMAXPDZrrb 2810
-VMAXPDZrrbk 2811
-VMAXPDZrrbkz 2812
-VMAXPDZrrk 2813
-VMAXPDZrrkz 2814
-VMAXPDrm 2815
-VMAXPDrr 2816
-VMAXPHZ 2817
-VMAXPHZrm 2818
-VMAXPHZrmb 2819
-VMAXPHZrmbk 2820
-VMAXPHZrmbkz 2821
-VMAXPHZrmk 2822
-VMAXPHZrmkz 2823
-VMAXPHZrr 2824
-VMAXPHZrrb 2825
-VMAXPHZrrbk 2826
-VMAXPHZrrbkz 2827
-VMAXPHZrrk 2828
-VMAXPHZrrkz 2829
-VMAXPSYrm 2830
-VMAXPSYrr 2831
-VMAXPSZ 2832
-VMAXPSZrm 2833
-VMAXPSZrmb 2834
-VMAXPSZrmbk 2835
-VMAXPSZrmbkz 2836
-VMAXPSZrmk 2837
-VMAXPSZrmkz 2838
-VMAXPSZrr 2839
-VMAXPSZrrb 2840
-VMAXPSZrrbk 2841
-VMAXPSZrrbkz 2842
-VMAXPSZrrk 2843
-VMAXPSZrrkz 2844
-VMAXPSrm 2845
-VMAXPSrr 2846
-VMAXSDZrm 2847
-VMAXSDZrm_Int 2848
-VMAXSDZrmk_Int 2849
-VMAXSDZrmkz_Int 2850
-VMAXSDZrr 2851
-VMAXSDZrr_Int 2852
-VMAXSDZrrb_Int 2853
-VMAXSDZrrbk_Int 2854
-VMAXSDZrrbkz_Int 2855
-VMAXSDZrrk_Int 2856
-VMAXSDZrrkz_Int 2857
-VMAXSDrm 2858
-VMAXSDrm_Int 2859
-VMAXSDrr 2860
-VMAXSDrr_Int 2861
-VMAXSHZrm 2862
-VMAXSHZrm_Int 2863
-VMAXSHZrmk_Int 2864
-VMAXSHZrmkz_Int 2865
-VMAXSHZrr 2866
-VMAXSHZrr_Int 2867
-VMAXSHZrrb_Int 2868
-VMAXSHZrrbk_Int 2869
-VMAXSHZrrbkz_Int 2870
-VMAXSHZrrk_Int 2871
-VMAXSHZrrkz_Int 2872
-VMAXSSZrm 2873
-VMAXSSZrm_Int 2874
-VMAXSSZrmk_Int 2875
-VMAXSSZrmkz_Int 2876
-VMAXSSZrr 2877
-VMAXSSZrr_Int 2878
-VMAXSSZrrb_Int 2879
-VMAXSSZrrbk_Int 2880
-VMAXSSZrrbkz_Int 2881
-VMAXSSZrrk_Int 2882
-VMAXSSZrrkz_Int 2883
-VMAXSSrm 2884
-VMAXSSrm_Int 2885
-VMAXSSrr 2886
-VMAXSSrr_Int 2887
-VMCALL 2888
-VMCLEARm 2889
-VMFUNC 2890
-VMINBF 2891
-VMINCPDYrm 2892
-VMINCPDYrr 2893
-VMINCPDZ 2894
-VMINCPDZrm 2895
-VMINCPDZrmb 2896
-VMINCPDZrmbk 2897
-VMINCPDZrmbkz 2898
-VMINCPDZrmk 2899
-VMINCPDZrmkz 2900
-VMINCPDZrr 2901
-VMINCPDZrrk 2902
-VMINCPDZrrkz 2903
-VMINCPDrm 2904
-VMINCPDrr 2905
-VMINCPHZ 2906
-VMINCPHZrm 2907
-VMINCPHZrmb 2908
-VMINCPHZrmbk 2909
-VMINCPHZrmbkz 2910
-VMINCPHZrmk 2911
-VMINCPHZrmkz 2912
-VMINCPHZrr 2913
-VMINCPHZrrk 2914
-VMINCPHZrrkz 2915
-VMINCPSYrm 2916
-VMINCPSYrr 2917
-VMINCPSZ 2918
-VMINCPSZrm 2919
-VMINCPSZrmb 2920
-VMINCPSZrmbk 2921
-VMINCPSZrmbkz 2922
-VMINCPSZrmk 2923
-VMINCPSZrmkz 2924
-VMINCPSZrr 2925
-VMINCPSZrrk 2926
-VMINCPSZrrkz 2927
-VMINCPSrm 2928
-VMINCPSrr 2929
-VMINCSDZrm 2930
-VMINCSDZrr 2931
-VMINCSDrm 2932
-VMINCSDrr 2933
-VMINCSHZrm 2934
-VMINCSHZrr 2935
-VMINCSSZrm 2936
-VMINCSSZrr 2937
-VMINCSSrm 2938
-VMINCSSrr 2939
-VMINMAXBF 2940
-VMINMAXPDZ 2941
-VMINMAXPDZrmbi 2942
-VMINMAXPDZrmbik 2943
-VMINMAXPDZrmbikz 2944
-VMINMAXPDZrmi 2945
-VMINMAXPDZrmik 2946
-VMINMAXPDZrmikz 2947
-VMINMAXPDZrri 2948
-VMINMAXPDZrrib 2949
-VMINMAXPDZrribk 2950
-VMINMAXPDZrribkz 2951
-VMINMAXPDZrrik 2952
-VMINMAXPDZrrikz 2953
-VMINMAXPHZ 2954
-VMINMAXPHZrmbi 2955
-VMINMAXPHZrmbik 2956
-VMINMAXPHZrmbikz 2957
-VMINMAXPHZrmi 2958
-VMINMAXPHZrmik 2959
-VMINMAXPHZrmikz 2960
-VMINMAXPHZrri 2961
-VMINMAXPHZrrib 2962
-VMINMAXPHZrribk 2963
-VMINMAXPHZrribkz 2964
-VMINMAXPHZrrik 2965
-VMINMAXPHZrrikz 2966
-VMINMAXPSZ 2967
-VMINMAXPSZrmbi 2968
-VMINMAXPSZrmbik 2969
-VMINMAXPSZrmbikz 2970
-VMINMAXPSZrmi 2971
-VMINMAXPSZrmik 2972
-VMINMAXPSZrmikz 2973
-VMINMAXPSZrri 2974
-VMINMAXPSZrrib 2975
-VMINMAXPSZrribk 2976
-VMINMAXPSZrribkz 2977
-VMINMAXPSZrrik 2978
-VMINMAXPSZrrikz 2979
-VMINMAXSDrmi 2980
-VMINMAXSDrmi_Int 2981
-VMINMAXSDrmik_Int 2982
-VMINMAXSDrmikz_Int 2983
-VMINMAXSDrri 2984
-VMINMAXSDrri_Int 2985
-VMINMAXSDrrib_Int 2986
-VMINMAXSDrribk_Int 2987
-VMINMAXSDrribkz_Int 2988
-VMINMAXSDrrik_Int 2989
-VMINMAXSDrrikz_Int 2990
-VMINMAXSHrmi 2991
-VMINMAXSHrmi_Int 2992
-VMINMAXSHrmik_Int 2993
-VMINMAXSHrmikz_Int 2994
-VMINMAXSHrri 2995
-VMINMAXSHrri_Int 2996
-VMINMAXSHrrib_Int 2997
-VMINMAXSHrribk_Int 2998
-VMINMAXSHrribkz_Int 2999
-VMINMAXSHrrik_Int 3000
-VMINMAXSHrrikz_Int 3001
-VMINMAXSSrmi 3002
-VMINMAXSSrmi_Int 3003
-VMINMAXSSrmik_Int 3004
-VMINMAXSSrmikz_Int 3005
-VMINMAXSSrri 3006
-VMINMAXSSrri_Int 3007
-VMINMAXSSrrib_Int 3008
-VMINMAXSSrribk_Int 3009
-VMINMAXSSrribkz_Int 3010
-VMINMAXSSrrik_Int 3011
-VMINMAXSSrrikz_Int 3012
-VMINPDYrm 3013
-VMINPDYrr 3014
-VMINPDZ 3015
-VMINPDZrm 3016
-VMINPDZrmb 3017
-VMINPDZrmbk 3018
-VMINPDZrmbkz 3019
-VMINPDZrmk 3020
-VMINPDZrmkz 3021
-VMINPDZrr 3022
-VMINPDZrrb 3023
-VMINPDZrrbk 3024
-VMINPDZrrbkz 3025
-VMINPDZrrk 3026
-VMINPDZrrkz 3027
-VMINPDrm 3028
-VMINPDrr 3029
-VMINPHZ 3030
-VMINPHZrm 3031
-VMINPHZrmb 3032
-VMINPHZrmbk 3033
-VMINPHZrmbkz 3034
-VMINPHZrmk 3035
-VMINPHZrmkz 3036
-VMINPHZrr 3037
-VMINPHZrrb 3038
-VMINPHZrrbk 3039
-VMINPHZrrbkz 3040
-VMINPHZrrk 3041
-VMINPHZrrkz 3042
-VMINPSYrm 3043
-VMINPSYrr 3044
-VMINPSZ 3045
-VMINPSZrm 3046
-VMINPSZrmb 3047
-VMINPSZrmbk 3048
-VMINPSZrmbkz 3049
-VMINPSZrmk 3050
-VMINPSZrmkz 3051
-VMINPSZrr 3052
-VMINPSZrrb 3053
-VMINPSZrrbk 3054
-VMINPSZrrbkz 3055
-VMINPSZrrk 3056
-VMINPSZrrkz 3057
-VMINPSrm 3058
-VMINPSrr 3059
-VMINSDZrm 3060
-VMINSDZrm_Int 3061
-VMINSDZrmk_Int 3062
-VMINSDZrmkz_Int 3063
-VMINSDZrr 3064
-VMINSDZrr_Int 3065
-VMINSDZrrb_Int 3066
-VMINSDZrrbk_Int 3067
-VMINSDZrrbkz_Int 3068
-VMINSDZrrk_Int 3069
-VMINSDZrrkz_Int 3070
-VMINSDrm 3071
-VMINSDrm_Int 3072
-VMINSDrr 3073
-VMINSDrr_Int 3074
-VMINSHZrm 3075
-VMINSHZrm_Int 3076
-VMINSHZrmk_Int 3077
-VMINSHZrmkz_Int 3078
-VMINSHZrr 3079
-VMINSHZrr_Int 3080
-VMINSHZrrb_Int 3081
-VMINSHZrrbk_Int 3082
-VMINSHZrrbkz_Int 3083
-VMINSHZrrk_Int 3084
-VMINSHZrrkz_Int 3085
-VMINSSZrm 3086
-VMINSSZrm_Int 3087
-VMINSSZrmk_Int 3088
-VMINSSZrmkz_Int 3089
-VMINSSZrr 3090
-VMINSSZrr_Int 3091
-VMINSSZrrb_Int 3092
-VMINSSZrrbk_Int 3093
-VMINSSZrrbkz_Int 3094
-VMINSSZrrk_Int 3095
-VMINSSZrrkz_Int 3096
-VMINSSrm 3097
-VMINSSrm_Int 3098
-VMINSSrr 3099
-VMINSSrr_Int 3100
-VMLAUNCH 3101
-VMLOAD 3102
-VMMCALL 3103
-VMOV 3104
-VMOVAPDYmr 3105
-VMOVAPDYrm 3106
-VMOVAPDYrr 3107
-VMOVAPDYrr_REV 3108
-VMOVAPDZ 3109
-VMOVAPDZmr 3110
-VMOVAPDZmrk 3111
-VMOVAPDZrm 3112
-VMOVAPDZrmk 3113
-VMOVAPDZrmkz 3114
-VMOVAPDZrr 3115
-VMOVAPDZrr_REV 3116
-VMOVAPDZrrk 3117
-VMOVAPDZrrk_REV 3118
-VMOVAPDZrrkz 3119
-VMOVAPDZrrkz_REV 3120
-VMOVAPDmr 3121
-VMOVAPDrm 3122
-VMOVAPDrr 3123
-VMOVAPDrr_REV 3124
-VMOVAPSYmr 3125
-VMOVAPSYrm 3126
-VMOVAPSYrr 3127
-VMOVAPSYrr_REV 3128
-VMOVAPSZ 3129
-VMOVAPSZmr 3130
-VMOVAPSZmrk 3131
-VMOVAPSZrm 3132
-VMOVAPSZrmk 3133
-VMOVAPSZrmkz 3134
-VMOVAPSZrr 3135
-VMOVAPSZrr_REV 3136
-VMOVAPSZrrk 3137
-VMOVAPSZrrk_REV 3138
-VMOVAPSZrrkz 3139
-VMOVAPSZrrkz_REV 3140
-VMOVAPSmr 3141
-VMOVAPSrm 3142
-VMOVAPSrr 3143
-VMOVAPSrr_REV 3144
-VMOVDDUPYrm 3145
-VMOVDDUPYrr 3146
-VMOVDDUPZ 3147
-VMOVDDUPZrm 3148
-VMOVDDUPZrmk 3149
-VMOVDDUPZrmkz 3150
-VMOVDDUPZrr 3151
-VMOVDDUPZrrk 3152
-VMOVDDUPZrrkz 3153
-VMOVDDUPrm 3154
-VMOVDDUPrr 3155
-VMOVDI 3156
-VMOVDQA 3157
-VMOVDQAYmr 3158
-VMOVDQAYrm 3159
-VMOVDQAYrr 3160
-VMOVDQAYrr_REV 3161
-VMOVDQAmr 3162
-VMOVDQArm 3163
-VMOVDQArr 3164
-VMOVDQArr_REV 3165
-VMOVDQU 3166
-VMOVDQUYmr 3167
-VMOVDQUYrm 3168
-VMOVDQUYrr 3169
-VMOVDQUYrr_REV 3170
-VMOVDQUmr 3171
-VMOVDQUrm 3172
-VMOVDQUrr 3173
-VMOVDQUrr_REV 3174
-VMOVHLPSZrr 3175
-VMOVHLPSrr 3176
-VMOVHPDZ 3177
-VMOVHPDmr 3178
-VMOVHPDrm 3179
-VMOVHPSZ 3180
-VMOVHPSmr 3181
-VMOVHPSrm 3182
-VMOVLHPSZrr 3183
-VMOVLHPSrr 3184
-VMOVLPDZ 3185
-VMOVLPDmr 3186
-VMOVLPDrm 3187
-VMOVLPSZ 3188
-VMOVLPSmr 3189
-VMOVLPSrm 3190
-VMOVMSKPDYrr 3191
-VMOVMSKPDrr 3192
-VMOVMSKPSYrr 3193
-VMOVMSKPSrr 3194
-VMOVNTDQAYrm 3195
-VMOVNTDQAZ 3196
-VMOVNTDQAZrm 3197
-VMOVNTDQArm 3198
-VMOVNTDQYmr 3199
-VMOVNTDQZ 3200
-VMOVNTDQZmr 3201
-VMOVNTDQmr 3202
-VMOVNTPDYmr 3203
-VMOVNTPDZ 3204
-VMOVNTPDZmr 3205
-VMOVNTPDmr 3206
-VMOVNTPSYmr 3207
-VMOVNTPSZ 3208
-VMOVNTPSZmr 3209
-VMOVNTPSmr 3210
-VMOVPDI 3211
-VMOVPQI 3212
-VMOVPQIto 3213
-VMOVQI 3214
-VMOVRSBZ 3215
-VMOVRSBZm 3216
-VMOVRSBZmk 3217
-VMOVRSBZmkz 3218
-VMOVRSDZ 3219
-VMOVRSDZm 3220
-VMOVRSDZmk 3221
-VMOVRSDZmkz 3222
-VMOVRSQZ 3223
-VMOVRSQZm 3224
-VMOVRSQZmk 3225
-VMOVRSQZmkz 3226
-VMOVRSWZ 3227
-VMOVRSWZm 3228
-VMOVRSWZmk 3229
-VMOVRSWZmkz 3230
-VMOVSDZmr 3231
-VMOVSDZmrk 3232
-VMOVSDZrm 3233
-VMOVSDZrm_alt 3234
-VMOVSDZrmk 3235
-VMOVSDZrmkz 3236
-VMOVSDZrr 3237
-VMOVSDZrr_REV 3238
-VMOVSDZrrk 3239
-VMOVSDZrrk_REV 3240
-VMOVSDZrrkz 3241
-VMOVSDZrrkz_REV 3242
-VMOVSDmr 3243
-VMOVSDrm 3244
-VMOVSDrm_alt 3245
-VMOVSDrr 3246
-VMOVSDrr_REV 3247
-VMOVSDto 3248
-VMOVSH 3249
-VMOVSHDUPYrm 3250
-VMOVSHDUPYrr 3251
-VMOVSHDUPZ 3252
-VMOVSHDUPZrm 3253
-VMOVSHDUPZrmk 3254
-VMOVSHDUPZrmkz 3255
-VMOVSHDUPZrr 3256
-VMOVSHDUPZrrk 3257
-VMOVSHDUPZrrkz 3258
-VMOVSHDUPrm 3259
-VMOVSHDUPrr 3260
-VMOVSHZmr 3261
-VMOVSHZmrk 3262
-VMOVSHZrm 3263
-VMOVSHZrm_alt 3264
-VMOVSHZrmk 3265
-VMOVSHZrmkz 3266
-VMOVSHZrr 3267
-VMOVSHZrr_REV 3268
-VMOVSHZrrk 3269
-VMOVSHZrrk_REV 3270
-VMOVSHZrrkz 3271
-VMOVSHZrrkz_REV 3272
-VMOVSHtoW 3273
-VMOVSLDUPYrm 3274
-VMOVSLDUPYrr 3275
-VMOVSLDUPZ 3276
-VMOVSLDUPZrm 3277
-VMOVSLDUPZrmk 3278
-VMOVSLDUPZrmkz 3279
-VMOVSLDUPZrr 3280
-VMOVSLDUPZrrk 3281
-VMOVSLDUPZrrkz 3282
-VMOVSLDUPrm 3283
-VMOVSLDUPrr 3284
-VMOVSS 3285
-VMOVSSZmr 3286
-VMOVSSZmrk 3287
-VMOVSSZrm 3288
-VMOVSSZrm_alt 3289
-VMOVSSZrmk 3290
-VMOVSSZrmkz 3291
-VMOVSSZrr 3292
-VMOVSSZrr_REV 3293
-VMOVSSZrrk 3294
-VMOVSSZrrk_REV 3295
-VMOVSSZrrkz 3296
-VMOVSSZrrkz_REV 3297
-VMOVSSmr 3298
-VMOVSSrm 3299
-VMOVSSrm_alt 3300
-VMOVSSrr 3301
-VMOVSSrr_REV 3302
-VMOVUPDYmr 3303
-VMOVUPDYrm 3304
-VMOVUPDYrr 3305
-VMOVUPDYrr_REV 3306
-VMOVUPDZ 3307
-VMOVUPDZmr 3308
-VMOVUPDZmrk 3309
-VMOVUPDZrm 3310
-VMOVUPDZrmk 3311
-VMOVUPDZrmkz 3312
-VMOVUPDZrr 3313
-VMOVUPDZrr_REV 3314
-VMOVUPDZrrk 3315
-VMOVUPDZrrk_REV 3316
-VMOVUPDZrrkz 3317
-VMOVUPDZrrkz_REV 3318
-VMOVUPDmr 3319
-VMOVUPDrm 3320
-VMOVUPDrr 3321
-VMOVUPDrr_REV 3322
-VMOVUPSYmr 3323
-VMOVUPSYrm 3324
-VMOVUPSYrr 3325
-VMOVUPSYrr_REV 3326
-VMOVUPSZ 3327
-VMOVUPSZmr 3328
-VMOVUPSZmrk 3329
-VMOVUPSZrm 3330
-VMOVUPSZrmk 3331
-VMOVUPSZrmkz 3332
-VMOVUPSZrr 3333
-VMOVUPSZrr_REV 3334
-VMOVUPSZrrk 3335
-VMOVUPSZrrk_REV 3336
-VMOVUPSZrrkz 3337
-VMOVUPSZrrkz_REV 3338
-VMOVUPSmr 3339
-VMOVUPSrm 3340
-VMOVUPSrr 3341
-VMOVUPSrr_REV 3342
-VMOVW 3343
-VMOVWmr 3344
-VMOVWrm 3345
-VMOVZPDILo 3346
-VMOVZPQILo 3347
-VMOVZPWILo 3348
-VMPSADBWYrmi 3349
-VMPSADBWYrri 3350
-VMPSADBWZ 3351
-VMPSADBWZrmi 3352
-VMPSADBWZrmik 3353
-VMPSADBWZrmikz 3354
-VMPSADBWZrri 3355
-VMPSADBWZrrik 3356
-VMPSADBWZrrikz 3357
-VMPSADBWrmi 3358
-VMPSADBWrri 3359
-VMPTRLDm 3360
-VMPTRSTm 3361
-VMREAD 3362
-VMRESUME 3363
-VMRUN 3364
-VMSAVE 3365
-VMULBF 3366
-VMULPDYrm 3367
-VMULPDYrr 3368
-VMULPDZ 3369
-VMULPDZrm 3370
-VMULPDZrmb 3371
-VMULPDZrmbk 3372
-VMULPDZrmbkz 3373
-VMULPDZrmk 3374
-VMULPDZrmkz 3375
-VMULPDZrr 3376
-VMULPDZrrb 3377
-VMULPDZrrbk 3378
-VMULPDZrrbkz 3379
-VMULPDZrrk 3380
-VMULPDZrrkz 3381
-VMULPDrm 3382
-VMULPDrr 3383
-VMULPHZ 3384
-VMULPHZrm 3385
-VMULPHZrmb 3386
-VMULPHZrmbk 3387
-VMULPHZrmbkz 3388
-VMULPHZrmk 3389
-VMULPHZrmkz 3390
-VMULPHZrr 3391
-VMULPHZrrb 3392
-VMULPHZrrbk 3393
-VMULPHZrrbkz 3394
-VMULPHZrrk 3395
-VMULPHZrrkz 3396
-VMULPSYrm 3397
-VMULPSYrr 3398
-VMULPSZ 3399
-VMULPSZrm 3400
-VMULPSZrmb 3401
-VMULPSZrmbk 3402
-VMULPSZrmbkz 3403
-VMULPSZrmk 3404
-VMULPSZrmkz 3405
-VMULPSZrr 3406
-VMULPSZrrb 3407
-VMULPSZrrbk 3408
-VMULPSZrrbkz 3409
-VMULPSZrrk 3410
-VMULPSZrrkz 3411
-VMULPSrm 3412
-VMULPSrr 3413
-VMULSDZrm 3414
-VMULSDZrm_Int 3415
-VMULSDZrmk_Int 3416
-VMULSDZrmkz_Int 3417
-VMULSDZrr 3418
-VMULSDZrr_Int 3419
-VMULSDZrrb_Int 3420
-VMULSDZrrbk_Int 3421
-VMULSDZrrbkz_Int 3422
-VMULSDZrrk_Int 3423
-VMULSDZrrkz_Int 3424
-VMULSDrm 3425
-VMULSDrm_Int 3426
-VMULSDrr 3427
-VMULSDrr_Int 3428
-VMULSHZrm 3429
-VMULSHZrm_Int 3430
-VMULSHZrmk_Int 3431
-VMULSHZrmkz_Int 3432
-VMULSHZrr 3433
-VMULSHZrr_Int 3434
-VMULSHZrrb_Int 3435
-VMULSHZrrbk_Int 3436
-VMULSHZrrbkz_Int 3437
-VMULSHZrrk_Int 3438
-VMULSHZrrkz_Int 3439
-VMULSSZrm 3440
-VMULSSZrm_Int 3441
-VMULSSZrmk_Int 3442
-VMULSSZrmkz_Int 3443
-VMULSSZrr 3444
-VMULSSZrr_Int 3445
-VMULSSZrrb_Int 3446
-VMULSSZrrbk_Int 3447
-VMULSSZrrbkz_Int 3448
-VMULSSZrrk_Int 3449
-VMULSSZrrkz_Int 3450
-VMULSSrm 3451
-VMULSSrm_Int 3452
-VMULSSrr 3453
-VMULSSrr_Int 3454
-VMWRITE 3455
-VMXOFF 3456
-VMXON 3457
-VORPDYrm 3458
-VORPDYrr 3459
-VORPDZ 3460
-VORPDZrm 3461
-VORPDZrmb 3462
-VORPDZrmbk 3463
-VORPDZrmbkz 3464
-VORPDZrmk 3465
-VORPDZrmkz 3466
-VORPDZrr 3467
-VORPDZrrk 3468
-VORPDZrrkz 3469
-VORPDrm 3470
-VORPDrr 3471
-VORPSYrm 3472
-VORPSYrr 3473
-VORPSZ 3474
-VORPSZrm 3475
-VORPSZrmb 3476
-VORPSZrmbk 3477
-VORPSZrmbkz 3478
-VORPSZrmk 3479
-VORPSZrmkz 3480
-VORPSZrr 3481
-VORPSZrrk 3482
-VORPSZrrkz 3483
-VORPSrm 3484
-VORPSrr 3485
-VP 3486
-VPABSBYrm 3487
-VPABSBYrr 3488
-VPABSBZ 3489
-VPABSBZrm 3490
-VPABSBZrmk 3491
-VPABSBZrmkz 3492
-VPABSBZrr 3493
-VPABSBZrrk 3494
-VPABSBZrrkz 3495
-VPABSBrm 3496
-VPABSBrr 3497
-VPABSDYrm 3498
-VPABSDYrr 3499
-VPABSDZ 3500
-VPABSDZrm 3501
-VPABSDZrmb 3502
-VPABSDZrmbk 3503
-VPABSDZrmbkz 3504
-VPABSDZrmk 3505
-VPABSDZrmkz 3506
-VPABSDZrr 3507
-VPABSDZrrk 3508
-VPABSDZrrkz 3509
-VPABSDrm 3510
-VPABSDrr 3511
-VPABSQZ 3512
-VPABSQZrm 3513
-VPABSQZrmb 3514
-VPABSQZrmbk 3515
-VPABSQZrmbkz 3516
-VPABSQZrmk 3517
-VPABSQZrmkz 3518
-VPABSQZrr 3519
-VPABSQZrrk 3520
-VPABSQZrrkz 3521
-VPABSWYrm 3522
-VPABSWYrr 3523
-VPABSWZ 3524
-VPABSWZrm 3525
-VPABSWZrmk 3526
-VPABSWZrmkz 3527
-VPABSWZrr 3528
-VPABSWZrrk 3529
-VPABSWZrrkz 3530
-VPABSWrm 3531
-VPABSWrr 3532
-VPACKSSDWYrm 3533
-VPACKSSDWYrr 3534
-VPACKSSDWZ 3535
-VPACKSSDWZrm 3536
-VPACKSSDWZrmb 3537
-VPACKSSDWZrmbk 3538
-VPACKSSDWZrmbkz 3539
-VPACKSSDWZrmk 3540
-VPACKSSDWZrmkz 3541
-VPACKSSDWZrr 3542
-VPACKSSDWZrrk 3543
-VPACKSSDWZrrkz 3544
-VPACKSSDWrm 3545
-VPACKSSDWrr 3546
-VPACKSSWBYrm 3547
-VPACKSSWBYrr 3548
-VPACKSSWBZ 3549
-VPACKSSWBZrm 3550
-VPACKSSWBZrmk 3551
-VPACKSSWBZrmkz 3552
-VPACKSSWBZrr 3553
-VPACKSSWBZrrk 3554
-VPACKSSWBZrrkz 3555
-VPACKSSWBrm 3556
-VPACKSSWBrr 3557
-VPACKUSDWYrm 3558
-VPACKUSDWYrr 3559
-VPACKUSDWZ 3560
-VPACKUSDWZrm 3561
-VPACKUSDWZrmb 3562
-VPACKUSDWZrmbk 3563
-VPACKUSDWZrmbkz 3564
-VPACKUSDWZrmk 3565
-VPACKUSDWZrmkz 3566
-VPACKUSDWZrr 3567
-VPACKUSDWZrrk 3568
-VPACKUSDWZrrkz 3569
-VPACKUSDWrm 3570
-VPACKUSDWrr 3571
-VPACKUSWBYrm 3572
-VPACKUSWBYrr 3573
-VPACKUSWBZ 3574
-VPACKUSWBZrm 3575
-VPACKUSWBZrmk 3576
-VPACKUSWBZrmkz 3577
-VPACKUSWBZrr 3578
-VPACKUSWBZrrk 3579
-VPACKUSWBZrrkz 3580
-VPACKUSWBrm 3581
-VPACKUSWBrr 3582
-VPADDBYrm 3583
-VPADDBYrr 3584
-VPADDBZ 3585
-VPADDBZrm 3586
-VPADDBZrmk 3587
-VPADDBZrmkz 3588
-VPADDBZrr 3589
-VPADDBZrrk 3590
-VPADDBZrrkz 3591
-VPADDBrm 3592
-VPADDBrr 3593
-VPADDDYrm 3594
-VPADDDYrr 3595
-VPADDDZ 3596
-VPADDDZrm 3597
-VPADDDZrmb 3598
-VPADDDZrmbk 3599
-VPADDDZrmbkz 3600
-VPADDDZrmk 3601
-VPADDDZrmkz 3602
-VPADDDZrr 3603
-VPADDDZrrk 3604
-VPADDDZrrkz 3605
-VPADDDrm 3606
-VPADDDrr 3607
-VPADDQYrm 3608
-VPADDQYrr 3609
-VPADDQZ 3610
-VPADDQZrm 3611
-VPADDQZrmb 3612
-VPADDQZrmbk 3613
-VPADDQZrmbkz 3614
-VPADDQZrmk 3615
-VPADDQZrmkz 3616
-VPADDQZrr 3617
-VPADDQZrrk 3618
-VPADDQZrrkz 3619
-VPADDQrm 3620
-VPADDQrr 3621
-VPADDSBYrm 3622
-VPADDSBYrr 3623
-VPADDSBZ 3624
-VPADDSBZrm 3625
-VPADDSBZrmk 3626
-VPADDSBZrmkz 3627
-VPADDSBZrr 3628
-VPADDSBZrrk 3629
-VPADDSBZrrkz 3630
-VPADDSBrm 3631
-VPADDSBrr 3632
-VPADDSWYrm 3633
-VPADDSWYrr 3634
-VPADDSWZ 3635
-VPADDSWZrm 3636
-VPADDSWZrmk 3637
-VPADDSWZrmkz 3638
-VPADDSWZrr 3639
-VPADDSWZrrk 3640
-VPADDSWZrrkz 3641
-VPADDSWrm 3642
-VPADDSWrr 3643
-VPADDUSBYrm 3644
-VPADDUSBYrr 3645
-VPADDUSBZ 3646
-VPADDUSBZrm 3647
-VPADDUSBZrmk 3648
-VPADDUSBZrmkz 3649
-VPADDUSBZrr 3650
-VPADDUSBZrrk 3651
-VPADDUSBZrrkz 3652
-VPADDUSBrm 3653
-VPADDUSBrr 3654
-VPADDUSWYrm 3655
-VPADDUSWYrr 3656
-VPADDUSWZ 3657
-VPADDUSWZrm 3658
-VPADDUSWZrmk 3659
-VPADDUSWZrmkz 3660
-VPADDUSWZrr 3661
-VPADDUSWZrrk 3662
-VPADDUSWZrrkz 3663
-VPADDUSWrm 3664
-VPADDUSWrr 3665
-VPADDWYrm 3666
-VPADDWYrr 3667
-VPADDWZ 3668
-VPADDWZrm 3669
-VPADDWZrmk 3670
-VPADDWZrmkz 3671
-VPADDWZrr 3672
-VPADDWZrrk 3673
-VPADDWZrrkz 3674
-VPADDWrm 3675
-VPADDWrr 3676
-VPALIGNRYrmi 3677
-VPALIGNRYrri 3678
-VPALIGNRZ 3679
-VPALIGNRZrmi 3680
-VPALIGNRZrmik 3681
-VPALIGNRZrmikz 3682
-VPALIGNRZrri 3683
-VPALIGNRZrrik 3684
-VPALIGNRZrrikz 3685
-VPALIGNRrmi 3686
-VPALIGNRrri 3687
-VPANDDZ 3688
-VPANDDZrm 3689
-VPANDDZrmb 3690
-VPANDDZrmbk 3691
-VPANDDZrmbkz 3692
-VPANDDZrmk 3693
-VPANDDZrmkz 3694
-VPANDDZrr 3695
-VPANDDZrrk 3696
-VPANDDZrrkz 3697
-VPANDNDZ 3698
-VPANDNDZrm 3699
-VPANDNDZrmb 3700
-VPANDNDZrmbk 3701
-VPANDNDZrmbkz 3702
-VPANDNDZrmk 3703
-VPANDNDZrmkz 3704
-VPANDNDZrr 3705
-VPANDNDZrrk 3706
-VPANDNDZrrkz 3707
-VPANDNQZ 3708
-VPANDNQZrm 3709
-VPANDNQZrmb 3710
-VPANDNQZrmbk 3711
-VPANDNQZrmbkz 3712
-VPANDNQZrmk 3713
-VPANDNQZrmkz 3714
-VPANDNQZrr 3715
-VPANDNQZrrk 3716
-VPANDNQZrrkz 3717
-VPANDNYrm 3718
-VPANDNYrr 3719
-VPANDNrm 3720
-VPANDNrr 3721
-VPANDQZ 3722
-VPANDQZrm 3723
-VPANDQZrmb 3724
-VPANDQZrmbk 3725
-VPANDQZrmbkz 3726
-VPANDQZrmk 3727
-VPANDQZrmkz 3728
-VPANDQZrr 3729
-VPANDQZrrk 3730
-VPANDQZrrkz 3731
-VPANDYrm 3732
-VPANDYrr 3733
-VPANDrm 3734
-VPANDrr 3735
-VPAVGBYrm 3736
-VPAVGBYrr 3737
-VPAVGBZ 3738
-VPAVGBZrm 3739
-VPAVGBZrmk 3740
-VPAVGBZrmkz 3741
-VPAVGBZrr 3742
-VPAVGBZrrk 3743
-VPAVGBZrrkz 3744
-VPAVGBrm 3745
-VPAVGBrr 3746
-VPAVGWYrm 3747
-VPAVGWYrr 3748
-VPAVGWZ 3749
-VPAVGWZrm 3750
-VPAVGWZrmk 3751
-VPAVGWZrmkz 3752
-VPAVGWZrr 3753
-VPAVGWZrrk 3754
-VPAVGWZrrkz 3755
-VPAVGWrm 3756
-VPAVGWrr 3757
-VPBLENDDYrmi 3758
-VPBLENDDYrri 3759
-VPBLENDDrmi 3760
-VPBLENDDrri 3761
-VPBLENDMBZ 3762
-VPBLENDMBZrm 3763
-VPBLENDMBZrmk 3764
-VPBLENDMBZrmkz 3765
-VPBLENDMBZrr 3766
-VPBLENDMBZrrk 3767
-VPBLENDMBZrrkz 3768
-VPBLENDMDZ 3769
-VPBLENDMDZrm 3770
-VPBLENDMDZrmb 3771
-VPBLENDMDZrmbk 3772
-VPBLENDMDZrmbkz 3773
-VPBLENDMDZrmk 3774
-VPBLENDMDZrmkz 3775
-VPBLENDMDZrr 3776
-VPBLENDMDZrrk 3777
-VPBLENDMDZrrkz 3778
-VPBLENDMQZ 3779
-VPBLENDMQZrm 3780
-VPBLENDMQZrmb 3781
-VPBLENDMQZrmbk 3782
-VPBLENDMQZrmbkz 3783
-VPBLENDMQZrmk 3784
-VPBLENDMQZrmkz 3785
-VPBLENDMQZrr 3786
-VPBLENDMQZrrk 3787
-VPBLENDMQZrrkz 3788
-VPBLENDMWZ 3789
-VPBLENDMWZrm 3790
-VPBLENDMWZrmk 3791
-VPBLENDMWZrmkz 3792
-VPBLENDMWZrr 3793
-VPBLENDMWZrrk 3794
-VPBLENDMWZrrkz 3795
-VPBLENDVBYrmr 3796
-VPBLENDVBYrrr 3797
-VPBLENDVBrmr 3798
-VPBLENDVBrrr 3799
-VPBLENDWYrmi 3800
-VPBLENDWYrri 3801
-VPBLENDWrmi 3802
-VPBLENDWrri 3803
-VPBROADCASTBYrm 3804
-VPBROADCASTBYrr 3805
-VPBROADCASTBZ 3806
-VPBROADCASTBZrm 3807
-VPBROADCASTBZrmk 3808
-VPBROADCASTBZrmkz 3809
-VPBROADCASTBZrr 3810
-VPBROADCASTBZrrk 3811
-VPBROADCASTBZrrkz 3812
-VPBROADCASTBrZ 3813
-VPBROADCASTBrZrr 3814
-VPBROADCASTBrZrrk 3815
-VPBROADCASTBrZrrkz 3816
-VPBROADCASTBrm 3817
-VPBROADCASTBrr 3818
-VPBROADCASTDYrm 3819
-VPBROADCASTDYrr 3820
-VPBROADCASTDZ 3821
-VPBROADCASTDZrm 3822
-VPBROADCASTDZrmk 3823
-VPBROADCASTDZrmkz 3824
-VPBROADCASTDZrr 3825
-VPBROADCASTDZrrk 3826
-VPBROADCASTDZrrkz 3827
-VPBROADCASTDrZ 3828
-VPBROADCASTDrZrr 3829
-VPBROADCASTDrZrrk 3830
-VPBROADCASTDrZrrkz 3831
-VPBROADCASTDrm 3832
-VPBROADCASTDrr 3833
-VPBROADCASTMB 3834
-VPBROADCASTMW 3835
-VPBROADCASTQYrm 3836
-VPBROADCASTQYrr 3837
-VPBROADCASTQZ 3838
-VPBROADCASTQZrm 3839
-VPBROADCASTQZrmk 3840
-VPBROADCASTQZrmkz 3841
-VPBROADCASTQZrr 3842
-VPBROADCASTQZrrk 3843
-VPBROADCASTQZrrkz 3844
-VPBROADCASTQrZ 3845
-VPBROADCASTQrZrr 3846
-VPBROADCASTQrZrrk 3847
-VPBROADCASTQrZrrkz 3848
-VPBROADCASTQrm 3849
-VPBROADCASTQrr 3850
-VPBROADCASTWYrm 3851
-VPBROADCASTWYrr 3852
-VPBROADCASTWZ 3853
-VPBROADCASTWZrm 3854
-VPBROADCASTWZrmk 3855
-VPBROADCASTWZrmkz 3856
-VPBROADCASTWZrr 3857
-VPBROADCASTWZrrk 3858
-VPBROADCASTWZrrkz 3859
-VPBROADCASTWrZ 3860
-VPBROADCASTWrZrr 3861
-VPBROADCASTWrZrrk 3862
-VPBROADCASTWrZrrkz 3863
-VPBROADCASTWrm 3864
-VPBROADCASTWrr 3865
-VPCLMULQDQYrmi 3866
-VPCLMULQDQYrri 3867
-VPCLMULQDQZ 3868
-VPCLMULQDQZrmi 3869
-VPCLMULQDQZrri 3870
-VPCLMULQDQrmi 3871
-VPCLMULQDQrri 3872
-VPCMOVYrmr 3873
-VPCMOVYrrm 3874
-VPCMOVYrrr 3875
-VPCMOVYrrr_REV 3876
-VPCMOVrmr 3877
-VPCMOVrrm 3878
-VPCMOVrrr 3879
-VPCMOVrrr_REV 3880
-VPCMPBZ 3881
-VPCMPBZrmi 3882
-VPCMPBZrmik 3883
-VPCMPBZrri 3884
-VPCMPBZrrik 3885
-VPCMPDZ 3886
-VPCMPDZrmbi 3887
-VPCMPDZrmbik 3888
-VPCMPDZrmi 3889
-VPCMPDZrmik 3890
-VPCMPDZrri 3891
-VPCMPDZrrik 3892
-VPCMPEQBYrm 3893
-VPCMPEQBYrr 3894
-VPCMPEQBZ 3895
-VPCMPEQBZrm 3896
-VPCMPEQBZrmk 3897
-VPCMPEQBZrr 3898
-VPCMPEQBZrrk 3899
-VPCMPEQBrm 3900
-VPCMPEQBrr 3901
-VPCMPEQDYrm 3902
-VPCMPEQDYrr 3903
-VPCMPEQDZ 3904
-VPCMPEQDZrm 3905
-VPCMPEQDZrmb 3906
-VPCMPEQDZrmbk 3907
-VPCMPEQDZrmk 3908
-VPCMPEQDZrr 3909
-VPCMPEQDZrrk 3910
-VPCMPEQDrm 3911
-VPCMPEQDrr 3912
-VPCMPEQQYrm 3913
-VPCMPEQQYrr 3914
-VPCMPEQQZ 3915
-VPCMPEQQZrm 3916
-VPCMPEQQZrmb 3917
-VPCMPEQQZrmbk 3918
-VPCMPEQQZrmk 3919
-VPCMPEQQZrr 3920
-VPCMPEQQZrrk 3921
-VPCMPEQQrm 3922
-VPCMPEQQrr 3923
-VPCMPEQWYrm 3924
-VPCMPEQWYrr 3925
-VPCMPEQWZ 3926
-VPCMPEQWZrm 3927
-VPCMPEQWZrmk 3928
-VPCMPEQWZrr 3929
-VPCMPEQWZrrk 3930
-VPCMPEQWrm 3931
-VPCMPEQWrr 3932
-VPCMPESTRIrmi 3933
-VPCMPESTRIrri 3934
-VPCMPESTRMrmi 3935
-VPCMPESTRMrri 3936
-VPCMPGTBYrm 3937
-VPCMPGTBYrr 3938
-VPCMPGTBZ 3939
-VPCMPGTBZrm 3940
-VPCMPGTBZrmk 3941
-VPCMPGTBZrr 3942
-VPCMPGTBZrrk 3943
-VPCMPGTBrm 3944
-VPCMPGTBrr 3945
-VPCMPGTDYrm 3946
-VPCMPGTDYrr 3947
-VPCMPGTDZ 3948
-VPCMPGTDZrm 3949
-VPCMPGTDZrmb 3950
-VPCMPGTDZrmbk 3951
-VPCMPGTDZrmk 3952
-VPCMPGTDZrr 3953
-VPCMPGTDZrrk 3954
-VPCMPGTDrm 3955
-VPCMPGTDrr 3956
-VPCMPGTQYrm 3957
-VPCMPGTQYrr 3958
-VPCMPGTQZ 3959
-VPCMPGTQZrm 3960
-VPCMPGTQZrmb 3961
-VPCMPGTQZrmbk 3962
-VPCMPGTQZrmk 3963
-VPCMPGTQZrr 3964
-VPCMPGTQZrrk 3965
-VPCMPGTQrm 3966
-VPCMPGTQrr 3967
-VPCMPGTWYrm 3968
-VPCMPGTWYrr 3969
-VPCMPGTWZ 3970
-VPCMPGTWZrm 3971
-VPCMPGTWZrmk 3972
-VPCMPGTWZrr 3973
-VPCMPGTWZrrk 3974
-VPCMPGTWrm 3975
-VPCMPGTWrr 3976
-VPCMPISTRIrmi 3977
-VPCMPISTRIrri 3978
-VPCMPISTRMrmi 3979
-VPCMPISTRMrri 3980
-VPCMPQZ 3981
-VPCMPQZrmbi 3982
-VPCMPQZrmbik 3983
-VPCMPQZrmi 3984
-VPCMPQZrmik 3985
-VPCMPQZrri 3986
-VPCMPQZrrik 3987
-VPCMPUBZ 3988
-VPCMPUBZrmi 3989
-VPCMPUBZrmik 3990
-VPCMPUBZrri 3991
-VPCMPUBZrrik 3992
-VPCMPUDZ 3993
-VPCMPUDZrmbi 3994
-VPCMPUDZrmbik 3995
-VPCMPUDZrmi 3996
-VPCMPUDZrmik 3997
-VPCMPUDZrri 3998
-VPCMPUDZrrik 3999
-VPCMPUQZ 4000
-VPCMPUQZrmbi 4001
-VPCMPUQZrmbik 4002
-VPCMPUQZrmi 4003
-VPCMPUQZrmik 4004
-VPCMPUQZrri 4005
-VPCMPUQZrrik 4006
-VPCMPUWZ 4007
-VPCMPUWZrmi 4008
-VPCMPUWZrmik 4009
-VPCMPUWZrri 4010
-VPCMPUWZrrik 4011
-VPCMPWZ 4012
-VPCMPWZrmi 4013
-VPCMPWZrmik 4014
-VPCMPWZrri 4015
-VPCMPWZrrik 4016
-VPCOMBmi 4017
-VPCOMBri 4018
-VPCOMDmi 4019
-VPCOMDri 4020
-VPCOMPRESSBZ 4021
-VPCOMPRESSBZmr 4022
-VPCOMPRESSBZmrk 4023
-VPCOMPRESSBZrr 4024
-VPCOMPRESSBZrrk 4025
-VPCOMPRESSBZrrkz 4026
-VPCOMPRESSDZ 4027
-VPCOMPRESSDZmr 4028
-VPCOMPRESSDZmrk 4029
-VPCOMPRESSDZrr 4030
-VPCOMPRESSDZrrk 4031
-VPCOMPRESSDZrrkz 4032
-VPCOMPRESSQZ 4033
-VPCOMPRESSQZmr 4034
-VPCOMPRESSQZmrk 4035
-VPCOMPRESSQZrr 4036
-VPCOMPRESSQZrrk 4037
-VPCOMPRESSQZrrkz 4038
-VPCOMPRESSWZ 4039
-VPCOMPRESSWZmr 4040
-VPCOMPRESSWZmrk 4041
-VPCOMPRESSWZrr 4042
-VPCOMPRESSWZrrk 4043
-VPCOMPRESSWZrrkz 4044
-VPCOMQmi 4045
-VPCOMQri 4046
-VPCOMUBmi 4047
-VPCOMUBri 4048
-VPCOMUDmi 4049
-VPCOMUDri 4050
-VPCOMUQmi 4051
-VPCOMUQri 4052
-VPCOMUWmi 4053
-VPCOMUWri 4054
-VPCOMWmi 4055
-VPCOMWri 4056
-VPCONFLICTDZ 4057
-VPCONFLICTDZrm 4058
-VPCONFLICTDZrmb 4059
-VPCONFLICTDZrmbk 4060
-VPCONFLICTDZrmbkz 4061
-VPCONFLICTDZrmk 4062
-VPCONFLICTDZrmkz 4063
-VPCONFLICTDZrr 4064
-VPCONFLICTDZrrk 4065
-VPCONFLICTDZrrkz 4066
-VPCONFLICTQZ 4067
-VPCONFLICTQZrm 4068
-VPCONFLICTQZrmb 4069
-VPCONFLICTQZrmbk 4070
-VPCONFLICTQZrmbkz 4071
-VPCONFLICTQZrmk 4072
-VPCONFLICTQZrmkz 4073
-VPCONFLICTQZrr 4074
-VPCONFLICTQZrrk 4075
-VPCONFLICTQZrrkz 4076
-VPDPBSSDSYrm 4077
-VPDPBSSDSYrr 4078
-VPDPBSSDSZ 4079
-VPDPBSSDSZrm 4080
-VPDPBSSDSZrmb 4081
-VPDPBSSDSZrmbk 4082
-VPDPBSSDSZrmbkz 4083
-VPDPBSSDSZrmk 4084
-VPDPBSSDSZrmkz 4085
-VPDPBSSDSZrr 4086
-VPDPBSSDSZrrk 4087
-VPDPBSSDSZrrkz 4088
-VPDPBSSDSrm 4089
-VPDPBSSDSrr 4090
-VPDPBSSDYrm 4091
-VPDPBSSDYrr 4092
-VPDPBSSDZ 4093
-VPDPBSSDZrm 4094
-VPDPBSSDZrmb 4095
-VPDPBSSDZrmbk 4096
-VPDPBSSDZrmbkz 4097
-VPDPBSSDZrmk 4098
-VPDPBSSDZrmkz 4099
-VPDPBSSDZrr 4100
-VPDPBSSDZrrk 4101
-VPDPBSSDZrrkz 4102
-VPDPBSSDrm 4103
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-VPDPBSUDSYrm 4105
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-VPDPBSUDSZrm 4108
-VPDPBSUDSZrmb 4109
-VPDPBSUDSZrmbk 4110
-VPDPBSUDSZrmbkz 4111
-VPDPBSUDSZrmk 4112
-VPDPBSUDSZrmkz 4113
-VPDPBSUDSZrr 4114
-VPDPBSUDSZrrk 4115
-VPDPBSUDSZrrkz 4116
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-VPDPBSUDSrr 4118
-VPDPBSUDYrm 4119
-VPDPBSUDYrr 4120
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-VPDPBSUDZrm 4122
-VPDPBSUDZrmb 4123
-VPDPBSUDZrmbk 4124
-VPDPBSUDZrmbkz 4125
-VPDPBSUDZrmk 4126
-VPDPBSUDZrmkz 4127
-VPDPBSUDZrr 4128
-VPDPBSUDZrrk 4129
-VPDPBSUDZrrkz 4130
-VPDPBSUDrm 4131
-VPDPBSUDrr 4132
-VPDPBUSDSYrm 4133
-VPDPBUSDSYrr 4134
-VPDPBUSDSZ 4135
-VPDPBUSDSZrm 4136
-VPDPBUSDSZrmb 4137
-VPDPBUSDSZrmbk 4138
-VPDPBUSDSZrmbkz 4139
-VPDPBUSDSZrmk 4140
-VPDPBUSDSZrmkz 4141
-VPDPBUSDSZrr 4142
-VPDPBUSDSZrrk 4143
-VPDPBUSDSZrrkz 4144
-VPDPBUSDSrm 4145
-VPDPBUSDSrr 4146
-VPDPBUSDYrm 4147
-VPDPBUSDYrr 4148
-VPDPBUSDZ 4149
-VPDPBUSDZrm 4150
-VPDPBUSDZrmb 4151
-VPDPBUSDZrmbk 4152
-VPDPBUSDZrmbkz 4153
-VPDPBUSDZrmk 4154
-VPDPBUSDZrmkz 4155
-VPDPBUSDZrr 4156
-VPDPBUSDZrrk 4157
-VPDPBUSDZrrkz 4158
-VPDPBUSDrm 4159
-VPDPBUSDrr 4160
-VPDPBUUDSYrm 4161
-VPDPBUUDSYrr 4162
-VPDPBUUDSZ 4163
-VPDPBUUDSZrm 4164
-VPDPBUUDSZrmb 4165
-VPDPBUUDSZrmbk 4166
-VPDPBUUDSZrmbkz 4167
-VPDPBUUDSZrmk 4168
-VPDPBUUDSZrmkz 4169
-VPDPBUUDSZrr 4170
-VPDPBUUDSZrrk 4171
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-VPDPBUUDZrmbkz 4181
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-VPDPBUUDZrr 4184
-VPDPBUUDZrrk 4185
-VPDPBUUDZrrkz 4186
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-VPDPWSSDSZ 4191
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-VPDPWSSDSZrmk 4196
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-VPDPWSSDSZrr 4198
-VPDPWSSDSZrrk 4199
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-VPDPWSSDZ 4205
-VPDPWSSDZrm 4206
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-VPDPWSSDZrrk 4213
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-VPDPWSUDSZrmkz 4225
-VPDPWSUDSZrr 4226
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-VPDPWSUDZ 4233
-VPDPWSUDZrm 4234
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-VPDPWSUDZrmk 4238
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-VPDPWSUDZrr 4240
-VPDPWSUDZrrk 4241
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-VPDPWUSDSZrrkz 4256
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-VPDPWUSDYrm 4259
-VPDPWUSDYrr 4260
-VPDPWUSDZ 4261
-VPDPWUSDZrm 4262
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-VPDPWUSDZrmbk 4264
-VPDPWUSDZrmbkz 4265
-VPDPWUSDZrmk 4266
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-VPDPWUSDZrr 4268
-VPDPWUSDZrrk 4269
-VPDPWUSDZrrkz 4270
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-VPDPWUUDSZrm 4276
-VPDPWUUDSZrmb 4277
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-VPDPWUUDSZrmbkz 4279
-VPDPWUUDSZrmk 4280
-VPDPWUUDSZrmkz 4281
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-VPERMBZ 4302
-VPERMBZrm 4303
-VPERMBZrmk 4304
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-VPERMBZrr 4306
-VPERMBZrrk 4307
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-VPERMDZrmbk 4314
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-VPERMDZrmk 4316
-VPERMDZrmkz 4317
-VPERMDZrr 4318
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-VPERMDZrrkz 4320
-VPERMI 4321
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-VPERMILPDYmi 4323
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-VPERMILPDZmbik 4329
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-VPERMILPDZmik 4332
-VPERMILPDZmikz 4333
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-VPERMILPDZrik 4335
-VPERMILPDZrikz 4336
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-VPERMILPDZrmk 4341
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-VPERMILPSZmikz 4360
-VPERMILPSZri 4361
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-VPERMPDZmbi 4380
-VPERMPDZmbik 4381
-VPERMPDZmbikz 4382
-VPERMPDZmi 4383
-VPERMPDZmik 4384
-VPERMPDZmikz 4385
-VPERMPDZri 4386
-VPERMPDZrik 4387
-VPERMPDZrikz 4388
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-VPERMPDZrmb 4390
-VPERMPDZrmbk 4391
-VPERMPDZrmbkz 4392
-VPERMPDZrmk 4393
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-VPERMPDZrr 4395
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-VPERMPSYrr 4399
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-VPERMPSZrm 4401
-VPERMPSZrmb 4402
-VPERMPSZrmbk 4403
-VPERMPSZrmbkz 4404
-VPERMPSZrmk 4405
-VPERMPSZrmkz 4406
-VPERMPSZrr 4407
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-VPERMQYmi 4410
-VPERMQYri 4411
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-VPERMQZmbi 4413
-VPERMQZmbik 4414
-VPERMQZmbikz 4415
-VPERMQZmi 4416
-VPERMQZmik 4417
-VPERMQZmikz 4418
-VPERMQZri 4419
-VPERMQZrik 4420
-VPERMQZrikz 4421
-VPERMQZrm 4422
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-VPERMQZrmbk 4424
-VPERMQZrmbkz 4425
-VPERMQZrmk 4426
-VPERMQZrmkz 4427
-VPERMQZrr 4428
-VPERMQZrrk 4429
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-VPERMT 4431
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-VPERMWZrm 4433
-VPERMWZrmk 4434
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-VPERMWZrrk 4437
-VPERMWZrrkz 4438
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-VPEXPANDDZ 4446
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-VPEXPANDDZrr 4450
-VPEXPANDDZrrk 4451
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-VPEXPANDQZ 4453
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-VPEXPANDQZrr 4457
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-VPEXPANDQZrrkz 4459
-VPEXPANDWZ 4460
-VPEXPANDWZrm 4461
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-VPEXPANDWZrmkz 4463
-VPEXPANDWZrr 4464
-VPEXPANDWZrrk 4465
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-VPEXTRBZmri 4467
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-VPEXTRDZmri 4471
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-VPEXTRDmri 4473
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-VPEXTRQZrri 4476
-VPEXTRQmri 4477
-VPEXTRQrri 4478
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-VPEXTRWZrri_REV 4481
-VPEXTRWmri 4482
-VPEXTRWrri 4483
-VPEXTRWrri_REV 4484
-VPGATHERDDYrm 4485
-VPGATHERDDZ 4486
-VPGATHERDDZrm 4487
-VPGATHERDDrm 4488
-VPGATHERDQYrm 4489
-VPGATHERDQZ 4490
-VPGATHERDQZrm 4491
-VPGATHERDQrm 4492
-VPGATHERQDYrm 4493
-VPGATHERQDZ 4494
-VPGATHERQDZrm 4495
-VPGATHERQDrm 4496
-VPGATHERQQYrm 4497
-VPGATHERQQZ 4498
-VPGATHERQQZrm 4499
-VPGATHERQQrm 4500
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-VPHADDBQrr 4504
-VPHADDBWrm 4505
-VPHADDBWrr 4506
-VPHADDDQrm 4507
-VPHADDDQrr 4508
-VPHADDDYrm 4509
-VPHADDDYrr 4510
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-VPHADDDrr 4512
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-VPHADDSWrm 4515
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-VPHADDUBQrr 4520
-VPHADDUBWrm 4521
-VPHADDUBWrr 4522
-VPHADDUDQrm 4523
-VPHADDUDQrr 4524
-VPHADDUWDrm 4525
-VPHADDUWDrr 4526
-VPHADDUWQrm 4527
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-VPHADDWDrr 4530
-VPHADDWQrm 4531
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-VPINSRDZrmi 4561
-VPINSRDZrri 4562
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-VPINSRQZrri 4566
-VPINSRQrmi 4567
-VPINSRQrri 4568
-VPINSRWZrmi 4569
-VPINSRWZrri 4570
-VPINSRWrmi 4571
-VPINSRWrri 4572
-VPLZCNTDZ 4573
-VPLZCNTDZrm 4574
-VPLZCNTDZrmb 4575
-VPLZCNTDZrmbk 4576
-VPLZCNTDZrmbkz 4577
-VPLZCNTDZrmk 4578
-VPLZCNTDZrmkz 4579
-VPLZCNTDZrr 4580
-VPLZCNTDZrrk 4581
-VPLZCNTDZrrkz 4582
-VPLZCNTQZ 4583
-VPLZCNTQZrm 4584
-VPLZCNTQZrmb 4585
-VPLZCNTQZrmbk 4586
-VPLZCNTQZrmbkz 4587
-VPLZCNTQZrmk 4588
-VPLZCNTQZrmkz 4589
-VPLZCNTQZrr 4590
-VPLZCNTQZrrk 4591
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-VPMACSDQHrr 4596
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-VPMACSSDQHrr 4602
-VPMACSSDQLrm 4603
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-VPMACSSWDrm 4605
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-VPMACSWDrm 4609
-VPMACSWDrr 4610
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-VPMADCSSWDrr 4614
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-VPMADDUBSWZrm 4621
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-VPMADDUBSWZrr 4624
-VPMADDUBSWZrrk 4625
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-VPMADDUBSWrm 4627
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-VPMADDWDZ 4631
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-VPMADDWDZrmkz 4634
-VPMADDWDZrr 4635
-VPMADDWDZrrk 4636
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-VPMADDWDrm 4638
-VPMADDWDrr 4639
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-VPMASKMOVDYrm 4641
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-VPMASKMOVQYmr 4644
-VPMASKMOVQYrm 4645
-VPMASKMOVQmr 4646
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-VPMAXSBYrr 4649
-VPMAXSBZ 4650
-VPMAXSBZrm 4651
-VPMAXSBZrmk 4652
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-VPMAXSBZrrk 4655
-VPMAXSBZrrkz 4656
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-VPMAXSDZrmbk 4664
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-VPMAXSDZrmk 4666
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-VPMAXSDZrr 4668
-VPMAXSDZrrk 4669
-VPMAXSDZrrkz 4670
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-VPMAXSQZrmbk 4676
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-VPMAXSQZrmk 4678
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-VPMAXSWZrr 4689
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-VREDUCEPDZrribk 6234
-VREDUCEPDZrribkz 6235
-VREDUCEPDZrrik 6236
-VREDUCEPDZrrikz 6237
-VREDUCEPHZ 6238
-VREDUCEPHZrmbi 6239
-VREDUCEPHZrmbik 6240
-VREDUCEPHZrmbikz 6241
-VREDUCEPHZrmi 6242
-VREDUCEPHZrmik 6243
-VREDUCEPHZrmikz 6244
-VREDUCEPHZrri 6245
-VREDUCEPHZrrib 6246
-VREDUCEPHZrribk 6247
-VREDUCEPHZrribkz 6248
-VREDUCEPHZrrik 6249
-VREDUCEPHZrrikz 6250
-VREDUCEPSZ 6251
-VREDUCEPSZrmbi 6252
-VREDUCEPSZrmbik 6253
-VREDUCEPSZrmbikz 6254
-VREDUCEPSZrmi 6255
-VREDUCEPSZrmik 6256
-VREDUCEPSZrmikz 6257
-VREDUCEPSZrri 6258
-VREDUCEPSZrrib 6259
-VREDUCEPSZrribk 6260
-VREDUCEPSZrribkz 6261
-VREDUCEPSZrrik 6262
-VREDUCEPSZrrikz 6263
-VREDUCESDZrmi 6264
-VREDUCESDZrmik 6265
-VREDUCESDZrmikz 6266
-VREDUCESDZrri 6267
-VREDUCESDZrrib 6268
-VREDUCESDZrribk 6269
-VREDUCESDZrribkz 6270
-VREDUCESDZrrik 6271
-VREDUCESDZrrikz 6272
-VREDUCESHZrmi 6273
-VREDUCESHZrmik 6274
-VREDUCESHZrmikz 6275
-VREDUCESHZrri 6276
-VREDUCESHZrrib 6277
-VREDUCESHZrribk 6278
-VREDUCESHZrribkz 6279
-VREDUCESHZrrik 6280
-VREDUCESHZrrikz 6281
-VREDUCESSZrmi 6282
-VREDUCESSZrmik 6283
-VREDUCESSZrmikz 6284
-VREDUCESSZrri 6285
-VREDUCESSZrrib 6286
-VREDUCESSZrribk 6287
-VREDUCESSZrribkz 6288
-VREDUCESSZrrik 6289
-VREDUCESSZrrikz 6290
-VRNDSCALEBF 6291
-VRNDSCALEPDZ 6292
-VRNDSCALEPDZrmbi 6293
-VRNDSCALEPDZrmbik 6294
-VRNDSCALEPDZrmbikz 6295
-VRNDSCALEPDZrmi 6296
-VRNDSCALEPDZrmik 6297
-VRNDSCALEPDZrmikz 6298
-VRNDSCALEPDZrri 6299
-VRNDSCALEPDZrrib 6300
-VRNDSCALEPDZrribk 6301
-VRNDSCALEPDZrribkz 6302
-VRNDSCALEPDZrrik 6303
-VRNDSCALEPDZrrikz 6304
-VRNDSCALEPHZ 6305
-VRNDSCALEPHZrmbi 6306
-VRNDSCALEPHZrmbik 6307
-VRNDSCALEPHZrmbikz 6308
-VRNDSCALEPHZrmi 6309
-VRNDSCALEPHZrmik 6310
-VRNDSCALEPHZrmikz 6311
-VRNDSCALEPHZrri 6312
-VRNDSCALEPHZrrib 6313
-VRNDSCALEPHZrribk 6314
-VRNDSCALEPHZrribkz 6315
-VRNDSCALEPHZrrik 6316
-VRNDSCALEPHZrrikz 6317
-VRNDSCALEPSZ 6318
-VRNDSCALEPSZrmbi 6319
-VRNDSCALEPSZrmbik 6320
-VRNDSCALEPSZrmbikz 6321
-VRNDSCALEPSZrmi 6322
-VRNDSCALEPSZrmik 6323
-VRNDSCALEPSZrmikz 6324
-VRNDSCALEPSZrri 6325
-VRNDSCALEPSZrrib 6326
-VRNDSCALEPSZrribk 6327
-VRNDSCALEPSZrribkz 6328
-VRNDSCALEPSZrrik 6329
-VRNDSCALEPSZrrikz 6330
-VRNDSCALESDZrmi 6331
-VRNDSCALESDZrmi_Int 6332
-VRNDSCALESDZrmik_Int 6333
-VRNDSCALESDZrmikz_Int 6334
-VRNDSCALESDZrri 6335
-VRNDSCALESDZrri_Int 6336
-VRNDSCALESDZrrib_Int 6337
-VRNDSCALESDZrribk_Int 6338
-VRNDSCALESDZrribkz_Int 6339
-VRNDSCALESDZrrik_Int 6340
-VRNDSCALESDZrrikz_Int 6341
-VRNDSCALESHZrmi 6342
-VRNDSCALESHZrmi_Int 6343
-VRNDSCALESHZrmik_Int 6344
-VRNDSCALESHZrmikz_Int 6345
-VRNDSCALESHZrri 6346
-VRNDSCALESHZrri_Int 6347
-VRNDSCALESHZrrib_Int 6348
-VRNDSCALESHZrribk_Int 6349
-VRNDSCALESHZrribkz_Int 6350
-VRNDSCALESHZrrik_Int 6351
-VRNDSCALESHZrrikz_Int 6352
-VRNDSCALESSZrmi 6353
-VRNDSCALESSZrmi_Int 6354
-VRNDSCALESSZrmik_Int 6355
-VRNDSCALESSZrmikz_Int 6356
-VRNDSCALESSZrri 6357
-VRNDSCALESSZrri_Int 6358
-VRNDSCALESSZrrib_Int 6359
-VRNDSCALESSZrribk_Int 6360
-VRNDSCALESSZrribkz_Int 6361
-VRNDSCALESSZrrik_Int 6362
-VRNDSCALESSZrrikz_Int 6363
-VROUNDPDYmi 6364
-VROUNDPDYri 6365
-VROUNDPDmi 6366
-VROUNDPDri 6367
-VROUNDPSYmi 6368
-VROUNDPSYri 6369
-VROUNDPSmi 6370
-VROUNDPSri 6371
-VROUNDSDmi 6372
-VROUNDSDmi_Int 6373
-VROUNDSDri 6374
-VROUNDSDri_Int 6375
-VROUNDSSmi 6376
-VROUNDSSmi_Int 6377
-VROUNDSSri 6378
-VROUNDSSri_Int 6379
-VRSQRT 6380
-VRSQRTBF 6381
-VRSQRTPHZ 6382
-VRSQRTPHZm 6383
-VRSQRTPHZmb 6384
-VRSQRTPHZmbk 6385
-VRSQRTPHZmbkz 6386
-VRSQRTPHZmk 6387
-VRSQRTPHZmkz 6388
-VRSQRTPHZr 6389
-VRSQRTPHZrk 6390
-VRSQRTPHZrkz 6391
-VRSQRTPSYm 6392
-VRSQRTPSYr 6393
-VRSQRTPSm 6394
-VRSQRTPSr 6395
-VRSQRTSHZrm 6396
-VRSQRTSHZrmk 6397
-VRSQRTSHZrmkz 6398
-VRSQRTSHZrr 6399
-VRSQRTSHZrrk 6400
-VRSQRTSHZrrkz 6401
-VRSQRTSSm 6402
-VRSQRTSSm_Int 6403
-VRSQRTSSr 6404
-VRSQRTSSr_Int 6405
-VSCALEFBF 6406
-VSCALEFPDZ 6407
-VSCALEFPDZrm 6408
-VSCALEFPDZrmb 6409
-VSCALEFPDZrmbk 6410
-VSCALEFPDZrmbkz 6411
-VSCALEFPDZrmk 6412
-VSCALEFPDZrmkz 6413
-VSCALEFPDZrr 6414
-VSCALEFPDZrrb 6415
-VSCALEFPDZrrbk 6416
-VSCALEFPDZrrbkz 6417
-VSCALEFPDZrrk 6418
-VSCALEFPDZrrkz 6419
-VSCALEFPHZ 6420
-VSCALEFPHZrm 6421
-VSCALEFPHZrmb 6422
-VSCALEFPHZrmbk 6423
-VSCALEFPHZrmbkz 6424
-VSCALEFPHZrmk 6425
-VSCALEFPHZrmkz 6426
-VSCALEFPHZrr 6427
-VSCALEFPHZrrb 6428
-VSCALEFPHZrrbk 6429
-VSCALEFPHZrrbkz 6430
-VSCALEFPHZrrk 6431
-VSCALEFPHZrrkz 6432
-VSCALEFPSZ 6433
-VSCALEFPSZrm 6434
-VSCALEFPSZrmb 6435
-VSCALEFPSZrmbk 6436
-VSCALEFPSZrmbkz 6437
-VSCALEFPSZrmk 6438
-VSCALEFPSZrmkz 6439
-VSCALEFPSZrr 6440
-VSCALEFPSZrrb 6441
-VSCALEFPSZrrbk 6442
-VSCALEFPSZrrbkz 6443
-VSCALEFPSZrrk 6444
-VSCALEFPSZrrkz 6445
-VSCALEFSDZrm 6446
-VSCALEFSDZrmk 6447
-VSCALEFSDZrmkz 6448
-VSCALEFSDZrr 6449
-VSCALEFSDZrrb_Int 6450
-VSCALEFSDZrrbk_Int 6451
-VSCALEFSDZrrbkz_Int 6452
-VSCALEFSDZrrk 6453
-VSCALEFSDZrrkz 6454
-VSCALEFSHZrm 6455
-VSCALEFSHZrmk 6456
-VSCALEFSHZrmkz 6457
-VSCALEFSHZrr 6458
-VSCALEFSHZrrb_Int 6459
-VSCALEFSHZrrbk_Int 6460
-VSCALEFSHZrrbkz_Int 6461
-VSCALEFSHZrrk 6462
-VSCALEFSHZrrkz 6463
-VSCALEFSSZrm 6464
-VSCALEFSSZrmk 6465
-VSCALEFSSZrmkz 6466
-VSCALEFSSZrr 6467
-VSCALEFSSZrrb_Int 6468
-VSCALEFSSZrrbk_Int 6469
-VSCALEFSSZrrbkz_Int 6470
-VSCALEFSSZrrk 6471
-VSCALEFSSZrrkz 6472
-VSCATTERDPDZ 6473
-VSCATTERDPDZmr 6474
-VSCATTERDPSZ 6475
-VSCATTERDPSZmr 6476
-VSCATTERPF 6477
-VSCATTERQPDZ 6478
-VSCATTERQPDZmr 6479
-VSCATTERQPSZ 6480
-VSCATTERQPSZmr 6481
-VSHA 6482
-VSHUFF 6483
-VSHUFI 6484
-VSHUFPDYrmi 6485
-VSHUFPDYrri 6486
-VSHUFPDZ 6487
-VSHUFPDZrmbi 6488
-VSHUFPDZrmbik 6489
-VSHUFPDZrmbikz 6490
-VSHUFPDZrmi 6491
-VSHUFPDZrmik 6492
-VSHUFPDZrmikz 6493
-VSHUFPDZrri 6494
-VSHUFPDZrrik 6495
-VSHUFPDZrrikz 6496
-VSHUFPDrmi 6497
-VSHUFPDrri 6498
-VSHUFPSYrmi 6499
-VSHUFPSYrri 6500
-VSHUFPSZ 6501
-VSHUFPSZrmbi 6502
-VSHUFPSZrmbik 6503
-VSHUFPSZrmbikz 6504
-VSHUFPSZrmi 6505
-VSHUFPSZrmik 6506
-VSHUFPSZrmikz 6507
-VSHUFPSZrri 6508
-VSHUFPSZrrik 6509
-VSHUFPSZrrikz 6510
-VSHUFPSrmi 6511
-VSHUFPSrri 6512
-VSM 6513
-VSQRTBF 6514
-VSQRTPDYm 6515
-VSQRTPDYr 6516
-VSQRTPDZ 6517
-VSQRTPDZm 6518
-VSQRTPDZmb 6519
-VSQRTPDZmbk 6520
-VSQRTPDZmbkz 6521
-VSQRTPDZmk 6522
-VSQRTPDZmkz 6523
-VSQRTPDZr 6524
-VSQRTPDZrb 6525
-VSQRTPDZrbk 6526
-VSQRTPDZrbkz 6527
-VSQRTPDZrk 6528
-VSQRTPDZrkz 6529
-VSQRTPDm 6530
-VSQRTPDr 6531
-VSQRTPHZ 6532
-VSQRTPHZm 6533
-VSQRTPHZmb 6534
-VSQRTPHZmbk 6535
-VSQRTPHZmbkz 6536
-VSQRTPHZmk 6537
-VSQRTPHZmkz 6538
-VSQRTPHZr 6539
-VSQRTPHZrb 6540
-VSQRTPHZrbk 6541
-VSQRTPHZrbkz 6542
-VSQRTPHZrk 6543
-VSQRTPHZrkz 6544
-VSQRTPSYm 6545
-VSQRTPSYr 6546
-VSQRTPSZ 6547
-VSQRTPSZm 6548
-VSQRTPSZmb 6549
-VSQRTPSZmbk 6550
-VSQRTPSZmbkz 6551
-VSQRTPSZmk 6552
-VSQRTPSZmkz 6553
-VSQRTPSZr 6554
-VSQRTPSZrb 6555
-VSQRTPSZrbk 6556
-VSQRTPSZrbkz 6557
-VSQRTPSZrk 6558
-VSQRTPSZrkz 6559
-VSQRTPSm 6560
-VSQRTPSr 6561
-VSQRTSDZm 6562
-VSQRTSDZm_Int 6563
-VSQRTSDZmk_Int 6564
-VSQRTSDZmkz_Int 6565
-VSQRTSDZr 6566
-VSQRTSDZr_Int 6567
-VSQRTSDZrb_Int 6568
-VSQRTSDZrbk_Int 6569
-VSQRTSDZrbkz_Int 6570
-VSQRTSDZrk_Int 6571
-VSQRTSDZrkz_Int 6572
-VSQRTSDm 6573
-VSQRTSDm_Int 6574
-VSQRTSDr 6575
-VSQRTSDr_Int 6576
-VSQRTSHZm 6577
-VSQRTSHZm_Int 6578
-VSQRTSHZmk_Int 6579
-VSQRTSHZmkz_Int 6580
-VSQRTSHZr 6581
-VSQRTSHZr_Int 6582
-VSQRTSHZrb_Int 6583
-VSQRTSHZrbk_Int 6584
-VSQRTSHZrbkz_Int 6585
-VSQRTSHZrk_Int 6586
-VSQRTSHZrkz_Int 6587
-VSQRTSSZm 6588
-VSQRTSSZm_Int 6589
-VSQRTSSZmk_Int 6590
-VSQRTSSZmkz_Int 6591
-VSQRTSSZr 6592
-VSQRTSSZr_Int 6593
-VSQRTSSZrb_Int 6594
-VSQRTSSZrbk_Int 6595
-VSQRTSSZrbkz_Int 6596
-VSQRTSSZrk_Int 6597
-VSQRTSSZrkz_Int 6598
-VSQRTSSm 6599
-VSQRTSSm_Int 6600
-VSQRTSSr 6601
-VSQRTSSr_Int 6602
-VSTMXCSR 6603
-VSUBBF 6604
-VSUBPDYrm 6605
-VSUBPDYrr 6606
-VSUBPDZ 6607
-VSUBPDZrm 6608
-VSUBPDZrmb 6609
-VSUBPDZrmbk 6610
-VSUBPDZrmbkz 6611
-VSUBPDZrmk 6612
-VSUBPDZrmkz 6613
-VSUBPDZrr 6614
-VSUBPDZrrb 6615
-VSUBPDZrrbk 6616
-VSUBPDZrrbkz 6617
-VSUBPDZrrk 6618
-VSUBPDZrrkz 6619
-VSUBPDrm 6620
-VSUBPDrr 6621
-VSUBPHZ 6622
-VSUBPHZrm 6623
-VSUBPHZrmb 6624
-VSUBPHZrmbk 6625
-VSUBPHZrmbkz 6626
-VSUBPHZrmk 6627
-VSUBPHZrmkz 6628
-VSUBPHZrr 6629
-VSUBPHZrrb 6630
-VSUBPHZrrbk 6631
-VSUBPHZrrbkz 6632
-VSUBPHZrrk 6633
-VSUBPHZrrkz 6634
-VSUBPSYrm 6635
-VSUBPSYrr 6636
-VSUBPSZ 6637
-VSUBPSZrm 6638
-VSUBPSZrmb 6639
-VSUBPSZrmbk 6640
-VSUBPSZrmbkz 6641
-VSUBPSZrmk 6642
-VSUBPSZrmkz 6643
-VSUBPSZrr 6644
-VSUBPSZrrb 6645
-VSUBPSZrrbk 6646
-VSUBPSZrrbkz 6647
-VSUBPSZrrk 6648
-VSUBPSZrrkz 6649
-VSUBPSrm 6650
-VSUBPSrr 6651
-VSUBSDZrm 6652
-VSUBSDZrm_Int 6653
-VSUBSDZrmk_Int 6654
-VSUBSDZrmkz_Int 6655
-VSUBSDZrr 6656
-VSUBSDZrr_Int 6657
-VSUBSDZrrb_Int 6658
-VSUBSDZrrbk_Int 6659
-VSUBSDZrrbkz_Int 6660
-VSUBSDZrrk_Int 6661
-VSUBSDZrrkz_Int 6662
-VSUBSDrm 6663
-VSUBSDrm_Int 6664
-VSUBSDrr 6665
-VSUBSDrr_Int 6666
-VSUBSHZrm 6667
-VSUBSHZrm_Int 6668
-VSUBSHZrmk_Int 6669
-VSUBSHZrmkz_Int 6670
-VSUBSHZrr 6671
-VSUBSHZrr_Int 6672
-VSUBSHZrrb_Int 6673
-VSUBSHZrrbk_Int 6674
-VSUBSHZrrbkz_Int 6675
-VSUBSHZrrk_Int 6676
-VSUBSHZrrkz_Int 6677
-VSUBSSZrm 6678
-VSUBSSZrm_Int 6679
-VSUBSSZrmk_Int 6680
-VSUBSSZrmkz_Int 6681
-VSUBSSZrr 6682
-VSUBSSZrr_Int 6683
-VSUBSSZrrb_Int 6684
-VSUBSSZrrbk_Int 6685
-VSUBSSZrrbkz_Int 6686
-VSUBSSZrrk_Int 6687
-VSUBSSZrrkz_Int 6688
-VSUBSSrm 6689
-VSUBSSrm_Int 6690
-VSUBSSrr 6691
-VSUBSSrr_Int 6692
-VTESTPDYrm 6693
-VTESTPDYrr 6694
-VTESTPDrm 6695
-VTESTPDrr 6696
-VTESTPSYrm 6697
-VTESTPSYrr 6698
-VTESTPSrm 6699
-VTESTPSrr 6700
-VUCOMISDZrm 6701
-VUCOMISDZrm_Int 6702
-VUCOMISDZrr 6703
-VUCOMISDZrr_Int 6704
-VUCOMISDZrrb 6705
-VUCOMISDrm 6706
-VUCOMISDrm_Int 6707
-VUCOMISDrr 6708
-VUCOMISDrr_Int 6709
-VUCOMISHZrm 6710
-VUCOMISHZrm_Int 6711
-VUCOMISHZrr 6712
-VUCOMISHZrr_Int 6713
-VUCOMISHZrrb 6714
-VUCOMISSZrm 6715
-VUCOMISSZrm_Int 6716
-VUCOMISSZrr 6717
-VUCOMISSZrr_Int 6718
-VUCOMISSZrrb 6719
-VUCOMISSrm 6720
-VUCOMISSrm_Int 6721
-VUCOMISSrr 6722
-VUCOMISSrr_Int 6723
-VUCOMXSDZrm 6724
-VUCOMXSDZrm_Int 6725
-VUCOMXSDZrr 6726
-VUCOMXSDZrr_Int 6727
-VUCOMXSDZrrb_Int 6728
-VUCOMXSHZrm 6729
-VUCOMXSHZrm_Int 6730
-VUCOMXSHZrr 6731
-VUCOMXSHZrr_Int 6732
-VUCOMXSHZrrb_Int 6733
-VUCOMXSSZrm 6734
-VUCOMXSSZrm_Int 6735
-VUCOMXSSZrr 6736
-VUCOMXSSZrr_Int 6737
-VUCOMXSSZrrb_Int 6738
-VUNPCKHPDYrm 6739
-VUNPCKHPDYrr 6740
-VUNPCKHPDZ 6741
-VUNPCKHPDZrm 6742
-VUNPCKHPDZrmb 6743
-VUNPCKHPDZrmbk 6744
-VUNPCKHPDZrmbkz 6745
-VUNPCKHPDZrmk 6746
-VUNPCKHPDZrmkz 6747
-VUNPCKHPDZrr 6748
-VUNPCKHPDZrrk 6749
-VUNPCKHPDZrrkz 6750
-VUNPCKHPDrm 6751
-VUNPCKHPDrr 6752
-VUNPCKHPSYrm 6753
-VUNPCKHPSYrr 6754
-VUNPCKHPSZ 6755
-VUNPCKHPSZrm 6756
-VUNPCKHPSZrmb 6757
-VUNPCKHPSZrmbk 6758
-VUNPCKHPSZrmbkz 6759
-VUNPCKHPSZrmk 6760
-VUNPCKHPSZrmkz 6761
-VUNPCKHPSZrr 6762
-VUNPCKHPSZrrk 6763
-VUNPCKHPSZrrkz 6764
-VUNPCKHPSrm 6765
-VUNPCKHPSrr 6766
-VUNPCKLPDYrm 6767
-VUNPCKLPDYrr 6768
-VUNPCKLPDZ 6769
-VUNPCKLPDZrm 6770
-VUNPCKLPDZrmb 6771
-VUNPCKLPDZrmbk 6772
-VUNPCKLPDZrmbkz 6773
-VUNPCKLPDZrmk 6774
-VUNPCKLPDZrmkz 6775
-VUNPCKLPDZrr 6776
-VUNPCKLPDZrrk 6777
-VUNPCKLPDZrrkz 6778
-VUNPCKLPDrm 6779
-VUNPCKLPDrr 6780
-VUNPCKLPSYrm 6781
-VUNPCKLPSYrr 6782
-VUNPCKLPSZ 6783
-VUNPCKLPSZrm 6784
-VUNPCKLPSZrmb 6785
-VUNPCKLPSZrmbk 6786
-VUNPCKLPSZrmbkz 6787
-VUNPCKLPSZrmk 6788
-VUNPCKLPSZrmkz 6789
-VUNPCKLPSZrr 6790
-VUNPCKLPSZrrk 6791
-VUNPCKLPSZrrkz 6792
-VUNPCKLPSrm 6793
-VUNPCKLPSrr 6794
-VXORPDYrm 6795
-VXORPDYrr 6796
-VXORPDZ 6797
-VXORPDZrm 6798
-VXORPDZrmb 6799
-VXORPDZrmbk 6800
-VXORPDZrmbkz 6801
-VXORPDZrmk 6802
-VXORPDZrmkz 6803
-VXORPDZrr 6804
-VXORPDZrrk 6805
-VXORPDZrrkz 6806
-VXORPDrm 6807
-VXORPDrr 6808
-VXORPSYrm 6809
-VXORPSYrr 6810
-VXORPSZ 6811
-VXORPSZrm 6812
-VXORPSZrmb 6813
-VXORPSZrmbk 6814
-VXORPSZrmbkz 6815
-VXORPSZrmk 6816
-VXORPSZrmkz 6817
-VXORPSZrr 6818
-VXORPSZrrk 6819
-VXORPSZrrkz 6820
-VXORPSrm 6821
-VXORPSrr 6822
-VZEROALL 6823
-VZEROUPPER 6824
-V_SET 6825
-V_SETALLONES 6826
-WAIT 6827
-WBINVD 6828
-WBNOINVD 6829
-WRFLAGS 6830
-WRFSBASE 6831
-WRGSBASE 6832
-WRMSR 6833
-WRMSRLIST 6834
-WRMSRNS 6835
-WRMSRNSir 6836
-WRMSRNSir_EVEX 6837
-WRPKRUr 6838
-WRSSD 6839
-WRSSD_EVEX 6840
-WRSSQ 6841
-WRSSQ_EVEX 6842
-WRUSSD 6843
-WRUSSD_EVEX 6844
-WRUSSQ 6845
-WRUSSQ_EVEX 6846
-XABORT 6847
-XABORT_DEF 6848
-XACQUIRE_PREFIX 6849
-XADD 6850
-XAM_F 6851
-XAM_Fp 6852
-XBEGIN 6853
-XCHG 6854
-XCH_F 6855
-XCRYPTCBC 6856
-XCRYPTCFB 6857
-XCRYPTCTR 6858
-XCRYPTECB 6859
-XCRYPTOFB 6860
-XEND 6861
-XGETBV 6862
-XLAT 6863
-XOR 6864
-XORPDrm 6865
-XORPDrr 6866
-XORPSrm 6867
-XORPSrr 6868
-XRELEASE_PREFIX 6869
-XRESLDTRK 6870
-XRSTOR 6871
-XRSTORS 6872
-XSAVE 6873
-XSAVEC 6874
-XSAVEOPT 6875
-XSAVES 6876
-XSETBV 6877
-XSHA 6878
-XSTORE 6879
-XSUSLDTRK 6880
-XTEST 6881
-Immediate 6882
-CImmediate 6883
-FPImmediate 6884
-MBB 6885
-FrameIndex 6886
-ConstantPoolIndex 6887
-TargetIndex 6888
-JumpTableIndex 6889
-ExternalSymbol 6890
-GlobalAddress 6891
-BlockAddress 6892
-RegisterMask 6893
-RegisterLiveOut 6894
-Metadata 6895
-MCSymbol 6896
-CFIIndex 6897
-IntrinsicID 6898
-Predicate 6899
-ShuffleMask 6900
-PhyReg_GR8 6901
-PhyReg_GRH8 6902
-PhyReg_GR8_NOREX2 6903
-PhyReg_GR8_NOREX 6904
-PhyReg_GR8_ABCD_H 6905
-PhyReg_GR8_ABCD_L 6906
-PhyReg_GRH16 6907
-PhyReg_GR16 6908
-PhyReg_GR16_NOREX2 6909
-PhyReg_GR16_NOREX 6910
-PhyReg_VK1 6911
-PhyReg_VK16 6912
-PhyReg_VK2 6913
-PhyReg_VK4 6914
-PhyReg_VK8 6915
-PhyReg_VK16WM 6916
-PhyReg_VK1WM 6917
-PhyReg_VK2WM 6918
-PhyReg_VK4WM 6919
-PhyReg_VK8WM 6920
-PhyReg_SEGMENT_REG 6921
-PhyReg_GR16_ABCD 6922
-PhyReg_FPCCR 6923
-PhyReg_FR16X 6924
-PhyReg_FR16 6925
-PhyReg_VK16PAIR 6926
-PhyReg_VK1PAIR 6927
-PhyReg_VK2PAIR 6928
-PhyReg_VK4PAIR 6929
-PhyReg_VK8PAIR 6930
-PhyReg_VK1PAIR_with_sub_mask_0_in_VK1WM 6931
-PhyReg_LOW32_ADDR_ACCESS_RBP 6932
-PhyReg_LOW32_ADDR_ACCESS 6933
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 6934
-PhyReg_FR32X 6935
-PhyReg_GR32 6936
-PhyReg_GR32_NOSP 6937
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 6938
-PhyReg_DEBUG_REG 6939
-PhyReg_FR32 6940
-PhyReg_GR32_NOREX2 6941
-PhyReg_GR32_NOREX2_NOSP 6942
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 6943
-PhyReg_GR32_NOREX 6944
-PhyReg_VK32 6945
-PhyReg_GR32_NOREX_NOSP 6946
-PhyReg_RFP32 6947
-PhyReg_VK32WM 6948
-PhyReg_GR32_ABCD 6949
-PhyReg_GR32_TC 6950
-PhyReg_GR32_ABCD_and_GR32_TC 6951
-PhyReg_GR32_AD 6952
-PhyReg_GR32_ArgRef 6953
-PhyReg_GR32_BPSP 6954
-PhyReg_GR32_BSI 6955
-PhyReg_GR32_CB 6956
-PhyReg_GR32_DC 6957
-PhyReg_GR32_DIBP 6958
-PhyReg_GR32_SIDI 6959
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 6960
-PhyReg_CCR 6961
-PhyReg_DFCCR 6962
-PhyReg_GR32_ABCD_and_GR32_BSI 6963
-PhyReg_GR32_AD_and_GR32_ArgRef 6964
-PhyReg_GR32_ArgRef_and_GR32_CB 6965
-PhyReg_GR32_BPSP_and_GR32_DIBP 6966
-PhyReg_GR32_BPSP_and_GR32_TC 6967
-PhyReg_GR32_BSI_and_GR32_SIDI 6968
-PhyReg_GR32_DIBP_and_GR32_SIDI 6969
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 6970
-PhyReg_LOW32_ADDR_ACCESS_with_sub_32bit 6971
-PhyReg_RFP64 6972
-PhyReg_GR64 6973
-PhyReg_FR64X 6974
-PhyReg_GR64_with_sub_8bit 6975
-PhyReg_GR64_NOSP 6976
-PhyReg_GR64_NOREX2 6977
-PhyReg_CONTROL_REG 6978
-PhyReg_FR64 6979
-PhyReg_GR64_with_sub_16bit_in_GR16_NOREX2 6980
-PhyReg_GR64_NOREX2_NOSP 6981
-PhyReg_GR64PLTSafe 6982
-PhyReg_GR64_TC 6983
-PhyReg_GR64_NOREX 6984
-PhyReg_GR64_TCW64 6985
-PhyReg_GR64_TC_with_sub_8bit 6986
-PhyReg_GR64_NOREX2_NOSP_and_GR64_TC 6987
-PhyReg_GR64_TCW64_with_sub_8bit 6988
-PhyReg_GR64_TC_and_GR64_TCW64 6989
-PhyReg_GR64_with_sub_16bit_in_GR16_NOREX 6990
-PhyReg_VK64 6991
-PhyReg_VR64 6992
-PhyReg_GR64PLTSafe_and_GR64_TC 6993
-PhyReg_GR64_NOREX2_NOSP_and_GR64_TCW64 6994
-PhyReg_GR64_NOREX_NOSP 6995
-PhyReg_GR64_NOREX_and_GR64_TC 6996
-PhyReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 6997
-PhyReg_VK64WM 6998
-PhyReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 6999
-PhyReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7000
-PhyReg_GR64PLTSafe_and_GR64_TCW64 7001
-PhyReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7002
-PhyReg_GR64_NOREX_and_GR64_TCW64 7003
-PhyReg_GR64_ABCD 7004
-PhyReg_GR64_with_sub_32bit_in_GR32_TC 7005
-PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7006
-PhyReg_GR64_AD 7007
-PhyReg_GR64_ArgRef 7008
-PhyReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7009
-PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef 7010
-PhyReg_GR64_with_sub_32bit_in_GR32_BPSP 7011
-PhyReg_GR64_with_sub_32bit_in_GR32_BSI 7012
-PhyReg_GR64_with_sub_32bit_in_GR32_CB 7013
-PhyReg_GR64_with_sub_32bit_in_GR32_DIBP 7014
-PhyReg_GR64_with_sub_32bit_in_GR32_SIDI 7015
-PhyReg_GR64_A 7016
-PhyReg_GR64_ArgRef_and_GR64_TC 7017
-PhyReg_GR64_and_LOW32_ADDR_ACCESS 7018
-PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7019
-PhyReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7020
-PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7021
-PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7022
-PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7023
-PhyReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7024
-PhyReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7025
-PhyReg_RST 7026
-PhyReg_RFP80 7027
-PhyReg_RFP80_7 7028
-PhyReg_VR128X 7029
-PhyReg_VR128 7030
-PhyReg_VR256X 7031
-PhyReg_VR256 7032
-PhyReg_VR512 7033
-PhyReg_VR512_0_15 7034
-PhyReg_TILE 7035
-PhyReg_TILEPAIR 7036
-VirtReg_GR8 7037
-VirtReg_GRH8 7038
-VirtReg_GR8_NOREX2 7039
-VirtReg_GR8_NOREX 7040
-VirtReg_GR8_ABCD_H 7041
-VirtReg_GR8_ABCD_L 7042
-VirtReg_GRH16 7043
-VirtReg_GR16 7044
-VirtReg_GR16_NOREX2 7045
-VirtReg_GR16_NOREX 7046
-VirtReg_VK1 7047
-VirtReg_VK16 7048
-VirtReg_VK2 7049
-VirtReg_VK4 7050
-VirtReg_VK8 7051
-VirtReg_VK16WM 7052
-VirtReg_VK1WM 7053
-VirtReg_VK2WM 7054
-VirtReg_VK4WM 7055
-VirtReg_VK8WM 7056
-VirtReg_SEGMENT_REG 7057
-VirtReg_GR16_ABCD 7058
-VirtReg_FPCCR 7059
-VirtReg_FR16X 7060
-VirtReg_FR16 7061
-VirtReg_VK16PAIR 7062
-VirtReg_VK1PAIR 7063
-VirtReg_VK2PAIR 7064
-VirtReg_VK4PAIR 7065
-VirtReg_VK8PAIR 7066
-VirtReg_VK1PAIR_with_sub_mask_0_in_VK1WM 7067
-VirtReg_LOW32_ADDR_ACCESS_RBP 7068
-VirtReg_LOW32_ADDR_ACCESS 7069
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 7070
-VirtReg_FR32X 7071
-VirtReg_GR32 7072
-VirtReg_GR32_NOSP 7073
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 7074
-VirtReg_DEBUG_REG 7075
-VirtReg_FR32 7076
-VirtReg_GR32_NOREX2 7077
-VirtReg_GR32_NOREX2_NOSP 7078
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 7079
-VirtReg_GR32_NOREX 7080
-VirtReg_VK32 7081
-VirtReg_GR32_NOREX_NOSP 7082
-VirtReg_RFP32 7083
-VirtReg_VK32WM 7084
-VirtReg_GR32_ABCD 7085
-VirtReg_GR32_TC 7086
-VirtReg_GR32_ABCD_and_GR32_TC 7087
-VirtReg_GR32_AD 7088
-VirtReg_GR32_ArgRef 7089
-VirtReg_GR32_BPSP 7090
-VirtReg_GR32_BSI 7091
-VirtReg_GR32_CB 7092
-VirtReg_GR32_DC 7093
-VirtReg_GR32_DIBP 7094
-VirtReg_GR32_SIDI 7095
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 7096
-VirtReg_CCR 7097
-VirtReg_DFCCR 7098
-VirtReg_GR32_ABCD_and_GR32_BSI 7099
-VirtReg_GR32_AD_and_GR32_ArgRef 7100
-VirtReg_GR32_ArgRef_and_GR32_CB 7101
-VirtReg_GR32_BPSP_and_GR32_DIBP 7102
-VirtReg_GR32_BPSP_and_GR32_TC 7103
-VirtReg_GR32_BSI_and_GR32_SIDI 7104
-VirtReg_GR32_DIBP_and_GR32_SIDI 7105
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 7106
-VirtReg_LOW32_ADDR_ACCESS_with_sub_32bit 7107
-VirtReg_RFP64 7108
-VirtReg_GR64 7109
-VirtReg_FR64X 7110
-VirtReg_GR64_with_sub_8bit 7111
-VirtReg_GR64_NOSP 7112
-VirtReg_GR64_NOREX2 7113
-VirtReg_CONTROL_REG 7114
-VirtReg_FR64 7115
-VirtReg_GR64_with_sub_16bit_in_GR16_NOREX2 7116
-VirtReg_GR64_NOREX2_NOSP 7117
-VirtReg_GR64PLTSafe 7118
-VirtReg_GR64_TC 7119
-VirtReg_GR64_NOREX 7120
-VirtReg_GR64_TCW64 7121
-VirtReg_GR64_TC_with_sub_8bit 7122
-VirtReg_GR64_NOREX2_NOSP_and_GR64_TC 7123
-VirtReg_GR64_TCW64_with_sub_8bit 7124
-VirtReg_GR64_TC_and_GR64_TCW64 7125
-VirtReg_GR64_with_sub_16bit_in_GR16_NOREX 7126
-VirtReg_VK64 7127
-VirtReg_VR64 7128
-VirtReg_GR64PLTSafe_and_GR64_TC 7129
-VirtReg_GR64_NOREX2_NOSP_and_GR64_TCW64 7130
-VirtReg_GR64_NOREX_NOSP 7131
-VirtReg_GR64_NOREX_and_GR64_TC 7132
-VirtReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 7133
-VirtReg_VK64WM 7134
-VirtReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 7135
-VirtReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7136
-VirtReg_GR64PLTSafe_and_GR64_TCW64 7137
-VirtReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7138
-VirtReg_GR64_NOREX_and_GR64_TCW64 7139
-VirtReg_GR64_ABCD 7140
-VirtReg_GR64_with_sub_32bit_in_GR32_TC 7141
-VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7142
-VirtReg_GR64_AD 7143
-VirtReg_GR64_ArgRef 7144
-VirtReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7145
-VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef 7146
-VirtReg_GR64_with_sub_32bit_in_GR32_BPSP 7147
-VirtReg_GR64_with_sub_32bit_in_GR32_BSI 7148
-VirtReg_GR64_with_sub_32bit_in_GR32_CB 7149
-VirtReg_GR64_with_sub_32bit_in_GR32_DIBP 7150
-VirtReg_GR64_with_sub_32bit_in_GR32_SIDI 7151
-VirtReg_GR64_A 7152
-VirtReg_GR64_ArgRef_and_GR64_TC 7153
-VirtReg_GR64_and_LOW32_ADDR_ACCESS 7154
-VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7155
-VirtReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7156
-VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7157
-VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7158
-VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7159
-VirtReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7160
-VirtReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7161
-VirtReg_RST 7162
-VirtReg_RFP80 7163
-VirtReg_RFP80_7 7164
-VirtReg_VR128X 7165
-VirtReg_VR128 7166
-VirtReg_VR256X 7167
-VirtReg_VR256 7168
-VirtReg_VR512 7169
-VirtReg_VR512_0_15 7170
-VirtReg_TILE 7171
-VirtReg_TILEPAIR 7172
+G_FPTRUNC_ODD 425
+G_FRAME_INDEX 426
+G_FREEZE 427
+G_FREM 428
+G_FRINT 429
+G_FSHL 430
+G_FSHR 431
+G_FSIN 432
+G_FSINCOS 433
+G_FSINH 434
+G_FSQRT 435
+G_FSUB 436
+G_FTAN 437
+G_FTANH 438
+G_GET_FPENV 439
+G_GET_FPMODE 440
+G_GET_ROUNDING 441
+G_GLOBAL_VALUE 442
+G_ICMP 443
+G_IMPLICIT_DEF 444
+G_INDEXED_LOAD 445
+G_INDEXED_SEXTLOAD 446
+G_INDEXED_STORE 447
+G_INDEXED_ZEXTLOAD 448
+G_INSERT 449
+G_INSERT_SUBVECTOR 450
+G_INSERT_VECTOR_ELT 451
+G_INTRINSIC 452
+G_INTRINSIC_CONVERGENT 453
+G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS 454
+G_INTRINSIC_FPTRUNC_ROUND 455
+G_INTRINSIC_LLRINT 456
+G_INTRINSIC_LRINT 457
+G_INTRINSIC_ROUND 458
+G_INTRINSIC_ROUNDEVEN 459
+G_INTRINSIC_TRUNC 460
+G_INTRINSIC_W_SIDE_EFFECTS 461
+G_INTTOPTR 462
+G_INVOKE_REGION_START 463
+G_IS_FPCLASS 464
+G_JUMP_TABLE 465
+G_LLROUND 466
+G_LOAD 467
+G_LROUND 468
+G_LSHR 469
+G_MEMCPY 470
+G_MEMCPY_INLINE 471
+G_MEMMOVE 472
+G_MEMSET 473
+G_MERGE_VALUES 474
+G_MUL 475
+G_OR 476
+G_PHI 477
+G_PREFETCH 478
+G_PTRAUTH_GLOBAL_VALUE 479
+G_PTRMASK 480
+G_PTRTOINT 481
+G_PTR_ADD 482
+G_READCYCLECOUNTER 483
+G_READSTEADYCOUNTER 484
+G_READ_REGISTER 485
+G_RESET_FPENV 486
+G_RESET_FPMODE 487
+G_ROTL 488
+G_ROTR 489
+G_SADDE 490
+G_SADDO 491
+G_SADDSAT 492
+G_SBFX 493
+G_SCMP 494
+G_SDIV 495
+G_SDIVFIX 496
+G_SDIVFIXSAT 497
+G_SDIVREM 498
+G_SELECT 499
+G_SET_FPENV 500
+G_SET_FPMODE 501
+G_SET_ROUNDING 502
+G_SEXT 503
+G_SEXTLOAD 504
+G_SEXT_INREG 505
+G_SHL 506
+G_SHUFFLE_VECTOR 507
+G_SITOFP 508
+G_SMAX 509
+G_SMIN 510
+G_SMULFIX 511
+G_SMULFIXSAT 512
+G_SMULH 513
+G_SMULO 514
+G_SPLAT_VECTOR 515
+G_SREM 516
+G_SSHLSAT 517
+G_SSUBE 518
+G_SSUBO 519
+G_SSUBSAT 520
+G_STACKRESTORE 521
+G_STACKSAVE 522
+G_STEP_VECTOR 523
+G_STORE 524
+G_STRICT_FADD 525
+G_STRICT_FDIV 526
+G_STRICT_FLDEXP 527
+G_STRICT_FMA 528
+G_STRICT_FMUL 529
+G_STRICT_FREM 530
+G_STRICT_FSQRT 531
+G_STRICT_FSUB 532
+G_SUB 533
+G_TRAP 534
+G_TRUNC 535
+G_TRUNC_SSAT_S 536
+G_TRUNC_SSAT_U 537
+G_TRUNC_USAT_U 538
+G_UADDE 539
+G_UADDO 540
+G_UADDSAT 541
+G_UBFX 542
+G_UBSANTRAP 543
+G_UCMP 544
+G_UDIV 545
+G_UDIVFIX 546
+G_UDIVFIXSAT 547
+G_UDIVREM 548
+G_UITOFP 549
+G_UMAX 550
+G_UMIN 551
+G_UMULFIX 552
+G_UMULFIXSAT 553
+G_UMULH 554
+G_UMULO 555
+G_UNMERGE_VALUES 556
+G_UREM 557
+G_USHLSAT 558
+G_USUBE 559
+G_USUBO 560
+G_USUBSAT 561
+G_VAARG 562
+G_VASTART 563
+G_VECREDUCE_ADD 564
+G_VECREDUCE_AND 565
+G_VECREDUCE_FADD 566
+G_VECREDUCE_FMAX 567
+G_VECREDUCE_FMAXIMUM 568
+G_VECREDUCE_FMIN 569
+G_VECREDUCE_FMINIMUM 570
+G_VECREDUCE_FMUL 571
+G_VECREDUCE_MUL 572
+G_VECREDUCE_OR 573
+G_VECREDUCE_SEQ_FADD 574
+G_VECREDUCE_SEQ_FMUL 575
+G_VECREDUCE_SMAX 576
+G_VECREDUCE_SMIN 577
+G_VECREDUCE_UMAX 578
+G_VECREDUCE_UMIN 579
+G_VECREDUCE_XOR 580
+G_VECTOR_COMPRESS 581
+G_VSCALE 582
+G_WRITE_REGISTER 583
+G_XOR 584
+G_ZEXT 585
+G_ZEXTLOAD 586
+HADDPDrm 587
+HADDPDrr 588
+HADDPSrm 589
+HADDPSrr 590
+HLT 591
+HRESET 592
+HSUBPDrm 593
+HSUBPDrr 594
+HSUBPSrm 595
+HSUBPSrr 596
+ICALL_BRANCH_FUNNEL 597
+IDIV 598
+ILD_F 599
+ILD_Fp 600
+IMPLICIT_DEF 601
+IMUL 602
+IMULZU 603
+IN 604
+INC 605
+INCSSPD 606
+INCSSPQ 607
+INDIRECT_THUNK_CALL 608
+INDIRECT_THUNK_TCRETURN 609
+INIT_UNDEF 610
+INLINEASM 611
+INLINEASM_BR 612
+INSB 613
+INSERTPSrmi 614
+INSERTPSrri 615
+INSERTQ 616
+INSERTQI 617
+INSERT_SUBREG 618
+INSL 619
+INSW 620
+INT 621
+INTO 622
+INVD 623
+INVEPT 624
+INVLPG 625
+INVLPGA 626
+INVLPGB 627
+INVPCID 628
+INVVPID 629
+IRET 630
+ISTT_FP 631
+ISTT_Fp 632
+IST_F 633
+IST_FP 634
+IST_Fp 635
+Int_eh_sjlj_setup_dispatch 636
+JCC 637
+JCXZ 638
+JECXZ 639
+JMP 640
+JMPABS 641
+JRCXZ 642
+JUMP_TABLE_DEBUG_INFO 643
+KADDBkk 644
+KADDDkk 645
+KADDQkk 646
+KADDWkk 647
+KANDBkk 648
+KANDDkk 649
+KANDNBkk 650
+KANDNDkk 651
+KANDNQkk 652
+KANDNWkk 653
+KANDQkk 654
+KANDWkk 655
+KCFI_CHECK 656
+KILL 657
+KMOVBkk 658
+KMOVBkk_EVEX 659
+KMOVBkm 660
+KMOVBkm_EVEX 661
+KMOVBkr 662
+KMOVBkr_EVEX 663
+KMOVBmk 664
+KMOVBmk_EVEX 665
+KMOVBrk 666
+KMOVBrk_EVEX 667
+KMOVDkk 668
+KMOVDkk_EVEX 669
+KMOVDkm 670
+KMOVDkm_EVEX 671
+KMOVDkr 672
+KMOVDkr_EVEX 673
+KMOVDmk 674
+KMOVDmk_EVEX 675
+KMOVDrk 676
+KMOVDrk_EVEX 677
+KMOVQkk 678
+KMOVQkk_EVEX 679
+KMOVQkm 680
+KMOVQkm_EVEX 681
+KMOVQkr 682
+KMOVQkr_EVEX 683
+KMOVQmk 684
+KMOVQmk_EVEX 685
+KMOVQrk 686
+KMOVQrk_EVEX 687
+KMOVWkk 688
+KMOVWkk_EVEX 689
+KMOVWkm 690
+KMOVWkm_EVEX 691
+KMOVWkr 692
+KMOVWkr_EVEX 693
+KMOVWmk 694
+KMOVWmk_EVEX 695
+KMOVWrk 696
+KMOVWrk_EVEX 697
+KNOTBkk 698
+KNOTDkk 699
+KNOTQkk 700
+KNOTWkk 701
+KORBkk 702
+KORDkk 703
+KORQkk 704
+KORTESTBkk 705
+KORTESTDkk 706
+KORTESTQkk 707
+KORTESTWkk 708
+KORWkk 709
+KSET 710
+KSHIFTLBki 711
+KSHIFTLDki 712
+KSHIFTLQki 713
+KSHIFTLWki 714
+KSHIFTRBki 715
+KSHIFTRDki 716
+KSHIFTRQki 717
+KSHIFTRWki 718
+KTESTBkk 719
+KTESTDkk 720
+KTESTQkk 721
+KTESTWkk 722
+KUNPCKBWkk 723
+KUNPCKDQkk 724
+KUNPCKWDkk 725
+KXNORBkk 726
+KXNORDkk 727
+KXNORQkk 728
+KXNORWkk 729
+KXORBkk 730
+KXORDkk 731
+KXORQkk 732
+KXORWkk 733
+LAHF 734
+LAR 735
+LCMPXCHG 736
+LDDQUrm 737
+LDMXCSR 738
+LDS 739
+LDTILECFG 740
+LDTILECFG_EVEX 741
+LD_F 742
+LD_Fp 743
+LD_Frr 744
+LEA 745
+LEAVE 746
+LES 747
+LFENCE 748
+LFS 749
+LGDT 750
+LGS 751
+LIDT 752
+LIFETIME_END 753
+LIFETIME_START 754
+LKGS 755
+LLDT 756
+LLWPCB 757
+LMSW 758
+LOADIWKEY 759
+LOAD_STACK_GUARD 760
+LOCAL_ESCAPE 761
+LOCK_ADD 762
+LOCK_AND 763
+LOCK_BTC 764
+LOCK_BTC_RM 765
+LOCK_BTR 766
+LOCK_BTR_RM 767
+LOCK_BTS 768
+LOCK_BTS_RM 769
+LOCK_DEC 770
+LOCK_INC 771
+LOCK_OR 772
+LOCK_PREFIX 773
+LOCK_SUB 774
+LOCK_XOR 775
+LODSB 776
+LODSL 777
+LODSQ 778
+LODSW 779
+LOOP 780
+LOOPE 781
+LOOPNE 782
+LRET 783
+LRETI 784
+LSL 785
+LSS 786
+LTRm 787
+LTRr 788
+LWPINS 789
+LWPVAL 790
+LXADD 791
+LZCNT 792
+MASKMOVDQU 793
+MASKPAIR 794
+MAXCPDrm 795
+MAXCPDrr 796
+MAXCPSrm 797
+MAXCPSrr 798
+MAXCSDrm 799
+MAXCSDrr 800
+MAXCSSrm 801
+MAXCSSrr 802
+MAXPDrm 803
+MAXPDrr 804
+MAXPSrm 805
+MAXPSrr 806
+MAXSDrm 807
+MAXSDrm_Int 808
+MAXSDrr 809
+MAXSDrr_Int 810
+MAXSSrm 811
+MAXSSrm_Int 812
+MAXSSrr 813
+MAXSSrr_Int 814
+MEMBARRIER 815
+MFENCE 816
+MINCPDrm 817
+MINCPDrr 818
+MINCPSrm 819
+MINCPSrr 820
+MINCSDrm 821
+MINCSDrr 822
+MINCSSrm 823
+MINCSSrr 824
+MINPDrm 825
+MINPDrr 826
+MINPSrm 827
+MINPSrr 828
+MINSDrm 829
+MINSDrm_Int 830
+MINSDrr 831
+MINSDrr_Int 832
+MINSSrm 833
+MINSSrm_Int 834
+MINSSrr 835
+MINSSrr_Int 836
+MMX_CVTPD 837
+MMX_CVTPI 838
+MMX_CVTPS 839
+MMX_CVTTPD 840
+MMX_CVTTPS 841
+MMX_EMMS 842
+MMX_MASKMOVQ 843
+MMX_MOVD 844
+MMX_MOVDQ 845
+MMX_MOVFR 846
+MMX_MOVNTQmr 847
+MMX_MOVQ 848
+MMX_PABSBrm 849
+MMX_PABSBrr 850
+MMX_PABSDrm 851
+MMX_PABSDrr 852
+MMX_PABSWrm 853
+MMX_PABSWrr 854
+MMX_PACKSSDWrm 855
+MMX_PACKSSDWrr 856
+MMX_PACKSSWBrm 857
+MMX_PACKSSWBrr 858
+MMX_PACKUSWBrm 859
+MMX_PACKUSWBrr 860
+MMX_PADDBrm 861
+MMX_PADDBrr 862
+MMX_PADDDrm 863
+MMX_PADDDrr 864
+MMX_PADDQrm 865
+MMX_PADDQrr 866
+MMX_PADDSBrm 867
+MMX_PADDSBrr 868
+MMX_PADDSWrm 869
+MMX_PADDSWrr 870
+MMX_PADDUSBrm 871
+MMX_PADDUSBrr 872
+MMX_PADDUSWrm 873
+MMX_PADDUSWrr 874
+MMX_PADDWrm 875
+MMX_PADDWrr 876
+MMX_PALIGNRrmi 877
+MMX_PALIGNRrri 878
+MMX_PANDNrm 879
+MMX_PANDNrr 880
+MMX_PANDrm 881
+MMX_PANDrr 882
+MMX_PAVGBrm 883
+MMX_PAVGBrr 884
+MMX_PAVGWrm 885
+MMX_PAVGWrr 886
+MMX_PCMPEQBrm 887
+MMX_PCMPEQBrr 888
+MMX_PCMPEQDrm 889
+MMX_PCMPEQDrr 890
+MMX_PCMPEQWrm 891
+MMX_PCMPEQWrr 892
+MMX_PCMPGTBrm 893
+MMX_PCMPGTBrr 894
+MMX_PCMPGTDrm 895
+MMX_PCMPGTDrr 896
+MMX_PCMPGTWrm 897
+MMX_PCMPGTWrr 898
+MMX_PEXTRWrri 899
+MMX_PHADDDrm 900
+MMX_PHADDDrr 901
+MMX_PHADDSWrm 902
+MMX_PHADDSWrr 903
+MMX_PHADDWrm 904
+MMX_PHADDWrr 905
+MMX_PHSUBDrm 906
+MMX_PHSUBDrr 907
+MMX_PHSUBSWrm 908
+MMX_PHSUBSWrr 909
+MMX_PHSUBWrm 910
+MMX_PHSUBWrr 911
+MMX_PINSRWrmi 912
+MMX_PINSRWrri 913
+MMX_PMADDUBSWrm 914
+MMX_PMADDUBSWrr 915
+MMX_PMADDWDrm 916
+MMX_PMADDWDrr 917
+MMX_PMAXSWrm 918
+MMX_PMAXSWrr 919
+MMX_PMAXUBrm 920
+MMX_PMAXUBrr 921
+MMX_PMINSWrm 922
+MMX_PMINSWrr 923
+MMX_PMINUBrm 924
+MMX_PMINUBrr 925
+MMX_PMOVMSKBrr 926
+MMX_PMULHRSWrm 927
+MMX_PMULHRSWrr 928
+MMX_PMULHUWrm 929
+MMX_PMULHUWrr 930
+MMX_PMULHWrm 931
+MMX_PMULHWrr 932
+MMX_PMULLWrm 933
+MMX_PMULLWrr 934
+MMX_PMULUDQrm 935
+MMX_PMULUDQrr 936
+MMX_PORrm 937
+MMX_PORrr 938
+MMX_PSADBWrm 939
+MMX_PSADBWrr 940
+MMX_PSHUFBrm 941
+MMX_PSHUFBrr 942
+MMX_PSHUFWmi 943
+MMX_PSHUFWri 944
+MMX_PSIGNBrm 945
+MMX_PSIGNBrr 946
+MMX_PSIGNDrm 947
+MMX_PSIGNDrr 948
+MMX_PSIGNWrm 949
+MMX_PSIGNWrr 950
+MMX_PSLLDri 951
+MMX_PSLLDrm 952
+MMX_PSLLDrr 953
+MMX_PSLLQri 954
+MMX_PSLLQrm 955
+MMX_PSLLQrr 956
+MMX_PSLLWri 957
+MMX_PSLLWrm 958
+MMX_PSLLWrr 959
+MMX_PSRADri 960
+MMX_PSRADrm 961
+MMX_PSRADrr 962
+MMX_PSRAWri 963
+MMX_PSRAWrm 964
+MMX_PSRAWrr 965
+MMX_PSRLDri 966
+MMX_PSRLDrm 967
+MMX_PSRLDrr 968
+MMX_PSRLQri 969
+MMX_PSRLQrm 970
+MMX_PSRLQrr 971
+MMX_PSRLWri 972
+MMX_PSRLWrm 973
+MMX_PSRLWrr 974
+MMX_PSUBBrm 975
+MMX_PSUBBrr 976
+MMX_PSUBDrm 977
+MMX_PSUBDrr 978
+MMX_PSUBQrm 979
+MMX_PSUBQrr 980
+MMX_PSUBSBrm 981
+MMX_PSUBSBrr 982
+MMX_PSUBSWrm 983
+MMX_PSUBSWrr 984
+MMX_PSUBUSBrm 985
+MMX_PSUBUSBrr 986
+MMX_PSUBUSWrm 987
+MMX_PSUBUSWrr 988
+MMX_PSUBWrm 989
+MMX_PSUBWrr 990
+MMX_PUNPCKHBWrm 991
+MMX_PUNPCKHBWrr 992
+MMX_PUNPCKHDQrm 993
+MMX_PUNPCKHDQrr 994
+MMX_PUNPCKHWDrm 995
+MMX_PUNPCKHWDrr 996
+MMX_PUNPCKLBWrm 997
+MMX_PUNPCKLBWrr 998
+MMX_PUNPCKLDQrm 999
+MMX_PUNPCKLDQrr 1000
+MMX_PUNPCKLWDrm 1001
+MMX_PUNPCKLWDrr 1002
+MMX_PXORrm 1003
+MMX_PXORrr 1004
+MMX_SET 1005
+MONITOR 1006
+MONITORX 1007
+MONTMUL 1008
+MORESTACK_RET 1009
+MORESTACK_RET_RESTORE_R 1010
+MOV 1011
+MOVAPDmr 1012
+MOVAPDrm 1013
+MOVAPDrr 1014
+MOVAPDrr_REV 1015
+MOVAPSmr 1016
+MOVAPSrm 1017
+MOVAPSrr 1018
+MOVAPSrr_REV 1019
+MOVBE 1020
+MOVDDUPrm 1021
+MOVDDUPrr 1022
+MOVDI 1023
+MOVDIR 1024
+MOVDIRI 1025
+MOVDQAmr 1026
+MOVDQArm 1027
+MOVDQArr 1028
+MOVDQArr_REV 1029
+MOVDQUmr 1030
+MOVDQUrm 1031
+MOVDQUrr 1032
+MOVDQUrr_REV 1033
+MOVHLPSrr 1034
+MOVHPDmr 1035
+MOVHPDrm 1036
+MOVHPSmr 1037
+MOVHPSrm 1038
+MOVLHPSrr 1039
+MOVLPDmr 1040
+MOVLPDrm 1041
+MOVLPSmr 1042
+MOVLPSrm 1043
+MOVMSKPDrr 1044
+MOVMSKPSrr 1045
+MOVNTDQArm 1046
+MOVNTDQmr 1047
+MOVNTI 1048
+MOVNTImr 1049
+MOVNTPDmr 1050
+MOVNTPSmr 1051
+MOVNTSD 1052
+MOVNTSS 1053
+MOVPC 1054
+MOVPDI 1055
+MOVPQI 1056
+MOVPQIto 1057
+MOVQI 1058
+MOVRS 1059
+MOVSB 1060
+MOVSDmr 1061
+MOVSDrm 1062
+MOVSDrm_alt 1063
+MOVSDrr 1064
+MOVSDrr_REV 1065
+MOVSDto 1066
+MOVSHDUPrm 1067
+MOVSHDUPrr 1068
+MOVSHPmr 1069
+MOVSHPrm 1070
+MOVSL 1071
+MOVSLDUPrm 1072
+MOVSLDUPrr 1073
+MOVSQ 1074
+MOVSS 1075
+MOVSSmr 1076
+MOVSSrm 1077
+MOVSSrm_alt 1078
+MOVSSrr 1079
+MOVSSrr_REV 1080
+MOVSW 1081
+MOVSX 1082
+MOVUPDmr 1083
+MOVUPDrm 1084
+MOVUPDrr 1085
+MOVUPDrr_REV 1086
+MOVUPSmr 1087
+MOVUPSrm 1088
+MOVUPSrr 1089
+MOVUPSrr_REV 1090
+MOVZPQILo 1091
+MOVZX 1092
+MPSADBWrmi 1093
+MPSADBWrri 1094
+MUL 1095
+MULPDrm 1096
+MULPDrr 1097
+MULPSrm 1098
+MULPSrr 1099
+MULSDrm 1100
+MULSDrm_Int 1101
+MULSDrr 1102
+MULSDrr_Int 1103
+MULSSrm 1104
+MULSSrm_Int 1105
+MULSSrr 1106
+MULSSrr_Int 1107
+MULX 1108
+MUL_F 1109
+MUL_FI 1110
+MUL_FPrST 1111
+MUL_FST 1112
+MUL_Fp 1113
+MUL_FpI 1114
+MUL_FrST 1115
+MWAITX 1116
+MWAITX_SAVE_RBX 1117
+MWAITXrrr 1118
+MWAITrr 1119
+NEG 1120
+NOOP 1121
+NOOPL 1122
+NOOPLr 1123
+NOOPQ 1124
+NOOPQr 1125
+NOOPW 1126
+NOOPWr 1127
+NOT 1128
+OR 1129
+ORPDrm 1130
+ORPDrr 1131
+ORPSrm 1132
+ORPSrr 1133
+OUT 1134
+OUTSB 1135
+OUTSL 1136
+OUTSW 1137
+PABSBrm 1138
+PABSBrr 1139
+PABSDrm 1140
+PABSDrr 1141
+PABSWrm 1142
+PABSWrr 1143
+PACKSSDWrm 1144
+PACKSSDWrr 1145
+PACKSSWBrm 1146
+PACKSSWBrr 1147
+PACKUSDWrm 1148
+PACKUSDWrr 1149
+PACKUSWBrm 1150
+PACKUSWBrr 1151
+PADDBrm 1152
+PADDBrr 1153
+PADDDrm 1154
+PADDDrr 1155
+PADDQrm 1156
+PADDQrr 1157
+PADDSBrm 1158
+PADDSBrr 1159
+PADDSWrm 1160
+PADDSWrr 1161
+PADDUSBrm 1162
+PADDUSBrr 1163
+PADDUSWrm 1164
+PADDUSWrr 1165
+PADDWrm 1166
+PADDWrr 1167
+PALIGNRrmi 1168
+PALIGNRrri 1169
+PANDNrm 1170
+PANDNrr 1171
+PANDrm 1172
+PANDrr 1173
+PATCHABLE_EVENT_CALL 1174
+PATCHABLE_FUNCTION_ENTER 1175
+PATCHABLE_FUNCTION_EXIT 1176
+PATCHABLE_OP 1177
+PATCHABLE_RET 1178
+PATCHABLE_TAIL_CALL 1179
+PATCHABLE_TYPED_EVENT_CALL 1180
+PATCHPOINT 1181
+PAUSE 1182
+PAVGBrm 1183
+PAVGBrr 1184
+PAVGUSBrm 1185
+PAVGUSBrr 1186
+PAVGWrm 1187
+PAVGWrr 1188
+PBLENDVBrm 1189
+PBLENDVBrr 1190
+PBLENDWrmi 1191
+PBLENDWrri 1192
+PBNDKB 1193
+PCLMULQDQrmi 1194
+PCLMULQDQrri 1195
+PCMPEQBrm 1196
+PCMPEQBrr 1197
+PCMPEQDrm 1198
+PCMPEQDrr 1199
+PCMPEQQrm 1200
+PCMPEQQrr 1201
+PCMPEQWrm 1202
+PCMPEQWrr 1203
+PCMPESTRIrmi 1204
+PCMPESTRIrri 1205
+PCMPESTRMrmi 1206
+PCMPESTRMrri 1207
+PCMPGTBrm 1208
+PCMPGTBrr 1209
+PCMPGTDrm 1210
+PCMPGTDrr 1211
+PCMPGTQrm 1212
+PCMPGTQrr 1213
+PCMPGTWrm 1214
+PCMPGTWrr 1215
+PCMPISTRIrmi 1216
+PCMPISTRIrri 1217
+PCMPISTRMrmi 1218
+PCMPISTRMrri 1219
+PCONFIG 1220
+PDEP 1221
+PEXT 1222
+PEXTRBmri 1223
+PEXTRBrri 1224
+PEXTRDmri 1225
+PEXTRDrri 1226
+PEXTRQmri 1227
+PEXTRQrri 1228
+PEXTRWmri 1229
+PEXTRWrri 1230
+PEXTRWrri_REV 1231
+PF 1232
+PFACCrm 1233
+PFACCrr 1234
+PFADDrm 1235
+PFADDrr 1236
+PFCMPEQrm 1237
+PFCMPEQrr 1238
+PFCMPGErm 1239
+PFCMPGErr 1240
+PFCMPGTrm 1241
+PFCMPGTrr 1242
+PFMAXrm 1243
+PFMAXrr 1244
+PFMINrm 1245
+PFMINrr 1246
+PFMULrm 1247
+PFMULrr 1248
+PFNACCrm 1249
+PFNACCrr 1250
+PFPNACCrm 1251
+PFPNACCrr 1252
+PFRCPIT 1253
+PFRCPrm 1254
+PFRCPrr 1255
+PFRSQIT 1256
+PFRSQRTrm 1257
+PFRSQRTrr 1258
+PFSUBRrm 1259
+PFSUBRrr 1260
+PFSUBrm 1261
+PFSUBrr 1262
+PHADDDrm 1263
+PHADDDrr 1264
+PHADDSWrm 1265
+PHADDSWrr 1266
+PHADDWrm 1267
+PHADDWrr 1268
+PHI 1269
+PHMINPOSUWrm 1270
+PHMINPOSUWrr 1271
+PHSUBDrm 1272
+PHSUBDrr 1273
+PHSUBSWrm 1274
+PHSUBSWrr 1275
+PHSUBWrm 1276
+PHSUBWrr 1277
+PI 1278
+PINSRBrmi 1279
+PINSRBrri 1280
+PINSRDrmi 1281
+PINSRDrri 1282
+PINSRQrmi 1283
+PINSRQrri 1284
+PINSRWrmi 1285
+PINSRWrri 1286
+PLDTILECFGV 1287
+PLEA 1288
+PMADDUBSWrm 1289
+PMADDUBSWrr 1290
+PMADDWDrm 1291
+PMADDWDrr 1292
+PMAXSBrm 1293
+PMAXSBrr 1294
+PMAXSDrm 1295
+PMAXSDrr 1296
+PMAXSWrm 1297
+PMAXSWrr 1298
+PMAXUBrm 1299
+PMAXUBrr 1300
+PMAXUDrm 1301
+PMAXUDrr 1302
+PMAXUWrm 1303
+PMAXUWrr 1304
+PMINSBrm 1305
+PMINSBrr 1306
+PMINSDrm 1307
+PMINSDrr 1308
+PMINSWrm 1309
+PMINSWrr 1310
+PMINUBrm 1311
+PMINUBrr 1312
+PMINUDrm 1313
+PMINUDrr 1314
+PMINUWrm 1315
+PMINUWrr 1316
+PMOVMSKBrr 1317
+PMOVSXBDrm 1318
+PMOVSXBDrr 1319
+PMOVSXBQrm 1320
+PMOVSXBQrr 1321
+PMOVSXBWrm 1322
+PMOVSXBWrr 1323
+PMOVSXDQrm 1324
+PMOVSXDQrr 1325
+PMOVSXWDrm 1326
+PMOVSXWDrr 1327
+PMOVSXWQrm 1328
+PMOVSXWQrr 1329
+PMOVZXBDrm 1330
+PMOVZXBDrr 1331
+PMOVZXBQrm 1332
+PMOVZXBQrr 1333
+PMOVZXBWrm 1334
+PMOVZXBWrr 1335
+PMOVZXDQrm 1336
+PMOVZXDQrr 1337
+PMOVZXWDrm 1338
+PMOVZXWDrr 1339
+PMOVZXWQrm 1340
+PMOVZXWQrr 1341
+PMULDQrm 1342
+PMULDQrr 1343
+PMULHRSWrm 1344
+PMULHRSWrr 1345
+PMULHRWrm 1346
+PMULHRWrr 1347
+PMULHUWrm 1348
+PMULHUWrr 1349
+PMULHWrm 1350
+PMULHWrr 1351
+PMULLDrm 1352
+PMULLDrr 1353
+PMULLWrm 1354
+PMULLWrr 1355
+PMULUDQrm 1356
+PMULUDQrr 1357
+POP 1358
+POPA 1359
+POPCNT 1360
+POPDS 1361
+POPES 1362
+POPF 1363
+POPFS 1364
+POPGS 1365
+POPP 1366
+POPSS 1367
+PORrm 1368
+PORrr 1369
+PREALLOCATED_ARG 1370
+PREALLOCATED_SETUP 1371
+PREFETCH 1372
+PREFETCHIT 1373
+PREFETCHNTA 1374
+PREFETCHRST 1375
+PREFETCHT 1376
+PREFETCHW 1377
+PREFETCHWT 1378
+PROBED_ALLOCA 1379
+PSADBWrm 1380
+PSADBWrr 1381
+PSEUDO_PROBE 1382
+PSHUFBrm 1383
+PSHUFBrr 1384
+PSHUFDmi 1385
+PSHUFDri 1386
+PSHUFHWmi 1387
+PSHUFHWri 1388
+PSHUFLWmi 1389
+PSHUFLWri 1390
+PSIGNBrm 1391
+PSIGNBrr 1392
+PSIGNDrm 1393
+PSIGNDrr 1394
+PSIGNWrm 1395
+PSIGNWrr 1396
+PSLLDQri 1397
+PSLLDri 1398
+PSLLDrm 1399
+PSLLDrr 1400
+PSLLQri 1401
+PSLLQrm 1402
+PSLLQrr 1403
+PSLLWri 1404
+PSLLWrm 1405
+PSLLWrr 1406
+PSMASH 1407
+PSRADri 1408
+PSRADrm 1409
+PSRADrr 1410
+PSRAWri 1411
+PSRAWrm 1412
+PSRAWrr 1413
+PSRLDQri 1414
+PSRLDri 1415
+PSRLDrm 1416
+PSRLDrr 1417
+PSRLQri 1418
+PSRLQrm 1419
+PSRLQrr 1420
+PSRLWri 1421
+PSRLWrm 1422
+PSRLWrr 1423
+PSUBBrm 1424
+PSUBBrr 1425
+PSUBDrm 1426
+PSUBDrr 1427
+PSUBQrm 1428
+PSUBQrr 1429
+PSUBSBrm 1430
+PSUBSBrr 1431
+PSUBSWrm 1432
+PSUBSWrr 1433
+PSUBUSBrm 1434
+PSUBUSBrr 1435
+PSUBUSWrm 1436
+PSUBUSWrr 1437
+PSUBWrm 1438
+PSUBWrr 1439
+PSWAPDrm 1440
+PSWAPDrr 1441
+PT 1442
+PTCMMIMFP 1443
+PTCMMRLFP 1444
+PTCONJTCMMIMFP 1445
+PTCONJTFP 1446
+PTCVTROWD 1447
+PTCVTROWPS 1448
+PTDPBF 1449
+PTDPBHF 1450
+PTDPBSSD 1451
+PTDPBSSDV 1452
+PTDPBSUD 1453
+PTDPBSUDV 1454
+PTDPBUSD 1455
+PTDPBUSDV 1456
+PTDPBUUD 1457
+PTDPBUUDV 1458
+PTDPFP 1459
+PTDPHBF 1460
+PTDPHF 1461
+PTESTrm 1462
+PTESTrr 1463
+PTILELOADD 1464
+PTILELOADDRS 1465
+PTILELOADDRST 1466
+PTILELOADDRSV 1467
+PTILELOADDT 1468
+PTILELOADDV 1469
+PTILEMOVROWrre 1470
+PTILEMOVROWrreV 1471
+PTILEMOVROWrri 1472
+PTILEMOVROWrriV 1473
+PTILEPAIRLOAD 1474
+PTILEPAIRSTORE 1475
+PTILESTORED 1476
+PTILESTOREDV 1477
+PTILEZERO 1478
+PTILEZEROV 1479
+PTMMULTF 1480
+PTTCMMIMFP 1481
+PTTCMMRLFP 1482
+PTTDPBF 1483
+PTTDPFP 1484
+PTTMMULTF 1485
+PTTRANSPOSED 1486
+PTTRANSPOSEDV 1487
+PTWRITE 1488
+PTWRITEm 1489
+PTWRITEr 1490
+PUNPCKHBWrm 1491
+PUNPCKHBWrr 1492
+PUNPCKHDQrm 1493
+PUNPCKHDQrr 1494
+PUNPCKHQDQrm 1495
+PUNPCKHQDQrr 1496
+PUNPCKHWDrm 1497
+PUNPCKHWDrr 1498
+PUNPCKLBWrm 1499
+PUNPCKLBWrr 1500
+PUNPCKLDQrm 1501
+PUNPCKLDQrr 1502
+PUNPCKLQDQrm 1503
+PUNPCKLQDQrr 1504
+PUNPCKLWDrm 1505
+PUNPCKLWDrr 1506
+PUSH 1507
+PUSHA 1508
+PUSHCS 1509
+PUSHDS 1510
+PUSHES 1511
+PUSHF 1512
+PUSHFS 1513
+PUSHGS 1514
+PUSHP 1515
+PUSHSS 1516
+PVALIDATE 1517
+PXORrm 1518
+PXORrr 1519
+RCL 1520
+RCPPSm 1521
+RCPPSr 1522
+RCPSSm 1523
+RCPSSm_Int 1524
+RCPSSr 1525
+RCPSSr_Int 1526
+RCR 1527
+RDFLAGS 1528
+RDFSBASE 1529
+RDGSBASE 1530
+RDMSR 1531
+RDMSRLIST 1532
+RDMSRri 1533
+RDMSRri_EVEX 1534
+RDPID 1535
+RDPKRUr 1536
+RDPMC 1537
+RDPRU 1538
+RDRAND 1539
+RDSEED 1540
+RDSSPD 1541
+RDSSPQ 1542
+RDTSC 1543
+RDTSCP 1544
+REG_SEQUENCE 1545
+REPNE_PREFIX 1546
+REP_MOVSB 1547
+REP_MOVSD 1548
+REP_MOVSQ 1549
+REP_MOVSW 1550
+REP_PREFIX 1551
+REP_STOSB 1552
+REP_STOSD 1553
+REP_STOSQ 1554
+REP_STOSW 1555
+RET 1556
+RETI 1557
+REX 1558
+RMPADJUST 1559
+RMPQUERY 1560
+RMPUPDATE 1561
+ROL 1562
+ROR 1563
+RORX 1564
+ROUNDPDmi 1565
+ROUNDPDri 1566
+ROUNDPSmi 1567
+ROUNDPSri 1568
+ROUNDSDmi 1569
+ROUNDSDmi_Int 1570
+ROUNDSDri 1571
+ROUNDSDri_Int 1572
+ROUNDSSmi 1573
+ROUNDSSmi_Int 1574
+ROUNDSSri 1575
+ROUNDSSri_Int 1576
+RSM 1577
+RSQRTPSm 1578
+RSQRTPSr 1579
+RSQRTSSm 1580
+RSQRTSSm_Int 1581
+RSQRTSSr 1582
+RSQRTSSr_Int 1583
+RSTORSSP 1584
+SAHF 1585
+SALC 1586
+SAR 1587
+SARX 1588
+SAVEPREVSSP 1589
+SBB 1590
+SCASB 1591
+SCASL 1592
+SCASQ 1593
+SCASW 1594
+SEAMCALL 1595
+SEAMOPS 1596
+SEAMRET 1597
+SEG_ALLOCA 1598
+SEH_BeginEpilogue 1599
+SEH_EndEpilogue 1600
+SEH_EndPrologue 1601
+SEH_PushFrame 1602
+SEH_PushReg 1603
+SEH_SaveReg 1604
+SEH_SaveXMM 1605
+SEH_SetFrame 1606
+SEH_StackAlign 1607
+SEH_StackAlloc 1608
+SEH_UnwindV 1609
+SEH_UnwindVersion 1610
+SENDUIPI 1611
+SERIALIZE 1612
+SETB_C 1613
+SETCCm 1614
+SETCCm_EVEX 1615
+SETCCr 1616
+SETCCr_EVEX 1617
+SETSSBSY 1618
+SETZUCCm 1619
+SETZUCCr 1620
+SFENCE 1621
+SGDT 1622
+SHA 1623
+SHL 1624
+SHLD 1625
+SHLDROT 1626
+SHLX 1627
+SHR 1628
+SHRD 1629
+SHRDROT 1630
+SHRX 1631
+SHUFPDrmi 1632
+SHUFPDrri 1633
+SHUFPSrmi 1634
+SHUFPSrri 1635
+SIDT 1636
+SKINIT 1637
+SLDT 1638
+SLWPCB 1639
+SMSW 1640
+SQRTPDm 1641
+SQRTPDr 1642
+SQRTPSm 1643
+SQRTPSr 1644
+SQRTSDm 1645
+SQRTSDm_Int 1646
+SQRTSDr 1647
+SQRTSDr_Int 1648
+SQRTSSm 1649
+SQRTSSm_Int 1650
+SQRTSSr 1651
+SQRTSSr_Int 1652
+SQRT_F 1653
+SQRT_Fp 1654
+SS_PREFIX 1655
+STAC 1656
+STACKALLOC_W_PROBING 1657
+STACKMAP 1658
+STATEPOINT 1659
+STC 1660
+STD 1661
+STGI 1662
+STI 1663
+STMXCSR 1664
+STOSB 1665
+STOSL 1666
+STOSQ 1667
+STOSW 1668
+STR 1669
+STRm 1670
+STTILECFG 1671
+STTILECFG_EVEX 1672
+STUI 1673
+ST_F 1674
+ST_FP 1675
+ST_FPrr 1676
+ST_Fp 1677
+ST_FpP 1678
+ST_Frr 1679
+SUB 1680
+SUBPDrm 1681
+SUBPDrr 1682
+SUBPSrm 1683
+SUBPSrr 1684
+SUBREG_TO_REG 1685
+SUBR_F 1686
+SUBR_FI 1687
+SUBR_FPrST 1688
+SUBR_FST 1689
+SUBR_Fp 1690
+SUBR_FpI 1691
+SUBR_FrST 1692
+SUBSDrm 1693
+SUBSDrm_Int 1694
+SUBSDrr 1695
+SUBSDrr_Int 1696
+SUBSSrm 1697
+SUBSSrm_Int 1698
+SUBSSrr 1699
+SUBSSrr_Int 1700
+SUB_F 1701
+SUB_FI 1702
+SUB_FPrST 1703
+SUB_FST 1704
+SUB_Fp 1705
+SUB_FpI 1706
+SUB_FrST 1707
+SWAPGS 1708
+SYSCALL 1709
+SYSENTER 1710
+SYSEXIT 1711
+SYSRET 1712
+T 1713
+TAILJMPd 1714
+TAILJMPd_CC 1715
+TAILJMPm 1716
+TAILJMPr 1717
+TCMMIMFP 1718
+TCMMRLFP 1719
+TCONJTCMMIMFP 1720
+TCONJTFP 1721
+TCRETURN_HIPE 1722
+TCRETURN_WIN 1723
+TCRETURN_WINmi 1724
+TCRETURNdi 1725
+TCRETURNdicc 1726
+TCRETURNmi 1727
+TCRETURNri 1728
+TCVTROWD 1729
+TCVTROWPS 1730
+TDCALL 1731
+TDPBF 1732
+TDPBHF 1733
+TDPBSSD 1734
+TDPBSUD 1735
+TDPBUSD 1736
+TDPBUUD 1737
+TDPFP 1738
+TDPHBF 1739
+TDPHF 1740
+TEST 1741
+TESTUI 1742
+TILELOADD 1743
+TILELOADDRS 1744
+TILELOADDRST 1745
+TILELOADDRS_EVEX 1746
+TILELOADDT 1747
+TILELOADD_EVEX 1748
+TILEMOVROWrre 1749
+TILEMOVROWrri 1750
+TILERELEASE 1751
+TILESTORED 1752
+TILESTORED_EVEX 1753
+TILEZERO 1754
+TLBSYNC 1755
+TLSCall 1756
+TLS_addr 1757
+TLS_addrX 1758
+TLS_base_addr 1759
+TLS_base_addrX 1760
+TLS_desc 1761
+TMMULTF 1762
+TPAUSE 1763
+TRAP 1764
+TST_F 1765
+TST_Fp 1766
+TTCMMIMFP 1767
+TTCMMRLFP 1768
+TTDPBF 1769
+TTDPFP 1770
+TTMMULTF 1771
+TTRANSPOSED 1772
+TZCNT 1773
+TZMSK 1774
+UBSAN_UD 1775
+UCOMISDrm 1776
+UCOMISDrm_Int 1777
+UCOMISDrr 1778
+UCOMISDrr_Int 1779
+UCOMISSrm 1780
+UCOMISSrm_Int 1781
+UCOMISSrr 1782
+UCOMISSrr_Int 1783
+UCOM_FIPr 1784
+UCOM_FIr 1785
+UCOM_FPPr 1786
+UCOM_FPr 1787
+UCOM_FpIr 1788
+UCOM_Fpr 1789
+UCOM_Fr 1790
+UD 1791
+UIRET 1792
+UMONITOR 1793
+UMWAIT 1794
+UNPCKHPDrm 1795
+UNPCKHPDrr 1796
+UNPCKHPSrm 1797
+UNPCKHPSrr 1798
+UNPCKLPDrm 1799
+UNPCKLPDrr 1800
+UNPCKLPSrm 1801
+UNPCKLPSrr 1802
+URDMSRri 1803
+URDMSRri_EVEX 1804
+URDMSRrr 1805
+URDMSRrr_EVEX 1806
+UWRMSRir 1807
+UWRMSRir_EVEX 1808
+UWRMSRrr 1809
+UWRMSRrr_EVEX 1810
+V 1811
+VAARG 1812
+VAARG_X 1813
+VADDBF 1814
+VADDPDYrm 1815
+VADDPDYrr 1816
+VADDPDZ 1817
+VADDPDZrm 1818
+VADDPDZrmb 1819
+VADDPDZrmbk 1820
+VADDPDZrmbkz 1821
+VADDPDZrmk 1822
+VADDPDZrmkz 1823
+VADDPDZrr 1824
+VADDPDZrrb 1825
+VADDPDZrrbk 1826
+VADDPDZrrbkz 1827
+VADDPDZrrk 1828
+VADDPDZrrkz 1829
+VADDPDrm 1830
+VADDPDrr 1831
+VADDPHZ 1832
+VADDPHZrm 1833
+VADDPHZrmb 1834
+VADDPHZrmbk 1835
+VADDPHZrmbkz 1836
+VADDPHZrmk 1837
+VADDPHZrmkz 1838
+VADDPHZrr 1839
+VADDPHZrrb 1840
+VADDPHZrrbk 1841
+VADDPHZrrbkz 1842
+VADDPHZrrk 1843
+VADDPHZrrkz 1844
+VADDPSYrm 1845
+VADDPSYrr 1846
+VADDPSZ 1847
+VADDPSZrm 1848
+VADDPSZrmb 1849
+VADDPSZrmbk 1850
+VADDPSZrmbkz 1851
+VADDPSZrmk 1852
+VADDPSZrmkz 1853
+VADDPSZrr 1854
+VADDPSZrrb 1855
+VADDPSZrrbk 1856
+VADDPSZrrbkz 1857
+VADDPSZrrk 1858
+VADDPSZrrkz 1859
+VADDPSrm 1860
+VADDPSrr 1861
+VADDSDZrm 1862
+VADDSDZrm_Int 1863
+VADDSDZrmk_Int 1864
+VADDSDZrmkz_Int 1865
+VADDSDZrr 1866
+VADDSDZrr_Int 1867
+VADDSDZrrb_Int 1868
+VADDSDZrrbk_Int 1869
+VADDSDZrrbkz_Int 1870
+VADDSDZrrk_Int 1871
+VADDSDZrrkz_Int 1872
+VADDSDrm 1873
+VADDSDrm_Int 1874
+VADDSDrr 1875
+VADDSDrr_Int 1876
+VADDSHZrm 1877
+VADDSHZrm_Int 1878
+VADDSHZrmk_Int 1879
+VADDSHZrmkz_Int 1880
+VADDSHZrr 1881
+VADDSHZrr_Int 1882
+VADDSHZrrb_Int 1883
+VADDSHZrrbk_Int 1884
+VADDSHZrrbkz_Int 1885
+VADDSHZrrk_Int 1886
+VADDSHZrrkz_Int 1887
+VADDSSZrm 1888
+VADDSSZrm_Int 1889
+VADDSSZrmk_Int 1890
+VADDSSZrmkz_Int 1891
+VADDSSZrr 1892
+VADDSSZrr_Int 1893
+VADDSSZrrb_Int 1894
+VADDSSZrrbk_Int 1895
+VADDSSZrrbkz_Int 1896
+VADDSSZrrk_Int 1897
+VADDSSZrrkz_Int 1898
+VADDSSrm 1899
+VADDSSrm_Int 1900
+VADDSSrr 1901
+VADDSSrr_Int 1902
+VADDSUBPDYrm 1903
+VADDSUBPDYrr 1904
+VADDSUBPDrm 1905
+VADDSUBPDrr 1906
+VADDSUBPSYrm 1907
+VADDSUBPSYrr 1908
+VADDSUBPSrm 1909
+VADDSUBPSrr 1910
+VAESDECLASTYrm 1911
+VAESDECLASTYrr 1912
+VAESDECLASTZ 1913
+VAESDECLASTZrm 1914
+VAESDECLASTZrr 1915
+VAESDECLASTrm 1916
+VAESDECLASTrr 1917
+VAESDECYrm 1918
+VAESDECYrr 1919
+VAESDECZ 1920
+VAESDECZrm 1921
+VAESDECZrr 1922
+VAESDECrm 1923
+VAESDECrr 1924
+VAESENCLASTYrm 1925
+VAESENCLASTYrr 1926
+VAESENCLASTZ 1927
+VAESENCLASTZrm 1928
+VAESENCLASTZrr 1929
+VAESENCLASTrm 1930
+VAESENCLASTrr 1931
+VAESENCYrm 1932
+VAESENCYrr 1933
+VAESENCZ 1934
+VAESENCZrm 1935
+VAESENCZrr 1936
+VAESENCrm 1937
+VAESENCrr 1938
+VAESIMCrm 1939
+VAESIMCrr 1940
+VAESKEYGENASSISTrmi 1941
+VAESKEYGENASSISTrri 1942
+VALIGNDZ 1943
+VALIGNDZrmbi 1944
+VALIGNDZrmbik 1945
+VALIGNDZrmbikz 1946
+VALIGNDZrmi 1947
+VALIGNDZrmik 1948
+VALIGNDZrmikz 1949
+VALIGNDZrri 1950
+VALIGNDZrrik 1951
+VALIGNDZrrikz 1952
+VALIGNQZ 1953
+VALIGNQZrmbi 1954
+VALIGNQZrmbik 1955
+VALIGNQZrmbikz 1956
+VALIGNQZrmi 1957
+VALIGNQZrmik 1958
+VALIGNQZrmikz 1959
+VALIGNQZrri 1960
+VALIGNQZrrik 1961
+VALIGNQZrrikz 1962
+VANDNPDYrm 1963
+VANDNPDYrr 1964
+VANDNPDZ 1965
+VANDNPDZrm 1966
+VANDNPDZrmb 1967
+VANDNPDZrmbk 1968
+VANDNPDZrmbkz 1969
+VANDNPDZrmk 1970
+VANDNPDZrmkz 1971
+VANDNPDZrr 1972
+VANDNPDZrrk 1973
+VANDNPDZrrkz 1974
+VANDNPDrm 1975
+VANDNPDrr 1976
+VANDNPSYrm 1977
+VANDNPSYrr 1978
+VANDNPSZ 1979
+VANDNPSZrm 1980
+VANDNPSZrmb 1981
+VANDNPSZrmbk 1982
+VANDNPSZrmbkz 1983
+VANDNPSZrmk 1984
+VANDNPSZrmkz 1985
+VANDNPSZrr 1986
+VANDNPSZrrk 1987
+VANDNPSZrrkz 1988
+VANDNPSrm 1989
+VANDNPSrr 1990
+VANDPDYrm 1991
+VANDPDYrr 1992
+VANDPDZ 1993
+VANDPDZrm 1994
+VANDPDZrmb 1995
+VANDPDZrmbk 1996
+VANDPDZrmbkz 1997
+VANDPDZrmk 1998
+VANDPDZrmkz 1999
+VANDPDZrr 2000
+VANDPDZrrk 2001
+VANDPDZrrkz 2002
+VANDPDrm 2003
+VANDPDrr 2004
+VANDPSYrm 2005
+VANDPSYrr 2006
+VANDPSZ 2007
+VANDPSZrm 2008
+VANDPSZrmb 2009
+VANDPSZrmbk 2010
+VANDPSZrmbkz 2011
+VANDPSZrmk 2012
+VANDPSZrmkz 2013
+VANDPSZrr 2014
+VANDPSZrrk 2015
+VANDPSZrrkz 2016
+VANDPSrm 2017
+VANDPSrr 2018
+VASTART_SAVE_XMM_REGS 2019
+VBCSTNEBF 2020
+VBCSTNESH 2021
+VBLENDMPDZ 2022
+VBLENDMPDZrm 2023
+VBLENDMPDZrmb 2024
+VBLENDMPDZrmbk 2025
+VBLENDMPDZrmbkz 2026
+VBLENDMPDZrmk 2027
+VBLENDMPDZrmkz 2028
+VBLENDMPDZrr 2029
+VBLENDMPDZrrk 2030
+VBLENDMPDZrrkz 2031
+VBLENDMPSZ 2032
+VBLENDMPSZrm 2033
+VBLENDMPSZrmb 2034
+VBLENDMPSZrmbk 2035
+VBLENDMPSZrmbkz 2036
+VBLENDMPSZrmk 2037
+VBLENDMPSZrmkz 2038
+VBLENDMPSZrr 2039
+VBLENDMPSZrrk 2040
+VBLENDMPSZrrkz 2041
+VBLENDPDYrmi 2042
+VBLENDPDYrri 2043
+VBLENDPDrmi 2044
+VBLENDPDrri 2045
+VBLENDPSYrmi 2046
+VBLENDPSYrri 2047
+VBLENDPSrmi 2048
+VBLENDPSrri 2049
+VBLENDVPDYrmr 2050
+VBLENDVPDYrrr 2051
+VBLENDVPDrmr 2052
+VBLENDVPDrrr 2053
+VBLENDVPSYrmr 2054
+VBLENDVPSYrrr 2055
+VBLENDVPSrmr 2056
+VBLENDVPSrrr 2057
+VBROADCASTF 2058
+VBROADCASTI 2059
+VBROADCASTSDYrm 2060
+VBROADCASTSDYrr 2061
+VBROADCASTSDZ 2062
+VBROADCASTSDZrm 2063
+VBROADCASTSDZrmk 2064
+VBROADCASTSDZrmkz 2065
+VBROADCASTSDZrr 2066
+VBROADCASTSDZrrk 2067
+VBROADCASTSDZrrkz 2068
+VBROADCASTSSYrm 2069
+VBROADCASTSSYrr 2070
+VBROADCASTSSZ 2071
+VBROADCASTSSZrm 2072
+VBROADCASTSSZrmk 2073
+VBROADCASTSSZrmkz 2074
+VBROADCASTSSZrr 2075
+VBROADCASTSSZrrk 2076
+VBROADCASTSSZrrkz 2077
+VBROADCASTSSrm 2078
+VBROADCASTSSrr 2079
+VCMPBF 2080
+VCMPPDYrmi 2081
+VCMPPDYrri 2082
+VCMPPDZ 2083
+VCMPPDZrmbi 2084
+VCMPPDZrmbik 2085
+VCMPPDZrmi 2086
+VCMPPDZrmik 2087
+VCMPPDZrri 2088
+VCMPPDZrrib 2089
+VCMPPDZrribk 2090
+VCMPPDZrrik 2091
+VCMPPDrmi 2092
+VCMPPDrri 2093
+VCMPPHZ 2094
+VCMPPHZrmbi 2095
+VCMPPHZrmbik 2096
+VCMPPHZrmi 2097
+VCMPPHZrmik 2098
+VCMPPHZrri 2099
+VCMPPHZrrib 2100
+VCMPPHZrribk 2101
+VCMPPHZrrik 2102
+VCMPPSYrmi 2103
+VCMPPSYrri 2104
+VCMPPSZ 2105
+VCMPPSZrmbi 2106
+VCMPPSZrmbik 2107
+VCMPPSZrmi 2108
+VCMPPSZrmik 2109
+VCMPPSZrri 2110
+VCMPPSZrrib 2111
+VCMPPSZrribk 2112
+VCMPPSZrrik 2113
+VCMPPSrmi 2114
+VCMPPSrri 2115
+VCMPSDZrmi 2116
+VCMPSDZrmi_Int 2117
+VCMPSDZrmik_Int 2118
+VCMPSDZrri 2119
+VCMPSDZrri_Int 2120
+VCMPSDZrrib_Int 2121
+VCMPSDZrribk_Int 2122
+VCMPSDZrrik_Int 2123
+VCMPSDrmi 2124
+VCMPSDrmi_Int 2125
+VCMPSDrri 2126
+VCMPSDrri_Int 2127
+VCMPSHZrmi 2128
+VCMPSHZrmi_Int 2129
+VCMPSHZrmik_Int 2130
+VCMPSHZrri 2131
+VCMPSHZrri_Int 2132
+VCMPSHZrrib_Int 2133
+VCMPSHZrribk_Int 2134
+VCMPSHZrrik_Int 2135
+VCMPSSZrmi 2136
+VCMPSSZrmi_Int 2137
+VCMPSSZrmik_Int 2138
+VCMPSSZrri 2139
+VCMPSSZrri_Int 2140
+VCMPSSZrrib_Int 2141
+VCMPSSZrribk_Int 2142
+VCMPSSZrrik_Int 2143
+VCMPSSrmi 2144
+VCMPSSrmi_Int 2145
+VCMPSSrri 2146
+VCMPSSrri_Int 2147
+VCOMISBF 2148
+VCOMISDZrm 2149
+VCOMISDZrm_Int 2150
+VCOMISDZrr 2151
+VCOMISDZrr_Int 2152
+VCOMISDZrrb 2153
+VCOMISDrm 2154
+VCOMISDrm_Int 2155
+VCOMISDrr 2156
+VCOMISDrr_Int 2157
+VCOMISHZrm 2158
+VCOMISHZrm_Int 2159
+VCOMISHZrr 2160
+VCOMISHZrr_Int 2161
+VCOMISHZrrb 2162
+VCOMISSZrm 2163
+VCOMISSZrm_Int 2164
+VCOMISSZrr 2165
+VCOMISSZrr_Int 2166
+VCOMISSZrrb 2167
+VCOMISSrm 2168
+VCOMISSrm_Int 2169
+VCOMISSrr 2170
+VCOMISSrr_Int 2171
+VCOMPRESSPDZ 2172
+VCOMPRESSPDZmr 2173
+VCOMPRESSPDZmrk 2174
+VCOMPRESSPDZrr 2175
+VCOMPRESSPDZrrk 2176
+VCOMPRESSPDZrrkz 2177
+VCOMPRESSPSZ 2178
+VCOMPRESSPSZmr 2179
+VCOMPRESSPSZmrk 2180
+VCOMPRESSPSZrr 2181
+VCOMPRESSPSZrrk 2182
+VCOMPRESSPSZrrkz 2183
+VCOMXSDZrm_Int 2184
+VCOMXSDZrr_Int 2185
+VCOMXSDZrrb_Int 2186
+VCOMXSHZrm_Int 2187
+VCOMXSHZrr_Int 2188
+VCOMXSHZrrb_Int 2189
+VCOMXSSZrm_Int 2190
+VCOMXSSZrr_Int 2191
+VCOMXSSZrrb_Int 2192
+VCVT 2193
+VCVTBF 2194
+VCVTBIASPH 2195
+VCVTDQ 2196
+VCVTHF 2197
+VCVTNE 2198
+VCVTNEEBF 2199
+VCVTNEEPH 2200
+VCVTNEOBF 2201
+VCVTNEOPH 2202
+VCVTNEPS 2203
+VCVTPD 2204
+VCVTPH 2205
+VCVTPS 2206
+VCVTQQ 2207
+VCVTSD 2208
+VCVTSH 2209
+VCVTSI 2210
+VCVTSS 2211
+VCVTTBF 2212
+VCVTTPD 2213
+VCVTTPH 2214
+VCVTTPS 2215
+VCVTTSD 2216
+VCVTTSH 2217
+VCVTTSS 2218
+VCVTUDQ 2219
+VCVTUQQ 2220
+VCVTUSI 2221
+VCVTUW 2222
+VCVTW 2223
+VDBPSADBWZ 2224
+VDBPSADBWZrmi 2225
+VDBPSADBWZrmik 2226
+VDBPSADBWZrmikz 2227
+VDBPSADBWZrri 2228
+VDBPSADBWZrrik 2229
+VDBPSADBWZrrikz 2230
+VDIVBF 2231
+VDIVPDYrm 2232
+VDIVPDYrr 2233
+VDIVPDZ 2234
+VDIVPDZrm 2235
+VDIVPDZrmb 2236
+VDIVPDZrmbk 2237
+VDIVPDZrmbkz 2238
+VDIVPDZrmk 2239
+VDIVPDZrmkz 2240
+VDIVPDZrr 2241
+VDIVPDZrrb 2242
+VDIVPDZrrbk 2243
+VDIVPDZrrbkz 2244
+VDIVPDZrrk 2245
+VDIVPDZrrkz 2246
+VDIVPDrm 2247
+VDIVPDrr 2248
+VDIVPHZ 2249
+VDIVPHZrm 2250
+VDIVPHZrmb 2251
+VDIVPHZrmbk 2252
+VDIVPHZrmbkz 2253
+VDIVPHZrmk 2254
+VDIVPHZrmkz 2255
+VDIVPHZrr 2256
+VDIVPHZrrb 2257
+VDIVPHZrrbk 2258
+VDIVPHZrrbkz 2259
+VDIVPHZrrk 2260
+VDIVPHZrrkz 2261
+VDIVPSYrm 2262
+VDIVPSYrr 2263
+VDIVPSZ 2264
+VDIVPSZrm 2265
+VDIVPSZrmb 2266
+VDIVPSZrmbk 2267
+VDIVPSZrmbkz 2268
+VDIVPSZrmk 2269
+VDIVPSZrmkz 2270
+VDIVPSZrr 2271
+VDIVPSZrrb 2272
+VDIVPSZrrbk 2273
+VDIVPSZrrbkz 2274
+VDIVPSZrrk 2275
+VDIVPSZrrkz 2276
+VDIVPSrm 2277
+VDIVPSrr 2278
+VDIVSDZrm 2279
+VDIVSDZrm_Int 2280
+VDIVSDZrmk_Int 2281
+VDIVSDZrmkz_Int 2282
+VDIVSDZrr 2283
+VDIVSDZrr_Int 2284
+VDIVSDZrrb_Int 2285
+VDIVSDZrrbk_Int 2286
+VDIVSDZrrbkz_Int 2287
+VDIVSDZrrk_Int 2288
+VDIVSDZrrkz_Int 2289
+VDIVSDrm 2290
+VDIVSDrm_Int 2291
+VDIVSDrr 2292
+VDIVSDrr_Int 2293
+VDIVSHZrm 2294
+VDIVSHZrm_Int 2295
+VDIVSHZrmk_Int 2296
+VDIVSHZrmkz_Int 2297
+VDIVSHZrr 2298
+VDIVSHZrr_Int 2299
+VDIVSHZrrb_Int 2300
+VDIVSHZrrbk_Int 2301
+VDIVSHZrrbkz_Int 2302
+VDIVSHZrrk_Int 2303
+VDIVSHZrrkz_Int 2304
+VDIVSSZrm 2305
+VDIVSSZrm_Int 2306
+VDIVSSZrmk_Int 2307
+VDIVSSZrmkz_Int 2308
+VDIVSSZrr 2309
+VDIVSSZrr_Int 2310
+VDIVSSZrrb_Int 2311
+VDIVSSZrrbk_Int 2312
+VDIVSSZrrbkz_Int 2313
+VDIVSSZrrk_Int 2314
+VDIVSSZrrkz_Int 2315
+VDIVSSrm 2316
+VDIVSSrm_Int 2317
+VDIVSSrr 2318
+VDIVSSrr_Int 2319
+VDPBF 2320
+VDPPDrmi 2321
+VDPPDrri 2322
+VDPPHPSZ 2323
+VDPPHPSZm 2324
+VDPPHPSZmb 2325
+VDPPHPSZmbk 2326
+VDPPHPSZmbkz 2327
+VDPPHPSZmk 2328
+VDPPHPSZmkz 2329
+VDPPHPSZr 2330
+VDPPHPSZrk 2331
+VDPPHPSZrkz 2332
+VDPPSYrmi 2333
+VDPPSYrri 2334
+VDPPSrmi 2335
+VDPPSrri 2336
+VERRm 2337
+VERRr 2338
+VERWm 2339
+VERWr 2340
+VEXP 2341
+VEXPANDPDZ 2342
+VEXPANDPDZrm 2343
+VEXPANDPDZrmk 2344
+VEXPANDPDZrmkz 2345
+VEXPANDPDZrr 2346
+VEXPANDPDZrrk 2347
+VEXPANDPDZrrkz 2348
+VEXPANDPSZ 2349
+VEXPANDPSZrm 2350
+VEXPANDPSZrmk 2351
+VEXPANDPSZrmkz 2352
+VEXPANDPSZrr 2353
+VEXPANDPSZrrk 2354
+VEXPANDPSZrrkz 2355
+VEXTRACTF 2356
+VEXTRACTI 2357
+VEXTRACTPSZmri 2358
+VEXTRACTPSZrri 2359
+VEXTRACTPSmri 2360
+VEXTRACTPSrri 2361
+VFCMADDCPHZ 2362
+VFCMADDCPHZm 2363
+VFCMADDCPHZmb 2364
+VFCMADDCPHZmbk 2365
+VFCMADDCPHZmbkz 2366
+VFCMADDCPHZmk 2367
+VFCMADDCPHZmkz 2368
+VFCMADDCPHZr 2369
+VFCMADDCPHZrb 2370
+VFCMADDCPHZrbk 2371
+VFCMADDCPHZrbkz 2372
+VFCMADDCPHZrk 2373
+VFCMADDCPHZrkz 2374
+VFCMADDCSHZm 2375
+VFCMADDCSHZmk 2376
+VFCMADDCSHZmkz 2377
+VFCMADDCSHZr 2378
+VFCMADDCSHZrb 2379
+VFCMADDCSHZrbk 2380
+VFCMADDCSHZrbkz 2381
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+VFCMADDCSHZrkz 2383
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+VSQRTPDZmb 6520
+VSQRTPDZmbk 6521
+VSQRTPDZmbkz 6522
+VSQRTPDZmk 6523
+VSQRTPDZmkz 6524
+VSQRTPDZr 6525
+VSQRTPDZrb 6526
+VSQRTPDZrbk 6527
+VSQRTPDZrbkz 6528
+VSQRTPDZrk 6529
+VSQRTPDZrkz 6530
+VSQRTPDm 6531
+VSQRTPDr 6532
+VSQRTPHZ 6533
+VSQRTPHZm 6534
+VSQRTPHZmb 6535
+VSQRTPHZmbk 6536
+VSQRTPHZmbkz 6537
+VSQRTPHZmk 6538
+VSQRTPHZmkz 6539
+VSQRTPHZr 6540
+VSQRTPHZrb 6541
+VSQRTPHZrbk 6542
+VSQRTPHZrbkz 6543
+VSQRTPHZrk 6544
+VSQRTPHZrkz 6545
+VSQRTPSYm 6546
+VSQRTPSYr 6547
+VSQRTPSZ 6548
+VSQRTPSZm 6549
+VSQRTPSZmb 6550
+VSQRTPSZmbk 6551
+VSQRTPSZmbkz 6552
+VSQRTPSZmk 6553
+VSQRTPSZmkz 6554
+VSQRTPSZr 6555
+VSQRTPSZrb 6556
+VSQRTPSZrbk 6557
+VSQRTPSZrbkz 6558
+VSQRTPSZrk 6559
+VSQRTPSZrkz 6560
+VSQRTPSm 6561
+VSQRTPSr 6562
+VSQRTSDZm 6563
+VSQRTSDZm_Int 6564
+VSQRTSDZmk_Int 6565
+VSQRTSDZmkz_Int 6566
+VSQRTSDZr 6567
+VSQRTSDZr_Int 6568
+VSQRTSDZrb_Int 6569
+VSQRTSDZrbk_Int 6570
+VSQRTSDZrbkz_Int 6571
+VSQRTSDZrk_Int 6572
+VSQRTSDZrkz_Int 6573
+VSQRTSDm 6574
+VSQRTSDm_Int 6575
+VSQRTSDr 6576
+VSQRTSDr_Int 6577
+VSQRTSHZm 6578
+VSQRTSHZm_Int 6579
+VSQRTSHZmk_Int 6580
+VSQRTSHZmkz_Int 6581
+VSQRTSHZr 6582
+VSQRTSHZr_Int 6583
+VSQRTSHZrb_Int 6584
+VSQRTSHZrbk_Int 6585
+VSQRTSHZrbkz_Int 6586
+VSQRTSHZrk_Int 6587
+VSQRTSHZrkz_Int 6588
+VSQRTSSZm 6589
+VSQRTSSZm_Int 6590
+VSQRTSSZmk_Int 6591
+VSQRTSSZmkz_Int 6592
+VSQRTSSZr 6593
+VSQRTSSZr_Int 6594
+VSQRTSSZrb_Int 6595
+VSQRTSSZrbk_Int 6596
+VSQRTSSZrbkz_Int 6597
+VSQRTSSZrk_Int 6598
+VSQRTSSZrkz_Int 6599
+VSQRTSSm 6600
+VSQRTSSm_Int 6601
+VSQRTSSr 6602
+VSQRTSSr_Int 6603
+VSTMXCSR 6604
+VSUBBF 6605
+VSUBPDYrm 6606
+VSUBPDYrr 6607
+VSUBPDZ 6608
+VSUBPDZrm 6609
+VSUBPDZrmb 6610
+VSUBPDZrmbk 6611
+VSUBPDZrmbkz 6612
+VSUBPDZrmk 6613
+VSUBPDZrmkz 6614
+VSUBPDZrr 6615
+VSUBPDZrrb 6616
+VSUBPDZrrbk 6617
+VSUBPDZrrbkz 6618
+VSUBPDZrrk 6619
+VSUBPDZrrkz 6620
+VSUBPDrm 6621
+VSUBPDrr 6622
+VSUBPHZ 6623
+VSUBPHZrm 6624
+VSUBPHZrmb 6625
+VSUBPHZrmbk 6626
+VSUBPHZrmbkz 6627
+VSUBPHZrmk 6628
+VSUBPHZrmkz 6629
+VSUBPHZrr 6630
+VSUBPHZrrb 6631
+VSUBPHZrrbk 6632
+VSUBPHZrrbkz 6633
+VSUBPHZrrk 6634
+VSUBPHZrrkz 6635
+VSUBPSYrm 6636
+VSUBPSYrr 6637
+VSUBPSZ 6638
+VSUBPSZrm 6639
+VSUBPSZrmb 6640
+VSUBPSZrmbk 6641
+VSUBPSZrmbkz 6642
+VSUBPSZrmk 6643
+VSUBPSZrmkz 6644
+VSUBPSZrr 6645
+VSUBPSZrrb 6646
+VSUBPSZrrbk 6647
+VSUBPSZrrbkz 6648
+VSUBPSZrrk 6649
+VSUBPSZrrkz 6650
+VSUBPSrm 6651
+VSUBPSrr 6652
+VSUBSDZrm 6653
+VSUBSDZrm_Int 6654
+VSUBSDZrmk_Int 6655
+VSUBSDZrmkz_Int 6656
+VSUBSDZrr 6657
+VSUBSDZrr_Int 6658
+VSUBSDZrrb_Int 6659
+VSUBSDZrrbk_Int 6660
+VSUBSDZrrbkz_Int 6661
+VSUBSDZrrk_Int 6662
+VSUBSDZrrkz_Int 6663
+VSUBSDrm 6664
+VSUBSDrm_Int 6665
+VSUBSDrr 6666
+VSUBSDrr_Int 6667
+VSUBSHZrm 6668
+VSUBSHZrm_Int 6669
+VSUBSHZrmk_Int 6670
+VSUBSHZrmkz_Int 6671
+VSUBSHZrr 6672
+VSUBSHZrr_Int 6673
+VSUBSHZrrb_Int 6674
+VSUBSHZrrbk_Int 6675
+VSUBSHZrrbkz_Int 6676
+VSUBSHZrrk_Int 6677
+VSUBSHZrrkz_Int 6678
+VSUBSSZrm 6679
+VSUBSSZrm_Int 6680
+VSUBSSZrmk_Int 6681
+VSUBSSZrmkz_Int 6682
+VSUBSSZrr 6683
+VSUBSSZrr_Int 6684
+VSUBSSZrrb_Int 6685
+VSUBSSZrrbk_Int 6686
+VSUBSSZrrbkz_Int 6687
+VSUBSSZrrk_Int 6688
+VSUBSSZrrkz_Int 6689
+VSUBSSrm 6690
+VSUBSSrm_Int 6691
+VSUBSSrr 6692
+VSUBSSrr_Int 6693
+VTESTPDYrm 6694
+VTESTPDYrr 6695
+VTESTPDrm 6696
+VTESTPDrr 6697
+VTESTPSYrm 6698
+VTESTPSYrr 6699
+VTESTPSrm 6700
+VTESTPSrr 6701
+VUCOMISDZrm 6702
+VUCOMISDZrm_Int 6703
+VUCOMISDZrr 6704
+VUCOMISDZrr_Int 6705
+VUCOMISDZrrb 6706
+VUCOMISDrm 6707
+VUCOMISDrm_Int 6708
+VUCOMISDrr 6709
+VUCOMISDrr_Int 6710
+VUCOMISHZrm 6711
+VUCOMISHZrm_Int 6712
+VUCOMISHZrr 6713
+VUCOMISHZrr_Int 6714
+VUCOMISHZrrb 6715
+VUCOMISSZrm 6716
+VUCOMISSZrm_Int 6717
+VUCOMISSZrr 6718
+VUCOMISSZrr_Int 6719
+VUCOMISSZrrb 6720
+VUCOMISSrm 6721
+VUCOMISSrm_Int 6722
+VUCOMISSrr 6723
+VUCOMISSrr_Int 6724
+VUCOMXSDZrm 6725
+VUCOMXSDZrm_Int 6726
+VUCOMXSDZrr 6727
+VUCOMXSDZrr_Int 6728
+VUCOMXSDZrrb_Int 6729
+VUCOMXSHZrm 6730
+VUCOMXSHZrm_Int 6731
+VUCOMXSHZrr 6732
+VUCOMXSHZrr_Int 6733
+VUCOMXSHZrrb_Int 6734
+VUCOMXSSZrm 6735
+VUCOMXSSZrm_Int 6736
+VUCOMXSSZrr 6737
+VUCOMXSSZrr_Int 6738
+VUCOMXSSZrrb_Int 6739
+VUNPCKHPDYrm 6740
+VUNPCKHPDYrr 6741
+VUNPCKHPDZ 6742
+VUNPCKHPDZrm 6743
+VUNPCKHPDZrmb 6744
+VUNPCKHPDZrmbk 6745
+VUNPCKHPDZrmbkz 6746
+VUNPCKHPDZrmk 6747
+VUNPCKHPDZrmkz 6748
+VUNPCKHPDZrr 6749
+VUNPCKHPDZrrk 6750
+VUNPCKHPDZrrkz 6751
+VUNPCKHPDrm 6752
+VUNPCKHPDrr 6753
+VUNPCKHPSYrm 6754
+VUNPCKHPSYrr 6755
+VUNPCKHPSZ 6756
+VUNPCKHPSZrm 6757
+VUNPCKHPSZrmb 6758
+VUNPCKHPSZrmbk 6759
+VUNPCKHPSZrmbkz 6760
+VUNPCKHPSZrmk 6761
+VUNPCKHPSZrmkz 6762
+VUNPCKHPSZrr 6763
+VUNPCKHPSZrrk 6764
+VUNPCKHPSZrrkz 6765
+VUNPCKHPSrm 6766
+VUNPCKHPSrr 6767
+VUNPCKLPDYrm 6768
+VUNPCKLPDYrr 6769
+VUNPCKLPDZ 6770
+VUNPCKLPDZrm 6771
+VUNPCKLPDZrmb 6772
+VUNPCKLPDZrmbk 6773
+VUNPCKLPDZrmbkz 6774
+VUNPCKLPDZrmk 6775
+VUNPCKLPDZrmkz 6776
+VUNPCKLPDZrr 6777
+VUNPCKLPDZrrk 6778
+VUNPCKLPDZrrkz 6779
+VUNPCKLPDrm 6780
+VUNPCKLPDrr 6781
+VUNPCKLPSYrm 6782
+VUNPCKLPSYrr 6783
+VUNPCKLPSZ 6784
+VUNPCKLPSZrm 6785
+VUNPCKLPSZrmb 6786
+VUNPCKLPSZrmbk 6787
+VUNPCKLPSZrmbkz 6788
+VUNPCKLPSZrmk 6789
+VUNPCKLPSZrmkz 6790
+VUNPCKLPSZrr 6791
+VUNPCKLPSZrrk 6792
+VUNPCKLPSZrrkz 6793
+VUNPCKLPSrm 6794
+VUNPCKLPSrr 6795
+VXORPDYrm 6796
+VXORPDYrr 6797
+VXORPDZ 6798
+VXORPDZrm 6799
+VXORPDZrmb 6800
+VXORPDZrmbk 6801
+VXORPDZrmbkz 6802
+VXORPDZrmk 6803
+VXORPDZrmkz 6804
+VXORPDZrr 6805
+VXORPDZrrk 6806
+VXORPDZrrkz 6807
+VXORPDrm 6808
+VXORPDrr 6809
+VXORPSYrm 6810
+VXORPSYrr 6811
+VXORPSZ 6812
+VXORPSZrm 6813
+VXORPSZrmb 6814
+VXORPSZrmbk 6815
+VXORPSZrmbkz 6816
+VXORPSZrmk 6817
+VXORPSZrmkz 6818
+VXORPSZrr 6819
+VXORPSZrrk 6820
+VXORPSZrrkz 6821
+VXORPSrm 6822
+VXORPSrr 6823
+VZEROALL 6824
+VZEROUPPER 6825
+V_SET 6826
+V_SETALLONES 6827
+WAIT 6828
+WBINVD 6829
+WBNOINVD 6830
+WRFLAGS 6831
+WRFSBASE 6832
+WRGSBASE 6833
+WRMSR 6834
+WRMSRLIST 6835
+WRMSRNS 6836
+WRMSRNSir 6837
+WRMSRNSir_EVEX 6838
+WRPKRUr 6839
+WRSSD 6840
+WRSSD_EVEX 6841
+WRSSQ 6842
+WRSSQ_EVEX 6843
+WRUSSD 6844
+WRUSSD_EVEX 6845
+WRUSSQ 6846
+WRUSSQ_EVEX 6847
+XABORT 6848
+XABORT_DEF 6849
+XACQUIRE_PREFIX 6850
+XADD 6851
+XAM_F 6852
+XAM_Fp 6853
+XBEGIN 6854
+XCHG 6855
+XCH_F 6856
+XCRYPTCBC 6857
+XCRYPTCFB 6858
+XCRYPTCTR 6859
+XCRYPTECB 6860
+XCRYPTOFB 6861
+XEND 6862
+XGETBV 6863
+XLAT 6864
+XOR 6865
+XORPDrm 6866
+XORPDrr 6867
+XORPSrm 6868
+XORPSrr 6869
+XRELEASE_PREFIX 6870
+XRESLDTRK 6871
+XRSTOR 6872
+XRSTORS 6873
+XSAVE 6874
+XSAVEC 6875
+XSAVEOPT 6876
+XSAVES 6877
+XSETBV 6878
+XSHA 6879
+XSTORE 6880
+XSUSLDTRK 6881
+XTEST 6882
+Immediate 6883
+CImmediate 6884
+FPImmediate 6885
+MBB 6886
+FrameIndex 6887
+ConstantPoolIndex 6888
+TargetIndex 6889
+JumpTableIndex 6890
+ExternalSymbol 6891
+GlobalAddress 6892
+BlockAddress 6893
+RegisterMask 6894
+RegisterLiveOut 6895
+Metadata 6896
+MCSymbol 6897
+CFIIndex 6898
+IntrinsicID 6899
+Predicate 6900
+ShuffleMask 6901
+PhyReg_GR8 6902
+PhyReg_GRH8 6903
+PhyReg_GR8_NOREX2 6904
+PhyReg_GR8_NOREX 6905
+PhyReg_GR8_ABCD_H 6906
+PhyReg_GR8_ABCD_L 6907
+PhyReg_GRH16 6908
+PhyReg_GR16 6909
+PhyReg_GR16_NOREX2 6910
+PhyReg_GR16_NOREX 6911
+PhyReg_VK1 6912
+PhyReg_VK16 6913
+PhyReg_VK2 6914
+PhyReg_VK4 6915
+PhyReg_VK8 6916
+PhyReg_VK16WM 6917
+PhyReg_VK1WM 6918
+PhyReg_VK2WM 6919
+PhyReg_VK4WM 6920
+PhyReg_VK8WM 6921
+PhyReg_SEGMENT_REG 6922
+PhyReg_GR16_ABCD 6923
+PhyReg_FPCCR 6924
+PhyReg_FR16X 6925
+PhyReg_FR16 6926
+PhyReg_VK16PAIR 6927
+PhyReg_VK1PAIR 6928
+PhyReg_VK2PAIR 6929
+PhyReg_VK4PAIR 6930
+PhyReg_VK8PAIR 6931
+PhyReg_VK1PAIR_with_sub_mask_0_in_VK1WM 6932
+PhyReg_LOW32_ADDR_ACCESS_RBP 6933
+PhyReg_LOW32_ADDR_ACCESS 6934
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 6935
+PhyReg_FR32X 6936
+PhyReg_GR32 6937
+PhyReg_GR32_NOSP 6938
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 6939
+PhyReg_DEBUG_REG 6940
+PhyReg_FR32 6941
+PhyReg_GR32_NOREX2 6942
+PhyReg_GR32_NOREX2_NOSP 6943
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 6944
+PhyReg_GR32_NOREX 6945
+PhyReg_VK32 6946
+PhyReg_GR32_NOREX_NOSP 6947
+PhyReg_RFP32 6948
+PhyReg_VK32WM 6949
+PhyReg_GR32_ABCD 6950
+PhyReg_GR32_TC 6951
+PhyReg_GR32_ABCD_and_GR32_TC 6952
+PhyReg_GR32_AD 6953
+PhyReg_GR32_ArgRef 6954
+PhyReg_GR32_BPSP 6955
+PhyReg_GR32_BSI 6956
+PhyReg_GR32_CB 6957
+PhyReg_GR32_DC 6958
+PhyReg_GR32_DIBP 6959
+PhyReg_GR32_SIDI 6960
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 6961
+PhyReg_CCR 6962
+PhyReg_DFCCR 6963
+PhyReg_GR32_ABCD_and_GR32_BSI 6964
+PhyReg_GR32_AD_and_GR32_ArgRef 6965
+PhyReg_GR32_ArgRef_and_GR32_CB 6966
+PhyReg_GR32_BPSP_and_GR32_DIBP 6967
+PhyReg_GR32_BPSP_and_GR32_TC 6968
+PhyReg_GR32_BSI_and_GR32_SIDI 6969
+PhyReg_GR32_DIBP_and_GR32_SIDI 6970
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 6971
+PhyReg_LOW32_ADDR_ACCESS_with_sub_32bit 6972
+PhyReg_RFP64 6973
+PhyReg_GR64 6974
+PhyReg_FR64X 6975
+PhyReg_GR64_with_sub_8bit 6976
+PhyReg_GR64_NOSP 6977
+PhyReg_GR64_NOREX2 6978
+PhyReg_CONTROL_REG 6979
+PhyReg_FR64 6980
+PhyReg_GR64_with_sub_16bit_in_GR16_NOREX2 6981
+PhyReg_GR64_NOREX2_NOSP 6982
+PhyReg_GR64PLTSafe 6983
+PhyReg_GR64_TC 6984
+PhyReg_GR64_NOREX 6985
+PhyReg_GR64_TCW64 6986
+PhyReg_GR64_TC_with_sub_8bit 6987
+PhyReg_GR64_NOREX2_NOSP_and_GR64_TC 6988
+PhyReg_GR64_TCW64_with_sub_8bit 6989
+PhyReg_GR64_TC_and_GR64_TCW64 6990
+PhyReg_GR64_with_sub_16bit_in_GR16_NOREX 6991
+PhyReg_VK64 6992
+PhyReg_VR64 6993
+PhyReg_GR64PLTSafe_and_GR64_TC 6994
+PhyReg_GR64_NOREX2_NOSP_and_GR64_TCW64 6995
+PhyReg_GR64_NOREX_NOSP 6996
+PhyReg_GR64_NOREX_and_GR64_TC 6997
+PhyReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 6998
+PhyReg_VK64WM 6999
+PhyReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 7000
+PhyReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7001
+PhyReg_GR64PLTSafe_and_GR64_TCW64 7002
+PhyReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7003
+PhyReg_GR64_NOREX_and_GR64_TCW64 7004
+PhyReg_GR64_ABCD 7005
+PhyReg_GR64_with_sub_32bit_in_GR32_TC 7006
+PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7007
+PhyReg_GR64_AD 7008
+PhyReg_GR64_ArgRef 7009
+PhyReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7010
+PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef 7011
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP 7012
+PhyReg_GR64_with_sub_32bit_in_GR32_BSI 7013
+PhyReg_GR64_with_sub_32bit_in_GR32_CB 7014
+PhyReg_GR64_with_sub_32bit_in_GR32_DIBP 7015
+PhyReg_GR64_with_sub_32bit_in_GR32_SIDI 7016
+PhyReg_GR64_A 7017
+PhyReg_GR64_ArgRef_and_GR64_TC 7018
+PhyReg_GR64_and_LOW32_ADDR_ACCESS 7019
+PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7020
+PhyReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7021
+PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7022
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7023
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7024
+PhyReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7025
+PhyReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7026
+PhyReg_RST 7027
+PhyReg_RFP80 7028
+PhyReg_RFP80_7 7029
+PhyReg_VR128X 7030
+PhyReg_VR128 7031
+PhyReg_VR256X 7032
+PhyReg_VR256 7033
+PhyReg_VR512 7034
+PhyReg_VR512_0_15 7035
+PhyReg_TILE 7036
+PhyReg_TILEPAIR 7037
+VirtReg_GR8 7038
+VirtReg_GRH8 7039
+VirtReg_GR8_NOREX2 7040
+VirtReg_GR8_NOREX 7041
+VirtReg_GR8_ABCD_H 7042
+VirtReg_GR8_ABCD_L 7043
+VirtReg_GRH16 7044
+VirtReg_GR16 7045
+VirtReg_GR16_NOREX2 7046
+VirtReg_GR16_NOREX 7047
+VirtReg_VK1 7048
+VirtReg_VK16 7049
+VirtReg_VK2 7050
+VirtReg_VK4 7051
+VirtReg_VK8 7052
+VirtReg_VK16WM 7053
+VirtReg_VK1WM 7054
+VirtReg_VK2WM 7055
+VirtReg_VK4WM 7056
+VirtReg_VK8WM 7057
+VirtReg_SEGMENT_REG 7058
+VirtReg_GR16_ABCD 7059
+VirtReg_FPCCR 7060
+VirtReg_FR16X 7061
+VirtReg_FR16 7062
+VirtReg_VK16PAIR 7063
+VirtReg_VK1PAIR 7064
+VirtReg_VK2PAIR 7065
+VirtReg_VK4PAIR 7066
+VirtReg_VK8PAIR 7067
+VirtReg_VK1PAIR_with_sub_mask_0_in_VK1WM 7068
+VirtReg_LOW32_ADDR_ACCESS_RBP 7069
+VirtReg_LOW32_ADDR_ACCESS 7070
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 7071
+VirtReg_FR32X 7072
+VirtReg_GR32 7073
+VirtReg_GR32_NOSP 7074
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 7075
+VirtReg_DEBUG_REG 7076
+VirtReg_FR32 7077
+VirtReg_GR32_NOREX2 7078
+VirtReg_GR32_NOREX2_NOSP 7079
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 7080
+VirtReg_GR32_NOREX 7081
+VirtReg_VK32 7082
+VirtReg_GR32_NOREX_NOSP 7083
+VirtReg_RFP32 7084
+VirtReg_VK32WM 7085
+VirtReg_GR32_ABCD 7086
+VirtReg_GR32_TC 7087
+VirtReg_GR32_ABCD_and_GR32_TC 7088
+VirtReg_GR32_AD 7089
+VirtReg_GR32_ArgRef 7090
+VirtReg_GR32_BPSP 7091
+VirtReg_GR32_BSI 7092
+VirtReg_GR32_CB 7093
+VirtReg_GR32_DC 7094
+VirtReg_GR32_DIBP 7095
+VirtReg_GR32_SIDI 7096
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 7097
+VirtReg_CCR 7098
+VirtReg_DFCCR 7099
+VirtReg_GR32_ABCD_and_GR32_BSI 7100
+VirtReg_GR32_AD_and_GR32_ArgRef 7101
+VirtReg_GR32_ArgRef_and_GR32_CB 7102
+VirtReg_GR32_BPSP_and_GR32_DIBP 7103
+VirtReg_GR32_BPSP_and_GR32_TC 7104
+VirtReg_GR32_BSI_and_GR32_SIDI 7105
+VirtReg_GR32_DIBP_and_GR32_SIDI 7106
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 7107
+VirtReg_LOW32_ADDR_ACCESS_with_sub_32bit 7108
+VirtReg_RFP64 7109
+VirtReg_GR64 7110
+VirtReg_FR64X 7111
+VirtReg_GR64_with_sub_8bit 7112
+VirtReg_GR64_NOSP 7113
+VirtReg_GR64_NOREX2 7114
+VirtReg_CONTROL_REG 7115
+VirtReg_FR64 7116
+VirtReg_GR64_with_sub_16bit_in_GR16_NOREX2 7117
+VirtReg_GR64_NOREX2_NOSP 7118
+VirtReg_GR64PLTSafe 7119
+VirtReg_GR64_TC 7120
+VirtReg_GR64_NOREX 7121
+VirtReg_GR64_TCW64 7122
+VirtReg_GR64_TC_with_sub_8bit 7123
+VirtReg_GR64_NOREX2_NOSP_and_GR64_TC 7124
+VirtReg_GR64_TCW64_with_sub_8bit 7125
+VirtReg_GR64_TC_and_GR64_TCW64 7126
+VirtReg_GR64_with_sub_16bit_in_GR16_NOREX 7127
+VirtReg_VK64 7128
+VirtReg_VR64 7129
+VirtReg_GR64PLTSafe_and_GR64_TC 7130
+VirtReg_GR64_NOREX2_NOSP_and_GR64_TCW64 7131
+VirtReg_GR64_NOREX_NOSP 7132
+VirtReg_GR64_NOREX_and_GR64_TC 7133
+VirtReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 7134
+VirtReg_VK64WM 7135
+VirtReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 7136
+VirtReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7137
+VirtReg_GR64PLTSafe_and_GR64_TCW64 7138
+VirtReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7139
+VirtReg_GR64_NOREX_and_GR64_TCW64 7140
+VirtReg_GR64_ABCD 7141
+VirtReg_GR64_with_sub_32bit_in_GR32_TC 7142
+VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7143
+VirtReg_GR64_AD 7144
+VirtReg_GR64_ArgRef 7145
+VirtReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7146
+VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef 7147
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP 7148
+VirtReg_GR64_with_sub_32bit_in_GR32_BSI 7149
+VirtReg_GR64_with_sub_32bit_in_GR32_CB 7150
+VirtReg_GR64_with_sub_32bit_in_GR32_DIBP 7151
+VirtReg_GR64_with_sub_32bit_in_GR32_SIDI 7152
+VirtReg_GR64_A 7153
+VirtReg_GR64_ArgRef_and_GR64_TC 7154
+VirtReg_GR64_and_LOW32_ADDR_ACCESS 7155
+VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7156
+VirtReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7157
+VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7158
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7159
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7160
+VirtReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7161
+VirtReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7162
+VirtReg_RST 7163
+VirtReg_RFP80 7164
+VirtReg_RFP80_7 7165
+VirtReg_VR128X 7166
+VirtReg_VR128 7167
+VirtReg_VR256X 7168
+VirtReg_VR256 7169
+VirtReg_VR512 7170
+VirtReg_VR512_0_15 7171
+VirtReg_TILE 7172
+VirtReg_TILEPAIR 7173
>From 76a03d68bcb463f1f76ecb6e8ecf242352187601 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 29 Oct 2025 13:29:49 +0000
Subject: [PATCH 12/13] Update reference_triplets.txt
---
.../llvm-ir2vec/output/reference_triplets.txt | 56 +++++++++----------
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
index dfbac4ce0c4d3..24c0d0e5daa7d 100644
--- a/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
+++ b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
@@ -1,33 +1,33 @@
MAX_RELATION=4
-187 7072 1
-187 6968 2
-187 187 0
-187 7072 1
+187 7073 1
187 6969 2
+187 187 0
+187 7073 1
+187 6970 2
187 10 0
-10 7072 1
-10 7072 2
-10 7072 3
-10 6961 4
+10 7073 1
+10 7073 2
+10 7073 3
+10 6962 4
10 187 0
-187 6952 1
-187 7072 2
-187 1555 0
-1555 6882 1
-1555 6952 2
-187 7072 1
-187 6968 2
-187 187 0
-187 7072 1
+187 6953 1
+187 7073 2
+187 1556 0
+1556 6883 1
+1556 6953 2
+187 7073 1
187 6969 2
-187 601 0
-601 7072 1
-601 7072 2
-601 7072 3
-601 6961 4
-601 187 0
-187 6952 1
-187 7072 2
-187 1555 0
-1555 6882 1
-1555 6952 2
+187 187 0
+187 7073 1
+187 6970 2
+187 602 0
+602 7073 1
+602 7073 2
+602 7073 3
+602 6962 4
+602 187 0
+187 6953 1
+187 7073 2
+187 1556 0
+1556 6883 1
+1556 6953 2
\ No newline at end of file
>From a5635b799ede3ce5a55ed9f847c0386eb2bec540 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 29 Oct 2025 14:08:34 +0000
Subject: [PATCH 13/13] Add trailing new line to reference_triplets.txt
---
llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
index 24c0d0e5daa7d..a35008c015605 100644
--- a/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
+++ b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
@@ -30,4 +30,4 @@ MAX_RELATION=4
187 7073 2
187 1556 0
1556 6883 1
-1556 6953 2
\ No newline at end of file
+1556 6953 2
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