[llvm] [AArch64] Allow FPRCVT Instructions to Run in Streaming Mode (PR #165432)

[via llvm-commits]

================
@@ -21,6 +22,14 @@ define half @scvtf_f16i32(<4 x i32> %x) {
 ; CHECK-NO-FPRCVT-NEXT:    scvtf s0, s0
 ; CHECK-NO-FPRCVT-NEXT:    fcvt h0, s0
 ; CHECK-NO-FPRCVT-NEXT:    ret
+;
+; CHECK-STREAMING-LABEL: scvtf_f16i32:
+; CHECK-STREAMING:       // %bb.0:
+; CHECK-STREAMING-NEXT:    ptrue p0.s
+; CHECK-STREAMING-NEXT:    // kill: def $q0 killed $q0 def $z0
+; CHECK-STREAMING-NEXT:    scvtf z0.h, p0/m, z0.s
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Lukacma wrote:

This is incorrect assembly to be emitted. There is no reason to use SVE instructions here. It seems like we neeed to modify this piece of code in Aarch64IselLowering:

```
  if (useSVEForFixedLengthVectorVT(VT, !Subtarget->isNeonAvailable()) ||
      useSVEForFixedLengthVectorVT(InVT, !Subtarget->isNeonAvailable()))
```
This gets trigger in this scenario even though it is perfectly fine to use either GPR to FPR variant of SCVTF instruction or because FPRCVT is enabled we could even use FPR to FPR variant 

https://github.com/llvm/llvm-project/pull/165432